set_clock
if (dc->hwss.set_clock)
return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
.set_clock = dcn10_set_clock,
enum dc_status (*set_clock)(struct dc *dc,
gpio->algo.setscl = set_clock;
set_clock(gpio, 1);
set_clock(gpio, 1);
chan->algo.setscl = set_clock;
set_clock(chan, 1);
chan->algo.setscl = set_clock;
set_clock(chan, 1);
set_clock(bus, 1);
set_clock(bus, 1);
algo->setscl = set_clock;
i2c->bit.setscl = set_clock;
if (vpif_config_data->set_clock) {
ret = vpif_config_data->set_clock(ch->vpifparams.std_info.
.set_clock = tegra210_emc_r21021_set_clock,
emc->sequence->set_clock(emc, clksrc);
void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
host->set_clock = renesas_sdhi_set_clock;
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_brcmstb_set_clock,
.set_clock = sdhci_brcmstb_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
host->ops->set_clock(host, host->clock);
.set_clock = esdhc_pltfm_set_clock,
.set_clock = esdhc_mcf_pltfm_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_msm_set_clock,
.set_clock = sdhci_arasan_set_clock,
.set_clock = sdhci_arasan_set_clock,
.set_clock = aspeed_sdhci_set_clock,
.set_clock = sdhci_at91_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = dwcmshc_rk3568_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_eic7700_set_clock,
.set_clock = esdhc_of_set_clock,
.set_clock = esdhc_of_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = spacemit_sdhci_set_clock,
.set_clock = ma35_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_omap_set_clock,
.set_clock = arasan_sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_intel_set_clock,
.set_clock = sdhci_intel_set_clock,
.set_clock = sdhci_snps_set_clock,
.set_clock = sdhci_gl9755_set_clock,
.set_clock = sdhci_gl9750_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_gl9767_set_clock,
.set_clock = sdhci_pci_o2_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = pxav3_set_clock,
.set_clock = sdhci_s3c_set_clock,
.set_clock = sdhci_cmu_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = sdhci_sprd_set_clock,
.set_clock = sdhci_set_clock,
.set_clock = tegra_sdhci_set_clock,
.set_clock = tegra_sdhci_set_clock,
.set_clock = tegra_sdhci_set_clock,
.set_clock = tegra_sdhci_set_clock,
host->ops->set_clock(host, ios->clock);
.set_clock = sdhci_set_clock,
host->ops->set_clock(host, ios->clock);
host->ops->set_clock(host, host->clock);
host->ops->set_clock(host, host->clock);
void (*set_clock)(struct sdhci_host *host, unsigned int clock);
.set_clock = sdhci_am654_set_clock,
.set_clock = sdhci_am654_set_clock,
.set_clock = sdhci_j721e_4bit_set_clock,
.set_clock = sdhci_set_clock,
void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
host->set_clock(host, 0);
host->set_clock(host, ios->clock);
host->set_clock(host, ios->clock);
_host->set_clock(_host, 0);
host->set_clock(host, 0);
host->set_clock(host, host->clk_cache);
host->set_clock = uniphier_sd_set_clock;
int (*set_clock)(int, int);
err = set_clock(tscm, rate, INT_MAX);
ret = set_clock(dev, regmap, function, entity->iot.clock, rate);