regmap_set_bits

drivers/clk/clk-si521xx.c

198

regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);

drivers/clk/clk-versaclock5.c

401

ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,

drivers/clk/clk-versaclock5.c

594

return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,

drivers/clk/clk-versaclock5.c

623

ret = regmap_set_bits(vc5->regmap,

drivers/clk/clk-versaclock5.c

648

ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),

drivers/clk/mediatek/clk-gate.c

69

regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs,

drivers/clk/qcom/clk-alpha-pll.c

3059

regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE);

drivers/clk/qcom/clk-alpha-pll.c

826

regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN);

drivers/clk/qcom/dispcc-eliza.c

2075

regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));

drivers/clk/qcom/ipq-cmn-pll.c

291

ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL,

drivers/clk/qcom/ipq-cmn-pll.c

306

ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,

drivers/clk/qcom/videocc-kaanapali.c

764

regmap_set_bits(regmap, 0x9f24, BIT(0));

drivers/clk/qcom/videocc-kaanapali.c

771

regmap_set_bits(regmap, 0x8088, ACCU_CFG_MASK);

drivers/clk/qcom/videocc-kaanapali.c

772

regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK);

drivers/clk/qcom/videocc-kaanapali.c

773

regmap_set_bits(regmap, 0x8100, ACCU_CFG_MASK);

drivers/clk/qcom/videocc-kaanapali.c

774

regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK);

drivers/clk/qcom/videocc-kaanapali.c

775

regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);

drivers/clk/sophgo/clk-sg2044-pll.c

311

return regmap_set_bits(pll->common.regmap,

drivers/clk/tenstorrent/atlantis-prcm.c

209

return regmap_set_bits(gate->common.regmap,

drivers/clk/tenstorrent/atlantis-prcm.c

402

regmap_set_bits(gate->common.regmap,

drivers/clk/thead/clk-th1520-ap.c

327

regmap_set_bits(pll->common.map, pll->common.cfg1,

drivers/counter/stm32-timer-cnt.c

440

regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits);

drivers/counter/stm32-timer-cnt.c

663

regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);

drivers/counter/ti-ecap-capture.c

258

regmap_set_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx));

drivers/dma/cv1800b-dmamux.c

157

regmap_set_bits(dmamux->regmap,

drivers/gpio/gpio-adp5585.c

122

return regmap_set_bits(adp5585_gpio->regmap, info->gpio_dir_a + bank,

drivers/gpio/gpio-bd71815.c

49

return regmap_set_bits(bd71815->regmap, BD71815_REG_GPO, bit);

drivers/gpio/gpio-bd72720.c

124

return regmap_set_bits(bdgpio->regmap, regs[offset],

drivers/gpio/gpio-exar.c

132

regmap_set_bits(exar_gpio->regmap, addr, BIT(bit));

drivers/gpio/gpio-tps65910.c

163

ret = regmap_set_bits(tps65910->regmap,

drivers/gpio/gpio-tps65910.c

46

return regmap_set_bits(tps65910->regmap,

drivers/gpio/gpio-tps65910.c

65

return regmap_set_bits(tps65910->regmap, TPS65910_GPIO0 + offset,

drivers/gpio/gpio-wcove.c

133

regmap_set_bits(wg->regmap, reg, mask);

drivers/gpio/gpio-wcove.c

356

regmap_set_bits(wg->regmap, reg, mask);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

1268

ret = regmap_set_bits(pdata->regmap, SN_IRQ_EVENTS_EN_REG,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

539

regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);

drivers/gpu/drm/ingenic/ingenic-ipu.c

357

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);

drivers/gpu/drm/ingenic/ingenic-ipu.c

360

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,

drivers/gpu/drm/ingenic/ingenic-ipu.c

385

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);

drivers/gpu/drm/ingenic/ingenic-ipu.c

479

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);

drivers/gpu/drm/ingenic/ingenic-ipu.c

557

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,

drivers/gpu/drm/ingenic/ingenic-ipu.c

660

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);

drivers/gpu/drm/ingenic/ingenic-ipu.c

793

regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);

drivers/gpu/drm/mediatek/mtk_hdmi.c

172

regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);

drivers/gpu/drm/mediatek/mtk_hdmi.c

201

regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);

drivers/gpu/drm/mediatek/mtk_hdmi.c

236

regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);

drivers/gpu/drm/mediatek/mtk_hdmi.c

622

regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT);

drivers/gpu/drm/mediatek/mtk_hdmi.c

85

regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

261

regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

276

regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

107

regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

1249

regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

134

regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

162

regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

163

regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

184

regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

185

regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

208

regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

209

regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

232

regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

233

regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

245

regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

252

regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

299

regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

300

regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

306

regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

337

regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

365

regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

427

regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

460

regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

569

regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

572

regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

573

regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

574

regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

591

regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

649

regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

656

regmap_set_bits(hdmi->regs, AIP_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

666

regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

69

regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

714

regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

720

regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

721

regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

732

regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

763

regmap_set_bits(hdmi->regs, VID_DOWNSAMPLE_CONFIG,

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

77

regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

78

regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

79

regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

92

regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

974

regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,

drivers/gpu/drm/panel/panel-abt-y030xx067a.c

208

regmap_set_bits(priv->map, 0x06, REG06_XPSAVE);

drivers/gpu/drm/panel/panel-auo-a030jtn01.c

118

ret = regmap_set_bits(priv->map, REG05, REG05_STDBY);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

867

regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);

drivers/gpu/drm/stm/ltdc.c

1052

regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);

drivers/gpu/drm/stm/ltdc.c

1137

regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);

drivers/gpu/drm/stm/ltdc.c

1166

ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);

drivers/gpu/drm/stm/ltdc.c

1738

regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);

drivers/gpu/drm/stm/ltdc.c

789

regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE);

drivers/gpu/drm/stm/ltdc.c

793

regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);

drivers/gpu/drm/stm/ltdc.c

818

regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);

drivers/gpu/drm/verisilicon/vs_bridge.c

161

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

165

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

169

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START,

drivers/gpu/drm/verisilicon/vs_bridge.c

172

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id),

drivers/gpu/drm/verisilicon/vs_bridge.c

237

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id),

drivers/gpu/drm/verisilicon/vs_crtc.c

135

regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id));

drivers/gpu/drm/verisilicon/vs_crtc.c

66

regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

73

regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

95

regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

58

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

72

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

91

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/hwmon/amc6821.c

975

err = regmap_set_bits(regmap, AMC6821_REG_CONF4, AMC6821_CONF4_MODE);

drivers/hwmon/jc42.c

504

ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS,

drivers/hwmon/ltc4282.c

1280

ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST,

drivers/hwmon/ltc4282.c

1466

ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB,

drivers/hwmon/ltc4282.c

1487

ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK);

drivers/hwmon/ltc4282.c

1667

ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK);

drivers/hwmon/ltc4283.c

1131

ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,

drivers/hwmon/ltc4283.c

1352

ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,

drivers/hwmon/ltc4283.c

1383

ret = regmap_set_bits(st->map, LTC4283_CONTROL_2,

drivers/hwmon/ltc4283.c

1390

ret = regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL,

drivers/hwmon/ltc4283.c

1429

ret = regmap_set_bits(st->map, LTC4283_CONFIG_3,

drivers/hwmon/ltc4283.c

1468

ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, LTC4283_RW_PAGE_MASK);

drivers/hwmon/ltc4283.c

694

ret = regmap_set_bits(st->map, reg, bit);

drivers/hwmon/max31760.c

270

return regmap_set_bits(state->regmap, REG_CR3, BIT(channel));

drivers/hwmon/max31760.c

285

return regmap_set_bits(state->regmap, REG_CR2, CR2_DFC);

drivers/hwmon/max31760.c

477

ret = regmap_set_bits(state->regmap, REG_CR1, CR1_HYST);

drivers/hwmon/max31760.c

537

ret = regmap_set_bits(state->regmap, REG_CR2, CR2_ALERTS);

drivers/hwmon/max31760.c

567

return regmap_set_bits(state->regmap, REG_CR2, CR2_STBY);

drivers/hwmon/max6639.c

328

err = regmap_set_bits(data->regmap, MAX6639_REG_GCONFIG,

drivers/hwmon/max6639.c

594

err = regmap_set_bits(data->regmap, MAX6639_REG_OUTPUT_MASK, BIT(1 - i));

drivers/hwmon/max6697.c

309

ret = regmap_set_bits(regmap, MAX6581_REG_OFFSET_SELECT,

drivers/hwmon/tps23861.c

535

regmap_set_bits(data->regmap,

drivers/iio/accel/adxl313_core.c

907

ret = regmap_set_bits(data->regmap, ADXL313_REG_INT_ENABLE,

drivers/iio/accel/adxl345_core.c

857

ret = regmap_set_bits(st->regmap, ADXL345_REG_TAP_AXIS,

drivers/iio/accel/fxls8962af-core.c

809

ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,

drivers/iio/accel/fxls8962af-core.c

853

ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN,

drivers/iio/accel/kionix-kx022a.c

1157

ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,

drivers/iio/accel/kionix-kx022a.c

476

ret = regmap_set_bits(data->regmap, data->chip_info->cntl,

drivers/iio/accel/kionix-kx022a.c

907

return regmap_set_bits(data->regmap, data->chip_info->cntl,

drivers/iio/accel/kionix-kx022a.c

930

return regmap_set_bits(data->regmap, data->ien_reg, mask);

drivers/iio/accel/kionix-kx022a.c

991

ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,

drivers/iio/accel/kionix-kx022a.c

997

ret = regmap_set_bits(data->regmap, data->ien_reg,

drivers/iio/adc/88pm886-gpadc.c

290

ret = regmap_set_bits(map, PM886_REG_GPADC_CONFIG(0x6), BIT(0));

drivers/iio/adc/ad4080.c

321

ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A,

drivers/iio/adc/ad4080.c

685

ret = regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A,

drivers/iio/adc/ad4080.c

713

ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A,

drivers/iio/adc/ad4080.c

719

ret = regmap_set_bits(st->regmap[ch],

drivers/iio/adc/ad4134.c

317

ret = regmap_set_bits(st->regmap, AD4134_SDO_PIN_SRC_SEL_REG,

drivers/iio/adc/ad4134.c

323

return regmap_set_bits(st->regmap, AD4134_IFACE_CONFIG_B_REG,

drivers/iio/adc/ad4695.c

1647

return regmap_set_bits(st->regmap, AD4695_REG_GP_MODE,

drivers/iio/adc/ad4695.c

1901

ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A,

drivers/iio/adc/ad4695.c

1917

ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,

drivers/iio/adc/ad4695.c

1939

ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,

drivers/iio/adc/ad4695.c

471

return regmap_set_bits(st->regmap, AD4695_REG_SETUP,

drivers/iio/adc/ad4695.c

874

ret = regmap_set_bits(st->regmap, AD4695_REG_GP_MODE,

drivers/iio/adc/ad4851.c

421

ret = regmap_set_bits(st->regmap, AD4851_REG_INTERFACE_CONFIG_A,

drivers/iio/adc/ad4851.c

428

ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,

drivers/iio/adc/ad4851.c

435

ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,

drivers/iio/adc/ad4851.c

461

ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,

drivers/iio/adc/ad7091r-base.c

160

return regmap_set_bits(st->map, AD7091R_REG_CONF,

drivers/iio/adc/ad7091r-base.c

353

ret = regmap_set_bits(st->map, AD7091R_REG_CONF,

drivers/iio/adc/ad7173.c

525

ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO,

drivers/iio/adc/ad7380.c

1181

ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,

drivers/iio/adc/ad7380.c

1807

ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,

drivers/iio/adc/ad7768-1.c

776

ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL,

drivers/iio/adc/ade9000.c

1495

return regmap_set_bits(st->regmap, ADE9000_REG_MASK0,

drivers/iio/adc/ade9000.c

1516

ret = regmap_set_bits(st->regmap, ADE9000_REG_WFB_CFG,

drivers/iio/adc/ade9000.c

1572

ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,

drivers/iio/adc/ade9000.c

1754

ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,

drivers/iio/adc/adi-axi-adc.c

134

ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,

drivers/iio/adc/adi-axi-adc.c

150

return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,

drivers/iio/adc/adi-axi-adc.c

193

return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,

drivers/iio/adc/adi-axi-adc.c

331

return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),

drivers/iio/adc/adi-axi-adc.c

421

return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,

drivers/iio/adc/adi-axi-adc.c

432

return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,

drivers/iio/adc/adi-axi-adc.c

446

ret = regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,

drivers/iio/adc/axp20x_adc.c

1131

regmap_set_bits(info->regmap, info->data->adc_en2,

drivers/iio/adc/axp288_adc.c

250

return regmap_set_bits(info->regmap, AXP20X_ADC_EN1,

drivers/iio/adc/berlin2-adc.c

340

regmap_set_bits(priv->regmap, BERLIN2_SM_CTRL,

drivers/iio/adc/cpcap-adc.c

387

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,

drivers/iio/adc/cpcap-adc.c

432

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,

drivers/iio/adc/cpcap-adc.c

437

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2, CPCAP_BIT_ASC);

drivers/iio/adc/cpcap-adc.c

599

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,

drivers/iio/adc/cpcap-adc.c

604

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,

drivers/iio/adc/cpcap-adc.c

609

error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,

drivers/iio/adc/fsl-imx25-gcq.c

120

regmap_set_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS);

drivers/iio/adc/fsl-imx25-gcq.c

273

regmap_set_bits(priv->regs, MX25_ADCQ_CR,

drivers/iio/adc/fsl-imx25-gcq.c

89

regmap_set_bits(priv->regs, MX25_ADCQ_MR,

drivers/iio/adc/intel_dc_ti_adc.c

158

ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG, DC_TI_ADC_EN);

drivers/iio/adc/intel_dc_ti_adc.c

177

ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG,

drivers/iio/adc/intel_dc_ti_adc.c

220

ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG,

drivers/iio/adc/max11410.c

288

ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER,

drivers/iio/adc/max11410.c

982

ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL,

drivers/iio/adc/max14001.c

342

ret = regmap_set_bits(st->regmap, MAX14001_REG_CFG,

drivers/iio/adc/meson_saradc.c

1068

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,

drivers/iio/adc/meson_saradc.c

553

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,

drivers/iio/adc/meson_saradc.c

556

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,

drivers/iio/adc/meson_saradc.c

559

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,

drivers/iio/adc/meson_saradc.c

570

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,

drivers/iio/adc/meson_saradc.c

589

regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY,

drivers/iio/adc/meson_saradc.c

882

regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,

drivers/iio/adc/meson_saradc.c

918

regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,

drivers/iio/adc/meson_saradc.c

921

regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,

drivers/iio/adc/meson_saradc.c

924

regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,

drivers/iio/adc/meson_saradc.c

927

regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,

drivers/iio/adc/meson_saradc.c

944

regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,

drivers/iio/adc/meson_saradc.c

946

regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,

drivers/iio/adc/mp2629_adc.c

133

ret = regmap_set_bits(info->regmap, MP2629_REG_ADC_CTRL,

drivers/iio/adc/mt6359-auxadc.c

457

regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR);

drivers/iio/adc/mt6359-auxadc.c

471

regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN);

drivers/iio/adc/mt6359-auxadc.c

472

regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN);

drivers/iio/adc/mt6359-auxadc.c

620

regmap_set_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL);

drivers/iio/adc/nct7201.c

376

err = regmap_set_bits(chip->regmap, NCT7201_REG_CONFIGURATION,

drivers/iio/adc/qcom-spmi-rradc.c

360

ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_LOG,

drivers/iio/adc/qcom-spmi-rradc.c

376

ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_CTL,

drivers/iio/adc/qcom-spmi-rradc.c

435

ret = regmap_set_bits(chip->regmap, chip->base + chan->trigger_addr,

drivers/iio/adc/qcom-spmi-rradc.c

482

ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,

drivers/iio/adc/qcom-spmi-rradc.c

489

ret = regmap_set_bits(chip->regmap,

drivers/iio/adc/qcom-spmi-rradc.c

960

ret = regmap_set_bits(chip->regmap,

drivers/iio/adc/rn5t618-adc.c

140

ret = regmap_set_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3,

drivers/iio/adc/rohm-bd79112.c

341

return regmap_set_bits(data->map, gpo_reg, bit);

drivers/iio/adc/rohm-bd79112.c

344

ret = regmap_set_bits(data->map, gpi_reg, bit);

drivers/iio/adc/rohm-bd79124.c

401

ret = regmap_set_bits(data->map, BD79124_REG_SEQ_CFG,

drivers/iio/adc/rohm-bd79124.c

450

return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG,

drivers/iio/adc/rohm-bd79124.c

522

ret = regmap_set_bits(data->map, BD79124_REG_ALERT_CH_SEL, BIT(channel));

drivers/iio/adc/rohm-bd79124.c

552

return regmap_set_bits(data->map, BD79124_REG_GEN_CFG,

drivers/iio/adc/rohm-bd79124.c

644

return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG,

drivers/iio/adc/rohm-bd79124.c

661

return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG,

drivers/iio/adc/rohm-bd79124.c

965

ret = regmap_set_bits(data->map, BD79124_REG_GEN_CFG,

drivers/iio/adc/rohm-bd79124.c

987

ret = regmap_set_bits(data->map, BD79124_REG_SEQ_CFG,

drivers/iio/adc/sc27xx_adc.c

511

ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL,

drivers/iio/adc/sc27xx_adc.c

516

ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,

drivers/iio/adc/sc27xx_adc.c

540

ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL,

drivers/iio/adc/sc27xx_adc.c

768

ret = regmap_set_bits(data->regmap, data->var_data->module_en,

drivers/iio/adc/sc27xx_adc.c

774

ret = regmap_set_bits(data->regmap, data->var_data->clk_en,

drivers/iio/adc/stm32-dfsdm-adc.c

1025

ret = regmap_set_bits(adc->dfsdm->regmap,

drivers/iio/adc/stm32-dfsdm-adc.c

1030

ret = regmap_set_bits(adc->dfsdm->regmap,

drivers/iio/adc/stm32-dfsdm-adc.c

1463

regmap_set_bits(regmap, DFSDM_ICR(adc->fl_id),

drivers/iio/addac/ad74413r.c

473

ret = regmap_set_bits(st->regmap,

drivers/iio/chemical/ens160_core.c

287

return regmap_set_bits(data->regmap, ENS160_REG_CONFIG,

drivers/iio/dac/ad3530r.c

217

return regmap_set_bits(st->regmap, st->chip_info->sw_ldac_trig_reg,

drivers/iio/dac/ad3530r.c

397

ret = regmap_set_bits(st->regmap, AD3530R_OUTPUT_CONTROL_0,

drivers/iio/dac/ad3530r.c

408

ret = regmap_set_bits(st->regmap, AD3530R_REFERENCE_CONTROL_0,

drivers/iio/dac/ad8460.c

95

ret = regmap_set_bits(state->regmap, AD8460_CTRL_REG(0x00),

drivers/iio/dac/ad9739a.c

176

ret = regmap_set_bits(st->regmap, AD9739A_REG_MODE, AD9739A_RESET_MASK);

drivers/iio/dac/ad9739a.c

257

ret = regmap_set_bits(st->regmap, AD9739A_REG_LVDS_REC_CNT1,

drivers/iio/dac/adi-axi-dac.c

126

ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,

drivers/iio/dac/adi-axi-dac.c

142

return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,

drivers/iio/dac/adi-axi-dac.c

324

return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,

drivers/iio/dac/adi-axi-dac.c

386

ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,

drivers/iio/dac/adi-axi-dac.c

427

ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,

drivers/iio/dac/adi-axi-dac.c

632

return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,

drivers/iio/dac/adi-axi-dac.c

659

return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,

drivers/iio/dac/adi-axi-dac.c

726

ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,

drivers/iio/dac/adi-axi-dac.c

968

ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,

drivers/iio/dac/ltc2664.c

639

return regmap_set_bits(st->regmap, LTC2664_CMD_CONFIG, LTC2664_REF_DISABLE);

drivers/iio/dac/ltc2688.c

856

ret = regmap_set_bits(st->regmap, LTC2688_CMD_CONFIG,

drivers/iio/dac/ltc2688.c

880

return regmap_set_bits(st->regmap, LTC2688_CMD_CONFIG,

drivers/iio/dac/max22007.c

448

ret = regmap_set_bits(st->regmap, MAX22007_CONFIG_REG,

drivers/iio/dac/stm32-dac-core.c

202

ret = regmap_set_bits(priv->common.regmap, STM32_DAC_CR,

drivers/iio/gyro/mpu3050-core.c

1000

ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,

drivers/iio/gyro/mpu3050-core.c

200

ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,

drivers/iio/gyro/mpu3050-core.c

517

ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,

drivers/iio/gyro/mpu3050-core.c

805

ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,

drivers/iio/gyro/mpu3050-core.c

899

ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,

drivers/iio/health/afe4403.c

422

ret = regmap_set_bits(afe->regmap, AFE440X_CONTROL2,

drivers/iio/health/afe4404.c

430

ret = regmap_set_bits(afe->regmap, AFE440X_CONTROL2,

drivers/iio/health/max30100.c

397

ret = regmap_set_bits(data->regmap, MAX30100_REG_MODE_CONFIG,

drivers/iio/health/max30102.c

449

ret = regmap_set_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,

drivers/iio/imu/bmi270/bmi270_core.c

1523

ret = regmap_set_bits(regmap, BMI270_INIT_CTRL_REG,

drivers/iio/imu/bmi270/bmi270_core.c

1551

ret = regmap_set_bits(regmap, BMI270_PWR_CTRL_REG,

drivers/iio/imu/bmi270/bmi270_core.c

1559

ret = regmap_set_bits(regmap, BMI270_ACC_CONF_REG,

drivers/iio/imu/bmi270/bmi270_core.c

1567

ret = regmap_set_bits(regmap, BMI270_GYR_CONF_REG,

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

269

ret = regmap_set_bits(st->map, INV_ICM42600_REG_INT_SOURCE0,

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

310

ret = regmap_set_bits(st->map, INV_ICM42600_REG_INT_SOURCE0,

drivers/iio/imu/inv_icm42600/inv_icm42600_core.c

419

return regmap_set_bits(st->map, INV_ICM42600_REG_INT_SOURCE1,

drivers/iio/imu/inv_icm42600/inv_icm42600_core.c

540

ret = regmap_set_bits(st->map, INV_ICM42600_REG_INTF_CONFIG0,

drivers/iio/imu/inv_icm45600/inv_icm45600_accel.c

708

ret = regmap_set_bits(st->map, INV_ICM45600_REG_SMC_CONTROL_0,

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

261

ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2,

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

266

ret = regmap_set_bits(st->map, INV_ICM45600_REG_INT1_CONFIG0,

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

280

ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3,

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

322

ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2,

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

556

return regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2,

drivers/iio/imu/inv_icm45600/inv_icm45600_core.c

655

return regmap_set_bits(st->map, INV_ICM45600_REG_SMC_CONTROL_0,

drivers/iio/imu/inv_icm45600/inv_icm45600_core.c

866

ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3,

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_fusion.c

51

return regmap_set_bits(hw->regmap, mux->addr, mux->mask);

drivers/iio/light/adux1020.c

531

ret = regmap_set_bits(data->regmap,

drivers/iio/light/adux1020.c

540

ret = regmap_set_bits(data->regmap, ADUX1020_REG_PROX_TYPE,

drivers/iio/light/adux1020.c

748

ret = regmap_set_bits(data->regmap, ADUX1020_REG_SW_RESET,

drivers/iio/light/bh1745.c

227

return regmap_set_bits(data->regmap, BH1745_SYS_CTRL,

drivers/iio/light/bh1745.c

234

return regmap_set_bits(data->regmap, BH1745_MODE_CTRL2,

drivers/iio/light/ltr390.c

188

ret = regmap_set_bits(data->regmap, LTR390_MAIN_CTRL, LTR390_UVS_MODE);

drivers/iio/light/ltr390.c

625

ret = regmap_set_bits(data->regmap, LTR390_INT_CFG, LTR390_LS_INT_EN);

drivers/iio/light/ltr390.c

642

return regmap_set_bits(data->regmap, LTR390_INT_CFG, LTR390_LS_INT_SEL_UVS);

drivers/iio/light/ltr390.c

821

regmap_set_bits(data->regmap, LTR390_MAIN_CTRL, LTR390_SW_RESET);

drivers/iio/light/ltr390.c

826

ret = regmap_set_bits(data->regmap, LTR390_MAIN_CTRL, LTR390_SENSOR_ENABLE);

drivers/iio/light/ltr390.c

866

return regmap_set_bits(data->regmap, LTR390_MAIN_CTRL,

drivers/iio/light/ltr390.c

883

return regmap_set_bits(data->regmap, LTR390_MAIN_CTRL, LTR390_SENSOR_ENABLE);

drivers/iio/light/ltrf216a.c

129

ret = regmap_set_bits(data->regmap,

drivers/iio/light/rohm-bu27034.c

834

return regmap_set_bits(data->regmap, BU27034_REG_MODE_CONTROL4,

drivers/iio/light/veml3235.c

84

return regmap_set_bits(data->regmap, VEML3235_REG_CONF,

drivers/iio/light/veml3328.c

111

return regmap_set_bits(data->regmap, VEML3328_REG_CONF,

drivers/iio/light/veml6030.c

242

return regmap_set_bits(data->regmap, VEML6030_REG_ALS_CONF,

drivers/iio/light/veml6046x00.c

302

ret = regmap_set_bits(data->regmap, VEML6046X00_REG_CONF0,

drivers/iio/light/veml6046x00.c

309

return regmap_set_bits(data->regmap, VEML6046X00_REG_CONF1,

drivers/iio/magnetometer/ak8974.c

329

return regmap_set_bits(ak8974->map, AK8974_CTRL3, AK8974_CTRL3_FORCE);

drivers/iio/magnetometer/ak8974.c

437

ret = regmap_set_bits(ak8974->map, AK8974_CTRL3, AK8974_CTRL3_SELFTEST);

drivers/iio/magnetometer/mmc35240.c

187

ret = regmap_set_bits(data->regmap, MMC35240_REG_CTRL0,

drivers/iio/magnetometer/mmc35240.c

198

return regmap_set_bits(data->regmap, MMC35240_REG_CTRL0, coil_bit);

drivers/iio/pressure/bmp280-core.c

2397

ret = regmap_set_bits(data->regmap, BMP580_REG_DSP_CONFIG,

drivers/iio/pressure/bmp280-core.c

2578

ret = regmap_set_bits(data->regmap, BMP580_REG_INT_SOURCE,

drivers/iio/pressure/rohm-bm1390.c

555

ret = regmap_set_bits(data->regmap, BM1390_REG_MODE_CTRL,

drivers/iio/pressure/rohm-bm1390.c

561

ret = regmap_set_bits(data->regmap, BM1390_REG_FIFO_CTRL,

drivers/iio/pressure/rohm-bm1390.c

703

return regmap_set_bits(data->regmap, BM1390_REG_MODE_CTRL,

drivers/iio/proximity/sx9324.c

844

ret = regmap_set_bits(data->regmap, SX9324_REG_STAT2,

drivers/iio/proximity/sx9360.c

680

ret = regmap_set_bits(data->regmap, SX9360_REG_STAT,

drivers/iio/proximity/sx9500.c

210

return regmap_set_bits(data->regmap, reg, bitmask);

drivers/iio/proximity/sx9500.c

781

ret = regmap_set_bits(data->regmap, SX9500_REG_PROX_CTRL0,

drivers/iio/proximity/sx_common.c

114

return regmap_set_bits(data->regmap, data->chip_info->reg_irq_msk,

drivers/iio/trigger/stm32-timer-trigger.c

166

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);

drivers/iio/trigger/stm32-timer-trigger.c

177

regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);

drivers/iio/trigger/stm32-timer-trigger.c

180

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

208

regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);

drivers/iio/trigger/stm32-timer-trigger.c

509

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

565

regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);

drivers/iio/trigger/stm32-timer-trigger.c

771

regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);

drivers/input/misc/tps65219-pwrbutton.c

126

ret = regmap_set_bits(tps->regmap, TPS65219_REG_MASK_CONFIG,

drivers/leds/flash/leds-s2m-flash.c

113

ret = regmap_set_bits(led->regmap, led->reg_enable, S2MU005_FLED_TORCH_EN(led->channel));

drivers/leds/flash/leds-s2m-flash.c

157

ret = regmap_set_bits(led->regmap, led->reg_enable, S2MU005_FLED_FLASH_EN(led->channel));

drivers/leds/flash/leds-s2m-flash.c

220

ret = regmap_set_bits(regmap, S2MU005_REG_FLED_CTRL1, S2MU005_FLED_CH_EN);

drivers/leds/leds-mt6323.c

412

ret = regmap_set_bits(regmap, regs->iwled_en_ctrl, BIT(led->id));

drivers/leds/leds-mt6323.c

416

ret = regmap_set_bits(regmap, regs->iwled_en_ctrl, BIT(led->id + 1));

drivers/leds/leds-mt6323.c

439

ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_32K_CK_PDN);

drivers/leds/leds-mt6323.c

443

ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_6M_CK_PDN);

drivers/leds/leds-mt6323.c

447

ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_1M_CK_PDN);

drivers/media/platform/nxp/imx8mq-mipi-csi2.c

218

regmap_set_bits(state->phy_gpr, CSI2SS_PLM_CTRL,

drivers/media/platform/nxp/imx8mq-mipi-csi2.c

226

regmap_set_bits(state->phy_gpr, CSI2SS_CTRL_CLK_RESET, CSI2SS_CTRL_CLK_RESET_EN);

drivers/mfd/adp5585.c

557

ret = regmap_set_bits(adp5585->regmap, ADP5589_LOCK_CFG, ADP5589_LOCK_EN);

drivers/mfd/tps65910.c

320

ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL,

drivers/mfd/tps65910.c

328

ret = regmap_set_bits(tps65910->regmap,

drivers/mfd/tps65910.c

338

ret = regmap_set_bits(tps65910->regmap,

drivers/mfd/tps65910.c

348

ret = regmap_set_bits(tps65910->regmap,

drivers/mfd/tps65910.c

510

ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL,

drivers/mfd/tps6594-core.c

722

ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,

drivers/misc/tps6594-esm.c

126

return regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,

drivers/misc/tps6594-esm.c

68

ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_MODE_CFG,

drivers/misc/tps6594-esm.c

73

ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,

drivers/misc/tps6594-pfsm.c

121

ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,

drivers/misc/tps6594-pfsm.c

130

ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,

drivers/misc/tps6594-pfsm.c

168

ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2,

drivers/misc/tps6594-pfsm.c

184

ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,

drivers/misc/tps6594-pfsm.c

207

ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,

drivers/mmc/host/dw_mmc-hi3798mv200.c

87

return regmap_set_bits(priv->crg_reg, priv->sap_dll_offset, SAP_DLL_CTRL_DLLMODE);

drivers/mmc/host/meson-mx-sdio.c

212

regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQC,

drivers/mmc/host/meson-mx-sdio.c

216

regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQS,

drivers/mmc/host/meson-mx-sdio.c

256

regmap_set_bits(host->regmap, MESON_MX_SDIO_CONF,

drivers/net/can/m_can/tcan4x5x-core.c

273

ret = regmap_set_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

1139

regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

1283

regmap_set_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

459

regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

461

regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

501

regmap_set_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

510

regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

594

regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

661

regmap_set_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);

drivers/net/dsa/lantiq/lantiq_gswip_common.c

710

regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(cpu_dp->index),

drivers/net/dsa/lantiq/lantiq_gswip_common.c

714

regmap_set_bits(priv->gswip,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

719

regmap_set_bits(priv->gswip, GSWIP_BM_QUEUE_GCTRL,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

723

regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,

drivers/net/dsa/lantiq/lantiq_gswip_common.c

727

regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

156

regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

246

ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

317

ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_TXB_CTL,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

327

ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_RXB_CTL,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

468

regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

683

return regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,

drivers/net/dsa/lantiq/mxl-gsw1xx.c

769

regmap_set_bits(priv->gpio, GPIO_ALTSEL0, 3);

drivers/net/dsa/lantiq/mxl-gsw1xx.c

770

regmap_set_bits(priv->gpio, GPIO_ALTSEL1, 3);

drivers/net/dsa/qca/qca8k-8xxx.c

1889

ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,

drivers/net/dsa/qca/qca8k-common.c

455

ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);

drivers/net/dsa/qca/qca8k-common.c

475

regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);

drivers/net/dsa/qca/qca8k-common.c

566

return regmap_set_bits(priv->regmap,

drivers/net/dsa/qca/qca8k-common.c

636

ret = regmap_set_bits(priv->regmap,

drivers/net/ethernet/airoha/airoha_npu.c

323

regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK);

drivers/net/ethernet/airoha/airoha_npu.c

591

regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q));

drivers/net/ethernet/mediatek/mtk_star_emac.c

1212

regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG,

drivers/net/ethernet/mediatek/mtk_star_emac.c

527

regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,

drivers/net/ethernet/mediatek/mtk_star_emac.c

529

regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,

drivers/net/ethernet/mediatek/mtk_star_emac.c

554

regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,

drivers/net/ethernet/mediatek/mtk_star_emac.c

560

regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,

drivers/net/ethernet/mediatek/mtk_star_emac.c

864

regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,

drivers/net/ethernet/mediatek/mtk_star_emac.c

866

regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1,

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1210

ret = regmap_set_bits(ppe_dev->regmap, reg, PPE_MC_MTU_CTRL_TBL_TX_CNT_EN);

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1216

return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN);

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1425

return regmap_set_bits(ppe_dev->regmap, reg, PPE_BM_PORT_FC_MODE_EN);

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1576

ret = regmap_set_bits(ppe_dev->regmap, PPE_EG_BRIDGE_CONFIG_ADDR,

drivers/net/ethernet/spacemit/k1_emac.c

197

regmap_set_bits(priv->regmap_apmu,

drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

82

ret = regmap_set_bits(dwc->eic7700_hsp_regmap,

drivers/net/pcs/pcs-mtk-lynxi.c

205

regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,

drivers/net/pcs/pcs-mtk-lynxi.c

209

regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,

drivers/net/pcs/pcs-mtk-lynxi.c

265

regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);

drivers/net/wan/framer/pef2256/pef2256.c

75

regmap_set_bits(pef2256->regmap, offset, set);

drivers/pci/controller/dwc/pci-imx6.c

1528

regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF);

drivers/pci/controller/dwc/pci-imx6.c

284

regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,

drivers/pci/controller/dwc/pci-imx6.c

684

regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,

drivers/pci/controller/dwc/pci-imx6.c

805

regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,

drivers/pci/controller/dwc/pci-imx6.c

820

regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,

drivers/pci/controller/dwc/pci-imx6.c

838

regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,

drivers/pci/controller/dwc/pci-imx6.c

913

regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,

drivers/pci/controller/dwc/pcie-spacemit-k1.c

157

regmap_set_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST);

drivers/pci/controller/dwc/pcie-spacemit-k1.c

165

regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET);

drivers/pci/controller/dwc/pcie-spacemit-k1.c

189

regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,

drivers/pci/controller/dwc/pcie-spacemit-k1.c

308

regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,

drivers/pci/controller/dwc/pcie-spacemit-k1.c

72

regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET);

drivers/phy/amlogic/phy-meson8b-usb2.c

167

regmap_set_bits(priv->regmap, REG_CONFIG, REG_CONFIG_CLK_32k_ALTSEL);

drivers/phy/amlogic/phy-meson8b-usb2.c

176

regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET);

drivers/phy/amlogic/phy-meson8b-usb2.c

181

regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT);

drivers/phy/amlogic/phy-meson8b-usb2.c

188

regmap_set_bits(priv->regmap, REG_ADP_BC,

drivers/phy/amlogic/phy-meson8b-usb2.c

212

regmap_set_bits(priv->regmap, REG_DBG_UART,

drivers/phy/amlogic/phy-meson8b-usb2.c

220

regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

224

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

226

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

228

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

232

regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

234

regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

237

regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

239

regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

252

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

256

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

260

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

292

regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

294

regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

296

regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

297

regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

339

regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

340

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

342

regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

240

regmap_set_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

276

regmap_set_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);

drivers/phy/sophgo/phy-cv1800-usb2.c

58

regmap_set_bits(phy->syscon, REG_USB_PHY_CTRL, PHY_VBUS_POWER);

drivers/phy/ti/phy-da8xx-usb.c

136

regmap_set_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);

drivers/pinctrl/airoha/pinctrl-airoha.c

2404

regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask);

drivers/pinctrl/pinctrl-ingenic.c

3834

regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +

drivers/platform/x86/uniwill/uniwill-acpi.c

1847

ret = regmap_set_bits(data->regmap, EC_ADDR_AP_OEM, ENABLE_MANUAL_CTRL);

drivers/platform/x86/uniwill/uniwill-acpi.c

2060

return regmap_set_bits(data->regmap, EC_ADDR_CTGP_DB_CTRL,

drivers/platform/x86/uniwill/uniwill-acpi.c

973

ret = regmap_set_bits(data->regmap, EC_ADDR_CTGP_DB_CTRL,

drivers/pmdomain/imx/imx8m-blk-ctrl.c

124

regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

134

regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

140

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

142

regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

446

regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

457

regmap_set_bits(bc->regmap, 0x8, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

458

regmap_set_bits(bc->regmap, 0xc, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

459

regmap_set_bits(bc->regmap, 0x10, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

460

regmap_set_bits(bc->regmap, 0x14, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

550

regmap_set_bits(bc->regmap, 0x8, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

551

regmap_set_bits(bc->regmap, 0xc, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

552

regmap_set_bits(bc->regmap, 0x10, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

553

regmap_set_bits(bc->regmap, 0x14, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

576

regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

577

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

646

regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

647

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

725

regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

726

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

741

regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL,

drivers/pmdomain/imx/imx8m-blk-ctrl.c

745

regmap_set_bits(bc->regmap, ISI_CACHE_CTRL,

drivers/pmdomain/imx/imx8m-blk-ctrl.c

871

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

872

regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));

drivers/pmdomain/imx/imx8m-blk-ctrl.c

883

regmap_set_bits(bc->regmap, 0x8, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

884

regmap_set_bits(bc->regmap, 0xc, 0xffffffff);

drivers/pmdomain/imx/imx8m-blk-ctrl.c

885

regmap_set_bits(bc->regmap, 0x10, 0xffffffff);

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

181

regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

184

regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

187

regmap_set_bits(bc->regmap, GPR_REG0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

232

regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

245

regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

314

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

315

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

318

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

321

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

322

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

324

regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

328

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

329

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

332

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

333

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

336

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

337

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

340

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

342

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

345

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

347

regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

350

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

351

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

352

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

356

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

357

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

403

regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

435

regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

437

regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));

drivers/pmdomain/imx/imx93-blk-ctrl.c

166

regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

drivers/pmdomain/imx/imx93-blk-ctrl.c

189

regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);

drivers/pmdomain/marvell/pxa1908-power-controller.c

122

return regmap_set_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK);

drivers/pmdomain/marvell/pxa1908-power-controller.c

138

return regmap_set_bits(ctrl->base, APMU_AUDIO_CLK, AUDIO_ULCX_ENABLE);

drivers/pmdomain/marvell/pxa1908-power-controller.c

82

regmap_set_bits(ctrl->base, data->reg_clk_res_ctrl, data->hw_mode);

drivers/pmdomain/marvell/pxa1908-power-controller.c

85

regmap_set_bits(ctrl->base, APMU_PWR_CTRL_REG, data->pwr_state);

drivers/pmdomain/mediatek/mtk-pm-domains.c

145

regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);

drivers/pmdomain/mediatek/mtk-pm-domains.c

160

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

175

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

184

regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);

drivers/pmdomain/mediatek/mtk-pm-domains.c

245

regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);

drivers/pmdomain/mediatek/mtk-pm-domains.c

480

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

481

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

490

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS);

drivers/pmdomain/mediatek/mtk-pm-domains.c

499

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

534

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS);

drivers/pmdomain/mediatek/mtk-pm-domains.c

536

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE);

drivers/pmdomain/mediatek/mtk-pm-domains.c

542

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE);

drivers/pmdomain/mediatek/mtk-pm-domains.c

546

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS);

drivers/pmdomain/mediatek/mtk-pm-domains.c

548

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE);

drivers/pmdomain/mediatek/mtk-pm-domains.c

565

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS);

drivers/pmdomain/mediatek/mtk-pm-domains.c

566

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE);

drivers/pmdomain/mediatek/mtk-pm-domains.c

569

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE_FLAG);

drivers/pmdomain/mediatek/mtk-pm-domains.c

572

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS);

drivers/pmdomain/mediatek/mtk-pm-domains.c

573

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE);

drivers/pmdomain/mediatek/mtk-pm-domains.c

582

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

588

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

601

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

603

regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);

drivers/pmdomain/mediatek/mtk-pm-domains.c

718

regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs,

drivers/power/reset/spacemit-p1-reboot.c

22

ret = regmap_set_bits(regmap, PWR_CTRL2, PWR_CTRL2_SHUTDOWN);

drivers/power/reset/spacemit-p1-reboot.c

37

ret = regmap_set_bits(regmap, PWR_CTRL2, PWR_CTRL2_RST);

drivers/power/supply/bd71828-power.c

432

ret = regmap_set_bits(pwr->regmap,

drivers/power/supply/max1720x_battery.c

349

ret = regmap_set_bits(info->regmap, MAX172XX_STATUS,

drivers/power/supply/s2m-charger.c

116

ret = regmap_set_bits(priv->regmap, S2MU005_REG_CHGR_CTRL4,

drivers/power/supply/smb347-charger.c

1428

ret = regmap_set_bits(smb->regmap, CMD_A, CMD_A_OTG_ENABLED);

drivers/power/supply/smb347-charger.c

751

ret = regmap_set_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CTRL);

drivers/pwm/pwm-adp5585.c

116

return regmap_set_bits(regmap, info->pwm_cfg, ADP5585_PWM_EN);

drivers/pwm/pwm-airoha.c

416

return regmap_set_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,

drivers/pwm/pwm-airoha.c

445

return regmap_set_bits(pc->regmap, addr, AIROHA_PWM_GPIO_FLASH_EN << shift);

drivers/pwm/pwm-axi-pwmgen.c

242

ret = regmap_set_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN);

drivers/pwm/pwm-fsl-ftm.c

315

regmap_set_bits(fpc->regmap, FTM_OUTMASK,

drivers/pwm/pwm-fsl-ftm.c

67

regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);

drivers/pwm/pwm-fsl-ftm.c

72

regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);

drivers/pwm/pwm-fsl-ftm.c

94

regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));

drivers/pwm/pwm-iqs620a.c

63

return regmap_set_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,

drivers/pwm/pwm-jz4740.c

186

regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),

drivers/pwm/pwm-jz4740.c

206

regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),

drivers/pwm/pwm-jz4740.c

92

regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);

drivers/pwm/pwm-stm32-lp.c

278

ret = regmap_set_bits(priv->regmap, STM32_LPTIM_CR,

drivers/pwm/pwm-stm32.c

333

ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);

drivers/pwm/pwm-stm32.c

361

ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);

drivers/pwm/pwm-stm32.c

376

regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);

drivers/pwm/pwm-stm32.c

379

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

467

regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);

drivers/pwm/pwm-stm32.c

468

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

474

regmap_set_bits(priv->regmap, TIM_CCER, ccen);

drivers/pwm/pwm-stm32.c

774

regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);

drivers/pwm/pwm-stm32.c

810

regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);

drivers/regulator/bd718x7-regulator.c

204

ret = regmap_set_bits(rdev->regmap,

drivers/regulator/bd718x7-regulator.c

478

return regmap_set_bits(rdev->regmap, BD718XX_REG_MVRFLTMASK2,

drivers/regulator/bd718x7-regulator.c

540

return regmap_set_bits(rdev->regmap, reg, bit);

drivers/regulator/bd718x7-regulator.c

561

return regmap_set_bits(rdev->regmap, reg, bit);

drivers/regulator/bd96801-regulator.c

503

ret = regmap_set_bits(regmap,

drivers/regulator/da9063-regulator.c

471

ret = regmap_set_bits(regl->hw->regmap, DA9063_REG_CONFIG_H,

drivers/regulator/max77857-regulator.c

148

return regmap_set_bits(rdev->regmap, reg, val);

drivers/regulator/max77857-regulator.c

205

return regmap_set_bits(rdev->regmap, MAX77859_REG_CONT3,

drivers/regulator/mt6316-regulator.c

193

ret = regmap_set_bits(regmap, info->modeset_reg, info->modeset_mask);

drivers/regulator/mt6316-regulator.c

214

ret = regmap_set_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);

drivers/regulator/mt6363-regulator.c

405

ret = regmap_set_bits(regmap, info->modeset_reg, info->modeset_mask);

drivers/regulator/mt6363-regulator.c

434

ret = regmap_set_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);

drivers/regulator/rt8092.c

163

return regmap_set_bits(regmap, enable_reg, RT8092_VOUTEN_MASK);

drivers/regulator/rtq2208-regulator.c

181

return regmap_set_bits(rdev->regmap, rdesc->suspend_config_reg, rdesc->suspend_enable_mask);

drivers/regulator/tps65219-regulator.c

169

return regmap_set_bits(tps->regmap, TPS65219_REG_STBY_1_CONFIG,

drivers/regulator/tps65910-regulator.c

1100

err = regmap_set_bits(pmic->mfd->regmap, TPS65910_DEVCTRL,

drivers/regulator/tps65910-regulator.c

405

return regmap_set_bits(regmap, reg,

drivers/regulator/tps65910-regulator.c

854

ret = regmap_set_bits(mfd->regmap,

drivers/regulator/tps65910-regulator.c

867

ret = regmap_set_bits(mfd->regmap,

drivers/regulator/tps65910-regulator.c

882

ret = regmap_set_bits(mfd->regmap,

drivers/regulator/tps65910-regulator.c

949

ret = regmap_set_bits(mfd->regmap,

drivers/remoteproc/imx_rproc.c

480

ret = regmap_set_bits(priv->gpr, dcfg->gpr_reg, dcfg->gpr_wait);

drivers/remoteproc/qcom_q6v5_mss.c

444

regmap_set_bits(qproc->conn_map, qproc->ext_bhs, EXTERNAL_BHS_ON);

drivers/reset/reset-eic7700.c

358

return regmap_set_bits(data->regmap, eic7700_reset[id].reg,

drivers/reset/reset-eic7700.c

414

regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,

drivers/reset/reset-mpfs.c

51

return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));

drivers/rtc/rtc-max31335.c

530

return regmap_set_bits(max31335->regmap, max31335->chip->clkout_reg,

drivers/rtc/rtc-pcf2127.c

1295

ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout,

drivers/rtc/rtc-pcf8563.c

496

err = regmap_set_bits(pcf8563->regmap, PCF8563_REG_TMRC,

drivers/rtc/rtc-rx8010.c

144

err = regmap_set_bits(rx8010->regs, RX8010_CTRL, RX8010_CTRL_STOP);

drivers/rtc/rtc-s5m.c

282

ret = regmap_set_bits(info->regmap, info->regs->udr_update,

drivers/rtc/rtc-s5m.c

339

ret = regmap_set_bits(info->regmap, info->regs->udr_update,

drivers/rtc/rtc-s5m.c

657

ret = regmap_set_bits(info->regmap, S2MPG10_RTC_WTSR,

drivers/rtc/rtc-spacemit-p1.c

117

return regmap_set_bits(regmap, RTC_CTRL, RTC_EN);

drivers/rtc/rtc-tps6594.c

145

return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,

drivers/rtc/rtc-tps6594.c

233

return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,

drivers/rtc/rtc-tps6594.c

376

ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_2,

drivers/rtc/rtc-tps6594.c

387

ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,

drivers/rtc/rtc-tps6594.c

79

return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,

drivers/soc/aspeed/aspeed-lpc-snoop.c

251

regmap_set_bits(lpc_snoop->regmap, HICR5, cfg->hicr5_en);

drivers/soc/aspeed/aspeed-lpc-snoop.c

257

regmap_set_bits(lpc_snoop->regmap, HICRB, cfg->hicrb_en);

drivers/soc/mediatek/mtk-infracfg.c

89

regmap_set_bits(infracfg, MT8192_INFRA_CTRL,

drivers/soc/qcom/ramp_controller.c

108

ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce);

drivers/soc/qcom/ramp_controller.c

113

ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN);

drivers/soc/qcom/ramp_controller.c

82

ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN);

drivers/spi/spi-airoha-snfi.c

699

err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,

drivers/spi/spi-airoha-snfi.c

888

err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,

drivers/spi/spi-ingenic.c

313

regmap_set_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);

drivers/spi/spi-ingenic.c

93

regmap_set_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);

drivers/spi/spi-ingenic.c

96

regmap_set_bits(priv->map, REG_SSICR0,

drivers/thermal/qoriq_thermal.c

396

ret = regmap_set_bits(data->regmap, REGS_TMR, TMR_CMD);

drivers/usb/phy/phy-tegra-usb.c

1220

err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);

drivers/usb/typec/mux/wcd939x-usbss.c

306

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_MG1_BIAS,

drivers/usb/typec/mux/wcd939x-usbss.c

312

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_MG2_BIAS,

drivers/usb/typec/mux/wcd939x-usbss.c

396

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE,

drivers/usb/typec/mux/wcd939x-usbss.c

408

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SELECT1,

drivers/usb/typec/mux/wcd939x-usbss.c

414

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE,

drivers/usb/typec/mux/wcd939x-usbss.c

420

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE,

drivers/usb/typec/mux/wcd939x-usbss.c

467

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_EQUALIZER1,

drivers/usb/typec/mux/wcd939x-usbss.c

485

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE,

drivers/usb/typec/mux/wcd939x-usbss.c

502

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_DISP_AUXP_THRESH,

drivers/usb/typec/mux/wcd939x-usbss.c

523

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE,

drivers/usb/typec/mux/wcd939x-usbss.c

658

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_DP_DN_MISC1,

drivers/usb/typec/mux/wcd939x-usbss.c

665

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_MG1_MISC,

drivers/usb/typec/mux/wcd939x-usbss.c

671

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_MG2_MISC,

drivers/usb/typec/mux/wcd939x-usbss.c

677

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_CPLDO_CTL2, 0xff);

drivers/usb/typec/mux/wcd939x-usbss.c

687

ret = regmap_set_bits(usbss->regmap, WCD_USBSS_USB_SS_CNTL,

include/linux/regmap.h

1439

return regmap_set_bits(map, reg, bits);

sound/hda/codecs/side-codecs/cs35l41_hda.c

637

regmap_set_bits(regmap, CS35L41_PROTECT_REL_ERR_IGN, mask);

sound/hda/codecs/side-codecs/cs35l56_hda.c

77

regmap_set_bits(cs35l56->base.regmap, CS35L56_ASP1_ENABLES1,

sound/soc/codecs/cs35l45.c

1022

regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);

sound/soc/codecs/cs35l45.c

132

regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL,

sound/soc/codecs/cs35l45.c

258

regmap_set_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES,

sound/soc/codecs/cs35l45.c

287

regmap_set_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES,

sound/soc/codecs/cs35l45.c

628

regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);

sound/soc/codecs/cs35l45.c

634

regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);

sound/soc/codecs/cs35l45.c

925

regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,

sound/soc/codecs/cs35l45.c

931

regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,

sound/soc/codecs/cs35l45.c

941

regmap_set_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2, CS35L45_DSP_VIRT2_MBOX_MASK);

sound/soc/codecs/cs35l56-shared.c

1130

regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG,

sound/soc/codecs/cs35l56-shared.c

1134

regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG,

sound/soc/codecs/cs35l56.c

2120

ret = regmap_set_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3,

sound/soc/codecs/cs42l42-sdw.c

146

regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);