arch/mips/include/asm/sn/sn0/hubio.h

203

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

445

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

467

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

514

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

556

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

672

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

709

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

824

u64 reg_value;

arch/mips/include/asm/sn/sn0/hubio.h

839

#define iprb_regval reg_value

arch/mips/pci/pci-mt7620.c

111

unsigned long reg_value = 0x0, retry = 0;

arch/mips/pci/pci-mt7620.c

114

reg_value = pcie_r32(PCIEPHY0_CFG);

arch/mips/pci/pci-mt7620.c

116

if (reg_value & BUSY)

arch/powerpc/platforms/pseries/rtas-fadump.c

340

be64_to_cpu(reg_entry->reg_value));

arch/powerpc/platforms/pseries/rtas-fadump.c

407

cpu = (be64_to_cpu(reg_entry->reg_value) &

arch/powerpc/platforms/pseries/rtas-fadump.h

107

__be64 reg_value;

drivers/accel/habanalabs/gaudi/gaudi.c

8831

struct hl_sync_to_engine_map *map, u32 reg_value,

drivers/accel/habanalabs/gaudi/gaudi.c

8840

if (reg_value == 0 || reg_value == 0xffffffff)

drivers/accel/habanalabs/gaudi/gaudi.c

8842

reg_value -= lower_32_bits(CFG_BASE);

drivers/accel/habanalabs/gaudi/gaudi.c

8850

entry->sync_id = reg_value;

drivers/accel/habanalabs/gaudi/gaudi.c

8851

hash_add(map->tb, &entry->node, reg_value);

drivers/accel/habanalabs/gaudi/gaudi.c

8861

u32 reg_value;

drivers/accel/habanalabs/gaudi/gaudi.c

8866

reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

8869

rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,

drivers/accel/habanalabs/gaudi/gaudi.c

8879

reg_value = RREG32(sds->props[SP_MME_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

8884

map, reg_value, ENGINE_MME,

drivers/accel/habanalabs/gaudi/gaudi.c

8893

reg_value = RREG32(sds->props[SP_DMA_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

8895

rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,

drivers/ata/ahci_imx.c

678

u32 reg_value;

drivers/ata/ahci_imx.c

683

const struct reg_value *values;

drivers/ata/ahci_imx.c

689

static const struct reg_value gpr13_tx_level[] = {

drivers/ata/ahci_imx.c

724

static const struct reg_value gpr13_tx_boost[] = {

drivers/ata/ahci_imx.c

743

static const struct reg_value gpr13_tx_atten[] = {

drivers/ata/ahci_imx.c

752

static const struct reg_value gpr13_rx_eq[] = {

drivers/ata/ahci_imx.c

795

u32 reg_value = 0;

drivers/ata/ahci_imx.c

803

reg_value |= prop->set_value;

drivers/ata/ahci_imx.c

805

reg_value |= prop->def_value;

drivers/ata/ahci_imx.c

812

reg_value |= prop->def_value;

drivers/ata/ahci_imx.c

819

prop->name, of_val, prop->values[j].reg_value);

drivers/ata/ahci_imx.c

820

reg_value |= prop->values[j].reg_value;

drivers/ata/ahci_imx.c

828

reg_value |= prop->def_value;

drivers/ata/ahci_imx.c

832

return reg_value;

drivers/ata/ahci_imx.c

887

u32 reg_value;

drivers/ata/ahci_imx.c

897

reg_value = imx_ahci_parse_props(dev, gpr13_props,

drivers/ata/ahci_imx.c

904

reg_value;

drivers/clk/clk-axi-clkgen.c

509

unsigned int tech, family, speed_grade, reg_value;

drivers/clk/clk-axi-clkgen.c

511

axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, &reg_value);

drivers/clk/clk-axi-clkgen.c

512

tech = ADI_AXI_INFO_FPGA_TECH(reg_value);

drivers/clk/clk-axi-clkgen.c

513

family = ADI_AXI_INFO_FPGA_FAMILY(reg_value);

drivers/clk/clk-axi-clkgen.c

514

speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value);

drivers/clk/clk-axi-clkgen.c

529

&reg_value);

drivers/clk/clk-axi-clkgen.c

530

if (ADI_CLKGEN_INFO_FPGA_VOLTAGE(reg_value) < 950) {

drivers/clk/clk-max9485.c

101

mask, value, drvdata->reg_value);

drivers/clk/clk-max9485.c

104

&drvdata->reg_value,

drivers/clk/clk-max9485.c

105

sizeof(drvdata->reg_value));

drivers/clk/clk-max9485.c

144

entry->reg_value);

drivers/clk/clk-max9485.c

152

u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;

drivers/clk/clk-max9485.c

156

if (val == entry->reg_value)

drivers/clk/clk-max9485.c

297

ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,

drivers/clk/clk-max9485.c

298

sizeof(drvdata->reg_value));

drivers/clk/clk-max9485.c

358

ret = i2c_master_send(client, &drvdata->reg_value,

drivers/clk/clk-max9485.c

359

sizeof(drvdata->reg_value));

drivers/clk/clk-max9485.c

36

u8 reg_value;

drivers/clk/clk-max9485.c

80

u8 reg_value;

drivers/clk/clk-max9485.c

96

drvdata->reg_value &= ~mask;

drivers/clk/clk-max9485.c

97

drvdata->reg_value |= value;

drivers/clk/sophgo/clk-sg2042-pll.c

100

ctrl->fbdiv = FIELD_GET(PLLCTRL_FBDIV_MASK, reg_value);

drivers/clk/sophgo/clk-sg2042-pll.c

101

ctrl->refdiv = FIELD_GET(PLLCTRL_REFDIV_MASK, reg_value);

drivers/clk/sophgo/clk-sg2042-pll.c

102

ctrl->postdiv1 = FIELD_GET(PLLCTRL_POSTDIV1_MASK, reg_value);

drivers/clk/sophgo/clk-sg2042-pll.c

103

ctrl->postdiv2 = FIELD_GET(PLLCTRL_POSTDIV2_MASK, reg_value);

drivers/clk/sophgo/clk-sg2042-pll.c

148

static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,

drivers/clk/sophgo/clk-sg2042-pll.c

154

sg2042_pll_ctrl_decode(reg_value, &ctrl_table);

drivers/clk/sophgo/clk-sg2042-pll.c

97

static inline void sg2042_pll_ctrl_decode(unsigned int reg_value,

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

569

unsigned long reg_value, val;

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

586

reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

591

reg_value &= ~(DMA_APB_HS_SEL_MASK <<

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

593

reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

594

lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

517

op_input.write_reg.reg_value = val;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

347

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1295

cmd->cmd.cmd_setup_reg_prog.reg_value = value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4697

ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4725

ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4753

ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7069

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7083

reg_value =

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7085

if (reg_value)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7088

j, k, reg_value,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

871

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

886

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

888

if (reg_value)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

891

j, k, reg_value, &sec_count,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

979

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

990

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

992

if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

993

REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

994

REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

999

j, reg_value);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1718

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1726

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1729

if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1730

REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1731

REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1733

j, reg_value);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1736

reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1738

WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

384

ib->ptr[ib->length_dw++] = init_regs[i].reg_value;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

815

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

819

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

820

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

823

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

824

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

824

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

828

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

829

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

832

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

833

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1347

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1351

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1352

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1355

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1356

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

967

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

971

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

972

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

975

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

976

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

620

misc_pkt.write_reg.reg_value = input->write_reg.reg_value;

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

661

misc_pkt.write_reg.reg_value = input->write_reg.reg_value;

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

550

misc_pkt.write_reg.reg_value = input->write_reg.reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

800

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

806

reg_value =

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

808

if (reg_value)

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

811

reg_value, &sec_count, &ded_count);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1274

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1280

reg_value =

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1282

if (reg_value)

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1284

reg_value, &sec_count, &ded_count);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1314

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1320

reg_value =

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1322

if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1323

REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1324

REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1326

i, reg_value);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1334

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1340

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1342

reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1345

reg_value);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1635

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1641

reg_value =

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1643

if (reg_value)

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1645

reg_value, &sec_count, &ded_count);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1677

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1683

reg_value =

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1685

if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1686

REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1687

REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1692

i, reg_value);

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

103

direct_wt->reg_value = value;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

73

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

94

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

257

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

278

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

287

direct_wt->reg_value = value;

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

107

direct_wt.reg_value = value; \

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

68

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

89

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

101

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

119

direct_wt.reg_value = value; \

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

80

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

100

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

118

direct_wt.reg_value = value; \

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

79

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

334

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2671

uint32_t reg_value = 0;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2673

reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2675

if (reg_value)

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2676

sdma_v4_0_get_ras_error_count(reg_value,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

201

uint32_t reg_value = 0;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

205

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

207

if (reg_value)

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

208

sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

212

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

214

if (reg_value)

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

215

sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,

drivers/gpu/drm/amd/amdgpu/soc15.h

65

uint32_t reg_value;

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

64

uint64_t reg_value;

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

75

reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

76

if (reg_value)

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

77

dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

82

reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

83

if (reg_value)

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

84

dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

89

reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

90

if (reg_value)

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

91

dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

2159

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

2163

reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

2164

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2265

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2269

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2270

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2094

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2098

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2099

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1680

uint32_t poison_stat = 0, reg_value = 0;

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1684

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1685

poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);

drivers/gpu/drm/amd/display/dc/basics/conversion.c

100

matrix[i] = (uint16_t)reg_value;

drivers/gpu/drm/amd/display/dc/basics/conversion.c

91

uint32_t reg_value =

drivers/gpu/drm/amd/display/dc/dm_services.h

103

uint32_t reg_value,

drivers/gpu/drm/amd/display/dc/dm_services.h

109

return (reg_value & ~mask) | (mask & (value << shift));

drivers/gpu/drm/amd/display/dc/dm_services.h

112

#define set_reg_field_value(reg_value, value, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

113

(reg_value) = set_reg_field_value_ex(\

drivers/gpu/drm/amd/display/dc/dm_services.h

114

(reg_value),\

drivers/gpu/drm/amd/display/dc/dm_services.h

165

#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

167

(reg_value),\

drivers/gpu/drm/amd/display/dc/dm_services.h

171

#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

172

(reg_value) = set_reg_field_value_ex(\

drivers/gpu/drm/amd/display/dc/dm_services.h

173

(reg_value),\

drivers/gpu/drm/amd/display/dc/dm_services.h

89

uint32_t reg_value,

drivers/gpu/drm/amd/display/dc/dm_services.h

93

return (mask & reg_value) >> shift;

drivers/gpu/drm/amd/display/dc/dm_services.h

96

#define get_reg_field_value(reg_value, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

98

(reg_value),\

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

196

uint32_t reg_value = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

214

reg_value = 1;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

217

REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, reg_value);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2392

value = lookup_table_index_ptr->reg_value;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2403

value = lookup_table_index_ptr->reg_value;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

13

const uint32_t reg_value;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

66

static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

69

return (mask & reg_value) >> shift;

drivers/gpu/drm/amd/include/mes_v11_api_def.h

591

uint32_t reg_value;

drivers/gpu/drm/amd/include/mes_v12_api_def.h

749

uint32_t reg_value;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1294

uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1296

(reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1930

u32 reg_value;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1931

reg_value = REG_READ(DSPCLK_GATE_D);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1933

reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |

drivers/gpu/drm/gma500/cdv_intel_dp.c

1940

REG_WRITE(DSPCLK_GATE_D, reg_value);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

50

#define dp_field_modify(reg_value, mask, val) \

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

52

(reg_value) &= ~(mask); \

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

53

(reg_value) |= FIELD_PREP(mask, val); \

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

61

u32 reg_value = readl(addr); \

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

62

dp_field_modify(reg_value, mask, val); \

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

63

writel(reg_value, addr); \

drivers/gpu/drm/i915/i915_hwmon.c

105

u32 reg_value;

drivers/gpu/drm/i915/i915_hwmon.c

108

reg_value = intel_uncore_read(uncore, rgadr);

drivers/gpu/drm/i915/i915_hwmon.c

110

reg_value = REG_FIELD_GET(field_msk, reg_value);

drivers/gpu/drm/i915/i915_hwmon.c

112

return mul_u64_u32_shr(reg_value, scale_factor, nshift);

drivers/gpu/drm/i915/i915_hwmon.c

365

u32 reg_value;

drivers/gpu/drm/i915/i915_hwmon.c

370

reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status);

drivers/gpu/drm/i915/i915_hwmon.c

372

*val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);

drivers/gpu/drm/i915/intel_uncore.c

2735

u32 reg_value = 0;

drivers/gpu/drm/i915/intel_uncore.c

2736

#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)

drivers/gpu/drm/i915/intel_uncore.c

2751

*out_value = reg_value;

drivers/gpu/drm/i915/intel_uncore.c

2786

u32 reg_value;

drivers/gpu/drm/i915/intel_uncore.c

2796

fast_timeout_us, 0, &reg_value);

drivers/gpu/drm/i915/intel_uncore.c

2802

ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,

drivers/gpu/drm/i915/intel_uncore.c

2804

(reg_value & mask) == value,

drivers/gpu/drm/i915/intel_uncore.c

2808

trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);

drivers/gpu/drm/i915/intel_uncore.c

2811

*out_value = reg_value;

drivers/gpu/drm/i915/vlv_suspend.c

285

u32 reg_value;

drivers/gpu/drm/i915/vlv_suspend.c

295

ret = wait_for(((reg_value =

drivers/gpu/drm/i915/vlv_suspend.c

300

trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);

drivers/gpu/drm/imagination/pvr_device.h

625

pvr_cr_poll_reg32(struct pvr_device *pvr_dev, u32 reg_addr, u32 reg_value,

drivers/gpu/drm/imagination/pvr_device.h

631

(value & reg_mask) == reg_value, 0, timeout_usec);

drivers/gpu/drm/imagination/pvr_device.h

648

pvr_cr_poll_reg64(struct pvr_device *pvr_dev, u32 reg_addr, u64 reg_value,

drivers/gpu/drm/imagination/pvr_device.h

654

(value & reg_mask) == reg_value, 0, timeout_usec);

drivers/gpu/drm/imagination/pvr_fw_startstop.c

212

u32 reg_value;

drivers/gpu/drm/imagination/pvr_fw_startstop.c

294

err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, &reg_value);

drivers/gpu/drm/imagination/pvr_fw_startstop.c

303

if (reg_value)

drivers/gpu/drm/xe/xe_eu_stall.c

660

u32 write_ptr_reg, write_ptr, read_ptr_reg, reg_value;

drivers/gpu/drm/xe/xe_eu_stall.c

698

reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,

drivers/gpu/drm/xe/xe_eu_stall.c

702

xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, reg_value);

drivers/gpu/drm/xe/xe_eu_stall.c

705

reg_value = xe_bo_ggtt_addr(stream->bo);

drivers/gpu/drm/xe/xe_eu_stall.c

706

reg_value |= REG_FIELD_PREP(XEHPC_EUSTALL_BASE_XECORE_BUF_SZ,

drivers/gpu/drm/xe/xe_eu_stall.c

708

reg_value |= XEHPC_EUSTALL_BASE_ENABLE_SAMPLING;

drivers/gpu/drm/xe/xe_eu_stall.c

709

xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

140

u32 id = 0, reg_value;

drivers/gpu/drm/xe/xe_survivability_mode.c

144

reg_value = info[CAPABILITY_INFO];

drivers/gpu/drm/xe/xe_survivability_mode.c

146

survivability->version = REG_FIELD_GET(BREADCRUMB_VERSION, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

149

survivability->fdo_mode = REG_FIELD_GET(FDO_MODE, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

151

if (reg_value & HISTORY_TRACKING) {

drivers/gpu/drm/xe/xe_survivability_mode.c

154

if (reg_value & OVERFLOW_SUPPORT)

drivers/gpu/drm/xe/xe_survivability_mode.c

159

if (reg_value & AUXINFO_SUPPORT) {

drivers/gpu/drm/xe/xe_survivability_mode.c

160

for (id = REG_FIELD_GET(AUXINFO_REG_OFFSET, reg_value);

drivers/hv/hv_kvp.c

131

kvp_register(int reg_value)

drivers/hv/hv_kvp.c

141

kvp_msg->kvp_hdr.operation = reg_value;

drivers/hwmon/aspeed-pwm-tacho.c

394

u32 reg_value = ((div_high << type_params[type].h_value) |

drivers/hwmon/aspeed-pwm-tacho.c

399

type_params[type].clk_ctrl_mask, reg_value);

drivers/hwmon/aspeed-pwm-tacho.c

413

u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;

drivers/hwmon/aspeed-pwm-tacho.c

415

reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;

drivers/hwmon/aspeed-pwm-tacho.c

418

pwm_port_params[pwm_port].type_mask, reg_value);

drivers/hwmon/aspeed-pwm-tacho.c

425

u32 reg_value = (rising <<

drivers/hwmon/aspeed-pwm-tacho.c

427

reg_value |= (falling <<

drivers/hwmon/aspeed-pwm-tacho.c

432

reg_value);

drivers/hwmon/aspeed-pwm-tacho.c

446

u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |

drivers/hwmon/aspeed-pwm-tacho.c

451

TYPE_CTRL_FAN_MASK, reg_value);

drivers/hwtracing/coresight/coresight-cti-core.c

344

u32 reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

375

reg_value = direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] :

drivers/hwtracing/coresight/coresight-cti-core.c

378

reg_value |= chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

380

reg_value &= ~chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

384

config->ctiinen[trigger_idx] = reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

386

config->ctiouten[trigger_idx] = reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

390

cti_write_single_reg(drvdata, reg_offset, reg_value);

drivers/hwtracing/coresight/coresight-cti-core.c

401

u32 reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

410

reg_value = config->ctigate;

drivers/hwtracing/coresight/coresight-cti-core.c

413

reg_value |= chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

417

reg_value &= ~chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

425

config->ctigate = reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

427

cti_write_single_reg(drvdata, CTIGATE, reg_value);

drivers/hwtracing/coresight/coresight-cti-core.c

439

u32 reg_value;

drivers/hwtracing/coresight/coresight-cti-core.c

449

reg_value = config->ctiappset;

drivers/hwtracing/coresight/coresight-cti-core.c

453

reg_value = config->ctiappset;

drivers/hwtracing/coresight/coresight-cti-core.c

459

reg_value = chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

465

reg_value = chan_bitmask;

drivers/hwtracing/coresight/coresight-cti-core.c

475

cti_write_single_reg(drvdata, reg_offset, reg_value);

drivers/i2c/busses/i2c-eg20t.c

207

u32 reg_value;

drivers/i2c/busses/i2c-eg20t.c

222

reg_value = PCH_I2CCTL_I2CMEN;

drivers/i2c/busses/i2c-eg20t.c

224

reg_value |= FAST_MODE_EN;

drivers/i2c/busses/i2c-eg20t.c

238

reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */

drivers/i2c/busses/i2c-eg20t.c

239

iowrite32(reg_value, p + PCH_I2CCTL);

drivers/iio/accel/bmc150-accel-core.c

184

u8 reg_value;

drivers/iio/accel/bmc150-accel-core.c

221

bmc150_accel_sleep_value_table[i].reg_value;

drivers/iio/imu/bmi323/bmi323_core.c

1000

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1004

raw = FIELD_GET(BMI323_TAP3_QT_BW_TAP_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1019

ret = bmi323_read_ext_reg(data, reg, &reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1023

raw = FIELD_GET(BMI323_MO1_SLOPE_TH_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1031

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1035

raw = FIELD_GET(BMI323_MO3_DURA_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1043

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1047

raw = FIELD_GET(BMI323_MO2_HYSTR_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1057

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

1061

raw = FIELD_GET(BMI323_STEP_SC1_WTRMRK_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

654

unsigned int reg_value, raw;

drivers/iio/imu/bmi323/bmi323_core.c

658

ret = bmi323_read_ext_reg(data, BMI323_TAP2_REG, &reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

663

raw = FIELD_GET(BMI323_TAP2_MAX_DUR_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

710

unsigned int reg_value, raw;

drivers/iio/imu/bmi323/bmi323_core.c

714

ret = bmi323_read_ext_reg(data, BMI323_TAP1_REG, &reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

719

raw = FIELD_GET(BMI323_TAP1_TIMOUT_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

969

unsigned int raw, reg_value;

drivers/iio/imu/bmi323/bmi323_core.c

979

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

983

raw = FIELD_GET(BMI323_TAP2_THRES_MSK, reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

989

&reg_value);

drivers/iio/imu/bmi323/bmi323_core.c

993

raw = FIELD_GET(BMI323_TAP3_QT_AFT_GES_MSK, reg_value);

drivers/iio/temperature/mlx90632.c

648

s32 *reg_value)

drivers/iio/temperature/mlx90632.c

664

*reg_value = (read << 16) | (value & 0xffff);

drivers/iio/temperature/mlx90635.c

268

s32 *reg_value)

drivers/iio/temperature/mlx90635.c

284

*reg_value = (read << 16) | (value & 0xffff);

drivers/media/dvb-frontends/cxd2841er.c

354

u32 reg_value = 0;

drivers/media/dvb-frontends/cxd2841er.c

363

reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);

drivers/media/dvb-frontends/cxd2841er.c

364

if ((reg_value == 0) || (reg_value > 0xFFFFF)) {

drivers/media/dvb-frontends/cxd2841er.c

369

data[0] = (u8)((reg_value >> 16) & 0x0F);

drivers/media/dvb-frontends/cxd2841er.c

370

data[1] = (u8)((reg_value >> 8) & 0xFF);

drivers/media/dvb-frontends/cxd2841er.c

371

data[2] = (u8)(reg_value & 0xFF);

drivers/media/dvb-frontends/cxd2880/cxd2880_io.c

49

const struct cxd2880_reg_value reg_value[],

drivers/media/dvb-frontends/cxd2880/cxd2880_io.c

59

ret = io->write_reg(io, tgt, reg_value[i].addr,

drivers/media/dvb-frontends/cxd2880/cxd2880_io.c

60

reg_value[i].value);

drivers/media/dvb-frontends/cxd2880/cxd2880_io.h

52

const struct cxd2880_reg_value reg_value[],

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1228

u16 *reg_value)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1236

if (!tnr_dmd || !reg_value)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1275

*reg_value = (data[0] << 8) | data[1];

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1281

u32 reg_value, int *snr)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1286

if (reg_value == 0)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1289

if (reg_value > 10876)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1290

reg_value = 10876;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1292

*snr = intlog10(reg_value) - intlog10(12600 - reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1301

u16 reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1319

ret = dvbt2_read_snr_reg(tnr_dmd, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1323

ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1340

u16 reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1360

ret = dvbt2_read_snr_reg(tnr_dmd, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1362

ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr_main);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1364

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1366

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1371

reg_value_sum += reg_value;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1373

ret = dvbt2_read_snr_reg(tnr_dmd->diver_sub, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1375

ret = dvbt2_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1377

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1379

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c

1384

reg_value_sum += reg_value;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

392

u16 *reg_value)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

397

if (!tnr_dmd || !reg_value)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

428

*reg_value = (rdata[0] << 8) | rdata[1];

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

434

u32 reg_value, int *snr)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

439

if (reg_value == 0)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

442

if (reg_value > 4996)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

443

reg_value = 4996;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

445

*snr = intlog10(reg_value) - intlog10(5350 - reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

454

u16 reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

472

ret = dvbt_read_snr_reg(tnr_dmd, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

476

ret = dvbt_calc_snr(tnr_dmd, reg_value, snr);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

493

u16 reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

513

ret = dvbt_read_snr_reg(tnr_dmd, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

515

ret = dvbt_calc_snr(tnr_dmd, reg_value, snr_main);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

517

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

519

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

524

reg_value_sum += reg_value;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

526

ret = dvbt_read_snr_reg(tnr_dmd->diver_sub, &reg_value);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

528

ret = dvbt_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

530

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

532

reg_value = 0;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c

537

reg_value_sum += reg_value;

drivers/media/dvb-frontends/si2165.c

827

u32 reg_value;

drivers/media/dvb-frontends/si2165.c

835

reg_value = oversamp & 0x3fffffff;

drivers/media/dvb-frontends/si2165.c

837

dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);

drivers/media/dvb-frontends/si2165.c

838

return si2165_writereg32(state, REG_OVERSAMP, reg_value);

drivers/media/dvb-frontends/si2165.c

845

s32 reg_value = 0;

drivers/media/dvb-frontends/si2165.c

863

reg_value = (s32)if_freq_shift;

drivers/media/dvb-frontends/si2165.c

866

reg_value = -reg_value;

drivers/media/dvb-frontends/si2165.c

868

reg_value = reg_value & 0x1fffffff;

drivers/media/dvb-frontends/si2165.c

871

return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);

drivers/media/dvb-frontends/stv0910.c

124

u32 reg_value;

drivers/media/dvb-frontends/stv0910.c

591

int table_size, u32 reg_value)

drivers/media/dvb-frontends/stv0910.c

600

if (reg_value >= table[0].reg_value) {

drivers/media/dvb-frontends/stv0910.c

602

} else if (reg_value <= table[imax].reg_value) {

drivers/media/dvb-frontends/stv0910.c

607

if ((table[imin].reg_value >= reg_value) &&

drivers/media/dvb-frontends/stv0910.c

608

(reg_value >= table[i].reg_value))

drivers/media/dvb-frontends/stv0910.c

614

reg_diff = table[imax].reg_value - table[imin].reg_value;

drivers/media/dvb-frontends/stv0910.c

617

value += ((s32)(reg_value - table[imin].reg_value) *

drivers/media/dvb-frontends/stv0910.c

988

u16 reg_value = (tmp[0] << 8) | tmp[1];

drivers/media/dvb-frontends/stv0910.c

990

reg_value);

drivers/media/dvb-frontends/stv6111.c

32

u16 reg_value;

drivers/media/dvb-frontends/stv6111.c

533

int table_size, u16 reg_value)

drivers/media/dvb-frontends/stv6111.c

542

if (reg_value <= table[0].reg_value) {

drivers/media/dvb-frontends/stv6111.c

544

} else if (reg_value >= table[imax].reg_value) {

drivers/media/dvb-frontends/stv6111.c

549

if ((table[imin].reg_value <= reg_value) &&

drivers/media/dvb-frontends/stv6111.c

550

(reg_value <= table[i].reg_value))

drivers/media/dvb-frontends/stv6111.c

555

reg_diff = table[imax].reg_value - table[imin].reg_value;

drivers/media/dvb-frontends/stv6111.c

558

gain += ((s32)(reg_value - table[imin].reg_value) *

drivers/media/i2c/ov5640.c

1715

const struct reg_value *regs, unsigned int regnum)

drivers/media/i2c/ov5640.c

399

const struct reg_value *reg_data;

drivers/media/i2c/ov5640.c

546

static const struct reg_value ov5640_init_setting[] = {

drivers/media/i2c/ov5640.c

624

static const struct reg_value ov5640_setting_low_res[] = {

drivers/media/i2c/ov5640.c

639

static const struct reg_value ov5640_setting_720P_1280_720[] = {

drivers/media/i2c/ov5640.c

654

static const struct reg_value ov5640_setting_1080P_1920_1080[] = {

drivers/media/i2c/ov5640.c

678

static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {

drivers/media/i2c/ov5645.c

116

static const struct reg_value ov5645_global_init_setting[] = {

drivers/media/i2c/ov5645.c

357

static const struct reg_value ov5645_setting_sxga[] = {

drivers/media/i2c/ov5645.c

405

static const struct reg_value ov5645_setting_1080p[] = {

drivers/media/i2c/ov5645.c

455

static const struct reg_value ov5645_setting_full[] = {

drivers/media/i2c/ov5645.c

616

const struct reg_value *settings,

drivers/media/i2c/ov5645.c

701

u32 reg_value = (value * 0x10) + 0x40;

drivers/media/i2c/ov5645.c

704

ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);

drivers/media/i2c/ov5645.c

708

return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);

drivers/media/i2c/ov5645.c

79

const struct reg_value *data;

drivers/media/i2c/ov7251.c

238

static const struct reg_value ov7251_global_init_setting[] = {

drivers/media/i2c/ov7251.c

243

static const struct reg_value ov7251_setting_vga_30fps[] = {

drivers/media/i2c/ov7251.c

371

static const struct reg_value ov7251_setting_vga_60fps[] = {

drivers/media/i2c/ov7251.c

499

static const struct reg_value ov7251_setting_vga_90fps[] = {

drivers/media/i2c/ov7251.c

79

const struct reg_value *data;

drivers/media/i2c/ov7251.c

891

const struct reg_value *settings,

drivers/media/platform/ti/omap3isp/isp.h

298

void isp_reg_writel(struct isp_device *isp, u32 reg_value,

drivers/media/platform/ti/omap3isp/isp.h

301

__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);

drivers/media/rc/ene_ir.c

463

u8 reg_value;

drivers/media/rc/ene_ir.c

470

reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;

drivers/media/rc/ene_ir.c

471

reg_value |= ENE_IRQ_UNK_EN;

drivers/media/rc/ene_ir.c

472

reg_value &= ~ENE_IRQ_STATUS;

drivers/media/rc/ene_ir.c

473

reg_value |= (dev->irq & ENE_IRQ_MASK);

drivers/media/rc/ene_ir.c

474

ene_write_reg(dev, ENE_IRQ, reg_value);

drivers/media/spi/gs1662.c

227

if (reg_fmt[i].reg_value == std) {

drivers/media/spi/gs1662.c

243

return reg_fmt[i].reg_value | MASK_FORCE_STD;

drivers/media/spi/gs1662.c

258

int reg_value;

drivers/media/spi/gs1662.c

263

reg_value = get_register_timings(timings);

drivers/media/spi/gs1662.c

264

if (reg_value == 0x0)

drivers/media/spi/gs1662.c

288

u16 reg_value, i;

drivers/media/spi/gs1662.c

302

gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, &reg_value);

drivers/media/spi/gs1662.c

303

if (reg_value)

drivers/media/spi/gs1662.c

311

gs_read_register(gs->pdev, REG_STATUS, &reg_value);

drivers/media/spi/gs1662.c

312

if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK))

drivers/media/spi/gs1662.c

314

if (!(reg_value & MASK_STD_LOCK))

drivers/media/spi/gs1662.c

317

ret = gs_status_format(reg_value, &fmt);

drivers/media/spi/gs1662.c

342

int reg_value;

drivers/media/spi/gs1662.c

351

reg_value = get_register_timings(&gs->current_timings);

drivers/media/spi/gs1662.c

352

return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value);

drivers/media/spi/gs1662.c

362

u16 reg_value, i;

drivers/media/spi/gs1662.c

371

REG_LINES_PER_FRAME + i, &reg_value);

drivers/media/spi/gs1662.c

372

if (reg_value)

drivers/media/spi/gs1662.c

384

ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value);

drivers/media/spi/gs1662.c

385

if (!(reg_value & MASK_H_LOCK))

drivers/media/spi/gs1662.c

387

if (!(reg_value & MASK_V_LOCK))

drivers/media/spi/gs1662.c

389

if (!(reg_value & MASK_STD_LOCK))

drivers/media/spi/gs1662.c

54

u16 reg_value;

drivers/misc/apds990x.c

308

u8 reg_value;

drivers/misc/apds990x.c

312

reg_value = 256 - ((time_ms * TIME_STEP_SCALER) / TIMESTEP);

drivers/misc/apds990x.c

314

chip->a_max_result = (u16)(256 - reg_value) * APDS990X_TIME_TO_ADC;

drivers/misc/apds990x.c

315

return apds990x_write_byte(chip, APDS990X_ATIME, reg_value);

drivers/misc/xilinx_sdfec.c

264

u32 reg_value;

drivers/misc/xilinx_sdfec.c

268

reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR);

drivers/misc/xilinx_sdfec.c

269

xsdfec->config.order = reg_value;

drivers/misc/xilinx_sdfec.c

279

reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);

drivers/misc/xilinx_sdfec.c

280

xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;

drivers/misc/xilinx_sdfec.c

282

reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);

drivers/misc/xilinx_sdfec.c

284

(reg_value & XSDFEC_ECC_ISR_MASK) > 0;

drivers/misc/xilinx_sdfec.c

286

reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);

drivers/misc/xilinx_sdfec.c

287

sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;

drivers/misc/xilinx_sdfec.c

438

u32 reg_value;

drivers/misc/xilinx_sdfec.c

446

reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR);

drivers/misc/xilinx_sdfec.c

448

turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >>

drivers/misc/xilinx_sdfec.c

450

turbo_params.alg = reg_value & 0x1;

drivers/misc/xilinx_sdfec.c

782

u32 reg_value;

drivers/misc/xilinx_sdfec.c

786

reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR);

drivers/misc/xilinx_sdfec.c

788

is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET);

drivers/misc/xilinx_sdfec.c

832

u32 reg_value;

drivers/misc/xilinx_sdfec.c

849

reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB;

drivers/misc/xilinx_sdfec.c

850

reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB;

drivers/misc/xilinx_sdfec.c

851

reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB;

drivers/misc/xilinx_sdfec.c

852

reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB;

drivers/misc/xilinx_sdfec.c

854

xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value);

drivers/mmc/host/dw_mmc-k3.c

223

u32 reg_value;

drivers/mmc/host/dw_mmc-k3.c

252

reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |

drivers/mmc/host/dw_mmc-k3.c

255

mci_writel(host, UHS_REG_EXT, reg_value);

drivers/mmc/host/dw_mmc-k3.c

259

reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |

drivers/mmc/host/dw_mmc-k3.c

261

mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);

drivers/mmc/host/dw_mmc-starfive.c

45

u32 reg_value = mci_readl(host, UHS_REG_EXT);

drivers/mmc/host/dw_mmc-starfive.c

48

reg_value &= ~STARFIVE_SMPL_PHASE;

drivers/mmc/host/dw_mmc-starfive.c

49

reg_value |= FIELD_PREP(STARFIVE_SMPL_PHASE, smpl_phase);

drivers/mmc/host/dw_mmc-starfive.c

50

mci_writel(host, UHS_REG_EXT, reg_value);

drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h

33

#define hbg_field_modify(reg_value, mask, value) ({ \

drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h

34

(reg_value) &= ~(mask); \

drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h

35

(reg_value) |= FIELD_PREP(mask, value); })

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

34

int reg_value;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

37

reg_value = dsaf_read_dev(ppe_cb,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

40

dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

43

dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

46

dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

49

dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

53

ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);

drivers/net/ethernet/hisilicon/hns_mdio.c

150

u32 reg_value;

drivers/net/ethernet/hisilicon/hns_mdio.c

156

ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);

drivers/net/ethernet/hisilicon/hns_mdio.c

160

reg_value &= st_msk;

drivers/net/ethernet/hisilicon/hns_mdio.c

161

if ((!!check_st) == (!!reg_value))

drivers/net/ethernet/hisilicon/hns_mdio.c

165

if ((!!check_st) != (!!reg_value))

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

1706

__le32 reg_value;

drivers/net/ethernet/intel/i40e/i40e_common.c

4672

cmd->reg_value = cpu_to_le32(reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4725

*reg_val = le32_to_cpu(cmd->reg_value);

drivers/net/ethernet/intel/ice/ice_ethtool.c

506

u32 reg_value = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);

drivers/net/ethernet/intel/ice/ice_ethtool.c

508

return FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1857

static u64 igc_ethtool_get_frame_ass_error(u32 reg_value)

drivers/net/ethernet/intel/igc/igc_ethtool.c

1863

ooo_frame_cnt = FIELD_GET(IGC_PRMEXCPRCNT_OOO_FRAME_CNT, reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1864

ooo_frag_cnt = FIELD_GET(IGC_PRMEXCPRCNT_OOO_FRAG_CNT, reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1866

reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1871

static u64 igc_ethtool_get_frame_smd_error(u32 reg_value)

drivers/net/ethernet/intel/igc/igc_ethtool.c

1873

return FIELD_GET(IGC_PRMEXCPRCNT_OOO_SMDC, reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1881

u32 reg_value;

drivers/net/ethernet/intel/igc/igc_ethtool.c

1883

reg_value = rd32(IGC_PRMEXCPRCNT);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1885

stats->MACMergeFrameAssErrorCount = igc_ethtool_get_frame_ass_error(reg_value);

drivers/net/ethernet/intel/igc/igc_ethtool.c

1886

stats->MACMergeFrameSmdErrorCount = igc_ethtool_get_frame_smd_error(reg_value);

drivers/net/ethernet/microchip/lan743x_ethtool.c

219

u32 reg_value;

drivers/net/ethernet/microchip/lan743x_ethtool.c

221

reg_value = lan743x_csr_read(adapter, HS_OTP_PWR_DN);

drivers/net/ethernet/microchip/lan743x_ethtool.c

222

if (reg_value & OTP_PWR_DN_PWRDN_N_) {

drivers/net/ethernet/microchip/lan743x_ethtool.c

223

reg_value &= ~OTP_PWR_DN_PWRDN_N_;

drivers/net/ethernet/microchip/lan743x_ethtool.c

224

lan743x_csr_write(adapter, HS_OTP_PWR_DN, reg_value);

drivers/net/ethernet/microchip/lan743x_ethtool.c

235

u32 reg_value;

drivers/net/ethernet/microchip/lan743x_ethtool.c

237

reg_value = lan743x_csr_read(adapter, HS_OTP_PWR_DN);

drivers/net/ethernet/microchip/lan743x_ethtool.c

238

if (!(reg_value & OTP_PWR_DN_PWRDN_N_)) {

drivers/net/ethernet/microchip/lan743x_ethtool.c

239

reg_value |= OTP_PWR_DN_PWRDN_N_;

drivers/net/ethernet/microchip/lan743x_ethtool.c

240

lan743x_csr_write(adapter, HS_OTP_PWR_DN, reg_value);

drivers/net/ethernet/microchip/lan743x_ethtool.c

32

u32 reg_value;

drivers/net/ethernet/microchip/lan743x_ethtool.c

34

reg_value = lan743x_csr_read(adapter, OTP_PWR_DN);

drivers/net/ethernet/microchip/lan743x_ethtool.c

36

if (reg_value & OTP_PWR_DN_PWRDN_N_) {

drivers/net/ethernet/microchip/lan743x_ethtool.c

38

reg_value &= ~OTP_PWR_DN_PWRDN_N_;

drivers/net/ethernet/microchip/lan743x_ethtool.c

39

lan743x_csr_write(adapter, OTP_PWR_DN, reg_value);

drivers/net/ethernet/microchip/lan743x_ethtool.c

49

u32 reg_value;

drivers/net/ethernet/microchip/lan743x_ethtool.c

51

reg_value = lan743x_csr_read(adapter, OTP_PWR_DN);

drivers/net/ethernet/microchip/lan743x_ethtool.c

52

if (!(reg_value & OTP_PWR_DN_PWRDN_N_)) {

drivers/net/ethernet/microchip/lan743x_ethtool.c

54

reg_value |= OTP_PWR_DN_PWRDN_N_;

drivers/net/ethernet/microchip/lan743x_ethtool.c

55

lan743x_csr_write(adapter, OTP_PWR_DN, reg_value);

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

44

u32 reg_value;

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

66

reg_value = data;

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

68

reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

70

writel(reg_value, ioaddr + PTP_SSIR);

drivers/net/phy/air_en8811h.c

490

int ret, reg_value;

drivers/net/phy/air_en8811h.c

499

EN8811H_PHY_FW_STATUS, reg_value,

drivers/net/phy/air_en8811h.c

500

reg_value == EN8811H_PHY_READY,

drivers/net/phy/air_en8811h.c

503

phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);

drivers/net/phy/open_alliance_helpers.c

33

int oa_1000bt1_get_ethtool_cable_result_code(u16 reg_value)

drivers/net/phy/open_alliance_helpers.c

35

u8 tdr_status = FIELD_GET(OA_1000BT1_HDD_TDR_STATUS_MASK, reg_value);

drivers/net/phy/open_alliance_helpers.c

36

u8 dist_val = FIELD_GET(OA_1000BT1_HDD_TDR_DISTANCE_MASK, reg_value);

drivers/net/phy/open_alliance_helpers.c

68

int oa_1000bt1_get_tdr_distance(u16 reg_value)

drivers/net/phy/open_alliance_helpers.c

70

u8 dist_val = FIELD_GET(OA_1000BT1_HDD_TDR_DISTANCE_MASK, reg_value);

drivers/net/phy/open_alliance_helpers.h

43

int oa_1000bt1_get_ethtool_cable_result_code(u16 reg_value);

drivers/net/phy/open_alliance_helpers.h

44

int oa_1000bt1_get_tdr_distance(u16 reg_value);

drivers/net/wireless/ath/ath10k/ce.c

296

u32 reg_value;

drivers/net/wireless/ath/ath10k/ce.c

298

reg_value = ath10k_ce_read32(ar, ce_ctrl_addr +

drivers/net/wireless/ath/ath10k/ce.c

300

reg_value &= ~CE_DESC_ADDR_HI_MASK;

drivers/net/wireless/ath/ath10k/ce.c

301

reg_value |= addr_hi;

drivers/net/wireless/ath/ath10k/ce.c

303

ar->hw_ce_regs->dr_base_addr_hi, reg_value);

drivers/net/wireless/marvell/mwifiex/debugfs.c

422

u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX;

drivers/net/wireless/marvell/mwifiex/debugfs.c

428

if (sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value) != 3) {

drivers/net/wireless/marvell/mwifiex/debugfs.c

439

saved_reg_value = reg_value;

drivers/net/wireless/marvell/mwifiex/debugfs.c

463

u32 reg_value;

drivers/net/wireless/marvell/mwifiex/debugfs.c

488

saved_reg_offset, &reg_value);

drivers/net/wireless/marvell/mwifiex/debugfs.c

495

saved_reg_offset, reg_value);

drivers/net/wireless/marvell/mwifiex/main.h

1508

u32 reg_offset, u32 reg_value);

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1296

u32 reg_offset, u32 reg_value)

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1302

reg_rw.value = reg_value;

drivers/phy/allwinner/phy-sun4i-usb.c

232

u32 bits, reg_value;

drivers/phy/allwinner/phy-sun4i-usb.c

246

reg_value = readl(phy->pmu);

drivers/phy/allwinner/phy-sun4i-usb.c

249

reg_value |= bits;

drivers/phy/allwinner/phy-sun4i-usb.c

251

reg_value &= ~bits;

drivers/phy/allwinner/phy-sun4i-usb.c

253

writel(reg_value, phy->pmu);

drivers/phy/allwinner/phy-sun9i-usb.c

46

u32 bits, reg_value;

drivers/phy/allwinner/phy-sun9i-usb.c

56

reg_value = readl(phy->pmu);

drivers/phy/allwinner/phy-sun9i-usb.c

59

reg_value |= bits;

drivers/phy/allwinner/phy-sun9i-usb.c

61

reg_value &= ~bits;

drivers/phy/allwinner/phy-sun9i-usb.c

63

writel(reg_value, phy->pmu);

drivers/platform/x86/intel/int1092/intel_sar.c

172

return sysfs_emit(buf, "%d\n", context->reg_value);

drivers/platform/x86/intel/int1092/intel_sar.c

189

context->reg_value = value;

drivers/platform/x86/intel/int1092/intel_sar.c

41

&context->config_data[context->reg_value];

drivers/platform/x86/intel/int1092/intel_sar.h

80

int reg_value;

drivers/power/supply/ab8500_charger.c

1169

u8 reg_value;

drivers/power/supply/ab8500_charger.c

1176

reg, &reg_value);

drivers/power/supply/ab8500_charger.c

1185

prev_curr_index = (reg_value >> shift_value);

drivers/power/supply/ab8500_charger.c

1193

prev_curr_index = (reg_value >> shift_value);

drivers/power/supply/ab8500_charger.c

1202

prev_curr_index = (reg_value >> shift_value);

drivers/power/supply/ab8500_charger.c

2004

u8 reg_value;

drivers/power/supply/ab8500_charger.c

2012

AB8500_CHARGER, AB8500_CH_STATUS2_REG, &reg_value);

drivers/power/supply/ab8500_charger.c

2017

if (!(reg_value & MAIN_CH_NOK)) {

drivers/power/supply/ab8500_charger.c

2025

&reg_value);

drivers/power/supply/ab8500_charger.c

2030

if (!(reg_value & VBUS_OVV_TH)) {

drivers/power/supply/ab8500_charger.c

2474

u8 reg_value;

drivers/power/supply/ab8500_charger.c

2482

AB8500_CHARGER, AB8500_CH_USBCH_STAT2_REG, &reg_value);

drivers/power/supply/ab8500_charger.c

2489

if (reg_value & VBUS_CH_NOK) {

drivers/power/supply/ab8500_charger.c

2513

u8 reg_value;

drivers/power/supply/ab8500_charger.c

2520

AB8500_CHARGER, AB8500_CH_STATUS2_REG, &reg_value);

drivers/power/supply/ab8500_charger.c

2525

if (reg_value & MAIN_CH_TH_PROT)

drivers/power/supply/ab8500_charger.c

2543

u8 reg_value;

drivers/power/supply/ab8500_charger.c

2550

AB8500_CHARGER, AB8500_CH_USBCH_STAT2_REG, &reg_value);

drivers/power/supply/ab8500_charger.c

2555

if (reg_value & USB_CH_TH_PROT)

drivers/power/supply/ab8500_charger.c

2672

u8 reg_value;

drivers/power/supply/ab8500_charger.c

2681

AB8500_CH_USBCH_STAT2_REG, &reg_value);

drivers/power/supply/ab8500_charger.c

2688

reg_value >> AUTO_VBUS_IN_CURR_LIM_SHIFT];

drivers/power/supply/ab8500_fg.c

1839

u8 reg_value;

drivers/power/supply/ab8500_fg.c

1850

&reg_value);

drivers/power/supply/ab8500_fg.c

1855

if ((reg_value & BATT_OVV) == BATT_OVV) {

drivers/power/supply/ab8500_fg.c

2576

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2581

AB8505_RTC_PCUT_FLAG_TIME_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2588

return sysfs_emit(buf, "%d\n", (reg_value & 0x7F));

drivers/power/supply/ab8500_fg.c

2599

int reg_value;

drivers/power/supply/ab8500_fg.c

2603

if (kstrtoint(buf, 10, &reg_value))

drivers/power/supply/ab8500_fg.c

2606

if (reg_value > 0x7F) {

drivers/power/supply/ab8500_fg.c

2612

AB8505_RTC_PCUT_FLAG_TIME_REG, (u8)reg_value);

drivers/power/supply/ab8500_fg.c

2626

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2631

AB8505_RTC_PCUT_MAX_TIME_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2638

return sysfs_emit(buf, "%d\n", (reg_value & 0x7F));

drivers/power/supply/ab8500_fg.c

2650

int reg_value;

drivers/power/supply/ab8500_fg.c

2654

if (kstrtoint(buf, 10, &reg_value))

drivers/power/supply/ab8500_fg.c

2657

if (reg_value > 0x7F) {

drivers/power/supply/ab8500_fg.c

2663

AB8505_RTC_PCUT_MAX_TIME_REG, (u8)reg_value);

drivers/power/supply/ab8500_fg.c

2677

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2682

AB8505_RTC_PCUT_RESTART_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2689

return sysfs_emit(buf, "%d\n", (reg_value & 0xF));

drivers/power/supply/ab8500_fg.c

2700

int reg_value;

drivers/power/supply/ab8500_fg.c

2704

if (kstrtoint(buf, 10, &reg_value))

drivers/power/supply/ab8500_fg.c

2707

if (reg_value > 0xF) {

drivers/power/supply/ab8500_fg.c

2713

AB8505_RTC_PCUT_RESTART_REG, (u8)reg_value);

drivers/power/supply/ab8500_fg.c

2728

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2733

AB8505_RTC_PCUT_TIME_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2740

return sysfs_emit(buf, "%d\n", (reg_value & 0x7F));

drivers/power/supply/ab8500_fg.c

2751

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2756

AB8505_RTC_PCUT_RESTART_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2763

return sysfs_emit(buf, "%d\n", (reg_value & 0xF0) >> 4);

drivers/power/supply/ab8500_fg.c

2774

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2779

AB8505_RTC_PCUT_CTL_STATUS_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2784

return sysfs_emit(buf, "%d\n", (reg_value & 0x1));

drivers/power/supply/ab8500_fg.c

2795

int reg_value;

drivers/power/supply/ab8500_fg.c

2799

if (kstrtoint(buf, 10, &reg_value))

drivers/power/supply/ab8500_fg.c

2802

if (reg_value > 0x1) {

drivers/power/supply/ab8500_fg.c

2808

AB8505_RTC_PCUT_CTL_STATUS_REG, (u8)reg_value);

drivers/power/supply/ab8500_fg.c

2823

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2828

AB8505_RTC_PCUT_CTL_STATUS_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2835

return sysfs_emit(buf, "%d\n", ((reg_value & 0x10) >> 4));

drivers/power/supply/ab8500_fg.c

2846

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2851

AB8505_RTC_PCUT_DEBOUNCE_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2858

return sysfs_emit(buf, "%d\n", (reg_value & 0x7));

drivers/power/supply/ab8500_fg.c

2869

int reg_value;

drivers/power/supply/ab8500_fg.c

2873

if (kstrtoint(buf, 10, &reg_value))

drivers/power/supply/ab8500_fg.c

2876

if (reg_value > 0x7) {

drivers/power/supply/ab8500_fg.c

2882

AB8505_RTC_PCUT_DEBOUNCE_REG, (u8)reg_value);

drivers/power/supply/ab8500_fg.c

2896

u8 reg_value;

drivers/power/supply/ab8500_fg.c

2901

AB8505_RTC_PCUT_CTL_STATUS_REG, &reg_value);

drivers/power/supply/ab8500_fg.c

2908

return sysfs_emit(buf, "%d\n", ((reg_value & 0x20) >> 5));

drivers/regulator/mc13892-regulator.c

442

u32 reg_value;

drivers/regulator/mc13892-regulator.c

447

reg_value = selector;

drivers/regulator/mc13892-regulator.c

467

reg_value -= MC13892_SWxHI_SEL_OFFSET;

drivers/regulator/mc13892-regulator.c

468

reg_value |= MC13892_SWITCHERS0_SWxHI;

drivers/regulator/mc13892-regulator.c

470

reg_value &= ~MC13892_SWITCHERS0_SWxHI;

drivers/regulator/mc13892-regulator.c

476

mask, reg_value);

drivers/regulator/mt6323-regulator.c

375

u32 reg_value;

drivers/regulator/mt6323-regulator.c

382

if (regmap_read(mt6323->regmap, MT6323_CID, &reg_value) < 0) {

drivers/regulator/mt6323-regulator.c

386

dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);

drivers/regulator/mt6331-regulator.c

447

u32 reg_value;

drivers/regulator/mt6331-regulator.c

454

if (regmap_read(mt6331->regmap, MT6331_HWCID, &reg_value) < 0) {

drivers/regulator/mt6331-regulator.c

458

reg_value &= GENMASK(7, 0);

drivers/regulator/mt6331-regulator.c

460

dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);

drivers/regulator/mt6331-regulator.c

469

if (reg_value == 0x10) {

drivers/regulator/mt6332-regulator.c

362

u32 reg_value;

drivers/regulator/mt6332-regulator.c

369

if (regmap_read(mt6332->regmap, MT6332_HWCID, &reg_value) < 0) {

drivers/regulator/mt6332-regulator.c

373

reg_value &= GENMASK(7, 0);

drivers/regulator/mt6332-regulator.c

375

dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);

drivers/regulator/mt6332-regulator.c

384

if (reg_value == 0x10) {

drivers/regulator/mt6397-regulator.c

355

u32 reg_value, version;

drivers/regulator/mt6397-regulator.c

362

if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {

drivers/regulator/mt6397-regulator.c

366

dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);

drivers/regulator/mt6397-regulator.c

368

version = (reg_value & 0xFF);

drivers/scsi/3w-sas.c

1241

u32 reg_value;

drivers/scsi/3w-sas.c

1243

reg_value = readl(reg);

drivers/scsi/3w-sas.c

1246

while ((reg_value & value) != result) {

drivers/scsi/3w-sas.c

1247

reg_value = readl(reg);

drivers/scsi/arm/acornscsi.c

614

unsigned char reg_value;

drivers/scsi/arm/acornscsi.c

637

if (syncxfer == sync_xfer_table[i].reg_value)

drivers/scsi/arm/acornscsi.c

674

return sync_xfer_table[round_period(period)].reg_value |

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

2774

u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

2777

switch (reg_value & (CHL_INT0_NOT_RDY_MSK |

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

2796

reg_value = hisi_sas_read32(hisi_hba,

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

2798

if (reg_value & BIT(phy_no)) {

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1860

u32 reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1865

reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1866

sphy->loss_of_dword_sync_count += reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1869

reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1870

sphy->phy_reset_problem_count += reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1873

reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1874

sphy->invalid_dword_count += reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1877

reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1878

sphy->running_disparity_error_count += reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1881

reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1882

phy->code_violation_err_count += reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1911

u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1915

phy_no, reg_value);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1916

if (reg_value & BIT(LINK_RESET_TIMEOUT_OFF))

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1941

u32 reg_value;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1945

HILINK_ERR_DFX, reg_value,

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1946

!((reg_value >> 8) & BIT(phy_no)),

drivers/scsi/isci/registers.h

187

#define SCU_SET_BIT(name, reg_value) \

drivers/scsi/isci/registers.h

188

((reg_value) | SCU_GEN_BIT(name))

drivers/scsi/isci/registers.h

190

#define SCU_CLEAR_BIT(name, reg_value) \

drivers/scsi/isci/registers.h

191

((reg_value)$ ~(SCU_GEN_BIT(name)))

drivers/scsi/wd33c93.c

1821

sx_table[0].reg_value = 0x20;

drivers/scsi/wd33c93.c

1824

sx_table[i].reg_value = (i+1)*0x10;

drivers/scsi/wd33c93.c

1826

sx_table[7].reg_value = 0;

drivers/scsi/wd33c93.c

1828

sx_table[8].reg_value = 0;

drivers/scsi/wd33c93.c

281

result = sx_table[round_period(period,sx_table)].reg_value;

drivers/scsi/wd33c93.h

203

uchar reg_value;

drivers/soc/qcom/qcom-geni-se.c

1192

u32 i, reg_value;

drivers/soc/qcom/qcom-geni-se.c

1240

reg_value = AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON |

drivers/soc/qcom/qcom-geni-se.c

1242

geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value);

drivers/soc/qcom/qcom-geni-se.c

1257

reg_value = geni_se_get_rx_fifo_depth(se);

drivers/soc/qcom/qcom-geni-se.c

1258

writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG);

drivers/soc/sunxi/sunxi_sram.c

168

unsigned int *reg_value)

drivers/soc/sunxi/sunxi_sram.c

203

if (reg_value)

drivers/soc/sunxi/sunxi_sram.c

204

*reg_value = func->reg_val;

drivers/spi/spi-axiado.c

467

u32 reg_value;

drivers/spi/spi-axiado.c

469

reg_value = ax_spi_read(xspi, AX_SPI_CR1);

drivers/spi/spi-axiado.c

470

reg_value |= AX_SPI_CR1_SCE;

drivers/spi/spi-axiado.c

472

ax_spi_write(xspi, AX_SPI_CR1, reg_value);

drivers/spi/spi-axiado.c

490

u32 reg_value;

drivers/spi/spi-axiado.c

493

reg_value = ax_spi_read(xspi, AX_SPI_CR1);

drivers/spi/spi-axiado.c

494

reg_value &= ~AX_SPI_CR1_SCE;

drivers/spi/spi-axiado.c

496

ax_spi_write(xspi, AX_SPI_CR1, reg_value);

drivers/spi/spi-axiado.c

72

u32 reg_value;

drivers/spi/spi-axiado.c

78

reg_value = ax_spi_read(xspi, AX_SPI_CR1);

drivers/spi/spi-axiado.c

79

reg_value |= AX_SPI_CR1_SCR | AX_SPI_CR1_SCE;

drivers/spi/spi-axiado.c

81

ax_spi_write(xspi, AX_SPI_CR1, reg_value);

drivers/spi/spi-axiado.c

84

reg_value = ax_spi_read(xspi, AX_SPI_CR2);

drivers/spi/spi-axiado.c

85

reg_value |= AX_SPI_CR2_SWD | AX_SPI_CR2_SRD;

drivers/spi/spi-axiado.c

87

ax_spi_write(xspi, AX_SPI_CR2, reg_value);

drivers/staging/sm750fb/sm750_accel.c

20

static inline void write_dpr(struct lynx_accel *accel, int offset, u32 reg_value)

drivers/staging/sm750fb/sm750_accel.c

22

writel(reg_value, accel->dpr_base + offset);

drivers/tty/serial/8250/8250_men_mcb.c

106

*uarts_available = reg_value >> 4;

drivers/tty/serial/8250/8250_men_mcb.c

84

int reg_value;

drivers/tty/serial/8250/8250_men_mcb.c

99

reg_value = MEN_READ_REGISTER(mem);

drivers/tty/synclink_gt.c

4724

unsigned int reg_value;

drivers/tty/synclink_gt.c

4750

reg_value = rd_reg32(info, TDCSR);

drivers/tty/synclink_gt.c

4753

if (reg_value & BIT0)

drivers/tty/synclink_gt.c

4757

total_count += (reg_value >> 8) & 0xff;

drivers/video/fbdev/via/hw.c

1014

int reg_value;

drivers/video/fbdev/via/hw.c

1020

reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);

drivers/video/fbdev/via/hw.c

1024

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

drivers/video/fbdev/via/hw.c

1027

reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);

drivers/video/fbdev/via/hw.c

1031

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);

drivers/video/fbdev/via/hw.c

1039

int reg_value;

drivers/video/fbdev/via/hw.c

1159

reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);

drivers/video/fbdev/via/hw.c

1163

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

drivers/video/fbdev/via/hw.c

1166

reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);

drivers/video/fbdev/via/hw.c

1173

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

drivers/video/fbdev/via/hw.c

1176

reg_value =

drivers/video/fbdev/via/hw.c

1184

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

drivers/video/fbdev/via/hw.c

1187

reg_value =

drivers/video/fbdev/via/hw.c

1196

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

drivers/video/fbdev/via/hw.c

1309

reg_value =

drivers/video/fbdev/via/hw.c

1319

viafb_load_reg(reg_value,

drivers/video/fbdev/via/hw.c

1324

reg_value =

drivers/video/fbdev/via/hw.c

1332

viafb_load_reg(reg_value,

drivers/video/fbdev/via/hw.c

1337

reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);

drivers/video/fbdev/via/hw.c

1344

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);

drivers/video/fbdev/via/hw.c

1347

reg_value =

drivers/video/fbdev/via/hw.c

1355

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);

drivers/video/fbdev/via/hw.c

1358

reg_value =

drivers/video/fbdev/via/hw.c

1367

viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);

drivers/video/fbdev/via/lcd.c

338

int reg_value = 0;

drivers/video/fbdev/via/lcd.c

353

reg_value =

drivers/video/fbdev/via/lcd.c

359

viafb_load_reg(reg_value,

drivers/video/fbdev/via/lcd.c

373

reg_value =

drivers/video/fbdev/via/lcd.c

380

viafb_load_reg(reg_value,

drivers/video/fbdev/via/lcd.c

385

DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);

drivers/video/fbdev/via/lcd.c

397

reg_value =

drivers/video/fbdev/via/lcd.c

403

viafb_load_reg(reg_value,

drivers/video/fbdev/via/lcd.c

417

reg_value =

drivers/video/fbdev/via/lcd.c

424

viafb_load_reg(reg_value,

drivers/video/fbdev/via/lcd.c

429

DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);

kernel/seccomp.c

773

unsigned int reg_value = 0;

kernel/seccomp.c

793

reg_value = sd->nr;

kernel/seccomp.c

796

reg_value = sd->arch;

kernel/seccomp.c

815

op_res = reg_value == k;

kernel/seccomp.c

818

op_res = reg_value >= k;

kernel/seccomp.c

821

op_res = reg_value > k;

kernel/seccomp.c

824

op_res = !!(reg_value & k);

kernel/seccomp.c

834

reg_value &= k;

sound/pci/echoaudio/echoaudio_gml.c

51

__le32 reg_value;

sound/pci/echoaudio/echoaudio_gml.c

62

reg_value = cpu_to_le32(value);

sound/pci/echoaudio/echoaudio_gml.c

63

if (reg_value != chip->comm_page->control_register || force) {

sound/pci/echoaudio/echoaudio_gml.c

66

chip->comm_page->control_register = reg_value;

sound/pci/oxygen/oxygen_mixer.c

149

unsigned int reg_value;

sound/pci/oxygen/oxygen_mixer.c

154

reg_value = reg_values[chip->dac_routing];

sound/pci/oxygen/oxygen_mixer.c

157

reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |

sound/pci/oxygen/oxygen_mixer.c

162

reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |

sound/pci/oxygen/oxygen_mixer.c

167

reg_value = chip->model.adjust_dac_routing(chip, reg_value);

sound/pci/oxygen/oxygen_mixer.c

168

oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING, reg_value,

sound/pci/oxygen/xonar_wm87x6.c

517

u16 reg_value;

sound/pci/oxygen/xonar_wm87x6.c

523

reg_value = data->wm8776_regs[reg_index] & ~bit;

sound/pci/oxygen/xonar_wm87x6.c

525

reg_value |= bit;

sound/pci/oxygen/xonar_wm87x6.c

526

changed = reg_value != data->wm8776_regs[reg_index];

sound/pci/oxygen/xonar_wm87x6.c

528

wm8776_write(chip, reg_index, reg_value);

sound/pci/oxygen/xonar_wm87x6.c

611

u16 mask, reg_value;

sound/pci/oxygen/xonar_wm87x6.c

632

reg_value = data->wm8776_regs[reg_index];

sound/pci/oxygen/xonar_wm87x6.c

633

reg_value &= ~(mask << shift);

sound/pci/oxygen/xonar_wm87x6.c

634

reg_value |= value << shift;

sound/pci/oxygen/xonar_wm87x6.c

635

wm8776_write_cached(chip, reg_index, reg_value);

sound/soc/codecs/aw88166.c

632

unsigned int reg_value;

sound/soc/codecs/aw88166.c

638

ret = regmap_read(aw_dev->regmap, AW88166_SYSCTRL2_REG, &reg_value);

sound/soc/codecs/aw88166.c

644

real_value = (real_value << AW88166_VOL_START_BIT) | (reg_value & AW88166_VOL_MASK);

sound/soc/codecs/aw88261.c

32

unsigned int reg_value;

sound/soc/codecs/aw88261.c

37

regmap_read(aw_dev->regmap, AW88261_SYSCTRL2_REG, &reg_value);

sound/soc/codecs/aw88261.c

39

real_value = (real_value | (reg_value & AW88261_VOL_START_MASK));

sound/soc/codecs/aw88395/aw88395_device.c

156

u32 reg_value;

sound/soc/codecs/aw88395/aw88395_device.c

180

if (regmap_read(aw_dev->regmap, AW88395_ID_REG, &reg_value))

sound/soc/codecs/aw88395/aw88395_device.c

262

unsigned int reg_value;

sound/soc/codecs/aw88395/aw88395_device.c

270

ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL2_REG, &reg_value);

sound/soc/codecs/aw88395/aw88395_device.c

277

real_value = (real_value << AW88395_VOL_START_BIT) | (reg_value & AW88395_VOL_MASK);

sound/soc/codecs/aw88395/aw88395_device.c

70

u32 reg_value;

sound/soc/codecs/aw88395/aw88395_device.c

94

if (regmap_read(aw_dev->regmap, AW88395_ID_REG, &reg_value))

sound/soc/codecs/aw88399.c

594

unsigned int reg_value;

sound/soc/codecs/aw88399.c

600

ret = regmap_read(aw_dev->regmap, AW88399_SYSCTRL2_REG, &reg_value);

sound/soc/codecs/aw88399.c

606

real_value = (real_value << AW88399_VOL_START_BIT) | (reg_value & AW88399_VOL_MASK);

sound/soc/codecs/tas2783-sdw.c

618

u32 reg_value;

sound/soc/codecs/tas2783-sdw.c

632

reg_value = cali_data[offset + i];

sound/soc/codecs/tas2783-sdw.c

633

buf[0] = reg_value >> 24;

sound/soc/codecs/tas2783-sdw.c

634

buf[1] = reg_value >> 16;

sound/soc/codecs/tas2783-sdw.c

635

buf[2] = reg_value >> 8;

sound/soc/codecs/tas2783-sdw.c

636

buf[3] = reg_value & 0xff;

sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

916

unsigned int reg_value;

sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

919

ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);

sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

922

reg_value = AFE_IRQ_STATUS_BITS;

sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

935

if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift)))

sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

944

reg_value & AFE_IRQ_STATUS_BITS);

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

56

unsigned int reg_value;

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

60

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

61

{ .rate = 12000, .reg_value = 1, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

62

{ .rate = 16000, .reg_value = 2, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

63

{ .rate = 24000, .reg_value = 3, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

64

{ .rate = 32000, .reg_value = 4, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

65

{ .rate = 48000, .reg_value = 5, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

66

{ .rate = 96000, .reg_value = 6, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

67

{ .rate = 192000, .reg_value = 7, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

68

{ .rate = 384000, .reg_value = 8, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

69

{ .rate = 7350, .reg_value = 16, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

70

{ .rate = 11025, .reg_value = 17, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

71

{ .rate = 14700, .reg_value = 18, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

72

{ .rate = 22050, .reg_value = 19, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

73

{ .rate = 29400, .reg_value = 20, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

74

{ .rate = 44100, .reg_value = 21, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

75

{ .rate = 88200, .reg_value = 22, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

76

{ .rate = 176400, .reg_value = 23, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

77

{ .rate = 352800, .reg_value = 24, },

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

86

return mt8188_afe_rates[i].reg_value;

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

114

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

115

{ .rate = 12000, .reg_value = 1, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

116

{ .rate = 16000, .reg_value = 2, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

117

{ .rate = 24000, .reg_value = 3, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

118

{ .rate = 32000, .reg_value = 4, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

119

{ .rate = 48000, .reg_value = 5, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

120

{ .rate = 96000, .reg_value = 7, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

121

{ .rate = 192000, .reg_value = 9, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

122

{ .rate = 384000, .reg_value = 11, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

123

{ .rate = 11025, .reg_value = 16, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

124

{ .rate = 22050, .reg_value = 17, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

125

{ .rate = 44100, .reg_value = 18, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

126

{ .rate = 88200, .reg_value = 19, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

127

{ .rate = 176400, .reg_value = 20, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

128

{ .rate = 352800, .reg_value = 21, },

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

137

return mt8188_etdm_rates[i].reg_value;

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

91

unsigned int reg_value;

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

34

unsigned int reg_value;

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

45

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

46

{ .rate = 16000, .reg_value = 1, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

47

{ .rate = 32000, .reg_value = 2, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

48

{ .rate = 48000, .reg_value = 3, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

49

{ .rate = 11025, .reg_value = 1, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

50

{ .rate = 22050, .reg_value = 2, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

51

{ .rate = 44100, .reg_value = 3, },

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

60

return mtk_dai_pcm_rates[i].reg_value;

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

640

unsigned int ul_rate, reg_value;

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

658

regmap_read(afe->regmap, AFE_SIDETONE_CON1, &reg_value);

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

683

regmap_read(afe->regmap, AFE_SIDETONE_CON0, &reg_value);

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

685

bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

702

AFE_SIDETONE_CON0, &reg_value);

sound/soc/mediatek/mt8192/mt8192-dai-adda.c

703

new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

49

unsigned int reg_value;

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

53

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

54

{ .rate = 12000, .reg_value = 1, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

55

{ .rate = 16000, .reg_value = 2, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

56

{ .rate = 24000, .reg_value = 3, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

57

{ .rate = 32000, .reg_value = 4, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

58

{ .rate = 48000, .reg_value = 5, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

59

{ .rate = 96000, .reg_value = 6, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

60

{ .rate = 192000, .reg_value = 7, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

61

{ .rate = 384000, .reg_value = 8, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

62

{ .rate = 7350, .reg_value = 16, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

63

{ .rate = 11025, .reg_value = 17, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

64

{ .rate = 14700, .reg_value = 18, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

65

{ .rate = 22050, .reg_value = 19, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

66

{ .rate = 29400, .reg_value = 20, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

67

{ .rate = 44100, .reg_value = 21, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

68

{ .rate = 88200, .reg_value = 22, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

69

{ .rate = 176400, .reg_value = 23, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

70

{ .rate = 352800, .reg_value = 24, },

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c

79

return mt8195_afe_rates[i].reg_value;

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

100

unsigned int reg_value;

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

123

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

124

{ .rate = 12000, .reg_value = 1, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

125

{ .rate = 16000, .reg_value = 2, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

126

{ .rate = 24000, .reg_value = 3, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

127

{ .rate = 32000, .reg_value = 4, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

128

{ .rate = 48000, .reg_value = 5, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

129

{ .rate = 96000, .reg_value = 7, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

130

{ .rate = 192000, .reg_value = 9, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

131

{ .rate = 384000, .reg_value = 11, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

132

{ .rate = 11025, .reg_value = 16, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

133

{ .rate = 22050, .reg_value = 17, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

134

{ .rate = 44100, .reg_value = 18, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

135

{ .rate = 88200, .reg_value = 19, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

136

{ .rate = 176400, .reg_value = 20, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

137

{ .rate = 352800, .reg_value = 21, },

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c

178

return mt8195_etdm_rates[i].reg_value;

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

32

unsigned int reg_value;

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

43

{ .rate = 8000, .reg_value = 0, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

44

{ .rate = 16000, .reg_value = 1, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

45

{ .rate = 32000, .reg_value = 2, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

46

{ .rate = 48000, .reg_value = 3, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

47

{ .rate = 11025, .reg_value = 1, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

48

{ .rate = 22050, .reg_value = 2, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

49

{ .rate = 44100, .reg_value = 3, },

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c

58

return mtk_dai_pcm_rates[i].reg_value;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1915

unsigned int reg_value;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1919

ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &reg_value);

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1922

reg_value = AFE_IRQ_STATUS_BITS;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1929

reg_value = AFE_IRQ_STATUS_BITS;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1934

reg_value &= mcu_irq_mask;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1945

if (!(reg_value & (1 << mcu_irq->irq_data->irq_clr_shift)))

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

1954

reg_value & AFE_IRQ_STATUS_BITS);