Symbol: reg_off
arch/x86/events/intel/pt.c
440
unsigned int reg_off;
arch/x86/events/intel/pt.c
445
.reg_off = RTIT_CTL_ADDR0_OFFSET,
arch/x86/events/intel/pt.c
450
.reg_off = RTIT_CTL_ADDR1_OFFSET,
arch/x86/events/intel/pt.c
455
.reg_off = RTIT_CTL_ADDR2_OFFSET,
arch/x86/events/intel/pt.c
460
.reg_off = RTIT_CTL_ADDR3_OFFSET,
arch/x86/events/intel/pt.c
499
rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off;
arch/x86/kernel/unwind_orc.c
463
static bool get_reg(struct unwind_state *state, unsigned int reg_off,
arch/x86/kernel/unwind_orc.c
466
unsigned int reg = reg_off/8;
arch/x86/kvm/lapic.c
84
static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
arch/x86/kvm/lapic.c
86
apic_set_reg(apic->regs, reg_off, val);
arch/x86/kvm/lapic.h
171
static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
arch/x86/kvm/lapic.h
173
return apic_get_reg(apic->regs, reg_off);
drivers/accel/habanalabs/goya/goya.c
1087
u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
drivers/accel/habanalabs/goya/goya.c
1100
WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
drivers/accel/habanalabs/goya/goya.c
1101
WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
drivers/accel/habanalabs/goya/goya.c
1103
WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
drivers/accel/habanalabs/goya/goya.c
1104
WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
drivers/accel/habanalabs/goya/goya.c
1105
WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
drivers/accel/habanalabs/goya/goya.c
1107
WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
drivers/accel/habanalabs/goya/goya.c
1108
WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
drivers/accel/habanalabs/goya/goya.c
1109
WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
drivers/accel/habanalabs/goya/goya.c
1110
WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
drivers/accel/habanalabs/goya/goya.c
1111
WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
drivers/accel/habanalabs/goya/goya.c
1112
WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
drivers/accel/habanalabs/goya/goya.c
1113
WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
drivers/accel/habanalabs/goya/goya.c
1117
WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
drivers/accel/habanalabs/goya/goya.c
1118
WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
drivers/accel/habanalabs/goya/goya.c
1121
WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
drivers/accel/habanalabs/goya/goya.c
1123
WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
drivers/accel/habanalabs/goya/goya.c
1128
WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
drivers/accel/habanalabs/goya/goya.c
1129
WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
drivers/accel/habanalabs/goya/goya.c
1136
u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
drivers/accel/habanalabs/goya/goya.c
1143
WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
drivers/accel/habanalabs/goya/goya.c
1144
WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
drivers/accel/habanalabs/goya/goya.c
1145
WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
drivers/accel/habanalabs/goya/goya.c
1154
WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
drivers/accel/habanalabs/goya/goya.c
1155
WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
drivers/accel/habanalabs/goya/goya.c
1936
u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
drivers/accel/habanalabs/goya/goya.c
1950
WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
drivers/accel/habanalabs/goya/goya.c
1951
WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
drivers/accel/habanalabs/goya/goya.c
1952
WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
drivers/accel/habanalabs/goya/goya.c
1953
WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
drivers/accel/habanalabs/goya/goya.c
1954
WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
drivers/accel/habanalabs/goya/goya.c
1955
WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
drivers/accel/habanalabs/goya/goya.c
1956
WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
drivers/accel/habanalabs/goya/goya.c
1957
WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
drivers/accel/habanalabs/goya/goya.c
1958
WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
drivers/accel/habanalabs/goya/goya.c
1960
WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
drivers/accel/habanalabs/goya/goya.c
1961
WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
drivers/accel/habanalabs/goya/goya.c
1962
WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
drivers/accel/habanalabs/goya/goya.c
1963
WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
drivers/accel/habanalabs/goya/goya.c
1965
WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
drivers/accel/habanalabs/goya/goya.c
1967
WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
drivers/accel/habanalabs/goya/goya.c
1968
WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
drivers/accel/habanalabs/goya/goya.c
1970
WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
drivers/accel/habanalabs/goya/goya.c
1973
WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
drivers/accel/habanalabs/goya/goya.c
1975
WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
drivers/accel/habanalabs/goya/goya.c
1977
WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
drivers/accel/habanalabs/goya/goya.c
1985
u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
drivers/accel/habanalabs/goya/goya.c
1997
WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
drivers/accel/habanalabs/goya/goya.c
1998
WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
drivers/accel/habanalabs/goya/goya.c
1999
WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
drivers/accel/habanalabs/goya/goya.c
2000
WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
drivers/accel/habanalabs/goya/goya.c
2002
WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
drivers/accel/habanalabs/goya/goya.c
2004
WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
drivers/accel/habanalabs/goya/goya.c
2005
WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
drivers/accel/habanalabs/goya/goya.c
2007
WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
drivers/accel/habanalabs/goya/goya.c
2010
WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
drivers/accel/habanalabs/goya/goya.c
2012
WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
drivers/accel/habanalabs/goya/goya.c
2014
WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
drivers/clk/meson/a1-peripherals.c
1647
.reg_off = CECA_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
1652
.reg_off = CECA_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
1657
.reg_off = CECA_CLK_CTRL1,
drivers/clk/meson/a1-peripherals.c
1662
.reg_off = CECA_CLK_CTRL1,
drivers/clk/meson/a1-peripherals.c
1667
.reg_off = CECA_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
1754
.reg_off = CECB_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
1759
.reg_off = CECB_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
1764
.reg_off = CECB_CLK_CTRL1,
drivers/clk/meson/a1-peripherals.c
1769
.reg_off = CECB_CLK_CTRL1,
drivers/clk/meson/a1-peripherals.c
1774
.reg_off = CECB_CLK_CTRL0,
drivers/clk/meson/a1-peripherals.c
183
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/a1-peripherals.c
188
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/a1-peripherals.c
193
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/a1-peripherals.c
198
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/a1-peripherals.c
203
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/a1-pll.c
103
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/a1-pll.c
108
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/a1-pll.c
113
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/a1-pll.c
118
.reg_off = ANACTRL_HIFIPLL_CTRL1,
drivers/clk/meson/a1-pll.c
123
.reg_off = ANACTRL_HIFIPLL_STS,
drivers/clk/meson/a1-pll.c
128
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/a1-pll.c
133
.reg_off = ANACTRL_HIFIPLL_CTRL2,
drivers/clk/meson/a1-pll.c
32
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/a1-pll.c
37
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/a1-pll.c
42
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/a1-pll.c
47
.reg_off = ANACTRL_FIXPLL_CTRL1,
drivers/clk/meson/a1-pll.c
52
.reg_off = ANACTRL_FIXPLL_STS,
drivers/clk/meson/a1-pll.c
57
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/axg-aoclk.c
104
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/axg-aoclk.c
109
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/axg-aoclk.c
114
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/axg-aoclk.c
94
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/axg-aoclk.c
99
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/axg-audio.c
143
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
148
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
166
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
171
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
176
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
193
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
211
.reg_off = (_reg), \
drivers/clk/meson/axg-audio.c
216
.reg_off = (_reg), \
drivers/clk/meson/axg.c
114
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
119
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
124
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
129
.reg_off = HHI_MPLL_CNTL2,
drivers/clk/meson/axg.c
134
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
139
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
178
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/axg.c
183
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/axg.c
188
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/axg.c
193
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/axg.c
198
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/axg.c
275
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/axg.c
280
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/axg.c
285
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/axg.c
290
.reg_off = HHI_GP0_PLL_CNTL1,
drivers/clk/meson/axg.c
295
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/axg.c
300
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/axg.c
347
.reg_off = HHI_HIFI_PLL_CNTL,
drivers/clk/meson/axg.c
352
.reg_off = HHI_HIFI_PLL_CNTL,
drivers/clk/meson/axg.c
357
.reg_off = HHI_HIFI_PLL_CNTL,
drivers/clk/meson/axg.c
362
.reg_off = HHI_HIFI_PLL_CNTL5,
drivers/clk/meson/axg.c
367
.reg_off = HHI_HIFI_PLL_CNTL,
drivers/clk/meson/axg.c
372
.reg_off = HHI_HIFI_PLL_CNTL,
drivers/clk/meson/axg.c
573
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/axg.c
578
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/axg.c
583
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/axg.c
588
.reg_off = HHI_PLL_TOP_MISC,
drivers/clk/meson/axg.c
623
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/axg.c
628
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/axg.c
633
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/axg.c
638
.reg_off = HHI_PLL_TOP_MISC,
drivers/clk/meson/axg.c
673
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/axg.c
678
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/axg.c
683
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/axg.c
688
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/axg.c
693
.reg_off = HHI_PLL_TOP_MISC,
drivers/clk/meson/axg.c
728
.reg_off = HHI_MPLL3_CNTL0,
drivers/clk/meson/axg.c
733
.reg_off = HHI_MPLL3_CNTL0,
drivers/clk/meson/axg.c
738
.reg_off = HHI_MPLL3_CNTL0,
drivers/clk/meson/axg.c
743
.reg_off = HHI_PLL_TOP_MISC,
drivers/clk/meson/axg.c
796
.reg_off = HHI_PCIE_PLL_CNTL,
drivers/clk/meson/axg.c
801
.reg_off = HHI_PCIE_PLL_CNTL,
drivers/clk/meson/axg.c
806
.reg_off = HHI_PCIE_PLL_CNTL,
drivers/clk/meson/axg.c
811
.reg_off = HHI_PCIE_PLL_CNTL1,
drivers/clk/meson/axg.c
816
.reg_off = HHI_PCIE_PLL_CNTL,
drivers/clk/meson/axg.c
821
.reg_off = HHI_PCIE_PLL_CNTL,
drivers/clk/meson/c3-peripherals.c
103
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/c3-peripherals.c
83
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/c3-peripherals.c
88
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/c3-peripherals.c
93
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/c3-peripherals.c
98
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/c3-pll.c
249
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/c3-pll.c
254
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/c3-pll.c
259
.reg_off = ANACTRL_GP0PLL_CTRL1,
drivers/clk/meson/c3-pll.c
264
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/c3-pll.c
269
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/c3-pll.c
274
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/c3-pll.c
332
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/c3-pll.c
337
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/c3-pll.c
342
.reg_off = ANACTRL_HIFIPLL_CTRL1,
drivers/clk/meson/c3-pll.c
347
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/c3-pll.c
352
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/c3-pll.c
357
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/c3-pll.c
409
.reg_off = ANACTRL_MPLL_CTRL0,
drivers/clk/meson/c3-pll.c
414
.reg_off = ANACTRL_MPLL_CTRL0,
drivers/clk/meson/c3-pll.c
419
.reg_off = ANACTRL_MPLL_CTRL0,
drivers/clk/meson/c3-pll.c
424
.reg_off = ANACTRL_MPLL_CTRL0,
drivers/clk/meson/c3-pll.c
429
.reg_off = ANACTRL_MPLL_CTRL0,
drivers/clk/meson/clk-cpu-dyndiv.c
57
return regmap_update_bits(clk->map, data->div.reg_off,
drivers/clk/meson/g12a-aoclk.c
116
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/g12a-aoclk.c
121
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/g12a-aoclk.c
126
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/g12a-aoclk.c
131
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/g12a-aoclk.c
136
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/g12a-aoclk.c
207
.reg_off = AO_CEC_CLK_CNTL_REG0,
drivers/clk/meson/g12a-aoclk.c
212
.reg_off = AO_CEC_CLK_CNTL_REG0,
drivers/clk/meson/g12a-aoclk.c
217
.reg_off = AO_CEC_CLK_CNTL_REG1,
drivers/clk/meson/g12a-aoclk.c
222
.reg_off = AO_CEC_CLK_CNTL_REG1,
drivers/clk/meson/g12a-aoclk.c
227
.reg_off = AO_CEC_CLK_CNTL_REG0,
drivers/clk/meson/g12a.c
1093
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
drivers/clk/meson/g12a.c
1098
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
drivers/clk/meson/g12a.c
1277
.reg_off = HHI_SYS_CPUB_CLK_CNTL,
drivers/clk/meson/g12a.c
1282
.reg_off = HHI_SYS_CPUB_CLK_CNTL,
drivers/clk/meson/g12a.c
143
.reg_off = HHI_FIX_PLL_CNTL0,
drivers/clk/meson/g12a.c
148
.reg_off = HHI_FIX_PLL_CNTL0,
drivers/clk/meson/g12a.c
153
.reg_off = HHI_FIX_PLL_CNTL0,
drivers/clk/meson/g12a.c
158
.reg_off = HHI_FIX_PLL_CNTL1,
drivers/clk/meson/g12a.c
163
.reg_off = HHI_FIX_PLL_CNTL0,
drivers/clk/meson/g12a.c
168
.reg_off = HHI_FIX_PLL_CNTL0,
drivers/clk/meson/g12a.c
212
.reg_off = HHI_SYS_PLL_CNTL0,
drivers/clk/meson/g12a.c
217
.reg_off = HHI_SYS_PLL_CNTL0,
drivers/clk/meson/g12a.c
222
.reg_off = HHI_SYS_PLL_CNTL0,
drivers/clk/meson/g12a.c
227
.reg_off = HHI_SYS_PLL_CNTL0,
drivers/clk/meson/g12a.c
2316
.reg_off = HHI_MPLL_CNTL1,
drivers/clk/meson/g12a.c
232
.reg_off = HHI_SYS_PLL_CNTL0,
drivers/clk/meson/g12a.c
2321
.reg_off = HHI_MPLL_CNTL1,
drivers/clk/meson/g12a.c
2326
.reg_off = HHI_MPLL_CNTL1,
drivers/clk/meson/g12a.c
2331
.reg_off = HHI_MPLL_CNTL1,
drivers/clk/meson/g12a.c
2369
.reg_off = HHI_MPLL_CNTL3,
drivers/clk/meson/g12a.c
2374
.reg_off = HHI_MPLL_CNTL3,
drivers/clk/meson/g12a.c
2379
.reg_off = HHI_MPLL_CNTL3,
drivers/clk/meson/g12a.c
2384
.reg_off = HHI_MPLL_CNTL3,
drivers/clk/meson/g12a.c
2422
.reg_off = HHI_MPLL_CNTL5,
drivers/clk/meson/g12a.c
2427
.reg_off = HHI_MPLL_CNTL5,
drivers/clk/meson/g12a.c
2432
.reg_off = HHI_MPLL_CNTL5,
drivers/clk/meson/g12a.c
2437
.reg_off = HHI_MPLL_CNTL5,
drivers/clk/meson/g12a.c
2475
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/g12a.c
2480
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/g12a.c
2485
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/g12a.c
2490
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/g12a.c
271
.reg_off = HHI_SYS1_PLL_CNTL0,
drivers/clk/meson/g12a.c
2747
.reg_off = HHI_VID_PLL_CLK_DIV,
drivers/clk/meson/g12a.c
2752
.reg_off = HHI_VID_PLL_CLK_DIV,
drivers/clk/meson/g12a.c
276
.reg_off = HHI_SYS1_PLL_CNTL0,
drivers/clk/meson/g12a.c
281
.reg_off = HHI_SYS1_PLL_CNTL0,
drivers/clk/meson/g12a.c
286
.reg_off = HHI_SYS1_PLL_CNTL0,
drivers/clk/meson/g12a.c
291
.reg_off = HHI_SYS1_PLL_CNTL0,
drivers/clk/meson/g12a.c
3324
.reg_off = HHI_VIID_CLK_DIV,
drivers/clk/meson/g12a.c
3329
.reg_off = HHI_VIID_CLK_DIV,
drivers/clk/meson/g12a.c
3334
.reg_off = HHI_VIID_CLK_DIV,
drivers/clk/meson/g12a.c
3368
.reg_off = HHI_VIID_CLK_CNTL,
drivers/clk/meson/g12a.c
3373
.reg_off = HHI_VIID_CLK_CNTL,
drivers/clk/meson/g12a.c
409
.reg_off = HHI_GP0_PLL_CNTL0,
drivers/clk/meson/g12a.c
414
.reg_off = HHI_GP0_PLL_CNTL0,
drivers/clk/meson/g12a.c
419
.reg_off = HHI_GP0_PLL_CNTL0,
drivers/clk/meson/g12a.c
424
.reg_off = HHI_GP0_PLL_CNTL1,
drivers/clk/meson/g12a.c
429
.reg_off = HHI_GP0_PLL_CNTL0,
drivers/clk/meson/g12a.c
434
.reg_off = HHI_GP0_PLL_CNTL0,
drivers/clk/meson/g12a.c
474
.reg_off = HHI_GP1_PLL_CNTL0,
drivers/clk/meson/g12a.c
479
.reg_off = HHI_GP1_PLL_CNTL0,
drivers/clk/meson/g12a.c
484
.reg_off = HHI_GP1_PLL_CNTL0,
drivers/clk/meson/g12a.c
489
.reg_off = HHI_GP1_PLL_CNTL1,
drivers/clk/meson/g12a.c
494
.reg_off = HHI_GP1_PLL_CNTL0,
drivers/clk/meson/g12a.c
499
.reg_off = HHI_GP1_PLL_CNTL0,
drivers/clk/meson/g12a.c
549
.reg_off = HHI_HIFI_PLL_CNTL0,
drivers/clk/meson/g12a.c
554
.reg_off = HHI_HIFI_PLL_CNTL0,
drivers/clk/meson/g12a.c
559
.reg_off = HHI_HIFI_PLL_CNTL0,
drivers/clk/meson/g12a.c
564
.reg_off = HHI_HIFI_PLL_CNTL1,
drivers/clk/meson/g12a.c
569
.reg_off = HHI_HIFI_PLL_CNTL0,
drivers/clk/meson/g12a.c
574
.reg_off = HHI_HIFI_PLL_CNTL0,
drivers/clk/meson/g12a.c
641
.reg_off = HHI_PCIE_PLL_CNTL0,
drivers/clk/meson/g12a.c
646
.reg_off = HHI_PCIE_PLL_CNTL0,
drivers/clk/meson/g12a.c
651
.reg_off = HHI_PCIE_PLL_CNTL0,
drivers/clk/meson/g12a.c
656
.reg_off = HHI_PCIE_PLL_CNTL1,
drivers/clk/meson/g12a.c
661
.reg_off = HHI_PCIE_PLL_CNTL0,
drivers/clk/meson/g12a.c
666
.reg_off = HHI_PCIE_PLL_CNTL0,
drivers/clk/meson/g12a.c
735
.reg_off = HHI_HDMI_PLL_CNTL0,
drivers/clk/meson/g12a.c
740
.reg_off = HHI_HDMI_PLL_CNTL0,
drivers/clk/meson/g12a.c
745
.reg_off = HHI_HDMI_PLL_CNTL0,
drivers/clk/meson/g12a.c
750
.reg_off = HHI_HDMI_PLL_CNTL1,
drivers/clk/meson/g12a.c
755
.reg_off = HHI_HDMI_PLL_CNTL0,
drivers/clk/meson/g12a.c
760
.reg_off = HHI_HDMI_PLL_CNTL0,
drivers/clk/meson/gxbb-aoclk.c
100
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/gxbb-aoclk.c
80
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/gxbb-aoclk.c
85
.reg_off = AO_RTC_ALT_CLK_CNTL0,
drivers/clk/meson/gxbb-aoclk.c
90
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/gxbb-aoclk.c
95
.reg_off = AO_RTC_ALT_CLK_CNTL1,
drivers/clk/meson/gxbb.c
122
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
127
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
132
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
137
.reg_off = HHI_MPLL_CNTL2,
drivers/clk/meson/gxbb.c
142
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
147
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
1880
.reg_off = HHI_VID_PLL_CLK_DIV,
drivers/clk/meson/gxbb.c
1885
.reg_off = HHI_VID_PLL_CLK_DIV,
drivers/clk/meson/gxbb.c
199
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
204
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
209
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
214
.reg_off = HHI_HDMI_PLL_CNTL2,
drivers/clk/meson/gxbb.c
219
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
224
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
247
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
252
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
257
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
268
.reg_off = HHI_HDMI_PLL_CNTL2,
drivers/clk/meson/gxbb.c
273
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
278
.reg_off = HHI_HDMI_PLL_CNTL,
drivers/clk/meson/gxbb.c
420
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/gxbb.c
425
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/gxbb.c
430
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/gxbb.c
435
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/gxbb.c
440
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/gxbb.c
517
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
522
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
527
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
532
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
537
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
595
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
600
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
605
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
610
.reg_off = HHI_GP0_PLL_CNTL1,
drivers/clk/meson/gxbb.c
615
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
620
.reg_off = HHI_GP0_PLL_CNTL,
drivers/clk/meson/gxbb.c
826
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/gxbb.c
831
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/gxbb.c
836
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/gxbb.c
854
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/gxbb.c
859
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/gxbb.c
864
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/gxbb.c
905
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/gxbb.c
910
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/gxbb.c
915
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/gxbb.c
947
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/gxbb.c
952
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/gxbb.c
957
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/meson8-ddr.c
29
.reg_off = AM_DDR_PLL_CNTL,
drivers/clk/meson/meson8-ddr.c
34
.reg_off = AM_DDR_PLL_CNTL,
drivers/clk/meson/meson8-ddr.c
39
.reg_off = AM_DDR_PLL_CNTL,
drivers/clk/meson/meson8-ddr.c
44
.reg_off = AM_DDR_PLL_CNTL,
drivers/clk/meson/meson8-ddr.c
49
.reg_off = AM_DDR_PLL_CNTL,
drivers/clk/meson/meson8b.c
125
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
130
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
135
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
140
.reg_off = HHI_MPLL_CNTL2,
drivers/clk/meson/meson8b.c
145
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
150
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
2053
.reg_off = HHI_GP_PLL_CNTL,
drivers/clk/meson/meson8b.c
2058
.reg_off = HHI_GP_PLL_CNTL,
drivers/clk/meson/meson8b.c
2063
.reg_off = HHI_GP_PLL_CNTL,
drivers/clk/meson/meson8b.c
2068
.reg_off = HHI_GP_PLL_CNTL,
drivers/clk/meson/meson8b.c
2073
.reg_off = HHI_GP_PLL_CNTL,
drivers/clk/meson/meson8b.c
241
.reg_off = HHI_VID_PLL_CNTL,
drivers/clk/meson/meson8b.c
246
.reg_off = HHI_VID_PLL_CNTL,
drivers/clk/meson/meson8b.c
251
.reg_off = HHI_VID_PLL_CNTL,
drivers/clk/meson/meson8b.c
256
.reg_off = HHI_VID_PLL_CNTL2,
drivers/clk/meson/meson8b.c
261
.reg_off = HHI_VID_PLL_CNTL,
drivers/clk/meson/meson8b.c
266
.reg_off = HHI_VID_PLL_CNTL,
drivers/clk/meson/meson8b.c
324
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/meson8b.c
329
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/meson8b.c
334
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/meson8b.c
339
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/meson8b.c
344
.reg_off = HHI_SYS_PLL_CNTL,
drivers/clk/meson/meson8b.c
539
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/meson8b.c
544
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/meson8b.c
549
.reg_off = HHI_MPLL_CNTL7,
drivers/clk/meson/meson8b.c
554
.reg_off = HHI_MPLL_CNTL,
drivers/clk/meson/meson8b.c
588
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/meson8b.c
593
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/meson8b.c
598
.reg_off = HHI_MPLL_CNTL8,
drivers/clk/meson/meson8b.c
632
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/meson8b.c
637
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/meson8b.c
642
.reg_off = HHI_MPLL_CNTL9,
drivers/clk/meson/parm.h
25
u16 reg_off;
drivers/clk/meson/parm.h
34
regmap_read(map, p->reg_off, &val);
drivers/clk/meson/parm.h
41
regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift),
drivers/clk/meson/s4-peripherals.c
104
.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/s4-peripherals.c
109
.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/s4-peripherals.c
114
.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/s4-peripherals.c
119
.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/s4-peripherals.c
124
.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/s4-peripherals.c
340
.reg_off = CLKCTRL_CECA_CTRL0,
drivers/clk/meson/s4-peripherals.c
345
.reg_off = CLKCTRL_CECA_CTRL0,
drivers/clk/meson/s4-peripherals.c
350
.reg_off = CLKCTRL_CECA_CTRL1,
drivers/clk/meson/s4-peripherals.c
355
.reg_off = CLKCTRL_CECA_CTRL1,
drivers/clk/meson/s4-peripherals.c
360
.reg_off = CLKCTRL_CECA_CTRL0,
drivers/clk/meson/s4-peripherals.c
447
.reg_off = CLKCTRL_CECB_CTRL0,
drivers/clk/meson/s4-peripherals.c
452
.reg_off = CLKCTRL_CECB_CTRL0,
drivers/clk/meson/s4-peripherals.c
457
.reg_off = CLKCTRL_CECB_CTRL1,
drivers/clk/meson/s4-peripherals.c
462
.reg_off = CLKCTRL_CECB_CTRL1,
drivers/clk/meson/s4-peripherals.c
467
.reg_off = CLKCTRL_CECB_CTRL0,
drivers/clk/meson/s4-peripherals.c
642
.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
drivers/clk/meson/s4-peripherals.c
647
.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
drivers/clk/meson/s4-pll.c
296
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/s4-pll.c
301
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/s4-pll.c
306
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/s4-pll.c
311
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/s4-pll.c
316
.reg_off = ANACTRL_GP0PLL_CTRL0,
drivers/clk/meson/s4-pll.c
367
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
372
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
377
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
382
.reg_off = ANACTRL_HIFIPLL_CTRL1,
drivers/clk/meson/s4-pll.c
387
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
392
.reg_off = ANACTRL_HIFIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
434
.reg_off = ANACTRL_HDMIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
439
.reg_off = ANACTRL_HDMIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
444
.reg_off = ANACTRL_HDMIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
449
.reg_off = ANACTRL_HDMIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
454
.reg_off = ANACTRL_HDMIPLL_CTRL0,
drivers/clk/meson/s4-pll.c
556
.reg_off = ANACTRL_MPLL_CTRL1,
drivers/clk/meson/s4-pll.c
561
.reg_off = ANACTRL_MPLL_CTRL1,
drivers/clk/meson/s4-pll.c
566
.reg_off = ANACTRL_MPLL_CTRL1,
drivers/clk/meson/s4-pll.c
57
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/s4-pll.c
571
.reg_off = ANACTRL_MPLL_CTRL1,
drivers/clk/meson/s4-pll.c
609
.reg_off = ANACTRL_MPLL_CTRL3,
drivers/clk/meson/s4-pll.c
614
.reg_off = ANACTRL_MPLL_CTRL3,
drivers/clk/meson/s4-pll.c
619
.reg_off = ANACTRL_MPLL_CTRL3,
drivers/clk/meson/s4-pll.c
62
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/s4-pll.c
624
.reg_off = ANACTRL_MPLL_CTRL3,
drivers/clk/meson/s4-pll.c
662
.reg_off = ANACTRL_MPLL_CTRL5,
drivers/clk/meson/s4-pll.c
667
.reg_off = ANACTRL_MPLL_CTRL5,
drivers/clk/meson/s4-pll.c
67
.reg_off = ANACTRL_FIXPLL_CTRL1,
drivers/clk/meson/s4-pll.c
672
.reg_off = ANACTRL_MPLL_CTRL5,
drivers/clk/meson/s4-pll.c
677
.reg_off = ANACTRL_MPLL_CTRL5,
drivers/clk/meson/s4-pll.c
715
.reg_off = ANACTRL_MPLL_CTRL7,
drivers/clk/meson/s4-pll.c
72
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/s4-pll.c
720
.reg_off = ANACTRL_MPLL_CTRL7,
drivers/clk/meson/s4-pll.c
725
.reg_off = ANACTRL_MPLL_CTRL7,
drivers/clk/meson/s4-pll.c
730
.reg_off = ANACTRL_MPLL_CTRL7,
drivers/clk/meson/s4-pll.c
77
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/s4-pll.c
82
.reg_off = ANACTRL_FIXPLL_CTRL0,
drivers/clk/meson/t7-peripherals.c
101
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/t7-peripherals.c
106
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/t7-peripherals.c
197
.reg_off = CECA_CTRL0,
drivers/clk/meson/t7-peripherals.c
202
.reg_off = CECA_CTRL0,
drivers/clk/meson/t7-peripherals.c
207
.reg_off = CECA_CTRL1,
drivers/clk/meson/t7-peripherals.c
212
.reg_off = CECA_CTRL1,
drivers/clk/meson/t7-peripherals.c
217
.reg_off = CECA_CTRL0,
drivers/clk/meson/t7-peripherals.c
303
.reg_off = CECB_CTRL0,
drivers/clk/meson/t7-peripherals.c
308
.reg_off = CECB_CTRL0,
drivers/clk/meson/t7-peripherals.c
313
.reg_off = CECB_CTRL1,
drivers/clk/meson/t7-peripherals.c
318
.reg_off = CECB_CTRL1,
drivers/clk/meson/t7-peripherals.c
323
.reg_off = CECB_CTRL0,
drivers/clk/meson/t7-peripherals.c
86
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/t7-peripherals.c
91
.reg_off = RTC_BY_OSCIN_CTRL0,
drivers/clk/meson/t7-peripherals.c
96
.reg_off = RTC_BY_OSCIN_CTRL1,
drivers/clk/meson/t7-pll.c
101
.reg_off = GP0PLL_CTRL0,
drivers/clk/meson/t7-pll.c
106
.reg_off = GP0PLL_STS,
drivers/clk/meson/t7-pll.c
111
.reg_off = GP0PLL_CTRL0,
drivers/clk/meson/t7-pll.c
165
.reg_off = GP1PLL_CTRL0,
drivers/clk/meson/t7-pll.c
170
.reg_off = GP1PLL_CTRL0,
drivers/clk/meson/t7-pll.c
175
.reg_off = GP1PLL_CTRL0,
drivers/clk/meson/t7-pll.c
180
.reg_off = GP1PLL_STS,
drivers/clk/meson/t7-pll.c
185
.reg_off = GP1PLL_CTRL0,
drivers/clk/meson/t7-pll.c
233
.reg_off = HIFIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
238
.reg_off = HIFIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
243
.reg_off = HIFIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
248
.reg_off = HIFIPLL_CTRL1,
drivers/clk/meson/t7-pll.c
253
.reg_off = HIFIPLL_STS,
drivers/clk/meson/t7-pll.c
258
.reg_off = HIFIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
318
.reg_off = PCIEPLL_CTRL0,
drivers/clk/meson/t7-pll.c
323
.reg_off = PCIEPLL_CTRL0,
drivers/clk/meson/t7-pll.c
328
.reg_off = PCIEPLL_CTRL0,
drivers/clk/meson/t7-pll.c
333
.reg_off = PCIEPLL_CTRL0,
drivers/clk/meson/t7-pll.c
338
.reg_off = PCIEPLL_CTRL0,
drivers/clk/meson/t7-pll.c
422
.reg_off = MPLL_CTRL1,
drivers/clk/meson/t7-pll.c
427
.reg_off = MPLL_CTRL1,
drivers/clk/meson/t7-pll.c
432
.reg_off = MPLL_CTRL1,
drivers/clk/meson/t7-pll.c
437
.reg_off = MPLL_CTRL1,
drivers/clk/meson/t7-pll.c
475
.reg_off = MPLL_CTRL3,
drivers/clk/meson/t7-pll.c
480
.reg_off = MPLL_CTRL3,
drivers/clk/meson/t7-pll.c
485
.reg_off = MPLL_CTRL3,
drivers/clk/meson/t7-pll.c
490
.reg_off = MPLL_CTRL3,
drivers/clk/meson/t7-pll.c
528
.reg_off = MPLL_CTRL5,
drivers/clk/meson/t7-pll.c
533
.reg_off = MPLL_CTRL5,
drivers/clk/meson/t7-pll.c
538
.reg_off = MPLL_CTRL5,
drivers/clk/meson/t7-pll.c
543
.reg_off = MPLL_CTRL5,
drivers/clk/meson/t7-pll.c
581
.reg_off = MPLL_CTRL7,
drivers/clk/meson/t7-pll.c
586
.reg_off = MPLL_CTRL7,
drivers/clk/meson/t7-pll.c
591
.reg_off = MPLL_CTRL7,
drivers/clk/meson/t7-pll.c
596
.reg_off = MPLL_CTRL7,
drivers/clk/meson/t7-pll.c
639
.reg_off = HDMIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
644
.reg_off = HDMIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
649
.reg_off = HDMIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
654
.reg_off = HDMIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
659
.reg_off = HDMIPLL_CTRL0,
drivers/clk/meson/t7-pll.c
728
.reg_off = MCLK_PLL_CNTL0,
drivers/clk/meson/t7-pll.c
733
.reg_off = MCLK_PLL_CNTL0,
drivers/clk/meson/t7-pll.c
738
.reg_off = MCLK_PLL_CNTL0,
drivers/clk/meson/t7-pll.c
743
.reg_off = MCLK_PLL_CNTL0,
drivers/clk/meson/t7-pll.c
748
.reg_off = MCLK_PLL_CNTL0,
drivers/clk/meson/t7-pll.c
753
.reg_off = MCLK_PLL_CNTL2,
drivers/clk/meson/t7-pll.c
91
.reg_off = GP0PLL_CTRL0,
drivers/clk/meson/t7-pll.c
96
.reg_off = GP0PLL_CTRL0,
drivers/clk/stm32/clk-stm32mp1.c
1180
.reg_off = _offset,\
drivers/clk/stm32/clk-stm32mp1.c
1208
.reg_off = _offset,\
drivers/clk/stm32/clk-stm32mp1.c
1229
.reg_off = _offset,\
drivers/clk/stm32/clk-stm32mp1.c
1292
.reg_off = _gate_offset,\
drivers/clk/stm32/clk-stm32mp1.c
1330
.reg_off = _div_offset,\
drivers/clk/stm32/clk-stm32mp1.c
1350
.reg_off = _offset,\
drivers/clk/stm32/clk-stm32mp1.c
1520
.reg_off = _gate_offset,\
drivers/clk/stm32/clk-stm32mp1.c
1704
.reg_off = _offset,\
drivers/clk/stm32/clk-stm32mp1.c
341
u32 reg_off;
drivers/clk/stm32/clk-stm32mp1.c
352
u32 reg_off;
drivers/clk/stm32/clk-stm32mp1.c
360
u32 reg_off;
drivers/clk/stm32/clk-stm32mp1.c
403
gate_cfg->reg_off + base,
drivers/clk/stm32/clk-stm32mp1.c
434
div_cfg->reg_off + base,
drivers/clk/stm32/clk-stm32mp1.c
452
mux_cfg->reg_off + base, mux_cfg->shift,
drivers/clk/stm32/clk-stm32mp1.c
497
mmux->mux.reg = cfg->mux->reg_off + base;
drivers/clk/stm32/clk-stm32mp1.c
512
mux->reg = cfg->mux->reg_off + base;
drivers/clk/stm32/clk-stm32mp1.c
535
div->reg = cfg->div->reg_off + base;
drivers/clk/stm32/clk-stm32mp1.c
558
mgate->gate.reg = cfg->gate->reg_off + base;
drivers/clk/stm32/clk-stm32mp1.c
573
gate->reg = cfg->gate->reg_off + base;
drivers/crypto/intel/keembay/ocs-hcu.c
376
int reg_off;
drivers/crypto/intel/keembay/ocs-hcu.c
379
for (reg_off = 0; reg_off < OCS_HCU_HW_KEY_LEN; reg_off += sizeof(u32))
drivers/crypto/intel/keembay/ocs-hcu.c
380
writel(0, hcu_dev->io_base + OCS_HCU_KEY_0 + reg_off);
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
25
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
26
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
24
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
24
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
24
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
25
[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
26
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
27
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
24
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
25
[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
26
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
27
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
24
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
25
[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
26
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
27
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
26
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
27
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
28
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
29
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
30
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
31
[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
32
[DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
33
[DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
34
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
35
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
36
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
37
[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
27
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
28
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
29
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
30
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
31
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
32
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
33
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
34
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
35
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
36
[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
26
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
27
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
28
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
29
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
30
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
31
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
26
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
27
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
28
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
29
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
30
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
27
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
28
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
29
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
30
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
31
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
32
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
33
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
34
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
15
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
16
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
17
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
18
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
19
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
27
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
28
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
29
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
30
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
31
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
32
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
33
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
34
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
35
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
27
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
28
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
29
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
30
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
31
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
32
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
33
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
34
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
35
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
27
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
28
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
29
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
30
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
31
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
32
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
24
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
25
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
26
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
27
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
28
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
29
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
26
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
27
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
28
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
29
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
25
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
26
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
27
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
28
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
29
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
30
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
31
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
32
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
33
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
34
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
24
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
25
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
26
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
27
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
24
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
25
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
26
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
27
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
28
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
29
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
30
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
23
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
24
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
24
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
25
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
25
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
26
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
27
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
28
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
29
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
30
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
31
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
32
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
33
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
34
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
24
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
25
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
26
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
27
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
28
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
25
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
26
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
27
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
28
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
29
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
30
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
31
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
32
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
33
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
25
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
26
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
27
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
28
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
29
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
30
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
31
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
32
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
33
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
34
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
24
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
25
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
26
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
27
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
28
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
29
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
30
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
31
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
32
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
33
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
25
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
25
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
24
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
387
u32 reg_off;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
623
.reg_off = SSPP_CLK_CTRL,
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
287
.reg_off = SSPP_CMN_CLK_CTRL,
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
105
name, reg_off, val);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
106
writel_relaxed(val, c->blk_addr + reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
109
int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
111
return readl_relaxed(c->blk_addr + reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
565
reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
572
DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
98
u32 reg_off,
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
341
u32 reg_off,
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
344
int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
100
reg_off += (xin_id / 4) * 4;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
102
reg_val = DPU_REG_READ(c, reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
105
DPU_REG_WRITE(c, reg_off, reg_val);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
113
u32 reg_off;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
118
reg_off = VBIF_IN_RD_LIM_CONF0;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
120
reg_off = VBIF_IN_WR_LIM_CONF0;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
122
reg_off += (xin_id / 4) * 4;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
124
reg_val = DPU_REG_READ(c, reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
61
u32 reg_off;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
76
reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
78
reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
81
reg_val = DPU_REG_READ(c, reg_off);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
84
DPU_REG_WRITE(c, reg_off, reg_val);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
92
u32 reg_off;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
96
reg_off = VBIF_IN_RD_LIM_CONF0;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
98
reg_off = VBIF_IN_WR_LIM_CONF0;
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
198
.reg_off = WB_CLK_CTRL,
drivers/iio/magnetometer/yamaha-yas530.c
1427
goto reg_off;
drivers/iio/magnetometer/yamaha-yas530.c
1505
reg_off:
drivers/infiniband/hw/efa/efa_admin_cmds_defs.h
1028
u16 reg_off;
drivers/infiniband/hw/efa/efa_com.c
109
read_resp->reg_off);
drivers/infiniband/hw/efa/efa_com.c
114
if (read_resp->reg_off != offset) {
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
3963
unsigned int reg_off, unsigned int ack_off)
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
3967
writel_relaxed(val, smmu->base + reg_off);
drivers/media/i2c/gc2145.c
1008
goto reg_off;
drivers/media/i2c/gc2145.c
1023
reg_off:
drivers/media/i2c/imx219.c
1042
goto reg_off;
drivers/media/i2c/imx219.c
1055
reg_off:
drivers/media/i2c/imx283.c
1187
goto reg_off;
drivers/media/i2c/imx283.c
1197
reg_off:
drivers/mmc/host/cavium-octeon.c
213
host->reg_off = 0;
drivers/mmc/host/cavium-thunderx.c
88
host->reg_off = 0x2000;
drivers/mmc/host/cavium.h
37
#define MIO_EMM_CFG(x) (0x00 + x->reg_off)
drivers/mmc/host/cavium.h
38
#define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
drivers/mmc/host/cavium.h
39
#define MIO_EMM_DMA(x) (0x50 + x->reg_off)
drivers/mmc/host/cavium.h
40
#define MIO_EMM_CMD(x) (0x58 + x->reg_off)
drivers/mmc/host/cavium.h
41
#define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
drivers/mmc/host/cavium.h
42
#define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
drivers/mmc/host/cavium.h
43
#define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
drivers/mmc/host/cavium.h
44
#define MIO_EMM_INT(x) (0x78 + x->reg_off)
drivers/mmc/host/cavium.h
45
#define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
drivers/mmc/host/cavium.h
46
#define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
drivers/mmc/host/cavium.h
47
#define MIO_EMM_SAMPLE(x) (0x90 + x->reg_off)
drivers/mmc/host/cavium.h
48
#define MIO_EMM_STS_MASK(x) (0x98 + x->reg_off)
drivers/mmc/host/cavium.h
49
#define MIO_EMM_RCA(x) (0xa0 + x->reg_off)
drivers/mmc/host/cavium.h
50
#define MIO_EMM_INT_EN_SET(x) (0xb0 + x->reg_off)
drivers/mmc/host/cavium.h
51
#define MIO_EMM_INT_EN_CLR(x) (0xb8 + x->reg_off)
drivers/mmc/host/cavium.h
52
#define MIO_EMM_BUF_IDX(x) (0xe0 + x->reg_off)
drivers/mmc/host/cavium.h
53
#define MIO_EMM_BUF_DAT(x) (0xe8 + x->reg_off)
drivers/mmc/host/cavium.h
59
int reg_off;
drivers/mmc/host/sunxi-mmc.c
703
static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
drivers/mmc/host/sunxi-mmc.c
717
writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
drivers/mtd/nand/qpic_common.c
231
int reg_off, const void *vaddr,
drivers/mtd/nand/qpic_common.c
249
offset = nandc->props->bam_offset + reg_off + 4 * i;
drivers/mtd/nand/qpic_common.c
356
int reg_off, const void *vaddr, int size,
drivers/mtd/nand/qpic_common.c
392
slave_conf.src_addr = nandc->base_dma + reg_off;
drivers/mtd/nand/qpic_common.c
400
slave_conf.dst_addr = nandc->base_dma + reg_off;
drivers/mtd/nand/qpic_common.c
516
int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
drivers/mtd/nand/qpic_common.c
522
return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
drivers/mtd/nand/qpic_common.c
537
int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
drivers/mtd/nand/qpic_common.c
543
return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
drivers/mtd/nand/raw/qcom_nandc.c
1067
int reg_off = FLASH_BUF_ACC;
drivers/mtd/nand/raw/qcom_nandc.c
1082
qcom_write_data_dma(nandc, reg_off, data_buf, data_size1,
drivers/mtd/nand/raw/qcom_nandc.c
1084
reg_off += data_size1;
drivers/mtd/nand/raw/qcom_nandc.c
1087
qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size1,
drivers/mtd/nand/raw/qcom_nandc.c
1089
reg_off += oob_size1;
drivers/mtd/nand/raw/qcom_nandc.c
1092
qcom_write_data_dma(nandc, reg_off, data_buf, data_size2,
drivers/mtd/nand/raw/qcom_nandc.c
1094
reg_off += data_size2;
drivers/mtd/nand/raw/qcom_nandc.c
1097
qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
drivers/mtd/nand/raw/qcom_nandc.c
479
int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
drivers/mtd/nand/raw/qcom_nandc.c
524
qcom_read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
drivers/mtd/nand/raw/qcom_nandc.c
525
reg_off += data_size1;
drivers/mtd/nand/raw/qcom_nandc.c
527
qcom_read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
drivers/mtd/nand/raw/qcom_nandc.c
528
reg_off += oob_size1;
drivers/mtd/nand/raw/qcom_nandc.c
530
qcom_read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
drivers/mtd/nand/raw/qcom_nandc.c
531
reg_off += data_size2;
drivers/mtd/nand/raw/qcom_nandc.c
533
qcom_read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
drivers/net/ethernet/amazon/ena/ena_admin_defs.h
1212
u16 reg_off;
drivers/net/ethernet/amazon/ena/ena_com.c
833
mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off);
drivers/net/ethernet/amazon/ena/ena_com.c
838
if (read_resp->reg_off != offset) {
drivers/net/ethernet/broadcom/bnxt/bnxt.c
14034
int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
drivers/net/ethernet/broadcom/bnxt/bnxt.c
14057
req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15042
u32 reg_type, reg_off, delay_msecs;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15046
reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15049
pci_write_config_dword(bp->pdev, reg_off, val);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15052
writel(reg_off & BNXT_GRC_BASE_MASK,
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15054
reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15057
writel(val, bp->bar0 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15060
writel(val, bp->bar1 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2433
u32 reg_type, reg_off, val = 0;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2436
reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2439
pci_read_config_dword(bp->pdev, reg_off, &val);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2442
reg_off = fw_health->mapped_regs[reg_idx];
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2445
val = readl(bp->bar0 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
2448
val = readl(bp->bar1 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2980
int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
drivers/net/ethernet/cavium/liquidio/octeon_device.h
733
#define octeon_write_csr(oct_dev, reg_off, value) \
drivers/net/ethernet/cavium/liquidio/octeon_device.h
734
writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/cavium/liquidio/octeon_device.h
736
#define octeon_write_csr64(oct_dev, reg_off, val64) \
drivers/net/ethernet/cavium/liquidio/octeon_device.h
737
writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/cavium/liquidio/octeon_device.h
739
#define octeon_read_csr(oct_dev, reg_off) \
drivers/net/ethernet/cavium/liquidio/octeon_device.h
740
readl((oct_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/cavium/liquidio/octeon_device.h
742
#define octeon_read_csr64(oct_dev, reg_off) \
drivers/net/ethernet/cavium/liquidio/octeon_device.h
743
readq((oct_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
343
#define octep_write_csr(octep_dev, reg_off, value) \
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
344
writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
346
#define octep_write_csr64(octep_dev, reg_off, val64) \
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
347
writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
349
#define octep_read_csr(octep_dev, reg_off) \
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
350
readl((octep_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
352
#define octep_read_csr64(octep_dev, reg_off) \
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
353
readq((octep_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
311
#define octep_vf_write_csr(octep_vf_dev, reg_off, value) \
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
312
writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
314
#define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
315
writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
317
#define octep_vf_read_csr(octep_vf_dev, reg_off) \
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
318
readl((octep_vf_dev)->mmio.hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
320
#define octep_vf_read_csr64(octep_vf_dev, reg_off) \
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
321
readq((octep_vf_dev)->mmio.hw_addr + (reg_off))
drivers/nvmem/imx-ocotp-ele.c
176
.reg_off = 0x8000,
drivers/nvmem/imx-ocotp-ele.c
191
.reg_off = 0x8000,
drivers/nvmem/imx-ocotp-ele.c
210
.reg_off = 0x8000,
drivers/nvmem/imx-ocotp-ele.c
31
u32 reg_off;
drivers/nvmem/imx-ocotp-ele.c
69
void __iomem *reg = priv->base + priv->data->reg_off;
drivers/pci/controller/cadence/pci-sky1.c
135
struct cdns_plat_pcie_of_data *reg_off;
drivers/pci/controller/cadence/pci-sky1.c
178
reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
drivers/pci/controller/cadence/pci-sky1.c
179
if (!reg_off)
drivers/pci/controller/cadence/pci-sky1.c
182
reg_off->ip_reg_bank_offset = SKY1_IP_REG_BANK;
drivers/pci/controller/cadence/pci-sky1.c
183
reg_off->ip_cfg_ctrl_reg_offset = SKY1_IP_CFG_CTRL_REG_BANK;
drivers/pci/controller/cadence/pci-sky1.c
184
reg_off->axi_mstr_common_offset = SKY1_IP_AXI_MASTER_COMMON;
drivers/pci/controller/cadence/pci-sky1.c
185
reg_off->axi_slave_offset = SKY1_AXI_SLAVE;
drivers/pci/controller/cadence/pci-sky1.c
186
reg_off->axi_master_offset = SKY1_AXI_MASTER;
drivers/pci/controller/cadence/pci-sky1.c
187
reg_off->axi_hls_offset = SKY1_AXI_HLS_REGISTERS;
drivers/pci/controller/cadence/pci-sky1.c
188
reg_off->axi_ras_offset = SKY1_AXI_RAS_REGISTERS;
drivers/pci/controller/cadence/pci-sky1.c
189
reg_off->axi_dti_offset = SKY1_DTI_REGISTERS;
drivers/pci/controller/cadence/pci-sky1.c
190
cdns_pcie->cdns_pcie_reg_offsets = reg_off;
drivers/pci/controller/dwc/pcie-designware-host.c
74
unsigned int reg_off = i * MSI_REG_CTRL_BLOCK_SIZE;
drivers/pci/controller/dwc/pcie-designware-host.c
78
status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off);
drivers/perf/hisilicon/hisi_pcie_pmu.c
161
hisi_pcie_parse_reg_value(struct hisi_pcie_pmu *pcie_pmu, u32 reg_off)
drivers/perf/hisilicon/hisi_pcie_pmu.c
163
u32 val = readl_relaxed(pcie_pmu->base + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
130
int bit_off, reg_off;
drivers/pinctrl/pinctrl-digicolor.c
133
dc_client_sel(group, &reg_off, &bit_off);
drivers/pinctrl/pinctrl-digicolor.c
135
reg = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
138
writeb_relaxed(reg, pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
148
int bit_off, reg_off;
drivers/pinctrl/pinctrl-digicolor.c
151
dc_client_sel(offset, &reg_off, &bit_off);
drivers/pinctrl/pinctrl-digicolor.c
153
reg = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
171
int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
drivers/pinctrl/pinctrl-digicolor.c
177
drive = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
179
writeb_relaxed(drive, pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
191
int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
drivers/pinctrl/pinctrl-digicolor.c
199
drive = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
201
writeb_relaxed(drive, pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
210
int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION);
drivers/pinctrl/pinctrl-digicolor.c
214
input = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
222
int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION);
drivers/pinctrl/pinctrl-digicolor.c
228
output = readb_relaxed(pmap->regs + reg_off);
drivers/pinctrl/pinctrl-digicolor.c
233
writeb_relaxed(output, pmap->regs + reg_off);
drivers/pinctrl/pinctrl-rp1.c
1719
int reg_off,
drivers/pinctrl/pinctrl-rp1.c
1730
regfield.reg = (additive_offset ? regfield.reg : 0) + reg_off;
drivers/pinctrl/pinctrl-rp1.c
1791
int reg_off;
drivers/pinctrl/pinctrl-rp1.c
1797
reg_off = bank->gpio_offset + pin->offset *
drivers/pinctrl/pinctrl-rp1.c
1802
reg_off,
drivers/pinctrl/pinctrl-rp1.c
1812
reg_off = bank->inte_offset;
drivers/pinctrl/pinctrl-rp1.c
1816
reg_off,
drivers/pinctrl/pinctrl-rp1.c
1826
reg_off = bank->rio_offset;
drivers/pinctrl/pinctrl-rp1.c
1830
reg_off,
drivers/pinctrl/pinctrl-rp1.c
1840
reg_off = bank->pads_offset + pin->offset * sizeof(u32);
drivers/pinctrl/pinctrl-rp1.c
1844
reg_off,
drivers/pinctrl/realtek/pinctrl-rtd.c
290
u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off;
drivers/pinctrl/realtek/pinctrl-rtd.c
307
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
320
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
332
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
345
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
358
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
366
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
400
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
403
reg_off += 0x4;
drivers/pinctrl/realtek/pinctrl-rtd.c
418
reg_off = sconfig_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
421
reg_off += 0x4;
drivers/pinctrl/realtek/pinctrl-rtd.c
435
reg_off = sconfig_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
438
reg_off += 0x4;
drivers/pinctrl/realtek/pinctrl-rtd.c
452
reg_off = config_desc->reg_offset;
drivers/pinctrl/realtek/pinctrl-rtd.c
463
ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val);
drivers/pinctrl/spear/pinctrl-plgpio.c
100
regmap_update_bits(regmap, reg_off, mask, mask);
drivers/pinctrl/spear/pinctrl-plgpio.c
106
u32 reg_off = REG_OFFSET(0, reg, pin);
drivers/pinctrl/spear/pinctrl-plgpio.c
110
regmap_update_bits(regmap, reg_off, mask, 0);
drivers/pinctrl/spear/pinctrl-plgpio.c
333
u32 reg_off;
drivers/pinctrl/spear/pinctrl-plgpio.c
350
reg_off = REG_OFFSET(0, plgpio->regs.eit, offset);
drivers/pinctrl/spear/pinctrl-plgpio.c
351
regmap_read(plgpio->regmap, reg_off, &val);
drivers/pinctrl/spear/pinctrl-plgpio.c
355
regmap_write(plgpio->regmap, reg_off, val | (1 << offset));
drivers/pinctrl/spear/pinctrl-plgpio.c
357
regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset));
drivers/pinctrl/spear/pinctrl-plgpio.c
85
u32 reg_off = REG_OFFSET(0, reg, pin);
drivers/pinctrl/spear/pinctrl-plgpio.c
88
regmap_read(regmap, reg_off, &val);
drivers/pinctrl/spear/pinctrl-plgpio.c
96
u32 reg_off = REG_OFFSET(0, reg, pin);
drivers/pinctrl/sunplus/sppctl.c
112
static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
drivers/pinctrl/sunplus/sppctl.c
117
*reg_off = (offset / 32) * 4;
drivers/pinctrl/sunplus/sppctl.c
123
static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
drivers/pinctrl/sunplus/sppctl.c
133
*reg_off = (offset / 16) * 4;
drivers/pinctrl/sunplus/sppctl.c
139
static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val)
drivers/pinctrl/sunplus/sppctl.c
143
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off);
drivers/pinctrl/sunplus/sppctl.c
227
static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz,
drivers/pinctrl/sunplus/sppctl.c
240
writel(reg, pctl->moon1_base + reg_off * 4);
drivers/pinctrl/sunplus/sppctl.c
264
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
266
bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
267
reg = sppctl_first_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
299
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
301
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
302
reg = sppctl_gpio_master_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
310
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
315
bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
316
reg = sppctl_first_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
323
sppctl_first_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
328
sppctl_first_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
338
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, (master == mux_m_gpio));
drivers/pinctrl/sunplus/sppctl.c
339
sppctl_gpio_master_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
346
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
348
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
drivers/pinctrl/sunplus/sppctl.c
349
sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
355
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
357
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
drivers/pinctrl/sunplus/sppctl.c
358
sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
364
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
366
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
367
reg = sppctl_gpio_od_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
376
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
378
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
drivers/pinctrl/sunplus/sppctl.c
379
sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
385
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
387
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
388
reg = sppctl_gpio_oe_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
396
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
399
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
404
reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
406
reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
417
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
419
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 0);
drivers/pinctrl/sunplus/sppctl.c
423
sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
433
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
435
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
drivers/pinctrl/sunplus/sppctl.c
439
sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
446
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
drivers/pinctrl/sunplus/sppctl.c
447
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
456
u32 reg_off, bit_off, reg;
drivers/pinctrl/sunplus/sppctl.c
458
bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
drivers/pinctrl/sunplus/sppctl.c
459
reg = sppctl_gpio_in_readl(spp_gchip, reg_off);
drivers/pinctrl/sunplus/sppctl.c
467
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
469
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
drivers/pinctrl/sunplus/sppctl.c
470
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
drivers/pinctrl/sunplus/sppctl.c
480
u32 reg_off, reg;
drivers/pinctrl/sunplus/sppctl.c
484
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
drivers/pinctrl/sunplus/sppctl.c
485
sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
drivers/rtc/rtc-sh.c
235
static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
drivers/rtc/rtc-sh.c
240
byte = readb(rtc->regbase + reg_off);
drivers/rtc/rtc-sh.c
273
int value, int reg_off)
drivers/rtc/rtc-sh.c
277
writeb(0, rtc->regbase + reg_off);
drivers/rtc/rtc-sh.c
279
writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
drivers/scsi/advansys.c
1878
#define AdvReadByteRegister(iop_base, reg_off) \
drivers/scsi/advansys.c
1879
(ADV_MEM_READB((iop_base) + (reg_off)))
drivers/scsi/advansys.c
1882
#define AdvWriteByteRegister(iop_base, reg_off, byte) \
drivers/scsi/advansys.c
1883
(ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
drivers/scsi/advansys.c
1886
#define AdvReadWordRegister(iop_base, reg_off) \
drivers/scsi/advansys.c
1887
(ADV_MEM_READW((iop_base) + (reg_off)))
drivers/scsi/advansys.c
1890
#define AdvWriteWordRegister(iop_base, reg_off, word) \
drivers/scsi/advansys.c
1891
(ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
drivers/scsi/advansys.c
1894
#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
drivers/scsi/advansys.c
1895
(ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
drivers/scsi/bnx2fc/bnx2fc_hwi.c
1447
u32 reg_off;
drivers/scsi/bnx2fc/bnx2fc_hwi.c
1454
reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
drivers/scsi/bnx2fc/bnx2fc_hwi.c
1455
tgt->ctx_base = ioremap(reg_base + reg_off, 4);
drivers/scsi/bnx2i/bnx2i_hwi.c
2704
u32 reg_off;
drivers/scsi/bnx2i/bnx2i_hwi.c
2715
reg_off = (1 << BNX2X_DB_SHIFT) * (cid_num & 0x1FFFF);
drivers/scsi/bnx2i/bnx2i_hwi.c
2716
ep->qp.ctx_base = ioremap(reg_base + reg_off, 4);
drivers/scsi/bnx2i/bnx2i_hwi.c
2728
reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE
drivers/scsi/bnx2i/bnx2i_hwi.c
2732
reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num);
drivers/scsi/bnx2i/bnx2i_hwi.c
2735
reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num);
drivers/scsi/bnx2i/bnx2i_hwi.c
2737
ep->qp.ctx_base = ioremap(ep->hba->reg_base + reg_off,
drivers/spi/spi-qpic-snand.c
1063
int reg_off = FLASH_BUF_ACC;
drivers/spi/spi-qpic-snand.c
1078
qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
drivers/spi/spi-qpic-snand.c
1080
reg_off += data_size1;
drivers/spi/spi-qpic-snand.c
1083
qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
drivers/spi/spi-qpic-snand.c
1086
reg_off += oob_size1;
drivers/spi/spi-qpic-snand.c
1088
qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
drivers/spi/spi-qpic-snand.c
1090
reg_off += data_size2;
drivers/spi/spi-qpic-snand.c
1093
qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
drivers/spi/spi-qpic-snand.c
713
int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
drivers/spi/spi-qpic-snand.c
777
qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
drivers/spi/spi-qpic-snand.c
778
reg_off += data_size1;
drivers/spi/spi-qpic-snand.c
780
qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
drivers/spi/spi-qpic-snand.c
781
reg_off += oob_size1;
drivers/spi/spi-qpic-snand.c
783
qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
drivers/spi/spi-qpic-snand.c
784
reg_off += data_size2;
drivers/spi/spi-qpic-snand.c
786
qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
drivers/thermal/loongson2_thermal.c
54
int reg_off = data->chip_data->thermal_sensor_sel * 2;
drivers/thermal/loongson2_thermal.c
59
writew(reg_ctrl, data->ctrl_reg + ctrl_reg + reg_off);
drivers/thermal/samsung/exynos_tmu.c
338
static void exynos_tmu_update_bit(struct exynos_tmu_data *data, int reg_off,
drivers/thermal/samsung/exynos_tmu.c
343
interrupt_en = readl(data->base + reg_off);
drivers/thermal/samsung/exynos_tmu.c
348
writel(interrupt_en, data->base + reg_off);
drivers/thermal/samsung/exynos_tmu.c
351
static void exynos_tmu_update_temp(struct exynos_tmu_data *data, int reg_off,
drivers/thermal/samsung/exynos_tmu.c
361
th = readl(data->base + reg_off);
drivers/thermal/samsung/exynos_tmu.c
364
writel(th, data->base + reg_off);
drivers/thermal/tegra/soctherm.c
528
u32 r, reg_off;
drivers/thermal/tegra/soctherm.c
537
reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
drivers/thermal/tegra/soctherm.c
551
r = readl(ts->regs + reg_off);
drivers/thermal/tegra/soctherm.c
557
writel(r, ts->regs + reg_off);
drivers/tty/serial/fsl_lpuart.c
2880
sport->port.membase += sdata->reg_off;
drivers/tty/serial/fsl_lpuart.c
2881
sport->port.mapbase = res->start + sdata->reg_off;
drivers/tty/serial/fsl_lpuart.c
299
u8 reg_off;
drivers/tty/serial/fsl_lpuart.c
324
.reg_off = IMX_REG_OFF,
drivers/tty/serial/fsl_lpuart.c
331
.reg_off = IMX_REG_OFF,
drivers/tty/serial/fsl_lpuart.c
338
.reg_off = IMX_REG_OFF,
drivers/tty/serial/fsl_lpuart.c
344
.reg_off = IMX_REG_OFF,
include/linux/mtd/nand-qpic-common.h
465
int reg_off, const void *vaddr, int size, unsigned int flags);
include/linux/mtd/nand-qpic-common.h
468
int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off,
include/linux/mtd/nand-qpic-common.h
474
int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
include/linux/mtd/nand-qpic-common.h
476
int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
kernel/bpf/verifier.c
6583
struct tnum reg_off;
kernel/bpf/verifier.c
6600
reg_off = tnum_add(reg->var_off, tnum_const(ip_align + reg->off + off));
kernel/bpf/verifier.c
6601
if (!tnum_is_aligned(reg_off, size)) {
kernel/bpf/verifier.c
6619
struct tnum reg_off;
kernel/bpf/verifier.c
6625
reg_off = tnum_add(reg->var_off, tnum_const(reg->off + off));
kernel/bpf/verifier.c
6626
if (!tnum_is_aligned(reg_off, size)) {
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
287
unsigned int val, reg_off;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
297
reg_off = i2s_data->reg_off_in;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
301
reg_off = i2s_data->reg_off_out;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
321
regmap_update_bits(afe->regmap, reg_off, ~(u32)AFE_I2S_CON_EN, val);
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
501
unsigned int reg_off;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
504
reg_off = i2s_data->reg_off_in;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
510
reg_off = i2s_data->reg_off_out;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
512
regmap_update_bits(afe->regmap, reg_off,
sound/soc/tegra/tegra210_mbdrc.c
788
u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE;
sound/soc/tegra/tegra210_mbdrc.c
791
reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
sound/soc/tegra/tegra210_mbdrc.c
792
reg_off + TEGRA210_MBDRC_CFG_RAM_DATA,
sound/soc/tegra/tegra210_mbdrc.c
850
u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE;
sound/soc/tegra/tegra210_mbdrc.c
853
reg_off + TEGRA210_MBDRC_IIR_CFG,
sound/soc/tegra/tegra210_mbdrc.c
859
reg_off + TEGRA210_MBDRC_IN_ATTACK,
sound/soc/tegra/tegra210_mbdrc.c
865
reg_off + TEGRA210_MBDRC_IN_RELEASE,
sound/soc/tegra/tegra210_mbdrc.c
871
reg_off + TEGRA210_MBDRC_FAST_ATTACK,
sound/soc/tegra/tegra210_mbdrc.c
890
reg_off + TEGRA210_MBDRC_IN_THRESHOLD,
sound/soc/tegra/tegra210_mbdrc.c
907
reg_off + TEGRA210_MBDRC_OUT_THRESHOLD,
sound/soc/tegra/tegra210_mbdrc.c
911
reg_off + TEGRA210_MBDRC_RATIO_1ST,
sound/soc/tegra/tegra210_mbdrc.c
916
reg_off + TEGRA210_MBDRC_RATIO_2ND,
sound/soc/tegra/tegra210_mbdrc.c
921
reg_off + TEGRA210_MBDRC_RATIO_3RD,
sound/soc/tegra/tegra210_mbdrc.c
926
reg_off + TEGRA210_MBDRC_RATIO_4TH,
sound/soc/tegra/tegra210_mbdrc.c
931
reg_off + TEGRA210_MBDRC_RATIO_5TH,
sound/soc/tegra/tegra210_mbdrc.c
936
reg_off + TEGRA210_MBDRC_MAKEUP_GAIN,
sound/soc/tegra/tegra210_mbdrc.c
942
reg_off + TEGRA210_MBDRC_INIT_GAIN,
sound/soc/tegra/tegra210_mbdrc.c
948
reg_off + TEGRA210_MBDRC_GAIN_ATTACK,
sound/soc/tegra/tegra210_mbdrc.c
954
reg_off + TEGRA210_MBDRC_GAIN_RELEASE,
sound/soc/tegra/tegra210_mbdrc.c
960
reg_off + TEGRA210_MBDRC_FAST_RELEASE,
sound/soc/tegra/tegra210_mbdrc.c
966
reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
sound/soc/tegra/tegra210_mbdrc.c
967
reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, 0,
sound/soc/xilinx/xlnx_i2s.c
120
reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
sound/soc/xilinx/xlnx_i2s.c
121
writel(chan_id, drv_data->base + reg_off);
sound/soc/xilinx/xlnx_i2s.c
94
u32 reg_off, chan_id;
tools/lib/bpf/usdt.bpf.h
204
err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off);
tools/lib/bpf/usdt.bpf.h
216
err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off);
tools/lib/bpf/usdt.bpf.h
234
err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off);
tools/lib/bpf/usdt.bpf.h
64
short reg_off;
tools/lib/bpf/usdt.c
1258
{ {"rip", "eip", "", ""}, reg_off(rip, eip) },
tools/lib/bpf/usdt.c
1259
{ {"rax", "eax", "ax", "al"}, reg_off(rax, eax) },
tools/lib/bpf/usdt.c
1260
{ {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) },
tools/lib/bpf/usdt.c
1261
{ {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) },
tools/lib/bpf/usdt.c
1262
{ {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) },
tools/lib/bpf/usdt.c
1263
{ {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) },
tools/lib/bpf/usdt.c
1264
{ {"rdi", "edi", "di", "dil"}, reg_off(rdi, edi) },
tools/lib/bpf/usdt.c
1265
{ {"rbp", "ebp", "bp", "bpl"}, reg_off(rbp, ebp) },
tools/lib/bpf/usdt.c
1266
{ {"rsp", "esp", "sp", "spl"}, reg_off(rsp, esp) },
tools/lib/bpf/usdt.c
1295
int len, reg_off, idx_reg_off, scale = 1;
tools/lib/bpf/usdt.c
1317
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1318
if (reg_off < 0)
tools/lib/bpf/usdt.c
1319
return reg_off;
tools/lib/bpf/usdt.c
1320
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1342
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1343
if (reg_off < 0)
tools/lib/bpf/usdt.c
1344
return reg_off;
tools/lib/bpf/usdt.c
1345
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1350
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1351
if (reg_off < 0)
tools/lib/bpf/usdt.c
1352
return reg_off;
tools/lib/bpf/usdt.c
1353
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1360
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1361
if (reg_off < 0)
tools/lib/bpf/usdt.c
1362
return reg_off;
tools/lib/bpf/usdt.c
1363
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1368
arg->reg_off = 0;
tools/lib/bpf/usdt.c
1393
arg->reg_off = offsetof(user_pt_regs, gprs[reg]);
tools/lib/bpf/usdt.c
1402
arg->reg_off = offsetof(user_pt_regs, gprs[reg]);
tools/lib/bpf/usdt.c
1407
arg->reg_off = 0;
tools/lib/bpf/usdt.c
1435
int len, reg_off;
tools/lib/bpf/usdt.c
1442
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1443
if (reg_off < 0)
tools/lib/bpf/usdt.c
1444
return reg_off;
tools/lib/bpf/usdt.c
1445
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1450
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1451
if (reg_off < 0)
tools/lib/bpf/usdt.c
1452
return reg_off;
tools/lib/bpf/usdt.c
1453
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1458
arg->reg_off = 0;
tools/lib/bpf/usdt.c
1463
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1464
if (reg_off < 0)
tools/lib/bpf/usdt.c
1465
return reg_off;
tools/lib/bpf/usdt.c
1466
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1529
int len, reg_off;
tools/lib/bpf/usdt.c
1536
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1537
if (reg_off < 0)
tools/lib/bpf/usdt.c
1538
return reg_off;
tools/lib/bpf/usdt.c
1539
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1544
arg->reg_off = 0;
tools/lib/bpf/usdt.c
1549
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1550
if (reg_off < 0)
tools/lib/bpf/usdt.c
1551
return reg_off;
tools/lib/bpf/usdt.c
1552
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1600
int len, reg_off;
tools/lib/bpf/usdt.c
1608
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1609
if (reg_off < 0)
tools/lib/bpf/usdt.c
1610
return reg_off;
tools/lib/bpf/usdt.c
1611
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1616
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1617
if (reg_off < 0)
tools/lib/bpf/usdt.c
1618
return reg_off;
tools/lib/bpf/usdt.c
1619
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
1624
arg->reg_off = 0;
tools/lib/bpf/usdt.c
1629
reg_off = calc_pt_regs_off(reg_name);
tools/lib/bpf/usdt.c
1630
if (reg_off < 0)
tools/lib/bpf/usdt.c
1631
return reg_off;
tools/lib/bpf/usdt.c
1632
arg->reg_off = reg_off;
tools/lib/bpf/usdt.c
219
short reg_off;
tools/testing/selftests/kvm/lib/arm64/vgic.c
155
uint64_t reg_off)
tools/testing/selftests/kvm/lib/arm64/vgic.c
159
uint64_t attr = reg_off + reg * 4;
tools/testing/selftests/kvm/riscv/get-reg-list.c
256
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG);
tools/testing/selftests/kvm/riscv/get-reg-list.c
260
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
279
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
285
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE);
tools/testing/selftests/kvm/riscv/get-reg-list.c
289
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
302
reg_off - KVM_REG_RISCV_CORE_REG(regs.t0));
tools/testing/selftests/kvm/riscv/get-reg-list.c
305
reg_off - KVM_REG_RISCV_CORE_REG(regs.s0));
tools/testing/selftests/kvm/riscv/get-reg-list.c
308
reg_off - KVM_REG_RISCV_CORE_REG(regs.a0));
tools/testing/selftests/kvm/riscv/get-reg-list.c
311
reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2);
tools/testing/selftests/kvm/riscv/get-reg-list.c
314
reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3);
tools/testing/selftests/kvm/riscv/get-reg-list.c
319
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
329
static const char *general_csr_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
332
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
357
return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
360
static const char *aia_csr_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
363
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
380
return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
383
static const char *smstateen_csr_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
386
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
391
TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
397
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
tools/testing/selftests/kvm/riscv/get-reg-list.c
398
__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
402
reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
406
return general_csr_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
408
return aia_csr_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
410
return smstateen_csr_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
413
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
419
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER);
tools/testing/selftests/kvm/riscv/get-reg-list.c
423
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
434
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
440
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F);
tools/testing/selftests/kvm/riscv/get-reg-list.c
444
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
447
return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
452
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
458
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D);
tools/testing/selftests/kvm/riscv/get-reg-list.c
462
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
465
return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
470
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
476
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR);
tools/testing/selftests/kvm/riscv/get-reg-list.c
481
if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0))
tools/testing/selftests/kvm/riscv/get-reg-list.c
482
reg_index = reg_off - KVM_REG_RISCV_VECTOR_REG(0);
tools/testing/selftests/kvm/riscv/get-reg-list.c
483
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
499
return strdup_printf("%lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
505
static const char *isa_ext_single_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
588
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
tools/testing/selftests/kvm/riscv/get-reg-list.c
589
return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
591
return kvm_isa_ext_reg_name[reg_off];
tools/testing/selftests/kvm/riscv/get-reg-list.c
594
static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
598
if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
tools/testing/selftests/kvm/riscv/get-reg-list.c
603
return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown);
tools/testing/selftests/kvm/riscv/get-reg-list.c
605
return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown);
tools/testing/selftests/kvm/riscv/get-reg-list.c
608
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
613
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);
tools/testing/selftests/kvm/riscv/get-reg-list.c
614
__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
618
reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
622
return isa_ext_single_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
625
return isa_ext_multi_id_to_str(reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
628
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
634
static const char *sbi_ext_single_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
654
if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name))
tools/testing/selftests/kvm/riscv/get-reg-list.c
655
return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
657
return kvm_sbi_ext_reg_name[reg_off];
tools/testing/selftests/kvm/riscv/get-reg-list.c
660
static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
664
if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST)
tools/testing/selftests/kvm/riscv/get-reg-list.c
669
return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown);
tools/testing/selftests/kvm/riscv/get-reg-list.c
671
return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown);
tools/testing/selftests/kvm/riscv/get-reg-list.c
674
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
679
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT);
tools/testing/selftests/kvm/riscv/get-reg-list.c
680
__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
684
reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
688
return sbi_ext_single_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
691
return sbi_ext_multi_id_to_str(reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
694
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
697
static const char *sbi_sta_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
699
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
703
return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
706
static const char *sbi_fwft_id_to_str(__u64 reg_off)
tools/testing/selftests/kvm/riscv/get-reg-list.c
708
switch (reg_off) {
tools/testing/selftests/kvm/riscv/get-reg-list.c
716
return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
721
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE);
tools/testing/selftests/kvm/riscv/get-reg-list.c
722
__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
726
reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
tools/testing/selftests/kvm/riscv/get-reg-list.c
730
return sbi_sta_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
732
return sbi_fwft_id_to_str(reg_off);
tools/testing/selftests/kvm/riscv/get-reg-list.c
735
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);