readl_relaxed_poll_timeout
ret = readl_relaxed_poll_timeout(dev->regs + NPU_REG_QREAD,
return readl_relaxed_poll_timeout(base + RNG_STAT, val,
return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
WARN_ON(readl_relaxed_poll_timeout(addr, regval, regval & lock,
ret = readl_relaxed_poll_timeout(base + field->offset, reg,
WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
ret = readl_relaxed_poll_timeout(qm->io_base + offset +
ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,
ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,
ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
ret = readl_relaxed_poll_timeout(trng->base + SW_DRBG_STATUS,
ret = readl_relaxed_poll_timeout(trng->base + SW_DRBG_STATUS,
ret = readl_relaxed_poll_timeout(qm->io_base + DAE_AM_RETURN_OFFSET,
ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,
ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,
ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_AES_CSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_AES_CSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_AES_CSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status,
return readl_relaxed_poll_timeout(cryp->base + STARFIVE_PKA_CASR_OFFSET, status,
return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->sr, status,
return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->cr, status,
return readl_relaxed_poll_timeout(hdev->io_base + HASH_STR, status,
return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
ret = readl_relaxed_poll_timeout(addr, tmp,
ret = readl_relaxed_poll_timeout(addr, tmp,
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO,
ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO,
ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val,
err = readl_relaxed_poll_timeout(status_reg, value,
ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET,
ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
return readl_relaxed_poll_timeout(addr, val, !(val & mask),
ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val,
ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE),
ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE),
ret = readl_relaxed_poll_timeout(csi2rx->base +
err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,
ret = readl_relaxed_poll_timeout(csidev->base + STM32_CSI_SR0,
ret = readl_relaxed_poll_timeout(csidev->base + STM32_CSI_SR0,
ret = readl_relaxed_poll_timeout(vcap->regs + DCMIPP_P0SR, status,
ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
ret = readl_relaxed_poll_timeout(host->ioaddr +
rc = readl_relaxed_poll_timeout(host->ioaddr +
ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
ret = readl_relaxed_poll_timeout(pmecc->regs.errloc +
ret = readl_relaxed_poll_timeout(pmecc->regs.base +
ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset,
ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
ret = readl_relaxed_poll_timeout(bch->base + BCH_BHINT, reg,
ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
rc = readl_relaxed_poll_timeout(nfc->regs + NFC_FMCTL, val,
return readl_relaxed_poll_timeout(ptr, reg,
ret = readl_relaxed_poll_timeout(
ret = readl_relaxed_poll_timeout(
ret = readl_relaxed_poll_timeout(addr + PCIE_UL_REG_V_PHY_ST_02,
err = readl_relaxed_poll_timeout(addr, val,
return readl_relaxed_poll_timeout(addr, val,
res = readl_relaxed_poll_timeout(port->phy + PHY_LANE_CFG,
res = readl_relaxed_poll_timeout(port->phy + PHY_LANE_CFG,
ret = readl_relaxed_poll_timeout(port->base + PORT_STATUS, stat,
return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10,
return readl_relaxed_poll_timeout(addr, val, (val & mask),
if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
ret = readl_relaxed_poll_timeout(qproc->reg_base + QDSP6V62SS_BHS_STATUS,
ret = readl_relaxed_poll_timeout(spi_engine->base + SPI_ENGINE_REG_SYNC_ID,
return readl_relaxed_poll_timeout(spi_engine->base + SPI_ENGINE_REG_SYNC_ID,
int ret = readl_relaxed_poll_timeout(reg, val,
return readl_relaxed_poll_timeout(reg, val,
return !readl_relaxed_poll_timeout
return !readl_relaxed_poll_timeout
return !readl_relaxed_poll_timeout(cdns_xspi->iobase +
return readl_relaxed_poll_timeout(cdns_xspi->iobase +
ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
return readl_relaxed_poll_timeout(addr, val,
ret = readl_relaxed_poll_timeout(sensor->base + DTS_DR_OFFSET, periods,
err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,
ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
ret = readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,