read_counter
u64 (*read_counter)(unsigned int idx);
new_raw_count = loongarch_pmu.read_counter(idx);
counter = loongarch_pmu.read_counter(n);
loongarch_pmu.read_counter = loongarch_pmu_read_counter;
counter = mipspmu.read_counter(n);
mipspmu.read_counter = mipsxx_pmu_read_counter_64;
mipspmu.read_counter = mipsxx_pmu_read_counter;
new_raw_count = mipspmu.read_counter(idx);
u64 (*read_counter)(unsigned int idx);
u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
return box->pmu->type->ops->read_counter(box, event);
.read_counter = uncore_msr_read_counter,
.read_counter = intel_generic_uncore_pci_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_msr_read_counter
.read_counter = snb_uncore_imc_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = ivbep_uncore_irp_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = hswep_uncore_irp_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = snbep_uncore_pci_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_msr_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = intel_generic_uncore_pci_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_mmio_read_counter,
.read_counter = uncore_msr_read_counter
.read_counter = snbep_uncore_pci_read_counter
read_counter(&devp->hd_timer->hpet_compare);
mc = read_counter(&hpet->hpet_mc);
write_counter(read_counter(&hpet->hpet_mc),
m = read_counter(&hpet->hpet_mc);
m = read_counter(&hpet->hpet_mc);
t = read_counter(&timer->hpet_compare);
start = read_counter(&hpet->hpet_mc);
m = read_counter(&hpet->hpet_mc);
.read_counter = omap_dm_timer_read_counter,
u64 (*read_counter)(struct fme_perf_priv *priv, u32 event, u32 portid);
.read_counter = basic_read_event_counter,},
.read_counter = cache_read_event_counter,},
.read_counter = fabric_read_event_counter,},
.read_counter = vtd_read_event_counter,},
.read_counter = vtd_sip_read_event_counter,},
now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base);
count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base);
cpu_pmu->read_counter = m1_pmu_read_counter;
new_raw_count = armpmu->read_counter(event);
cpu_pmu->read_counter = armv8pmu_read_counter;
cpu_pmu->read_counter = armv6pmu_read_counter;
cpu_pmu->read_counter = armv7pmu_read_counter;
cpu_pmu->read_counter = xscale1pmu_read_counter;
cpu_pmu->read_counter = xscale2pmu_read_counter;
.read_counter = hisi_cpa_pmu_read_counter,
.read_counter = hisi_ddrc_pmu_read_counter,
.read_counter = hisi_hha_pmu_read_counter,
.read_counter = hisi_l3c_pmu_read_counter,
.read_counter = hisi_mn_pmu_read_counter,
.read_counter = hisi_noc_pmu_read_counter,
.read_counter = hisi_pa_pmu_read_counter,
new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
u64 (*read_counter)(struct hisi_pmu *, struct hw_perf_event *);
.read_counter = hisi_sllc_pmu_read_counter,
.read_counter = hisi_uc_pmu_read_counter,
u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
.read_counter = xgene_pmu_read_counter32,
.read_counter = xgene_pmu_read_counter64,
new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
__be32 read_counter;
u64 (*read_counter)(struct perf_event *event);
unsigned int (*read_counter)(struct omap_dm_timer *timer);
counter_value_pre = read_counter(counter, ctrinfo_arr[counter]);
counter_value_post = read_counter(counter, ctrinfo_arr[counter]);
counter_value_pre = read_counter(counter, ctrinfo_arr[counter]);
counter_value_post = read_counter(counter, ctrinfo_arr[counter]);
counter_value_post = read_counter(counter, ctrinfo_arr[counter]);
counter_value_pre = read_counter(counter, ctrinfo_arr[counter]);