rdmsr_safe
return rdmsr_safe(msr_no, l, h);
if (!rdmsr_safe(MSR_EFER,
if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);
rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);
rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept, &vpid);
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
if (rdmsr_safe(address, &low, &high))
if (!rdmsr_safe(smca_config, &low, &high)) {
if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
if (rdmsr_safe(address, &low, &high))
if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0)
rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h);
if (rdmsr_safe(address, &low, &high))
ret = rdmsr_safe(MSR_IA32_MKTME_KEYID_PARTITIONING, &_nr_mktme_keyids,
rdmsr_safe(MSR_IA32_THERM_CONTROL,
rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config_lo, &dummy);
rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
err = rdmsr_safe(msr, &low, &high);
vector = rdmsr_safe(MSR_IA32_APERF, &msr_val);
vector = rdmsr_safe(MSR_IA32_APERF, &msr_val);
vector = rdmsr_safe(msr->idx, &msr_val);
vector = rdmsr_safe(msr->idx, &ignored);
vec = rdmsr_safe(msr, &val);
vec = rdmsr_safe(msr->index, &val);
vector = rdmsr_safe(MSR_PLATFORM_INFO, &msr_platform_info);
vector = rdmsr_safe(msr, &val);