arch/mips/alchemy/common/clock.c

109

#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))

arch/mips/alchemy/common/platform.c

37

alchemy_uart_enable(CPHYSADDR(port->membase));

arch/mips/alchemy/common/platform.c

42

alchemy_uart_disable(CPHYSADDR(port->membase));

arch/mips/alchemy/devboards/bcsr.c

33

bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));

arch/mips/alchemy/devboards/bcsr.c

34

bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));

arch/mips/bcm47xx/prom.c

79

off = CPHYSADDR((unsigned long)prom_init);

arch/mips/dec/kn01-berr.c

106

address = CPHYSADDR(vaddr);

arch/mips/dec/tc.c

45

tbus->slot_base = CPHYSADDR((long)rex_slot_address(0));

arch/mips/include/asm/addrspace.h

78

#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)

arch/mips/include/asm/addrspace.h

79

#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)

arch/mips/include/asm/addrspace.h

80

#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)

arch/mips/include/asm/addrspace.h

81

#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)

arch/mips/include/asm/addrspace.h

85

#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)

arch/mips/include/asm/addrspace.h

86

#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)

arch/mips/include/asm/addrspace.h

87

#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)

arch/mips/include/asm/addrspace.h

88

#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)

arch/mips/include/asm/addrspace.h

93

#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)

arch/mips/include/asm/addrspace.h

94

#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)

arch/mips/include/asm/addrspace.h

95

#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)

arch/mips/include/asm/addrspace.h

96

#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)

arch/mips/include/asm/mach-au1x00/au1000_dma.h

241

__raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);

arch/mips/include/asm/mach-au1x00/au1000_dma.h

306

__raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);

arch/mips/include/asm/mach-dec/mc146818rtc.h

20

#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)

arch/mips/include/asm/mach-jazz/floppy.h

111

vdma_alloc(CPHYSADDR(mem), size); /* XXX error checking */

arch/mips/include/asm/mach-jazz/floppy.h

118

vdma_free(vdma_phys2log(CPHYSADDR(addr)));

arch/mips/include/asm/mach-jazz/floppy.h

67

vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a)));

arch/mips/include/asm/page.h

161

return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);

arch/mips/include/asm/page.h

171

return CPHYSADDR(x);

arch/mips/jazz/jazzdma.c

83

CPHYSADDR((unsigned long)pgtbl));

arch/mips/lantiq/prom.c

60

if (CPHYSADDR(p) && *p) {

arch/mips/lantiq/xway/vmmc.c

36

(void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,

arch/mips/mm/page.c

620

u64 to_phys = CPHYSADDR((unsigned long)page);

arch/mips/mm/page.c

645

u64 from_phys = CPHYSADDR((unsigned long)from);

arch/mips/mm/page.c

646

u64 to_phys = CPHYSADDR((unsigned long)to);

arch/mips/pci/pci-malta.c

100

GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));

arch/mips/ralink/mt7621.c

68

if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)

arch/mips/ralink/prom.c

50

if (CPHYSADDR(p) && *p) {

arch/mips/sgi-ip22/ip28-berr.c

414

CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp);

arch/mips/sibyte/common/cfe.c

89

initrd_pstart = CPHYSADDR(initrd_start);

arch/mips/sibyte/common/cfe.c

90

initrd_pend = CPHYSADDR(initrd_end);

drivers/gpio/gpio-mm-lantiq.c

93

ltq_ebu_w32(CPHYSADDR((__force void *)chip->regs) | 0x1, LTQ_EBU_ADDRSEL1);

drivers/mtd/nand/raw/xway_nand.c

208

ltq_ebu_w32(CPHYSADDR(data->nandaddr)

drivers/net/ethernet/amd/declance.c

1109

CPHYSADDR(dev->mem_start) << 3);

drivers/net/ethernet/lantiq_etop.c

116

CPHYSADDR(ch->skb[ch->dma.desc]->data);

drivers/net/ethernet/lantiq_etop.c

494

byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);

drivers/tty/serial/lantiq.c

836

if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))

include/linux/lantiq.h

14

#ifndef CPHYSADDR