arch/mips/include/asm/octeon/cvmx-mio-defs.h

2632

uint64_t pps:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

2670

uint64_t pps:1;

drivers/block/zram/zram_drv.c

1016

release_pp_slot(zram, req->pps);

drivers/block/zram/zram_drv.c

1017

req->pps = NULL;

drivers/block/zram/zram_drv.c

1042

struct zram_pp_slot *pps;

drivers/block/zram/zram_drv.c

1046

while ((pps = select_pp_slot(ctl))) {

drivers/block/zram/zram_drv.c

1081

index = pps->index;

drivers/block/zram/zram_drv.c

1103

list_del_init(&pps->entry);

drivers/block/zram/zram_drv.c

1106

req->pps = pps;

drivers/block/zram/zram_drv.c

1120

release_pp_slot(zram, pps);

drivers/block/zram/zram_drv.c

2539

struct zram_pp_slot *pps;

drivers/block/zram/zram_drv.c

263

static void release_pp_slot(struct zram *zram, struct zram_pp_slot *pps)

drivers/block/zram/zram_drv.c

2641

while ((pps = select_pp_slot(ctl))) {

drivers/block/zram/zram_drv.c

2647

slot_lock(zram, pps->index);

drivers/block/zram/zram_drv.c

2648

if (!test_slot_flag(zram, pps->index, ZRAM_PP_SLOT))

drivers/block/zram/zram_drv.c

265

list_del_init(&pps->entry);

drivers/block/zram/zram_drv.c

2651

err = recompress_slot(zram, pps->index, page,

drivers/block/zram/zram_drv.c

2654

slot_unlock(zram, pps->index);

drivers/block/zram/zram_drv.c

2655

release_pp_slot(zram, pps);

drivers/block/zram/zram_drv.c

267

slot_lock(zram, pps->index);

drivers/block/zram/zram_drv.c

268

clear_slot_flag(zram, pps->index, ZRAM_PP_SLOT);

drivers/block/zram/zram_drv.c

269

slot_unlock(zram, pps->index);

drivers/block/zram/zram_drv.c

271

kfree(pps);

drivers/block/zram/zram_drv.c

283

struct zram_pp_slot *pps;

drivers/block/zram/zram_drv.c

285

pps = list_first_entry(&ctl->pp_buckets[idx],

drivers/block/zram/zram_drv.c

288

release_pp_slot(zram, pps);

drivers/block/zram/zram_drv.c

298

struct zram_pp_slot *pps;

drivers/block/zram/zram_drv.c

301

pps = kmalloc_obj(*pps, GFP_NOIO | __GFP_NOWARN);

drivers/block/zram/zram_drv.c

302

if (!pps)

drivers/block/zram/zram_drv.c

305

INIT_LIST_HEAD(&pps->entry);

drivers/block/zram/zram_drv.c

306

pps->index = index;

drivers/block/zram/zram_drv.c

308

bid = get_slot_size(zram, pps->index) / PP_BUCKET_SIZE_RANGE;

drivers/block/zram/zram_drv.c

309

list_add(&pps->entry, &ctl->pp_buckets[bid]);

drivers/block/zram/zram_drv.c

311

set_slot_flag(zram, pps->index, ZRAM_PP_SLOT);

drivers/block/zram/zram_drv.c

317

struct zram_pp_slot *pps = NULL;

drivers/block/zram/zram_drv.c

322

pps = list_first_entry_or_null(&ctl->pp_buckets[idx],

drivers/block/zram/zram_drv.c

325

if (pps)

drivers/block/zram/zram_drv.c

330

return pps;

drivers/block/zram/zram_drv.c

514

struct zram_pp_slot *pps;

drivers/block/zram/zram_drv.c

922

u32 index = req->pps->index;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1317

panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1318

panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1319

panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1320

panel_config->pps.extra_post_t7_ms = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1321

panel_config->pps.extra_pre_t11_ms = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1322

panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1323

panel_config->pps.extra_post_OUI_ms = 0;

drivers/gpu/drm/amd/display/dc/dc_types.h

1312

} pps;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

202

dsc_log_pps(dsc, &dsc20->reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

221

drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

222

dsc_log_pps(dsc, &dsc_reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

290

void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

293

int bits_per_pixel = pps->bits_per_pixel;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

295

DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

296

DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

297

DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

298

DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

299

DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

300

DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

301

DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

302

DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

304

DC_LOG_DSC("\tpic_height %d", pps->pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

305

DC_LOG_DSC("\tpic_width %d", pps->pic_width);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

306

DC_LOG_DSC("\tslice_height %d", pps->slice_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

307

DC_LOG_DSC("\tslice_width %d", pps->slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

308

DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

309

DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

310

DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

311

DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

312

DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

313

DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

314

DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

315

DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

316

DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

317

DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

318

DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

319

DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

320

DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

322

DC_LOG_DSC("\tnative_420 %d", pps->native_420);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

323

DC_LOG_DSC("\tnative_422 %d", pps->native_422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

324

DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

325

DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

326

DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

327

DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

328

DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

329

DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

330

DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

331

DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

332

DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

335

DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

338

DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

339

DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

340

DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

409

dsc_reg_vals->pps.dsc_version_minor = (u8)dsc_cfg->dc_dsc_cfg.version_minor;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

410

dsc_reg_vals->pps.pic_width = (u16)dsc_cfg->pic_width;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

411

dsc_reg_vals->pps.pic_height = (u16)dsc_cfg->pic_height;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

412

dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

413

dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

414

dsc_reg_vals->pps.line_buf_depth = (u8)dsc_cfg->dc_dsc_cfg.linebuf_depth;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

415

dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

419

dsc_reg_vals->pps.slice_width = (u16)((dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

422

dsc_reg_vals->pps.slice_height = (u16)(dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

424

ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

425

if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

432

dsc_reg_vals->pps.bits_per_pixel = (u16)dsc_reg_vals->bpp_x32;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

434

dsc_reg_vals->pps.bits_per_pixel = (u16)(dsc_reg_vals->bpp_x32 >> 1);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

436

dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

437

dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

438

dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

439

dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

441

calc_rc_params(&rc, &dsc_reg_vals->pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

446

if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

454

dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

540

reg_vals->pps.dsc_version_minor = 2;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

541

reg_vals->pps.dsc_version_major = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

542

reg_vals->pps.line_buf_depth = 9;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

543

reg_vals->pps.bits_per_component = 8;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

544

reg_vals->pps.block_pred_enable = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

545

reg_vals->pps.slice_chunk_size = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

546

reg_vals->pps.pic_width = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

547

reg_vals->pps.pic_height = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

548

reg_vals->pps.slice_width = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

549

reg_vals->pps.slice_height = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

550

reg_vals->pps.initial_xmit_delay = 170;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

551

reg_vals->pps.initial_dec_delay = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

552

reg_vals->pps.initial_scale_value = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

553

reg_vals->pps.scale_increment_interval = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

554

reg_vals->pps.scale_decrement_interval = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

555

reg_vals->pps.nfl_bpg_offset = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

556

reg_vals->pps.slice_bpg_offset = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

557

reg_vals->pps.nsl_bpg_offset = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

558

reg_vals->pps.initial_offset = 6144;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

559

reg_vals->pps.final_offset = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

560

reg_vals->pps.flatness_min_qp = 3;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

561

reg_vals->pps.flatness_max_qp = 12;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

562

reg_vals->pps.rc_model_size = 8192;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

563

reg_vals->pps.rc_edge_factor = 6;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

564

reg_vals->pps.rc_quant_incr_limit0 = 11;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

565

reg_vals->pps.rc_quant_incr_limit1 = 11;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

566

reg_vals->pps.rc_tgt_offset_low = 3;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

567

reg_vals->pps.rc_tgt_offset_high = 3;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

578

reg_vals->pps = dsc_params->pps;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

582

reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

601

DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

604

PIC_WIDTH, reg_vals->pps.pic_width,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

605

PIC_HEIGHT, reg_vals->pps.pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

634

DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

635

LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

636

DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

647

BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

650

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

653

PIC_WIDTH, reg_vals->pps.pic_width,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

654

PIC_HEIGHT, reg_vals->pps.pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

657

SLICE_WIDTH, reg_vals->pps.slice_width,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

658

SLICE_HEIGHT, reg_vals->pps.slice_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

661

INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

664

INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

665

SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

668

SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

669

FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

670

SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

673

NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

674

SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

677

NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

678

SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

681

INITIAL_OFFSET, reg_vals->pps.initial_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

682

FINAL_OFFSET, reg_vals->pps.final_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

685

FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

686

FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

687

RC_MODEL_SIZE, reg_vals->pps.rc_model_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

690

RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

691

RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

692

RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

693

RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

694

RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

697

RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

698

RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

699

RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

700

RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

703

RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

704

RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

705

RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

706

RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

709

RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

710

RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

711

RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

712

RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

715

RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

716

RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

717

RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

718

RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

719

RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

722

RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

723

RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

724

RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

725

RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

726

RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

727

RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

730

RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

731

RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

732

RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

733

RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

734

RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

735

RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

738

RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

739

RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

740

RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

741

RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

742

RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

743

RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

746

RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

747

RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

748

RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

749

RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

750

RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

751

RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

754

RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

755

RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

756

RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

757

RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

758

RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

759

RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

762

RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

763

RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

764

RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

765

RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

766

RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

767

RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

770

RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

771

RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

772

RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

773

RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

774

RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

775

RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

541

struct drm_dsc_config pps;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

576

struct drm_dsc_config *pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

141

dsc_log_pps(dsc, &dsc401->reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

220

DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

253

DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

254

LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

255

DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

266

BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

269

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

272

PIC_WIDTH, reg_vals->pps.pic_width,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

273

PIC_HEIGHT, reg_vals->pps.pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

276

SLICE_WIDTH, reg_vals->pps.slice_width,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

277

SLICE_HEIGHT, reg_vals->pps.slice_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

280

INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

283

INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

284

SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

287

SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

288

FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

289

SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

292

NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

293

SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

296

NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

297

SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

300

INITIAL_OFFSET, reg_vals->pps.initial_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

301

FINAL_OFFSET, reg_vals->pps.final_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

304

FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

305

FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

306

RC_MODEL_SIZE, reg_vals->pps.rc_model_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

309

RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

310

RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

311

RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

312

RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

313

RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

316

RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

317

RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

318

RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

319

RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

322

RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

323

RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

324

RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

325

RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

328

RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

329

RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

330

RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

331

RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

334

RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

335

RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

336

RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

337

RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

338

RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

341

RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

342

RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

343

RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

344

RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

345

RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

346

RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

349

RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

350

RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

351

RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

352

RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

353

RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

354

RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

357

RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

358

RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

359

RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

360

RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

361

RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

362

RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

365

RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

366

RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

367

RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

368

RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

369

RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

370

RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

373

RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

374

RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

375

RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

376

RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

377

RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

378

RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

381

RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

382

RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

383

RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

384

RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

385

RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

386

RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

389

RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

390

RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

391

RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

392

RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

393

RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

394

RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h

42

struct drm_dsc_config pps;

drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h

51

int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

40

void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

46

u16 drm_bpp = pps->bits_per_pixel;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

47

int slice_width = pps->slice_width;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

48

int slice_height = pps->slice_height;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

50

mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 :

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

51

(pps->native_422 ? CM_422 :

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

52

pps->native_420 ? CM_420 : CM_444));

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

53

bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10)

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

56

is_navite_422_or_420 = pps->native_422 || pps->native_420;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c

61

pps->dsc_version_minor);

drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h

32

void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

105

dsc_params->pps = *pps;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

106

dsc_params->pps.initial_scale_value = (u8)(8 * rc->rc_model_size /

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

109

copy_pps_fields(&dsc_cfg, &dsc_params->pps);

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

112

dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64;

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

119

copy_pps_fields(&dsc_params->pps, &dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c

98

int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1092

post_T7_delay += link->panel_config.pps.extra_post_t7_ms;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1118

pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

800

if (link->panel_config.pps.extra_t3_ms > 0) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

801

int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

875

link->panel_config.pps.extra_t12_ms;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

981

t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2102

post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

447

if (link && link->panel_config.pps.extra_delay_backlight_off > 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

448

fsleep(link->panel_config.pps.extra_delay_backlight_off * 1000);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

505

if (link && link->panel_config.pps.extra_t7_ms > 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

506

fsleep(link->panel_config.pps.extra_t7_ms * 1000);

drivers/gpu/drm/drm_mipi_dsi.c

1554

const struct drm_dsc_picture_parameter_set *pps)

drivers/gpu/drm/drm_mipi_dsi.c

1563

ret = mipi_dsi_picture_parameter_set(dsi, pps);

drivers/gpu/drm/drm_mipi_dsi.c

721

const struct drm_dsc_picture_parameter_set *pps)

drivers/gpu/drm/drm_mipi_dsi.c

726

.tx_len = sizeof(*pps),

drivers/gpu/drm/drm_mipi_dsi.c

727

.tx_buf = pps,

drivers/gpu/drm/gma500/intel_bios.c

82

dev_priv->edp.pps = *edp_pps;

drivers/gpu/drm/gma500/intel_bios.c

85

dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,

drivers/gpu/drm/gma500/intel_bios.c

86

dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,

drivers/gpu/drm/gma500/intel_bios.c

87

dev_priv->edp.pps.t11_t12);

drivers/gpu/drm/gma500/psb_drv.h

534

struct edp_power_seq pps;

drivers/gpu/drm/i915/display/g4x_dp.c

459

msleep(intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/intel_bios.c

1427

static void vbt_edp_to_pps_delays(struct intel_pps_delays *pps,

drivers/gpu/drm/i915/display/intel_bios.c

1430

pps->power_up = edp_pps->t1_t3;

drivers/gpu/drm/i915/display/intel_bios.c

1431

pps->backlight_on = edp_pps->t8;

drivers/gpu/drm/i915/display/intel_bios.c

1432

pps->backlight_off = edp_pps->t9;

drivers/gpu/drm/i915/display/intel_bios.c

1433

pps->power_down = edp_pps->t10;

drivers/gpu/drm/i915/display/intel_bios.c

1434

pps->power_cycle = edp_pps->t11_t12;

drivers/gpu/drm/i915/display/intel_bios.c

1464

vbt_edp_to_pps_delays(&panel->vbt.edp.pps,

drivers/gpu/drm/i915/display/intel_bios.c

1722

const struct mipi_pps_data *pps;

drivers/gpu/drm/i915/display/intel_bios.c

1747

pps = &start->pps[panel_type];

drivers/gpu/drm/i915/display/intel_bios.c

1754

panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_bios.c

1755

if (!panel->vbt.dsi.pps) {

drivers/gpu/drm/i915/display/intel_bios.c

3391

kfree(panel->vbt.dsi.pps);

drivers/gpu/drm/i915/display/intel_bios.c

3392

panel->vbt.dsi.pps = NULL;

drivers/gpu/drm/i915/display/intel_display_core.h

554

} pps;

drivers/gpu/drm/i915/display/intel_display_driver.c

184

mutex_init(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_display_types.h

1871

struct intel_pps pps;

drivers/gpu/drm/i915/display/intel_display_types.h

349

struct intel_pps_delays pps;

drivers/gpu/drm/i915/display/intel_display_types.h

382

struct mipi_pps_data *pps;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

768

struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

854

intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

855

intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

856

intel_dsi->panel_on_delay = pps->panel_on_delay / 10;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

857

intel_dsi->panel_off_delay = pps->panel_off_delay / 10;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

858

intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;

drivers/gpu/drm/i915/display/intel_lvds.c

158

struct intel_lvds_pps *pps)

drivers/gpu/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_lvds.c

166

pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

167

pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

168

pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

171

pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

172

pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

175

pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

185

pps->delays.power_cycle = val * 1000;

drivers/gpu/drm/i915/display/intel_lvds.c

188

pps->delays.power_up == 0 &&

drivers/gpu/drm/i915/display/intel_lvds.c

189

pps->delays.backlight_on == 0 &&

drivers/gpu/drm/i915/display/intel_lvds.c

190

pps->delays.power_down == 0 &&

drivers/gpu/drm/i915/display/intel_lvds.c

191

pps->delays.backlight_off == 0) {

drivers/gpu/drm/i915/display/intel_lvds.c

196

pps->delays.power_up = 40 * 10;

drivers/gpu/drm/i915/display/intel_lvds.c

197

pps->delays.backlight_on = 200 * 10;

drivers/gpu/drm/i915/display/intel_lvds.c

199

pps->delays.power_down = 35 * 10;

drivers/gpu/drm/i915/display/intel_lvds.c

200

pps->delays.backlight_off = 200 * 10;

drivers/gpu/drm/i915/display/intel_lvds.c

205

pps->delays.power_up, pps->delays.power_down,

drivers/gpu/drm/i915/display/intel_lvds.c

206

pps->delays.power_cycle, pps->delays.backlight_on,

drivers/gpu/drm/i915/display/intel_lvds.c

207

pps->delays.backlight_off, pps->divider,

drivers/gpu/drm/i915/display/intel_lvds.c

208

pps->port, pps->powerdown_on_reset);

drivers/gpu/drm/i915/display/intel_lvds.c

212

struct intel_lvds_pps *pps)

drivers/gpu/drm/i915/display/intel_lvds.c

219

if (pps->powerdown_on_reset)

drivers/gpu/drm/i915/display/intel_lvds.c

224

REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |

drivers/gpu/drm/i915/display/intel_lvds.c

225

REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |

drivers/gpu/drm/i915/display/intel_lvds.c

226

REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));

drivers/gpu/drm/i915/display/intel_lvds.c

229

REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |

drivers/gpu/drm/i915/display/intel_lvds.c

230

REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));

drivers/gpu/drm/i915/display/intel_lvds.c

233

REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |

drivers/gpu/drm/i915/display/intel_lvds.c

235

DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));

drivers/gpu/drm/i915/display/intel_pps.c

1004

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1033

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1042

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

1055

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

1061

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

1068

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

1124

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1157

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1160

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1183

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1191

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1196

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pps.c

1201

if (intel_dp->pps.vlv_pps_pipe != pipe)

drivers/gpu/drm/i915/display/intel_pps.c

1230

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1231

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1238

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1253

pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1269

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1271

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1273

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

1274

intel_dp->pps.vlv_pps_pipe != crtc->pipe) {

drivers/gpu/drm/i915/display/intel_pps.c

1289

intel_dp->pps.vlv_active_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1295

intel_dp->pps.vlv_pps_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1314

intel_dp->pps.vlv_active_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1322

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1337

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

1338

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

1362

intel_dp->pps.panel_power_off_time = 0;

drivers/gpu/drm/i915/display/intel_pps.c

1363

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1364

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1422

struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1460

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1462

if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))

drivers/gpu/drm/i915/display/intel_pps.c

1463

intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);

drivers/gpu/drm/i915/display/intel_pps.c

1465

*bios = intel_dp->pps.bios_pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1476

*vbt = connector->panel.vbt.edp.pps;

drivers/gpu/drm/i915/display/intel_pps.c

1502

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1518

*final = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1520

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1542

intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);

drivers/gpu/drm/i915/display/intel_pps.c

1543

intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);

drivers/gpu/drm/i915/display/intel_pps.c

1544

intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);

drivers/gpu/drm/i915/display/intel_pps.c

1545

intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);

drivers/gpu/drm/i915/display/intel_pps.c

1546

intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);

drivers/gpu/drm/i915/display/intel_pps.c

1550

intel_dp->pps.panel_power_up_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1551

intel_dp->pps.panel_power_down_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1552

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1555

intel_dp->pps.backlight_on_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1556

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1583

const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1585

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1698

intel_dp->pps.initializing = true;

drivers/gpu/drm/i915/display/intel_pps.c

1699

INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

1728

intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,

drivers/gpu/drm/i915/display/intel_pps.c

1731

intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);

drivers/gpu/drm/i915/display/intel_pps.c

1734

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

1743

memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));

drivers/gpu/drm/i915/display/intel_pps.c

1747

intel_dp->pps.initializing = false;

drivers/gpu/drm/i915/display/intel_pps.c

1775

display->pps.mmio_base = PCH_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1777

display->pps.mmio_base = VLV_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1779

display->pps.mmio_base = PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1791

intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1793

intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1795

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1797

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1799

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

184

intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

185

intel_dp->pps.vlv_active_pipe !=

drivers/gpu/drm/i915/display/intel_pps.c

186

intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

188

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

189

pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

192

intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

194

if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

195

pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

212

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

217

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

218

intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

220

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

221

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

233

intel_dp->pps.vlv_pps_pipe = pipe;

drivers/gpu/drm/i915/display/intel_pps.c

250

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

257

int pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

259

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

264

if (!intel_dp->pps.bxt_pps_reset)

drivers/gpu/drm/i915/display/intel_pps.c

267

intel_dp->pps.bxt_pps_reset = false;

drivers/gpu/drm/i915/display/intel_pps.c

325

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

329

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

332

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

333

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

336

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

337

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

341

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {

drivers/gpu/drm/i915/display/intel_pps.c

36

struct intel_pps *pps = &intel_dp->pps;

drivers/gpu/drm/i915/display/intel_pps.c

378

if (intel_dp->pps.pps_idx == 1 &&

drivers/gpu/drm/i915/display/intel_pps.c

39

switch (pps->vlv_pps_pipe) {

drivers/gpu/drm/i915/display/intel_pps.c

406

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

415

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

417

intel_dp->pps.pps_idx = 0;

drivers/gpu/drm/i915/display/intel_pps.c

419

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

drivers/gpu/drm/i915/display/intel_pps.c

420

intel_dp->pps.pps_idx = -1;

drivers/gpu/drm/i915/display/intel_pps.c

423

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

424

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

426

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

427

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

drivers/gpu/drm/i915/display/intel_pps.c

429

if (intel_dp->pps.pps_idx < 0) {

drivers/gpu/drm/i915/display/intel_pps.c

430

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

drivers/gpu/drm/i915/display/intel_pps.c

466

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

469

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

486

intel_dp->pps.bxt_pps_reset = true;

drivers/gpu/drm/i915/display/intel_pps.c

51

MISSING_CASE(pps->vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

511

pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

55

switch (pps->pps_idx) {

drivers/gpu/drm/i915/display/intel_pps.c

550

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

553

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

563

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

566

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

61

MISSING_CASE(pps->pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

614

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

679

panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);

drivers/gpu/drm/i915/display/intel_pps.c

681

remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);

drivers/gpu/drm/i915/display/intel_pps.c

707

wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,

drivers/gpu/drm/i915/display/intel_pps.c

708

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

713

wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,

drivers/gpu/drm/i915/display/intel_pps.c

714

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

726

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

748

bool need_to_disable = !intel_dp->pps.want_panel_vdd;

drivers/gpu/drm/i915/display/intel_pps.c

753

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

755

cancel_delayed_work(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

756

intel_dp->pps.want_panel_vdd = true;

drivers/gpu/drm/i915/display/intel_pps.c

761

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

762

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

78

mutex_lock(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

794

msleep(intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

831

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

833

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

860

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

866

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

87

mutex_unlock(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

874

cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

885

struct intel_pps *pps = container_of(to_delayed_work(__work),

drivers/gpu/drm/i915/display/intel_pps.c

887

struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);

drivers/gpu/drm/i915/display/intel_pps.c

890

if (!intel_dp->pps.want_panel_vdd)

drivers/gpu/drm/i915/display/intel_pps.c

904

if (intel_dp->pps.initializing)

drivers/gpu/drm/i915/display/intel_pps.c

912

delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);

drivers/gpu/drm/i915/display/intel_pps.c

914

&intel_dp->pps.panel_vdd_work, delay);

drivers/gpu/drm/i915/display/intel_pps.c

929

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

931

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

937

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

960

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

98

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

drivers/gpu/drm/i915/display/intel_vbt_defs.h

1017

struct sdvo_lvds_pps pps[4];

drivers/gpu/drm/i915/display/intel_vbt_defs.h

1531

struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */

drivers/gpu/drm/i915/display/intel_vdsc.c

485

static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,

drivers/gpu/drm/i915/display/intel_vdsc.c

498

dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);

drivers/gpu/drm/i915/display/intel_vdsc.c

500

dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);

drivers/gpu/drm/i915/display/intel_vdsc.c

502

dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);

drivers/gpu/drm/i915/display/intel_vdsc.c

506

int pps, u32 pps_val)

drivers/gpu/drm/i915/display/intel_vdsc.c

517

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

drivers/gpu/drm/i915/display/intel_vdsc.c

786

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/i915/display/intel_vdsc.c

792

drm_dsc_pps_payload_pack(&pps, vdsc_cfg);

drivers/gpu/drm/i915/display/intel_vdsc.c

797

mipi_dsi_picture_parameter_set(dsi, &pps);

drivers/gpu/drm/i915/display/intel_vdsc.c

928

static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,

drivers/gpu/drm/i915/display/intel_vdsc.c

941

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

drivers/gpu/drm/i915/display/intel_vdsc.c

957

static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)

drivers/gpu/drm/i915/display/intel_vdsc.c

963

val = intel_dsc_pps_read(crtc_state, pps, &all_equal);

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

58

#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

59

#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

81

#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

82

#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

83

#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

513

.pps = 1920 * 1080 * 30,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

517

.pps = 1920 * 1080 * 60,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

521

.pps = 3840 * 2160 * 30,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

561

u64 pps;

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

293

(u64 *)&cfg->pps);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

307

(u64 *)&cfg->pps);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

63

u64 pps;

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

74

pps = params->frame_rate;

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

75

pps *= params->width;

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

76

pps *= params->height;

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

82

if (pps <= tbl->cfg[i].pps) {

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

91

pps, *ot_lim);

drivers/gpu/drm/omapdrm/dss/dsi.c

3580

int bl, wc, pps, tot;

drivers/gpu/drm/omapdrm/dss/dsi.c

3583

pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */

drivers/gpu/drm/omapdrm/dss/dsi.c

3585

tot = bl + pps;

drivers/gpu/drm/omapdrm/dss/dsi.c

3593

t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,

drivers/gpu/drm/omapdrm/dss/dsi.c

3594

bl, pps, tot,

drivers/gpu/drm/omapdrm/dss/dsi.c

3599

TO_DSI_T(pps),

drivers/gpu/drm/omapdrm/dss/dsi.c

3603

TO_DSI_T(pps),

drivers/gpu/drm/panel/panel-himax-hx83121a.c

115

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-himax-hx83121a.c

116

mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);

drivers/gpu/drm/panel/panel-himax-hx83121a.c

90

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

490

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

550

drm_dsc_pps_payload_pack(&pps, &tianma_il79900a_dsc);

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

552

mipi_dsi_picture_parameter_set_multi(&ctx, &pps);

drivers/gpu/drm/panel/panel-lg-sw43408.c

111

drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc);

drivers/gpu/drm/panel/panel-lg-sw43408.c

113

mipi_dsi_picture_parameter_set_multi(&ctx, &pps);

drivers/gpu/drm/panel/panel-lg-sw43408.c

69

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

131

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

145

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-novatek-nt37801.c

147

ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps);

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

143

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

154

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

156

mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

186

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

201

drm_dsc_pps_payload_pack(&pps, &priv->dsc);

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

204

mipi_dsi_picture_parameter_set_multi(&ctx, &pps);

drivers/gpu/drm/panel/panel-visionox-r66451.c

175

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-visionox-r66451.c

183

drm_dsc_pps_payload_pack(&pps, dsi->dsc);

drivers/gpu/drm/panel/panel-visionox-r66451.c

184

mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

192

struct drm_dsc_picture_parameter_set pps;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

209

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

210

mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);

drivers/infiniband/core/security.c

111

static int check_qp_port_pkey_settings(struct ib_ports_pkeys *pps,

drivers/infiniband/core/security.c

118

if (!pps)

drivers/infiniband/core/security.c

121

if (pps->main.state != IB_PORT_PKEY_NOT_VALID) {

drivers/infiniband/core/security.c

122

ret = get_pkey_and_subnet_prefix(&pps->main,

drivers/infiniband/core/security.c

135

if (pps->alt.state != IB_PORT_PKEY_NOT_VALID) {

drivers/infiniband/core/security.c

136

ret = get_pkey_and_subnet_prefix(&pps->alt,

drivers/media/platform/allegro-dvt/allegro-core.c

1729

struct nal_h264_pps *pps;

drivers/media/platform/allegro-dvt/allegro-core.c

1732

pps = kzalloc_obj(*pps);

drivers/media/platform/allegro-dvt/allegro-core.c

1733

if (!pps)

drivers/media/platform/allegro-dvt/allegro-core.c

1736

pps->pic_parameter_set_id = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1737

pps->seq_parameter_set_id = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1738

pps->entropy_coding_mode_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1739

pps->bottom_field_pic_order_in_frame_present_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1740

pps->num_slice_groups_minus1 = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1741

pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1742

pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1743

pps->weighted_pred_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1744

pps->weighted_bipred_idc = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1745

pps->pic_init_qp_minus26 = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1746

pps->pic_init_qs_minus26 = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1747

pps->chroma_qp_index_offset = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1748

pps->deblocking_filter_control_present_flag = 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1749

pps->constrained_intra_pred_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1750

pps->redundant_pic_cnt_present_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1751

pps->transform_8x8_mode_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1752

pps->pic_scaling_matrix_present_flag = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1753

pps->second_chroma_qp_index_offset = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1755

size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);

drivers/media/platform/allegro-dvt/allegro-core.c

1757

kfree(pps);

drivers/media/platform/allegro-dvt/allegro-core.c

1928

struct nal_hevc_pps *pps;

drivers/media/platform/allegro-dvt/allegro-core.c

1932

pps = kzalloc_obj(*pps);

drivers/media/platform/allegro-dvt/allegro-core.c

1933

if (!pps)

drivers/media/platform/allegro-dvt/allegro-core.c

1936

pps->pps_pic_parameter_set_id = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1937

pps->pps_seq_parameter_set_id = 0;

drivers/media/platform/allegro-dvt/allegro-core.c

1940

pps->tiles_enabled_flag = 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1941

pps->num_tile_columns_minus1 = msg->num_column - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1942

pps->num_tile_rows_minus1 = msg->num_row - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1945

pps->column_width_minus1[i] = msg->tile_width[i] - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1948

pps->row_height_minus1[i] = msg->tile_height[i] - 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1951

pps->loop_filter_across_tiles_enabled_flag =

drivers/media/platform/allegro-dvt/allegro-core.c

1953

pps->pps_loop_filter_across_slices_enabled_flag =

drivers/media/platform/allegro-dvt/allegro-core.c

1955

pps->deblocking_filter_control_present_flag = 1;

drivers/media/platform/allegro-dvt/allegro-core.c

1956

pps->deblocking_filter_override_enabled_flag =

drivers/media/platform/allegro-dvt/allegro-core.c

1958

pps->pps_beta_offset_div2 = BETA_OFFSET_DIV_2;

drivers/media/platform/allegro-dvt/allegro-core.c

1959

pps->pps_tc_offset_div2 = TC_OFFSET_DIV_2;

drivers/media/platform/allegro-dvt/allegro-core.c

1961

pps->lists_modification_present_flag = channel->enable_reordering;

drivers/media/platform/allegro-dvt/allegro-core.c

1963

size = nal_hevc_write_pps(&dev->plat_dev->dev, dest, n, pps);

drivers/media/platform/allegro-dvt/allegro-core.c

1965

kfree(pps);

drivers/media/platform/allegro-dvt/nal-h264.c

283

static void nal_h264_rbsp_pps(struct rbsp *rbsp, struct nal_h264_pps *pps)

drivers/media/platform/allegro-dvt/nal-h264.c

287

rbsp_uev(rbsp, &pps->pic_parameter_set_id);

drivers/media/platform/allegro-dvt/nal-h264.c

288

rbsp_uev(rbsp, &pps->seq_parameter_set_id);

drivers/media/platform/allegro-dvt/nal-h264.c

289

rbsp_bit(rbsp, &pps->entropy_coding_mode_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

290

rbsp_bit(rbsp, &pps->bottom_field_pic_order_in_frame_present_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

291

rbsp_uev(rbsp, &pps->num_slice_groups_minus1);

drivers/media/platform/allegro-dvt/nal-h264.c

292

if (pps->num_slice_groups_minus1 > 0) {

drivers/media/platform/allegro-dvt/nal-h264.c

293

rbsp_uev(rbsp, &pps->slice_group_map_type);

drivers/media/platform/allegro-dvt/nal-h264.c

294

switch (pps->slice_group_map_type) {

drivers/media/platform/allegro-dvt/nal-h264.c

296

for (i = 0; i < pps->num_slice_groups_minus1; i++)

drivers/media/platform/allegro-dvt/nal-h264.c

297

rbsp_uev(rbsp, &pps->run_length_minus1[i]);

drivers/media/platform/allegro-dvt/nal-h264.c

300

for (i = 0; i < pps->num_slice_groups_minus1; i++) {

drivers/media/platform/allegro-dvt/nal-h264.c

301

rbsp_uev(rbsp, &pps->top_left[i]);

drivers/media/platform/allegro-dvt/nal-h264.c

302

rbsp_uev(rbsp, &pps->bottom_right[i]);

drivers/media/platform/allegro-dvt/nal-h264.c

306

rbsp_bit(rbsp, &pps->slice_group_change_direction_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

307

rbsp_uev(rbsp, &pps->slice_group_change_rate_minus1);

drivers/media/platform/allegro-dvt/nal-h264.c

310

rbsp_uev(rbsp, &pps->pic_size_in_map_units_minus1);

drivers/media/platform/allegro-dvt/nal-h264.c

311

for (i = 0; i < pps->pic_size_in_map_units_minus1; i++)

drivers/media/platform/allegro-dvt/nal-h264.c

313

order_base_2(pps->num_slice_groups_minus1 + 1),

drivers/media/platform/allegro-dvt/nal-h264.c

314

&pps->slice_group_id[i]);

drivers/media/platform/allegro-dvt/nal-h264.c

320

rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1);

drivers/media/platform/allegro-dvt/nal-h264.c

321

rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1);

drivers/media/platform/allegro-dvt/nal-h264.c

322

rbsp_bit(rbsp, &pps->weighted_pred_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

323

rbsp_bits(rbsp, 2, &pps->weighted_bipred_idc);

drivers/media/platform/allegro-dvt/nal-h264.c

324

rbsp_sev(rbsp, &pps->pic_init_qp_minus26);

drivers/media/platform/allegro-dvt/nal-h264.c

325

rbsp_sev(rbsp, &pps->pic_init_qs_minus26);

drivers/media/platform/allegro-dvt/nal-h264.c

326

rbsp_sev(rbsp, &pps->chroma_qp_index_offset);

drivers/media/platform/allegro-dvt/nal-h264.c

327

rbsp_bit(rbsp, &pps->deblocking_filter_control_present_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

328

rbsp_bit(rbsp, &pps->constrained_intra_pred_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

329

rbsp_bit(rbsp, &pps->redundant_pic_cnt_present_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

331

rbsp_bit(rbsp, &pps->transform_8x8_mode_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

332

rbsp_bit(rbsp, &pps->pic_scaling_matrix_present_flag);

drivers/media/platform/allegro-dvt/nal-h264.c

333

if (pps->pic_scaling_matrix_present_flag)

drivers/media/platform/allegro-dvt/nal-h264.c

335

rbsp_sev(rbsp, &pps->second_chroma_qp_index_offset);

drivers/media/platform/allegro-dvt/nal-h264.c

445

void *dest, size_t n, struct nal_h264_pps *pps)

drivers/media/platform/allegro-dvt/nal-h264.c

464

nal_h264_rbsp_pps(&rbsp, pps);

drivers/media/platform/allegro-dvt/nal-h264.c

487

struct nal_h264_pps *pps, void *src, size_t n)

drivers/media/platform/allegro-dvt/nal-h264.c

501

nal_h264_rbsp_pps(&rbsp, pps);

drivers/media/platform/allegro-dvt/nal-h264.h

396

void *dest, size_t n, struct nal_h264_pps *pps);

drivers/media/platform/allegro-dvt/nal-h264.h

398

struct nal_h264_pps *pps, void *src, size_t n);

drivers/media/platform/allegro-dvt/nal-h264.h

399

void nal_h264_print_pps(const struct device *dev, struct nal_h264_pps *pps);

drivers/media/platform/allegro-dvt/nal-hevc.c

430

static void nal_hevc_rbsp_pps(struct rbsp *rbsp, struct nal_hevc_pps *pps)

drivers/media/platform/allegro-dvt/nal-hevc.c

434

rbsp_uev(rbsp, &pps->pps_pic_parameter_set_id);

drivers/media/platform/allegro-dvt/nal-hevc.c

435

rbsp_uev(rbsp, &pps->pps_seq_parameter_set_id);

drivers/media/platform/allegro-dvt/nal-hevc.c

436

rbsp_bit(rbsp, &pps->dependent_slice_segments_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

437

rbsp_bit(rbsp, &pps->output_flag_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

438

rbsp_bits(rbsp, 3, &pps->num_extra_slice_header_bits);

drivers/media/platform/allegro-dvt/nal-hevc.c

439

rbsp_bit(rbsp, &pps->sign_data_hiding_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

440

rbsp_bit(rbsp, &pps->cabac_init_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

441

rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1);

drivers/media/platform/allegro-dvt/nal-hevc.c

442

rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1);

drivers/media/platform/allegro-dvt/nal-hevc.c

443

rbsp_sev(rbsp, &pps->init_qp_minus26);

drivers/media/platform/allegro-dvt/nal-hevc.c

444

rbsp_bit(rbsp, &pps->constrained_intra_pred_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

445

rbsp_bit(rbsp, &pps->transform_skip_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

446

rbsp_bit(rbsp, &pps->cu_qp_delta_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

447

if (pps->cu_qp_delta_enabled_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

448

rbsp_uev(rbsp, &pps->diff_cu_qp_delta_depth);

drivers/media/platform/allegro-dvt/nal-hevc.c

449

rbsp_sev(rbsp, &pps->pps_cb_qp_offset);

drivers/media/platform/allegro-dvt/nal-hevc.c

450

rbsp_sev(rbsp, &pps->pps_cr_qp_offset);

drivers/media/platform/allegro-dvt/nal-hevc.c

451

rbsp_bit(rbsp, &pps->pps_slice_chroma_qp_offsets_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

452

rbsp_bit(rbsp, &pps->weighted_pred_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

453

rbsp_bit(rbsp, &pps->weighted_bipred_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

454

rbsp_bit(rbsp, &pps->transquant_bypass_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

455

rbsp_bit(rbsp, &pps->tiles_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

456

rbsp_bit(rbsp, &pps->entropy_coding_sync_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

457

if (pps->tiles_enabled_flag) {

drivers/media/platform/allegro-dvt/nal-hevc.c

458

rbsp_uev(rbsp, &pps->num_tile_columns_minus1);

drivers/media/platform/allegro-dvt/nal-hevc.c

459

rbsp_uev(rbsp, &pps->num_tile_rows_minus1);

drivers/media/platform/allegro-dvt/nal-hevc.c

460

rbsp_bit(rbsp, &pps->uniform_spacing_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

461

if (!pps->uniform_spacing_flag) {

drivers/media/platform/allegro-dvt/nal-hevc.c

462

for (i = 0; i < pps->num_tile_columns_minus1; i++)

drivers/media/platform/allegro-dvt/nal-hevc.c

463

rbsp_uev(rbsp, &pps->column_width_minus1[i]);

drivers/media/platform/allegro-dvt/nal-hevc.c

464

for (i = 0; i < pps->num_tile_rows_minus1; i++)

drivers/media/platform/allegro-dvt/nal-hevc.c

465

rbsp_uev(rbsp, &pps->row_height_minus1[i]);

drivers/media/platform/allegro-dvt/nal-hevc.c

467

rbsp_bit(rbsp, &pps->loop_filter_across_tiles_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

469

rbsp_bit(rbsp, &pps->pps_loop_filter_across_slices_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

470

rbsp_bit(rbsp, &pps->deblocking_filter_control_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

471

if (pps->deblocking_filter_control_present_flag) {

drivers/media/platform/allegro-dvt/nal-hevc.c

472

rbsp_bit(rbsp, &pps->deblocking_filter_override_enabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

473

rbsp_bit(rbsp, &pps->pps_deblocking_filter_disabled_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

474

if (!pps->pps_deblocking_filter_disabled_flag) {

drivers/media/platform/allegro-dvt/nal-hevc.c

475

rbsp_sev(rbsp, &pps->pps_beta_offset_div2);

drivers/media/platform/allegro-dvt/nal-hevc.c

476

rbsp_sev(rbsp, &pps->pps_tc_offset_div2);

drivers/media/platform/allegro-dvt/nal-hevc.c

479

rbsp_bit(rbsp, &pps->pps_scaling_list_data_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

480

if (pps->pps_scaling_list_data_present_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

482

rbsp_bit(rbsp, &pps->lists_modification_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

483

rbsp_uev(rbsp, &pps->log2_parallel_merge_level_minus2);

drivers/media/platform/allegro-dvt/nal-hevc.c

484

rbsp_bit(rbsp, &pps->slice_segment_header_extension_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

485

rbsp_bit(rbsp, &pps->pps_extension_present_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

486

if (pps->pps_extension_present_flag) {

drivers/media/platform/allegro-dvt/nal-hevc.c

487

rbsp_bit(rbsp, &pps->pps_range_extension_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

488

rbsp_bit(rbsp, &pps->pps_multilayer_extension_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

489

rbsp_bit(rbsp, &pps->pps_3d_extension_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

490

rbsp_bit(rbsp, &pps->pps_scc_extension_flag);

drivers/media/platform/allegro-dvt/nal-hevc.c

491

rbsp_bits(rbsp, 4, &pps->pps_extension_4bits);

drivers/media/platform/allegro-dvt/nal-hevc.c

493

if (pps->pps_range_extension_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

495

if (pps->pps_multilayer_extension_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

497

if (pps->pps_3d_extension_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

499

if (pps->pps_scc_extension_flag)

drivers/media/platform/allegro-dvt/nal-hevc.c

501

if (pps->pps_extension_4bits)

drivers/media/platform/allegro-dvt/nal-hevc.c

710

void *dest, size_t n, struct nal_hevc_pps *pps)

drivers/media/platform/allegro-dvt/nal-hevc.c

731

nal_hevc_rbsp_pps(&rbsp, pps);

drivers/media/platform/allegro-dvt/nal-hevc.c

754

struct nal_hevc_pps *pps, void *src, size_t n)

drivers/media/platform/allegro-dvt/nal-hevc.c

775

nal_hevc_rbsp_pps(&rbsp, pps);

drivers/media/platform/allegro-dvt/nal-hevc.h

513

void *dest, size_t n, struct nal_hevc_pps *pps);

drivers/media/platform/allegro-dvt/nal-hevc.h

515

struct nal_hevc_pps *pps, void *src, size_t n);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

100

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

120

pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

121

if (IS_ERR(pps))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

122

return PTR_ERR(pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

132

mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

21

struct mtk_h264_pps_param pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

275

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

291

pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

292

if (IS_ERR(pps))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

293

return PTR_ERR(pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

302

mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

315

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

335

pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

336

if (IS_ERR(pps))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

337

return PTR_ERR(pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

347

mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

44

struct mtk_h264_pps_param pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

715

size_t *bs_size, struct mtk_h264_pps_param *pps)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

725

if (pps->entropy_coding_mode_flag || *bs_size > 20 ||

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

780

&share_info->h264_slice_params.pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

913

&share_info->h264_slice_params.pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

246

struct mtk_hevc_pps_param pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

595

const struct v4l2_ctrl_hevc_pps *pps;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

611

pps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_PPS);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

612

if (IS_ERR(pps))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

613

return PTR_ERR(pps);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

616

vdec_hevc_copy_pps_params(&slice_param->pps, pps);

drivers/media/platform/nvidia/tegra-vde/h264.c

874

if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)

drivers/media/platform/nvidia/tegra-vde/h264.c

886

if (h->pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)

drivers/media/platform/nvidia/tegra-vde/h264.c

889

if (h->pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)

drivers/media/platform/nvidia/tegra-vde/h264.c

892

if (h->pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT)

drivers/media/platform/nvidia/tegra-vde/h264.c

902

h264->num_ref_idx_l0_active_minus1 = h->pps->num_ref_idx_l0_default_active_minus1;

drivers/media/platform/nvidia/tegra-vde/h264.c

903

h264->num_ref_idx_l1_active_minus1 = h->pps->num_ref_idx_l1_default_active_minus1;

drivers/media/platform/nvidia/tegra-vde/h264.c

904

h264->chroma_qp_index_offset = h->pps->chroma_qp_index_offset & 0x1f;

drivers/media/platform/nvidia/tegra-vde/h264.c

905

h264->pic_init_qp = h->pps->pic_init_qp_minus26 + 26;

drivers/media/platform/nvidia/tegra-vde/v4l2.c

64

ctx->h264.pps = data;

drivers/media/platform/nvidia/tegra-vde/vde.h

142

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c

107

const struct v4l2_ctrl_h264_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c

109

if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT))

drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c

209

run->pps = ctrl ? ctrl->p_cur.p : NULL;

drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h

37

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

107

hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

146

WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

147

WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

148

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

150

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

152

WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1,

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

154

WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1,

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

156

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

158

WRITE_PPS(pps->weighted_bipred_idc, WEIGHTED_BIPRED_IDC);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

159

WRITE_PPS(pps->pic_init_qp_minus26, PIC_INIT_QP_MINUS26);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

160

WRITE_PPS(pps->pic_init_qs_minus26, PIC_INIT_QS_MINUS26);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

161

WRITE_PPS(pps->chroma_qp_index_offset, CHROMA_QP_INDEX_OFFSET);

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

162

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

164

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

166

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

168

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

170

WRITE_PPS(pps->second_chroma_qp_index_offset,

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

173

WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c

92

const struct v4l2_ctrl_h264_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

39

const struct v4l2_ctrl_hevc_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

42

for (i = 0; i < pps->num_tile_columns_minus1 + 1; i++)

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

435

run->pps = ctrl ? ctrl->p_cur.p : NULL;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

44

(pps->num_tile_columns_minus1 + 1) -

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

46

(pps->num_tile_columns_minus1 + 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

48

for (i = 0; i < pps->num_tile_rows_minus1 + 1; i++)

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

50

(pps->num_tile_rows_minus1 + 1) -

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

52

(pps->num_tile_rows_minus1 + 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

59

const struct v4l2_ctrl_hevc_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

63

for (i = 0; i < pps->num_tile_columns_minus1; i++) {

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

64

column_width[i] = pps->column_width_minus1[i] + 1;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

70

for (i = 0; i < pps->num_tile_rows_minus1; i++) {

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c

71

row_height[i] = pps->row_height_minus1[i] + 1;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h

47

const struct v4l2_ctrl_hevc_pps *pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

124

const struct v4l2_ctrl_hevc_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

138

hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

193

WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

195

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

197

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

199

WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

200

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

202

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

204

WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

206

WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

208

WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

209

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

211

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

213

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

220

log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

222

WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

223

WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

224

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

226

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

228

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

230

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

232

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

234

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

236

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

238

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

240

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

242

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

244

WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

245

WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

246

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

248

WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

249

WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

251

WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

252

WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

254

if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

256

for (i = 0; i <= pps->num_tile_columns_minus1; i++)

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

257

WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

258

for (i = 0; i <= pps->num_tile_rows_minus1; i++)

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

259

WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

567

reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ?

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

106

hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

145

hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

146

hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

147

hw_ps->pps.entropy_coding_mode_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

148

!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

149

hw_ps->pps.bottom_field_pic_order_in_frame_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

150

!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

151

hw_ps->pps.num_ref_idx_l0_default_active_minus1 =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

152

pps->num_ref_idx_l0_default_active_minus1;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

153

hw_ps->pps.num_ref_idx_l1_default_active_minus1 =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

154

pps->num_ref_idx_l1_default_active_minus1;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

155

hw_ps->pps.weighted_pred_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

156

!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

157

hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

158

hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

159

hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

160

hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

161

hw_ps->pps.deblocking_filter_control_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

162

!!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

163

hw_ps->pps.constrained_intra_pred_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

164

!!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

165

hw_ps->pps.redundant_pic_cnt_present =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

166

!!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

167

hw_ps->pps.transform_8x8_mode_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

168

!!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

169

hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

170

hw_ps->pps.scaling_list_enable_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

171

!!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

178

hw_ps->pps.scaling_list_address = scaling_list_address;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

182

hw_ps->pps.is_longterm |= (1 << i);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

69

struct rkvdec_pps pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c

91

const struct v4l2_ctrl_h264_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

101

struct rkvdec_hevc_pps pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

129

const struct v4l2_ctrl_hevc_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

148

hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

202

hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

203

hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

204

hw_ps->pps.dependent_slice_segments_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

205

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

206

hw_ps->pps.output_flag_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

207

!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

208

hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

209

hw_ps->pps.sign_data_hiding_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

210

!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

211

hw_ps->pps.cabac_init_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

212

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

213

hw_ps->pps.num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

214

hw_ps->pps.num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

215

hw_ps->pps.init_qp_minus26 = pps->init_qp_minus26;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

216

hw_ps->pps.constrained_intra_pred_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

217

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

218

hw_ps->pps.transform_skip_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

219

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

220

hw_ps->pps.cu_qp_delta_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

221

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

222

hw_ps->pps.log2_min_cb_size = log2_min_cb_size +

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

224

pps->diff_cu_qp_delta_depth;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

225

hw_ps->pps.pps_cb_qp_offset = pps->pps_cb_qp_offset;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

226

hw_ps->pps.pps_cr_qp_offset = pps->pps_cr_qp_offset;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

227

hw_ps->pps.pps_slice_chroma_qp_offsets_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

228

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

229

hw_ps->pps.weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

230

hw_ps->pps.weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

231

hw_ps->pps.transquant_bypass_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

232

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

234

tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

235

hw_ps->pps.tiles_enabled_flag = tiles_enabled;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

236

hw_ps->pps.entropy_coding_sync_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

237

!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

238

hw_ps->pps.pps_loop_filter_across_slices_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

239

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

240

hw_ps->pps.loop_filter_across_tiles_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

241

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

242

hw_ps->pps.deblocking_filter_override_enabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

243

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

244

hw_ps->pps.pps_deblocking_filter_disabled_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

245

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

246

hw_ps->pps.pps_beta_offset_div2 = pps->pps_beta_offset_div2;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

247

hw_ps->pps.pps_tc_offset_div2 = pps->pps_tc_offset_div2;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

248

hw_ps->pps.lists_modification_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

249

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

250

hw_ps->pps.log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

251

hw_ps->pps.slice_segment_header_extension_present_flag =

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

252

!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

253

hw_ps->pps.num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 0;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

254

hw_ps->pps.num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 0;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

255

hw_ps->pps.sps_pps_mode = 0;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

256

hw_ps->pps.reserved_bits = 0x3fff;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

257

hw_ps->pps.reserved = 0xffff;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

267

if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c

268

if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) {

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

111

hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

160

rkvdec_set_bw_field(hw_ps->info, PIC_PARAMETER_SET_ID, pps->pic_parameter_set_id);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

161

rkvdec_set_bw_field(hw_ps->info, PPS_SEQ_PARAMETER_SET_ID, pps->seq_parameter_set_id);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

163

!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

165

!!(pps->flags &

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

168

pps->num_ref_idx_l0_default_active_minus1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

170

pps->num_ref_idx_l1_default_active_minus1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

172

!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

173

rkvdec_set_bw_field(hw_ps->info, WEIGHTED_BIPRED_IDC, pps->weighted_bipred_idc);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

174

rkvdec_set_bw_field(hw_ps->info, PIC_INIT_QP_MINUS26, pps->pic_init_qp_minus26);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

175

rkvdec_set_bw_field(hw_ps->info, PIC_INIT_QS_MINUS26, pps->pic_init_qs_minus26);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

176

rkvdec_set_bw_field(hw_ps->info, CHROMA_QP_INDEX_OFFSET, pps->chroma_qp_index_offset);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

178

!!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

180

!!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

182

!!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

184

!!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

186

pps->second_chroma_qp_index_offset);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

188

!!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c

97

const struct v4l2_ctrl_h264_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

136

const struct v4l2_ctrl_hevc_pps *pps = run->pps;

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

219

rkvdec_set_bw_field(hw_ps->info, PIC_PARAMETER_SET_ID, pps->pic_parameter_set_id);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

222

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

224

!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

226

pps->num_extra_slice_header_bits);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

228

!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

230

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

232

pps->num_ref_idx_l0_default_active_minus1 + 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

234

pps->num_ref_idx_l1_default_active_minus1 + 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

235

rkvdec_set_bw_field(hw_ps->info, INIT_QP_MINUS26, pps->init_qp_minus26);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

237

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

239

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

241

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

244

pps->diff_cu_qp_delta_depth);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

245

rkvdec_set_bw_field(hw_ps->info, PPS_CB_QP_OFFSET, pps->pps_cb_qp_offset);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

246

rkvdec_set_bw_field(hw_ps->info, PPS_CR_QP_OFFSET, pps->pps_cr_qp_offset);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

248

!!(pps->flags &

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

251

!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

253

!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

255

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

256

tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

259

!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

261

!!(pps->flags &

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

264

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

266

!!(pps->flags &

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

269

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

270

rkvdec_set_bw_field(hw_ps->info, PPS_BETA_OFFSET_DIV2, pps->pps_beta_offset_div2);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

271

rkvdec_set_bw_field(hw_ps->info, PPS_TC_OFFSET_DIV2, pps->pps_tc_offset_div2);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

273

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

275

pps->log2_parallel_merge_level_minus2 + 2);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

277

!!(pps->flags &

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

280

tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

282

tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 1);

drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c

294

if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) {

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

103

reg = G1_REG_DEC_CTRL6_PPS_ID(pps->pic_parameter_set_id) |

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

104

G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

105

G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

27

const struct v4l2_ctrl_h264_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

58

reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) |

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

59

G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

61

if (pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

69

G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) |

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

76

G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

77

if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

83

if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

90

if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

92

if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

94

if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT)

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

96

if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE)

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

111

const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

114

if (pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT)

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

145

const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

15

const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

18

unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

19

unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

206

!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

208

if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

210

hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

216

hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

217

hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

219

hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

220

hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

222

!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

223

hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

225

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

227

!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

229

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

231

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

233

!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

235

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

239

pps->log2_parallel_merge_level_minus2 + 2);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

25

tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

26

uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

262

hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

264

!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

266

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

268

!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

270

!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

272

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

274

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

276

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

278

!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

280

pps->num_ref_idx_l0_default_active_minus1 + 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

282

pps->num_ref_idx_l1_default_active_minus1 + 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

377

const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

421

!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

423

!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

57

h = pps->row_height_minus1[i] + 1;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

62

tmp_w += pps->column_width_minus1[j] + 1;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

63

*p++ = pps->column_width_minus1[j] + 1;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

86

(pps->column_width_minus1[0] + 1) == 1 &&

drivers/media/platform/verisilicon/hantro_h264.c

206

const struct v4l2_ctrl_h264_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_h264.c

215

if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT))

drivers/media/platform/verisilicon/hantro_h264.c

461

ctrls->pps =

drivers/media/platform/verisilicon/hantro_h264.c

463

if (WARN_ON(!ctrls->pps))

drivers/media/platform/verisilicon/hantro_hevc.c

203

ctrls->pps =

drivers/media/platform/verisilicon/hantro_hevc.c

205

if (WARN_ON(!ctrls->pps))

drivers/media/platform/verisilicon/hantro_hevc.c

80

const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/hantro_hevc.c

82

unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;

drivers/media/platform/verisilicon/hantro_hw.h

138

const struct v4l2_ctrl_hevc_pps *pps;

drivers/media/platform/verisilicon/hantro_hw.h

87

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

198

const struct v4l2_ctrl_h264_pps *pps = ctrls->pps;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

209

reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

261

reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

262

VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

267

reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

271

reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

272

VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

281

reg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

282

VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

283

VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

290

VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

291

VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

292

VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

293

VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) |

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

294

VDPU_REG_TYPE1_QUANT_E(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) |

drivers/media/test-drivers/visl/visl-dec.c

523

trace_v4l2_ctrl_h264_pps(run->h264.pps);

drivers/media/test-drivers/visl/visl-dec.c

541

trace_v4l2_ctrl_hevc_pps(run->hevc.pps);

drivers/media/test-drivers/visl/visl-dec.c

605

run.h264.pps = visl_find_control_data(ctx, V4L2_CID_STATELESS_H264_PPS);

drivers/media/test-drivers/visl/visl-dec.c

613

run.hevc.pps = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_PPS);

drivers/media/test-drivers/visl/visl-dec.h

34

const struct v4l2_ctrl_h264_pps *pps;

drivers/media/test-drivers/visl/visl-dec.h

43

const struct v4l2_ctrl_hevc_pps *pps;

drivers/net/dsa/hirschmann/hellcreek_ptp.c

424

hellcreek->ptp_clock_info.pps = 0;

drivers/net/dsa/mv88e6xxx/ptp.c

503

chip->ptp_clock_info.pps = 0;

drivers/net/dsa/ocelot/felix_vsc9959.c

867

.pps = 0,

drivers/net/ethernet/amazon/ena/ena_phc.c

68

.pps = 0,

drivers/net/ethernet/amd/xgbe/xgbe-ptp.c

120

pps_cfg = &pdata->pps[request->perout.index];

drivers/net/ethernet/amd/xgbe/xgbe.h

1172

struct xgbe_pps_config pps[XGBE_MAX_PPS_OUT];

drivers/net/ethernet/aquantia/atlantic/aq_ptp.c

1250

.pps = 0,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

13806

bp->ptp_clock_info.pps = 0;

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

401

struct bnxt_pps *pps;

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

408

pps = &ptp->pps_info;

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

410

if (pps->pins[pin].state) {

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

411

rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

412

if (!rc && pps->pins[pin].event)

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

414

pps->pins[pin].event);

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

919

.pps = 0,

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

994

ptp_info->pps = 1;

drivers/net/ethernet/broadcom/tg3.c

6348

.pps = 0,

drivers/net/ethernet/cadence/macb_ptp.c

199

.pps = 1,

drivers/net/ethernet/cavium/common/cavium_ptp.c

266

.pps = 0,

drivers/net/ethernet/cavium/liquidio/lio_main.c

1638

lio->ptp_info.pps = 0;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c

409

.pps = 0,

drivers/net/ethernet/emulex/benet/be_main.c

2146

u32 pps, delta;

drivers/net/ethernet/emulex/benet/be_main.c

2186

pps = (((u32)(rx_pkts - aic->rx_pkts_prev) * 1000) / delta) +

drivers/net/ethernet/emulex/benet/be_main.c

2188

eqd = (pps / 15000) << 2;

drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c

80

.pps = 1,

drivers/net/ethernet/freescale/enetc/enetc_ptp.c

18

.pps = 1,

drivers/net/ethernet/freescale/fec_ptp.c

758

fep->ptp_caps.pps = 1;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c

440

ptp->info.pps = 0;

drivers/net/ethernet/intel/e1000e/ptp.c

248

.pps = 0,

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1342

pf->ptp_caps.pps = 1;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1362

pf->ptp_caps.pps = 1;

drivers/net/ethernet/intel/ice/ice_dpll.c

3149

struct ice_dpll *dp = &pf->dplls.pps;

drivers/net/ethernet/intel/ice/ice_dpll.c

3825

struct ice_dpll *dp = &d->pps;

drivers/net/ethernet/intel/ice/ice_dpll.c

3849

pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

3854

pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4091

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4099

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4109

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4118

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4143

&ice_dpll_pin_ufl_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4147

&ice_dpll_pin_sma_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4152

output_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4157

input_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4295

struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;

drivers/net/ethernet/intel/ice/ice_dpll.c

4365

struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;

drivers/net/ethernet/intel/ice/ice_dpll.c

4658

kfree(pf->dplls.pps.input_prio);

drivers/net/ethernet/intel/ice/ice_dpll.c

4659

pf->dplls.pps.input_prio = NULL;

drivers/net/ethernet/intel/ice/ice_dpll.c

4730

struct ice_dpll *dp = &pf->dplls.pps;

drivers/net/ethernet/intel/ice/ice_dpll.c

4858

if (!IS_ERR_OR_NULL(pf->dplls.pps.dpll))

drivers/net/ethernet/intel/ice/ice_dpll.c

4859

ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);

drivers/net/ethernet/intel/ice/ice_dpll.c

4950

err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS);

drivers/net/ethernet/intel/ice/ice_dpll.c

4968

ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);

drivers/net/ethernet/intel/ice/ice_dpll.c

727

pin->state[pf->dplls.pps.dpll_idx] =

drivers/net/ethernet/intel/ice/ice_dpll.c

728

pin->pin == pf->dplls.pps.active_input ?

drivers/net/ethernet/intel/ice/ice_dpll.c

734

pin->state[pf->dplls.pps.dpll_idx] =

drivers/net/ethernet/intel/ice/ice_dpll.c

740

pin->state[pf->dplls.pps.dpll_idx] =

drivers/net/ethernet/intel/ice/ice_dpll.c

757

pin->state[pf->dplls.pps.dpll_idx] =

drivers/net/ethernet/intel/ice/ice_dpll.c

758

parent == pf->dplls.pps.dpll_idx ?

drivers/net/ethernet/intel/ice/ice_dpll.c

764

pin->state[pf->dplls.pps.dpll_idx] =

drivers/net/ethernet/intel/ice/ice_dpll.h

178

struct ice_dpll pps;

drivers/net/ethernet/intel/igb/igb_main.c

7072

if (adapter->ptp_caps.pps)

drivers/net/ethernet/intel/igb/igb_ptp.c

1316

adapter->ptp_caps.pps = 0;

drivers/net/ethernet/intel/igb/igb_ptp.c

1338

adapter->ptp_caps.pps = 0;

drivers/net/ethernet/intel/igb/igb_ptp.c

1367

adapter->ptp_caps.pps = 1;

drivers/net/ethernet/intel/igc/igc_main.c

5578

if (adapter->ptp_caps.pps)

drivers/net/ethernet/intel/igc/igc_ptp.c

1191

adapter->ptp_caps.pps = 1;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1391

adapter->ptp_caps.pps = 1;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1408

adapter->ptp_caps.pps = 0;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1425

adapter->ptp_caps.pps = 1;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

394

u32 burst, u64 rate, bool pps)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

430

if (pps) {

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h

40

u32 burst, u64 rate, bool pps);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c

430

.pps = 0,

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

311

struct npc_install_flow_req *req, bool pps)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

331

node->is_pps = pps;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

421

bool pps = false, mcast = false;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

494

pps = true;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

547

mark, req, pps);

drivers/net/ethernet/mellanox/mlx4/en_clock.c

237

.pps = 0,

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1034

.pps = 0,

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1092

clock->ptp_info.pps = 1;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1170

int pin = eqe->data.pps.pin;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1179

be64_to_cpu(eqe->data.pps.time_stamp)) :

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1181

be64_to_cpu(eqe->data.pps.time_stamp));

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

389

#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \

drivers/net/ethernet/microchip/lan743x_ptp.c

1535

ptp->ptp_clock_info.pps = LAN743X_PTP_N_PPS;

drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c

841

bool pps = false;

drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c

863

pps = true;

drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c

873

if (ts_phase.tv_sec || (ts_phase.tv_nsec && !pps)) {

drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c

890

if (pps) {

drivers/net/ethernet/mscc/ocelot_ptp.c

206

bool pps = false;

drivers/net/ethernet/mscc/ocelot_ptp.c

231

pps = true;

drivers/net/ethernet/mscc/ocelot_ptp.c

250

if (ts_phase.tv_sec || (ts_phase.tv_nsec && !pps)) {

drivers/net/ethernet/mscc/ocelot_ptp.c

267

if (pps) {

drivers/net/ethernet/mscc/ocelot_ptp.c

279

if (pps) {

drivers/net/ethernet/mscc/ocelot_vsc7514.c

113

.pps = 0,

drivers/net/ethernet/netronome/nfp/flower/main.h

725

bool pps, u32 id, u32 rate, u32 burst);

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

180

bool pps;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

271

pps = false;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

273

pps = true;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

275

pps, netdev_port_id,

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

702

bool pps_support, pps;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

739

pps = false;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

741

pps = true;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

742

nfp_flower_offload_one_police(app, false, pps, meter_id,

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

759

bool pps;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

775

pps = !meter_entry->bps;

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

786

if (pps)

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

87

bool pps, u32 id, u32 rate, u32 burst)

drivers/net/ethernet/netronome/nfp/flower/qos_conf.c

99

if (pps)

drivers/net/ethernet/qlogic/qede/qede_ptp.c

478

ptp->clock_info.pps = 0;

drivers/net/ethernet/sfc/ptp.c

1549

.pps = 1,

drivers/net/ethernet/sfc/siena/ptp.c

1431

.pps = 1,

drivers/net/ethernet/stmicro/stmmac/stmmac.h

376

struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c

185

cfg = &priv->pps[rq->perout.index];

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c

304

.pps = 0,

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c

321

.pps = 0,

drivers/net/ethernet/ti/am65-cpts.c

1207

cpts->ptp_info.pps = 1;

drivers/net/ethernet/ti/cpts.c

425

.pps = 0,

drivers/net/ethernet/ti/icssg/icss_iep.c

797

iep->ptp_info.pps = 1;

drivers/net/ethernet/ti/icssg/icss_iep.c

799

iep->ptp_info.pps = 1;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

503

wx->ptp_caps.pps = 0;

drivers/net/ethernet/xscale/ptp_ixp46x.c

220

.pps = 0,

drivers/net/phy/dp83640.c

970

clock->caps.pps = 0;

drivers/net/phy/micrel.c

4536

shared->ptp_clock_info.pps = 0;

drivers/net/phy/microchip_rds_ptp.c

1278

clock->caps.pps = 0;

drivers/net/phy/mscc/mscc_ptp.c

1269

.pps = 0,

drivers/net/wireless/intel/iwlegacy/3945-rs.c

176

u32 packet_count, duration, pps;

drivers/net/wireless/intel/iwlegacy/3945-rs.c

197

pps = (packet_count * 1000) / duration;

drivers/net/wireless/intel/iwlegacy/3945-rs.c

199

pps = 0;

drivers/net/wireless/intel/iwlegacy/3945-rs.c

201

if (pps) {

drivers/net/wireless/intel/iwlegacy/3945-rs.c

202

duration = (IL_AVERAGE_PACKETS * 1000) / pps;

drivers/pinctrl/qcom/pinctrl-ipq5210.c

760

MSM_PIN_FUNCTION(pps),

drivers/pinctrl/qcom/pinctrl-ipq5210.c

818

[18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _),

drivers/pps/clients/pps-gpio.c

204

data->pps = pps_register_source(&data->info, pps_default_params);

drivers/pps/clients/pps-gpio.c

205

if (IS_ERR(data->pps)) {

drivers/pps/clients/pps-gpio.c

208

return PTR_ERR(data->pps);

drivers/pps/clients/pps-gpio.c

215

pps_unregister_source(data->pps);

drivers/pps/clients/pps-gpio.c

220

dev_dbg(&data->pps->dev, "Registered IRQ %d as PPS source\n",

drivers/pps/clients/pps-gpio.c

231

pps_unregister_source(data->pps);

drivers/pps/clients/pps-gpio.c

28

struct pps_device *pps; /* PPS source device */

drivers/pps/clients/pps-gpio.c

59

pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data);

drivers/pps/clients/pps-gpio.c

63

pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data);

drivers/pps/clients/pps-gpio.c

65

dev_warn_ratelimited(&info->pps->dev, "IRQ did not trigger any PPS event\n");

drivers/pps/clients/pps-gpio.c

71

static void pps_gpio_echo(struct pps_device *pps, int event, void *data)

drivers/pps/clients/pps-gpio.c

78

if (pps->params.mode & PPS_ECHOASSERT)

drivers/pps/clients/pps-gpio.c

83

if (pps->params.mode & PPS_ECHOCLEAR)

drivers/pps/clients/pps-gpio.c

89

if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) {

drivers/pps/clients/pps-ktimer.c

21

static struct pps_device *pps;

drivers/pps/clients/pps-ktimer.c

35

pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL);

drivers/pps/clients/pps-ktimer.c

59

dev_dbg(&pps->dev, "ktimer PPS source unregistered\n");

drivers/pps/clients/pps-ktimer.c

62

pps_unregister_source(pps);

drivers/pps/clients/pps-ktimer.c

67

pps = pps_register_source(&pps_ktimer_info,

drivers/pps/clients/pps-ktimer.c

69

if (IS_ERR(pps)) {

drivers/pps/clients/pps-ktimer.c

71

return PTR_ERR(pps);

drivers/pps/clients/pps-ktimer.c

77

dev_dbg(&pps->dev, "ktimer PPS source registered\n");

drivers/pps/clients/pps-ldisc.c

18

struct pps_device *pps;

drivers/pps/clients/pps-ldisc.c

23

pps = pps_lookup_dev(tty);

drivers/pps/clients/pps-ldisc.c

28

if (WARN_ON_ONCE(pps == NULL))

drivers/pps/clients/pps-ldisc.c

32

pps_event(pps, &ts, active ? PPS_CAPTUREASSERT :

drivers/pps/clients/pps-ldisc.c

35

dev_dbg(&pps->dev, "PPS %s at %lu\n",

drivers/pps/clients/pps-ldisc.c

46

struct pps_device *pps;

drivers/pps/clients/pps-ldisc.c

57

pps = pps_register_source(&info, PPS_CAPTUREBOTH | \

drivers/pps/clients/pps-ldisc.c

59

if (IS_ERR(pps)) {

drivers/pps/clients/pps-ldisc.c

61

return PTR_ERR(pps);

drivers/pps/clients/pps-ldisc.c

63

pps->lookup_cookie = tty;

drivers/pps/clients/pps-ldisc.c

72

dev_dbg(&pps->dev, "source \"%s\" added\n", info.path);

drivers/pps/clients/pps-ldisc.c

77

pps_unregister_source(pps);

drivers/pps/clients/pps-ldisc.c

85

struct pps_device *pps = pps_lookup_dev(tty);

drivers/pps/clients/pps-ldisc.c

89

if (WARN_ON(!pps))

drivers/pps/clients/pps-ldisc.c

92

dev_info(&pps->dev, "removed\n");

drivers/pps/clients/pps-ldisc.c

93

pps_unregister_source(pps);

drivers/pps/clients/pps_parport.c

101

dev_err(&dev->pps->dev, "disabled clear edge capture after %d"

drivers/pps/clients/pps_parport.c

109

pps_event(dev->pps, &ts_assert,

drivers/pps/clients/pps_parport.c

115

pps_event(dev->pps, &ts_assert,

drivers/pps/clients/pps_parport.c

118

pps_event(dev->pps, &ts_clear,

drivers/pps/clients/pps_parport.c

173

device->pps = pps_register_source(&info,

drivers/pps/clients/pps_parport.c

175

if (IS_ERR(device->pps)) {

drivers/pps/clients/pps_parport.c

212

pps_unregister_source(device->pps);

drivers/pps/clients/pps_parport.c

41

struct pps_device *pps; /* PPS device */

drivers/pps/clients/pps_parport.c

84

dev_err(&dev->pps->dev, "lost the signal\n");

drivers/pps/kapi.c

100

if ((pps->info.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) &&

drivers/pps/kapi.c

101

pps->info.echo == NULL)

drivers/pps/kapi.c

102

pps->info.echo = pps_echo_client_default;

drivers/pps/kapi.c

104

init_waitqueue_head(&pps->queue);

drivers/pps/kapi.c

105

spin_lock_init(&pps->lock);

drivers/pps/kapi.c

108

err = pps_register_cdev(pps);

drivers/pps/kapi.c

115

dev_dbg(&pps->dev, "new PPS source %s\n", info->name);

drivers/pps/kapi.c

117

return pps;

drivers/pps/kapi.c

133

void pps_unregister_source(struct pps_device *pps)

drivers/pps/kapi.c

135

pps_kc_remove(pps);

drivers/pps/kapi.c

136

pps_unregister_cdev(pps);

drivers/pps/kapi.c

156

void pps_event(struct pps_device *pps, struct pps_event_time *ts, int event,

drivers/pps/kapi.c

166

dev_dbg(&pps->dev, "PPS event at %ptSp\n", &ts->ts_real);

drivers/pps/kapi.c

170

spin_lock_irqsave(&pps->lock, flags);

drivers/pps/kapi.c

173

if ((pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)))

drivers/pps/kapi.c

174

pps->info.echo(pps, event, data);

drivers/pps/kapi.c

177

pps->current_mode = pps->params.mode;

drivers/pps/kapi.c

178

if (event & pps->params.mode & PPS_CAPTUREASSERT) {

drivers/pps/kapi.c

180

if (pps->params.mode & PPS_OFFSETASSERT)

drivers/pps/kapi.c

182

&pps->params.assert_off_tu);

drivers/pps/kapi.c

185

pps->assert_tu = ts_real;

drivers/pps/kapi.c

186

pps->assert_sequence++;

drivers/pps/kapi.c

187

dev_dbg(&pps->dev, "capture assert seq #%u\n",

drivers/pps/kapi.c

188

pps->assert_sequence);

drivers/pps/kapi.c

192

if (event & pps->params.mode & PPS_CAPTURECLEAR) {

drivers/pps/kapi.c

194

if (pps->params.mode & PPS_OFFSETCLEAR)

drivers/pps/kapi.c

196

&pps->params.clear_off_tu);

drivers/pps/kapi.c

199

pps->clear_tu = ts_real;

drivers/pps/kapi.c

200

pps->clear_sequence++;

drivers/pps/kapi.c

201

dev_dbg(&pps->dev, "capture clear seq #%u\n",

drivers/pps/kapi.c

202

pps->clear_sequence);

drivers/pps/kapi.c

207

pps_kc_event(pps, ts, event);

drivers/pps/kapi.c

211

pps->last_ev++;

drivers/pps/kapi.c

212

wake_up_interruptible_all(&pps->queue);

drivers/pps/kapi.c

214

kill_fasync(&pps->async_queue, SIGIO, POLL_IN);

drivers/pps/kapi.c

217

spin_unlock_irqrestore(&pps->lock, flags);

drivers/pps/kapi.c

41

static void pps_echo_client_default(struct pps_device *pps, int event,

drivers/pps/kapi.c

44

dev_info(&pps->dev, "echo %s %s\n",

drivers/pps/kapi.c

68

struct pps_device *pps;

drivers/pps/kapi.c

86

pps = kzalloc_obj(struct pps_device);

drivers/pps/kapi.c

87

if (pps == NULL) {

drivers/pps/kapi.c

95

pps->params.api_version = PPS_API_VERS;

drivers/pps/kapi.c

96

pps->params.mode = default_params;

drivers/pps/kapi.c

97

pps->info = *info;

drivers/pps/kc.c

106

if (pps == pps_kc_hardpps_dev && event & pps_kc_hardpps_mode)

drivers/pps/kc.c

36

int pps_kc_bind(struct pps_device *pps, struct pps_bind_args *bind_args)

drivers/pps/kc.c

42

if (pps_kc_hardpps_dev == pps) {

drivers/pps/kc.c

46

dev_info(&pps->dev, "unbound kernel"

drivers/pps/kc.c

50

dev_err(&pps->dev, "selected kernel consumer"

drivers/pps/kc.c

56

pps_kc_hardpps_dev == pps) {

drivers/pps/kc.c

58

pps_kc_hardpps_dev = pps;

drivers/pps/kc.c

60

dev_info(&pps->dev, "bound kernel consumer: "

drivers/pps/kc.c

64

dev_err(&pps->dev, "another kernel consumer"

drivers/pps/kc.c

79

void pps_kc_remove(struct pps_device *pps)

drivers/pps/kc.c

82

if (pps == pps_kc_hardpps_dev) {

drivers/pps/kc.c

86

dev_info(&pps->dev, "unbound kernel consumer"

drivers/pps/kc.c

99

void pps_kc_event(struct pps_device *pps, struct pps_event_time *ts,

drivers/pps/kc.h

16

extern int pps_kc_bind(struct pps_device *pps,

drivers/pps/kc.h

18

extern void pps_kc_remove(struct pps_device *pps);

drivers/pps/kc.h

19

extern void pps_kc_event(struct pps_device *pps,

drivers/pps/kc.h

25

static inline int pps_kc_bind(struct pps_device *pps,

drivers/pps/kc.h

27

static inline void pps_kc_remove(struct pps_device *pps) {}

drivers/pps/kc.h

28

static inline void pps_kc_event(struct pps_device *pps,

drivers/pps/pps.c

107

dev_dbg(&pps->dev, "PPS_GETPARAMS\n");

drivers/pps/pps.c

109

spin_lock_irq(&pps->lock);

drivers/pps/pps.c

112

params = pps->params;

drivers/pps/pps.c

114

spin_unlock_irq(&pps->lock);

drivers/pps/pps.c

123

dev_dbg(&pps->dev, "PPS_SETPARAMS\n");

drivers/pps/pps.c

133

dev_dbg(&pps->dev, "capture mode unspecified (%x)\n",

drivers/pps/pps.c

139

if ((params.mode & ~pps->info.mode) != 0) {

drivers/pps/pps.c

140

dev_dbg(&pps->dev, "unsupported capabilities (%x)\n",

drivers/pps/pps.c

145

spin_lock_irq(&pps->lock);

drivers/pps/pps.c

148

pps->params = params;

drivers/pps/pps.c

153

dev_dbg(&pps->dev, "time format unspecified (%x)\n",

drivers/pps/pps.c

155

pps->params.mode |= PPS_TSFMT_TSPEC;

drivers/pps/pps.c

157

if (pps->info.mode & PPS_CANWAIT)

drivers/pps/pps.c

158

pps->params.mode |= PPS_CANWAIT;

drivers/pps/pps.c

159

pps->params.api_version = PPS_API_VERS;

drivers/pps/pps.c

166

pps->params.assert_off_tu.flags = 0;

drivers/pps/pps.c

167

pps->params.clear_off_tu.flags = 0;

drivers/pps/pps.c

169

spin_unlock_irq(&pps->lock);

drivers/pps/pps.c

174

dev_dbg(&pps->dev, "PPS_GETCAP\n");

drivers/pps/pps.c

176

err = put_user(pps->info.mode, iuarg);

drivers/pps/pps.c

185

dev_dbg(&pps->dev, "PPS_FETCH\n");

drivers/pps/pps.c

191

err = pps_cdev_pps_fetch(pps, &fdata);

drivers/pps/pps.c

196

spin_lock_irq(&pps->lock);

drivers/pps/pps.c

198

pps->last_fetched_ev = pps->last_ev;

drivers/pps/pps.c

200

fdata.info.assert_sequence = pps->assert_sequence;

drivers/pps/pps.c

201

fdata.info.clear_sequence = pps->clear_sequence;

drivers/pps/pps.c

202

fdata.info.assert_tu = pps->assert_tu;

drivers/pps/pps.c

203

fdata.info.clear_tu = pps->clear_tu;

drivers/pps/pps.c

204

fdata.info.current_mode = pps->current_mode;

drivers/pps/pps.c

206

spin_unlock_irq(&pps->lock);

drivers/pps/pps.c

217

dev_dbg(&pps->dev, "PPS_KC_BIND\n");

drivers/pps/pps.c

228

if ((bind_args.edge & ~pps->info.mode) != 0) {

drivers/pps/pps.c

229

dev_err(&pps->dev, "unsupported capabilities (%x)\n",

drivers/pps/pps.c

238

dev_err(&pps->dev, "invalid kernel consumer bind"

drivers/pps/pps.c

243

err = pps_kc_bind(pps, &bind_args);

drivers/pps/pps.c

260

struct pps_device *pps = file->private_data;

drivers/pps/pps.c

270

dev_dbg(&pps->dev, "PPS_FETCH\n");

drivers/pps/pps.c

279

err = pps_cdev_pps_fetch(pps, &fdata);

drivers/pps/pps.c

284

spin_lock_irq(&pps->lock);

drivers/pps/pps.c

286

pps->last_fetched_ev = pps->last_ev;

drivers/pps/pps.c

288

compat.info.assert_sequence = pps->assert_sequence;

drivers/pps/pps.c

289

compat.info.clear_sequence = pps->clear_sequence;

drivers/pps/pps.c

290

compat.info.current_mode = pps->current_mode;

drivers/pps/pps.c

292

memcpy(&compat.info.assert_tu, &pps->assert_tu,

drivers/pps/pps.c

294

memcpy(&compat.info.clear_tu, &pps->clear_tu,

drivers/pps/pps.c

297

spin_unlock_irq(&pps->lock);

drivers/pps/pps.c

311

struct pps_device *pps;

drivers/pps/pps.c

314

pps = idr_find(&pps_idr, id);

drivers/pps/pps.c

315

if (pps)

drivers/pps/pps.c

316

get_device(&pps->dev);

drivers/pps/pps.c

319

return pps;

drivers/pps/pps.c

324

struct pps_device *pps = pps_idr_get(iminor(inode));

drivers/pps/pps.c

326

if (!pps)

drivers/pps/pps.c

329

file->private_data = pps;

drivers/pps/pps.c

335

struct pps_device *pps = file->private_data;

drivers/pps/pps.c

337

WARN_ON(pps->id != iminor(inode));

drivers/pps/pps.c

338

put_device(&pps->dev);

drivers/pps/pps.c

358

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/pps.c

360

pr_debug("deallocating pps%d\n", pps->id);

drivers/pps/pps.c

361

kfree(pps);

drivers/pps/pps.c

364

int pps_register_cdev(struct pps_device *pps)

drivers/pps/pps.c

373

err = idr_alloc(&pps_idr, pps, 0, PPS_MAX_SOURCES, GFP_KERNEL);

drivers/pps/pps.c

377

pps->info.name);

drivers/pps/pps.c

380

kfree(pps);

drivers/pps/pps.c

383

pps->id = err;

drivers/pps/pps.c

385

pps->dev.class = &pps_class;

drivers/pps/pps.c

386

pps->dev.parent = pps->info.dev;

drivers/pps/pps.c

387

pps->dev.devt = MKDEV(pps_major, pps->id);

drivers/pps/pps.c

388

dev_set_drvdata(&pps->dev, pps);

drivers/pps/pps.c

389

dev_set_name(&pps->dev, "pps%d", pps->id);

drivers/pps/pps.c

390

pps->dev.release = pps_device_destruct;

drivers/pps/pps.c

391

err = device_register(&pps->dev);

drivers/pps/pps.c

395

pr_debug("source %s got cdev (%d:%d)\n", pps->info.name, pps_major,

drivers/pps/pps.c

396

pps->id);

drivers/pps/pps.c

398

get_device(&pps->dev);

drivers/pps/pps.c

403

idr_remove(&pps_idr, pps->id);

drivers/pps/pps.c

404

put_device(&pps->dev);

drivers/pps/pps.c

410

void pps_unregister_cdev(struct pps_device *pps)

drivers/pps/pps.c

412

pr_debug("unregistering pps%d\n", pps->id);

drivers/pps/pps.c

413

pps->lookup_cookie = NULL;

drivers/pps/pps.c

414

device_destroy(&pps_class, pps->dev.devt);

drivers/pps/pps.c

418

idr_remove(&pps_idr, pps->id);

drivers/pps/pps.c

419

put_device(&pps->dev);

drivers/pps/pps.c

43

struct pps_device *pps = file->private_data;

drivers/pps/pps.c

448

struct pps_device *pps;

drivers/pps/pps.c

45

poll_wait(file, &pps->queue, wait);

drivers/pps/pps.c

452

idr_for_each_entry(&pps_idr, pps, id)

drivers/pps/pps.c

453

if (cookie == pps->lookup_cookie)

drivers/pps/pps.c

456

return pps;

drivers/pps/pps.c

47

if (pps->last_fetched_ev == pps->last_ev)

drivers/pps/pps.c

55

struct pps_device *pps = file->private_data;

drivers/pps/pps.c

56

return fasync_helper(fd, file, on, &pps->async_queue);

drivers/pps/pps.c

59

static int pps_cdev_pps_fetch(struct pps_device *pps, struct pps_fdata *fdata)

drivers/pps/pps.c

61

unsigned int ev = pps->last_ev;

drivers/pps/pps.c

66

err = wait_event_interruptible(pps->queue,

drivers/pps/pps.c

67

ev != pps->last_ev);

drivers/pps/pps.c

71

dev_dbg(&pps->dev, "timeout %lld.%09d\n",

drivers/pps/pps.c

79

pps->queue,

drivers/pps/pps.c

80

ev != pps->last_ev,

drivers/pps/pps.c

89

dev_dbg(&pps->dev, "pending signal caught\n");

drivers/pps/pps.c

99

struct pps_device *pps = file->private_data;

drivers/pps/sysfs.c

21

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

23

if (!(pps->info.mode & PPS_CAPTUREASSERT))

drivers/pps/sysfs.c

27

(long long) pps->assert_tu.sec, pps->assert_tu.nsec,

drivers/pps/sysfs.c

28

pps->assert_sequence);

drivers/pps/sysfs.c

35

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

37

if (!(pps->info.mode & PPS_CAPTURECLEAR))

drivers/pps/sysfs.c

41

(long long) pps->clear_tu.sec, pps->clear_tu.nsec,

drivers/pps/sysfs.c

42

pps->clear_sequence);

drivers/pps/sysfs.c

49

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

51

return sprintf(buf, "%4x\n", pps->info.mode);

drivers/pps/sysfs.c

58

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

60

return sprintf(buf, "%d\n", !!pps->info.echo);

drivers/pps/sysfs.c

67

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

69

return sprintf(buf, "%s\n", pps->info.name);

drivers/pps/sysfs.c

76

struct pps_device *pps = dev_get_drvdata(dev);

drivers/pps/sysfs.c

78

return sprintf(buf, "%s\n", pps->info.path);

drivers/ptp/ptp_chardev.c

188

.pps = ptp->info->pps,

drivers/ptp/ptp_chardev.c

63

if (info->pps) {

drivers/ptp/ptp_clock.c

414

if (info->pps) {

drivers/ptp/ptp_clock.c

415

struct pps_source_info pps;

drivers/ptp/ptp_clock.c

416

memset(&pps, 0, sizeof(pps));

drivers/ptp/ptp_clock.c

417

snprintf(pps.name, PPS_MAX_NAME_LEN, "ptp%d", index);

drivers/ptp/ptp_clock.c

418

pps.mode = PTP_PPS_MODE;

drivers/ptp/ptp_clock.c

419

pps.owner = info->owner;

drivers/ptp/ptp_clock.c

420

ptp->pps_source = pps_register_source(&pps, PTP_PPS_DEFAULTS);

drivers/ptp/ptp_dte.c

221

.pps = 0,

drivers/ptp/ptp_kvm_common.c

117

.pps = 0,

drivers/ptp/ptp_netc.c

741

.pps = 1,

drivers/ptp/ptp_ocp.c

1126

OCP_EXT_RESOURCE(pps),

drivers/ptp/ptp_ocp.c

1663

ext = bp->pps;

drivers/ptp/ptp_ocp.c

1669

ext = bp->pps;

drivers/ptp/ptp_ocp.c

1746

.pps = true,

drivers/ptp/ptp_ocp.c

2428

if (ext == ext->bp->pps) {

drivers/ptp/ptp_ocp.c

2461

if (ext == bp->pps) {

drivers/ptp/ptp_ocp.c

378

struct ptp_ocp_ext_src *pps;

drivers/ptp/ptp_ocp.c

4488

if (bp->pps) {

drivers/ptp/ptp_ocp.c

4489

ts_reg = bp->pps->mem;

drivers/ptp/ptp_ocp.c

4787

struct pps_device *pps;

drivers/ptp/ptp_ocp.c

4793

pps = pps_lookup_dev(bp->ptp);

drivers/ptp/ptp_ocp.c

4794

if (pps)

drivers/ptp/ptp_ocp.c

4795

ptp_ocp_symlink(bp, &pps->dev, "pps");

drivers/ptp/ptp_ocp.c

4883

if (bp->pps)

drivers/ptp/ptp_ocp.c

4884

ptp_ocp_ts_enable(bp->pps, ~0, false);

drivers/ptp/ptp_ocp.c

4893

ptp_ocp_unregister_ext(bp->pps);

drivers/ptp/ptp_ocp.c

593

OCP_EXT_RESOURCE(pps),

drivers/ptp/ptp_ocp.c

846

OCP_EXT_RESOURCE(pps),

drivers/ptp/ptp_ocp.c

943

OCP_EXT_RESOURCE(pps),

drivers/ptp/ptp_pch.c

432

.pps = 0,

drivers/ptp/ptp_qoriq.c

357

.pps = 1,

drivers/ptp/ptp_sysfs.c

357

if (!info->pps)

drivers/ptp/ptp_sysfs.c

45

PTP_SHOW_INT(pps_available, pps);

drivers/ptp/ptp_vmclock.c

323

.pps = 0,

drivers/scsi/be2iscsi/be_main.c

5177

unsigned int pps, delta;

drivers/scsi/be2iscsi/be_main.c

5200

pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);

drivers/scsi/be2iscsi/be_main.c

5201

eqd = (pps / 1500) << 2;

drivers/staging/media/sunxi/cedrus/cedrus.h

57

const struct v4l2_ctrl_h264_pps *pps;

drivers/staging/media/sunxi/cedrus/cedrus.h

72

const struct v4l2_ctrl_hevc_pps *pps;

drivers/staging/media/sunxi/cedrus/cedrus_dec.c

55

run.h264.pps = cedrus_find_control_data(ctx,

drivers/staging/media/sunxi/cedrus/cedrus_dec.c

70

run.h265.pps = cedrus_find_control_data(ctx,

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

264

const struct v4l2_ctrl_h264_pps *pps = run->h264.pps;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

267

if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT))

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

349

const struct v4l2_ctrl_h264_pps *pps = run->h264.pps;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

394

if (V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice))

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

413

reg |= (pps->weighted_bipred_idc & 0x3) << 2;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

414

if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

416

if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED)

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

418

if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

420

if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE)

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

469

reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

470

reg |= (pps->chroma_qp_index_offset & 0x3f) << 8;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

471

reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f;

drivers/staging/media/sunxi/cedrus/cedrus_h264.c

472

if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT))

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

364

const struct v4l2_ctrl_hevc_pps *pps;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

370

pps = run->h265.pps;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

375

for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) {

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

376

if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x)

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

379

x += pps->column_width_minus1[tx] + 1;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

382

for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) {

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

383

if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y)

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

386

y += pps->row_height_minus1[ty] + 1;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

391

((y + pps->row_height_minus1[ty]) << 16) |

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

392

((x + pps->column_width_minus1[tx]) << 0));

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

394

if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) {

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

399

if (tx + 1 >= pps->num_tile_columns_minus1 + 1) {

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

402

y += pps->row_height_minus1[ty++] + 1;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

404

x += pps->column_width_minus1[tx++] + 1;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

411

((y + pps->row_height_minus1[ty]) << 16) |

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

412

((x + pps->column_width_minus1[tx]) << 0);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

421

const struct v4l2_ctrl_hevc_pps *pps;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

440

pps = run->h265.pps;

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

518

if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ||

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

519

(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

615

reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

616

VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) |

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

617

VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) |

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

618

VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

622

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

626

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

630

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

634

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

638

reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

642

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

646

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

650

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

654

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

658

pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

661

V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

664

V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags);

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

786

if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) ||

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

787

(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED))

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

805

if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)

drivers/staging/sm750fb/sm750_hw.c

392

unsigned int dpms, pps, crtdb;

drivers/staging/sm750fb/sm750_hw.c

395

pps = 0;

drivers/staging/sm750fb/sm750_hw.c

401

pps = PANEL_DISPLAY_CTRL_DATA;

drivers/staging/sm750fb/sm750_hw.c

434

val |= pps;

drivers/video/fbdev/clps711x-fb.c

105

u32 lcdcon, pps;

drivers/video/fbdev/clps711x-fb.c

131

pps = clk_get_rate(cfb->clk) / (PICOS2KHZ(info->var.pixclock) * 1000);

drivers/video/fbdev/clps711x-fb.c

132

if (pps)

drivers/video/fbdev/clps711x-fb.c

133

pps--;

drivers/video/fbdev/clps711x-fb.c

134

lcdcon |= (pps & 0x3f) << 19;

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4322

int bl, wc, pps, tot;

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4325

pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4327

tot = bl + pps;

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4335

t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4336

bl, pps, tot,

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4341

TO_DSI_T(pps),

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

4345

TO_DSI_T(pps),

include/drm/drm_mipi_dsi.h

282

const struct drm_dsc_picture_parameter_set *pps);

include/drm/drm_mipi_dsi.h

291

const struct drm_dsc_picture_parameter_set *pps);

include/linux/mlx5/device.h

776

struct mlx5_eqe_pps pps;

include/linux/mlx5/mlx5_ifc.h

1805

u8 pps[0x1];

include/linux/pps_kernel.h

28

void (*echo)(struct pps_device *pps,

include/linux/pps_kernel.h

78

extern int pps_register_cdev(struct pps_device *pps);

include/linux/pps_kernel.h

79

extern void pps_unregister_cdev(struct pps_device *pps);

include/linux/pps_kernel.h

87

extern void pps_unregister_source(struct pps_device *pps);

include/linux/pps_kernel.h

88

extern void pps_event(struct pps_device *pps,

include/linux/ptp_clock_kernel.h

201

int pps;

include/uapi/linux/gen_stats.h

38

__u32 pps;

include/uapi/linux/gen_stats.h

48

__u64 pps;

include/uapi/linux/pkt_sched.h

41

__u32 pps; /* Current flow packet rate */

include/uapi/linux/ptp_clock.h

102

int pps; /* Whether the clock supports a PPS callback. */

include/uapi/linux/v4l2-controls.h

1526

#define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \

include/uapi/linux/v4l2-controls.h

1527

((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \

include/uapi/linux/v4l2-controls.h

1530

((pps)->weighted_bipred_idc == 1 && \

net/ceph/osdmap.c

2564

u32 pps = raw_pg_to_pps(pi, raw_pgid);

net/ceph/osdmap.c

2570

*ppps = pps;

net/ceph/osdmap.c

2587

len = do_crush(osdmap, ruleno, pps, raw->osds, pi->size,

net/ceph/osdmap.c

2705

u32 pps,

net/ceph/osdmap.c

2745

pps, osd) >> 16) >= aff) {

net/ceph/osdmap.c

2832

u32 pps;

net/ceph/osdmap.c

2837

pg_to_raw_osds(osdmap, pi, raw_pgid, up, &pps);

net/ceph/osdmap.c

2840

apply_primary_affinity(osdmap, pi, pps, up);

net/core/gen_estimator.c

274

sample->pps = est->avpps >> 8;

net/core/gen_stats.c

318

est.pps = sample.pps;

net/core/gen_stats.c

322

d->tc_stats.pps = est.pps;

net/core/pktgen.c

3343

__u64 bps, mbps, pps;

net/core/pktgen.c

3356

pps = div64_u64(pkt_dev->sofar * NSEC_PER_SEC,

net/core/pktgen.c

3370

bps = pps * 8 * pkt_dev->cur_pkt_size;

net/core/pktgen.c

3376

(unsigned long long)pps,

net/netfilter/xt_rateest.c

26

pps1 = info->pps1 >= sample.pps ? info->pps1 - sample.pps : 0;

net/netfilter/xt_rateest.c

29

pps1 = sample.pps;

net/netfilter/xt_rateest.c

40

pps2 = info->pps2 >= sample.pps ? info->pps2 - sample.pps : 0;

net/netfilter/xt_rateest.c

43

pps2 = sample.pps;

net/sched/act_police.c

194

pps = nla_get_u64(tb[TCA_POLICE_PKTRATE64]);

net/sched/act_police.c

198

psched_ppscfg_precompute(&new->ppsrate, pps);

net/sched/act_police.c

57

u64 pps, ppsburst;

samples/bpf/xdp_sample_user.c

1006

double pps, drop, info, err;

samples/bpf/xdp_sample_user.c

1045

pps = calc_pps(&r->total, &p->total, t);

samples/bpf/xdp_sample_user.c

1049

info = (pps + drop) / info; /* calc avg bulk */

samples/bpf/xdp_sample_user.c

1054

out->totals.xmit += pps;

samples/bpf/xdp_sample_user.c

1069

if (pps || drop || err) {

samples/bpf/xdp_sample_user.c

1072

__COLUMN(".2f") "\n", str, XMIT(pps), DROP(drop),

samples/bpf/xdp_sample_user.c

1083

pps = calc_pps(rc, pc, t);

samples/bpf/xdp_sample_user.c

1087

if (!pps && !drop && !err)

samples/bpf/xdp_sample_user.c

1093

info = (pps + drop) / info; /* calc avg bulk */

samples/bpf/xdp_sample_user.c

1096

__COLUMN(".2f") "\n", str, XMIT(pps),

samples/bpf/xdp_sample_user.c

1122

str = (sample_log_level & LL_DEFAULT) && out->rx_cnt.pps ?

samples/bpf/xdp_sample_user.c

1127

str, PPS(out->rx_cnt.pps), DROP(out->rx_cnt.drop),

samples/bpf/xdp_sample_user.c

1170

str = (sample_log_level & LL_DEFAULT) && out->xmit_cnt.pps ?

samples/bpf/xdp_sample_user.c

1177

str, XMIT(out->xmit_cnt.pps),

samples/bpf/xdp_sample_user.c

123

__u64 pps;

samples/bpf/xdp_sample_user.c

137

__u64 pps;

samples/bpf/xdp_sample_user.c

592

__u64 pps = 0;

samples/bpf/xdp_sample_user.c

596

pps = sample_round(packets / period_);

samples/bpf/xdp_sample_user.c

598

return pps;

samples/bpf/xdp_sample_user.c

60

#define PPS(pps) pps, "pkt/s"

samples/bpf/xdp_sample_user.c

604

__u64 pps = 0;

samples/bpf/xdp_sample_user.c

608

pps = sample_round(packets / period_);

samples/bpf/xdp_sample_user.c

610

return pps;

samples/bpf/xdp_sample_user.c

616

__u64 pps = 0;

samples/bpf/xdp_sample_user.c

620

pps = sample_round(packets / period_);

samples/bpf/xdp_sample_user.c

622

return pps;

samples/bpf/xdp_sample_user.c

628

__u64 pps = 0;

samples/bpf/xdp_sample_user.c

632

pps = sample_round(packets / period_);

samples/bpf/xdp_sample_user.c

634

return pps;

samples/bpf/xdp_sample_user.c

653

double t, pps, drop, err;

samples/bpf/xdp_sample_user.c

665

pps = calc_pps(r, p, t);

samples/bpf/xdp_sample_user.c

668

if (!pps && !drop && !err)

samples/bpf/xdp_sample_user.c

674

str, PPS(pps), DROP(drop), ERR(err));

samples/bpf/xdp_sample_user.c

678

pps = calc_pps(&rec->total, &prev->total, t);

samples/bpf/xdp_sample_user.c

682

out->rx_cnt.pps = pps;

samples/bpf/xdp_sample_user.c

685

out->totals.rx += pps;

samples/bpf/xdp_sample_user.c

696

double t, pps, drop, err;

samples/bpf/xdp_sample_user.c

705

pps = calc_pps(&rec->total, &prev->total, t);

samples/bpf/xdp_sample_user.c

709

if (pps > 0 || drop > 0) {

samples/bpf/xdp_sample_user.c

715

err = pps / err; /* calc average bulk size */

samples/bpf/xdp_sample_user.c

720

str, PPS(pps), DROP(drop), err, "bulk-avg");

samples/bpf/xdp_sample_user.c

728

pps = calc_pps(r, p, t);

samples/bpf/xdp_sample_user.c

731

if (!pps && !drop && !err)

samples/bpf/xdp_sample_user.c

736

err = pps / err; /* calc average bulk size */

samples/bpf/xdp_sample_user.c

740

str, PPS(pps), DROP(drop), err, "bulk-avg");

samples/bpf/xdp_sample_user.c

789

double t, pps, drop, err;

samples/bpf/xdp_sample_user.c

796

pps = calc_pps(&rec->total, &prev->total, t);

samples/bpf/xdp_sample_user.c

801

pps ? "kthread total" : "kthread", PPS(pps), DROP(drop), err,

samples/bpf/xdp_sample_user.c

809

pps = calc_pps(r, p, t);

samples/bpf/xdp_sample_user.c

812

if (!pps && !drop && !err)

samples/bpf/xdp_sample_user.c

818

str, PPS(pps), DROP(drop), err, "sched");

samples/bpf/xdp_sample_user.c

828

double t, pps;

samples/bpf/xdp_sample_user.c

839

pps = calc_pps(r, p, t);

samples/bpf/xdp_sample_user.c

840

if (!pps)

samples/bpf/xdp_sample_user.c

844

print_default(" %-18s " FMT_COLUMNf "\n", str, REDIR(pps));

samples/bpf/xdp_sample_user.c

848

pps = calc_pps(&rec->total, &prev->total, t);

samples/bpf/xdp_sample_user.c

849

out->redir_cnt.suc = pps;

samples/bpf/xdp_sample_user.c

850

out->totals.redir += pps;

samples/bpf/xdp_sample_user.c

953

double pps, drop, info, err;

samples/bpf/xdp_sample_user.c

966

pps = calc_pps(r, p, t);

samples/bpf/xdp_sample_user.c

970

if (!pps && !drop && !err)

samples/bpf/xdp_sample_user.c

976

info = (pps + drop) / info; /* calc avg bulk */

samples/bpf/xdp_sample_user.c

979

str, XMIT(pps), DROP(drop), err, "drv_err/s",

samples/bpf/xdp_sample_user.c

983

pps = calc_pps(&rec->total, &prev->total, t);

samples/bpf/xdp_sample_user.c

987

info = (pps + drop) / info; /* calc avg bulk */

samples/bpf/xdp_sample_user.c

990

out->xmit_cnt.pps = pps;

samples/bpf/xdp_sample_user.c

994

out->totals.xmit += pps;

sound/usb/card.h

111

unsigned int pps; /* packets per second */

sound/usb/endpoint.c

1369

ep->pps = 1000 >> ep->datainterval;

sound/usb/endpoint.c

1372

ep->pps = 8000 >> ep->datainterval;

sound/usb/endpoint.c

1375

ep->sample_rem = ep->cur_rate % ep->pps;

sound/usb/endpoint.c

1376

ep->packsize[0] = ep->cur_rate / ep->pps;

sound/usb/endpoint.c

1377

ep->packsize[1] = (ep->cur_rate + (ep->pps - 1)) / ep->pps;

sound/usb/endpoint.c

1380

ep->maxpacksize, ep->cur_rate, ep->pps);

sound/usb/endpoint.c

195

if (sample_accum >= ep->pps) {

sound/usb/endpoint.c

196

sample_accum -= ep->pps;

tools/include/uapi/linux/pkt_sched.h

40

__u32 pps; /* Current flow packet rate */

tools/testing/selftests/ptp/testptp.c

192

int pps = -1;

tools/testing/selftests/ptp/testptp.c

262

pps = atoi(optarg);

tools/testing/selftests/ptp/testptp.c

353

caps.pps,

tools/testing/selftests/ptp/testptp.c

544

if (pps != -1) {

tools/testing/selftests/ptp/testptp.c

545

int enable = pps ? 1 : 0;