Symbol: push
arch/arc/include/asm/entry-arcv2.h
160
; - K mode: add the offset from current SP where H/w starts auto push
arch/arc/include/asm/entry-arcv2.h
295
push r13
arch/arc/include/asm/entry-arcv2.h
296
push r14
arch/arc/include/asm/entry-arcv2.h
297
push r15
arch/arc/include/asm/entry-arcv2.h
298
push r16
arch/arc/include/asm/entry-arcv2.h
299
push r17
arch/arc/include/asm/entry-arcv2.h
300
push r18
arch/arc/include/asm/entry-arcv2.h
301
push r19
arch/arc/include/asm/entry-arcv2.h
302
push r20
arch/arc/include/asm/entry-arcv2.h
303
push r21
arch/arc/include/asm/entry-arcv2.h
304
push r22
arch/arc/include/asm/entry-arcv2.h
305
push r23
arch/arc/include/asm/entry-arcv2.h
306
push r24
arch/arc/include/asm/entry-arcv2.h
307
push r25
arch/arc/include/asm/entry-compact.h
100
push r23
arch/arc/include/asm/entry-compact.h
101
push r24
arch/arc/include/asm/entry-compact.h
102
push r25
arch/arc/include/asm/entry-compact.h
49
push r9
arch/arc/include/asm/entry-compact.h
58
push r0
arch/arc/include/asm/entry-compact.h
59
push r1
arch/arc/include/asm/entry-compact.h
60
push r2
arch/arc/include/asm/entry-compact.h
61
push r3
arch/arc/include/asm/entry-compact.h
62
push r4
arch/arc/include/asm/entry-compact.h
63
push r5
arch/arc/include/asm/entry-compact.h
64
push r6
arch/arc/include/asm/entry-compact.h
65
push r7
arch/arc/include/asm/entry-compact.h
66
push r8
arch/arc/include/asm/entry-compact.h
67
push r9
arch/arc/include/asm/entry-compact.h
68
push r10
arch/arc/include/asm/entry-compact.h
69
push r11
arch/arc/include/asm/entry-compact.h
70
push r12
arch/arc/include/asm/entry-compact.h
90
push r13
arch/arc/include/asm/entry-compact.h
91
push r14
arch/arc/include/asm/entry-compact.h
92
push r15
arch/arc/include/asm/entry-compact.h
93
push r16
arch/arc/include/asm/entry-compact.h
94
push r17
arch/arc/include/asm/entry-compact.h
95
push r18
arch/arc/include/asm/entry-compact.h
96
push r19
arch/arc/include/asm/entry-compact.h
97
push r20
arch/arc/include/asm/entry-compact.h
98
push r21
arch/arc/include/asm/entry-compact.h
99
push r22
arch/mips/include/asm/asm-eva.h
135
.set push; \
arch/mips/include/asm/asm.h
103
.set push; \
arch/mips/include/asm/asm.h
116
.set push; \
arch/mips/include/asm/asmmacro-32.h
17
.set push
arch/mips/include/asm/asmmacro-32.h
41
.set push
arch/mips/include/asm/asmmacro.h
109
.set push
arch/mips/include/asm/asmmacro.h
144
.set push
arch/mips/include/asm/asmmacro.h
168
.set push
arch/mips/include/asm/asmmacro.h
250
.set push
arch/mips/include/asm/asmmacro.h
259
.set push
arch/mips/include/asm/asmmacro.h
268
.set push
arch/mips/include/asm/asmmacro.h
277
.set push
arch/mips/include/asm/asmmacro.h
286
.set push
arch/mips/include/asm/asmmacro.h
295
.set push
arch/mips/include/asm/asmmacro.h
304
.set push
arch/mips/include/asm/asmmacro.h
313
.set push
arch/mips/include/asm/asmmacro.h
322
.set push
arch/mips/include/asm/asmmacro.h
331
.set push
arch/mips/include/asm/asmmacro.h
340
.set push
arch/mips/include/asm/asmmacro.h
349
.set push
arch/mips/include/asm/asmmacro.h
358
.set push
arch/mips/include/asm/asmmacro.h
367
.set push
arch/mips/include/asm/asmmacro.h
380
.set push
arch/mips/include/asm/asmmacro.h
390
.set push
arch/mips/include/asm/asmmacro.h
400
.set push
arch/mips/include/asm/asmmacro.h
410
.set push
arch/mips/include/asm/asmmacro.h
420
.set push
arch/mips/include/asm/asmmacro.h
430
.set push
arch/mips/include/asm/asmmacro.h
440
.set push
arch/mips/include/asm/asmmacro.h
450
.set push
arch/mips/include/asm/asmmacro.h
460
.set push
arch/mips/include/asm/asmmacro.h
470
.set push
arch/mips/include/asm/asmmacro.h
480
.set push
arch/mips/include/asm/asmmacro.h
489
.set push
arch/mips/include/asm/asmmacro.h
498
.set push
arch/mips/include/asm/asmmacro.h
507
.set push
arch/mips/include/asm/asmmacro.h
525
.set push
arch/mips/include/asm/asmmacro.h
569
.set push
arch/mips/include/asm/asmmacro.h
625
.set push
arch/mips/include/asm/asmmacro.h
85
.set push
arch/mips/include/asm/hazards.h
272
.set push; \
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
162
.set push
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
27
.set push
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
20
.set push
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
51
.set push
arch/mips/include/asm/mach-malta/kernel-entry-init.h
41
.set push
arch/mips/include/asm/pm.h
109
.set push
arch/mips/include/asm/pm.h
40
.set push
arch/mips/include/asm/sibyte/sb1250_scd.h
142
.set push ; \
arch/mips/include/asm/stackframe.h
195
.set push
arch/mips/include/asm/stackframe.h
299
.set push
arch/mips/include/asm/stackframe.h
358
.set push
arch/mips/include/asm/stackframe.h
385
.set push
arch/mips/include/asm/stackframe.h
396
.set push
arch/mips/include/asm/stackframe.h
433
.set push
arch/mips/include/asm/stackframe.h
52
.set push
arch/mips/include/asm/sync.h
179
.set push; \
arch/powerpc/include/asm/ppc_asm.h
490
.machine push; \
arch/powerpc/include/asm/ppc_asm.h
511
.machine push; \
arch/powerpc/include/asm/ppc_asm.h
519
.machine push; \
arch/riscv/include/asm/alternative-macros.h
24
.option push
arch/riscv/include/asm/alternative-macros.h
38
.option push
arch/riscv/include/asm/asm.h
120
.option push
arch/x86/include/asm/frame.h
17
push %_ASM_BP
arch/x86/include/asm/uprobes.h
51
} push;
arch/x86/kernel/uprobes.c
1351
unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;
arch/x86/kernel/uprobes.c
1355
regs->ip += auprobe->push.ilen;
arch/x86/kernel/uprobes.c
1527
auprobe->push.reg_offset = reg_offset;
arch/x86/kernel/uprobes.c
1528
auprobe->push.ilen = insn->length;
arch/x86/math-emu/fpu_aux.c
118
push();
arch/x86/math-emu/fpu_trig.c
206
push();
arch/x86/math-emu/fpu_trig.c
211
push();
arch/x86/math-emu/fpu_trig.c
219
push();
arch/x86/math-emu/fpu_trig.c
287
push();
arch/x86/math-emu/fpu_trig.c
320
push();
arch/x86/math-emu/fpu_trig.c
326
push();
arch/x86/math-emu/fpu_trig.c
346
push();
arch/x86/math-emu/fpu_trig.c
371
push();
arch/x86/math-emu/fpu_trig.c
390
push();
arch/x86/math-emu/fpu_trig.c
403
push();
arch/x86/math-emu/fpu_trig.c
410
push();
arch/x86/math-emu/fpu_trig.c
418
push();
arch/x86/math-emu/fpu_trig.c
425
push();
arch/x86/math-emu/fpu_trig.c
702
push();
arch/x86/math-emu/fpu_trig.c
725
push();
arch/x86/math-emu/fpu_trig.c
733
push();
arch/x86/math-emu/reg_constant.c
61
push();
drivers/atm/atmtcp.c
228
out_vcc->push(out_vcc,new_skb);
drivers/atm/atmtcp.c
327
out_vcc->push(out_vcc,new_skb);
drivers/atm/atmtcp.c
71
out_vcc->push(out_vcc,skb);
drivers/atm/eni.c
766
vcc->push(vcc,skb);
drivers/atm/fore200e.c
1045
vcc->push(vcc, skb);
drivers/atm/he.c
1764
vcc->push(vcc, skb);
drivers/atm/idt77252.c
1100
vcc->push(vcc, sb);
drivers/atm/idt77252.c
1172
vcc->push(vcc, skb);
drivers/atm/idt77252.c
1195
vcc->push(vcc, skb);
drivers/atm/idt77252.c
1331
vcc->push(vcc, sb);
drivers/atm/iphase.c
1352
vcc->push(vcc,skb);
drivers/atm/lanai.c
1415
lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
drivers/atm/nicstar.c
2061
vcc->push(vcc, sb);
drivers/atm/nicstar.c
2179
vcc->push(vcc, skb);
drivers/atm/nicstar.c
2197
vcc->push(vcc, sb);
drivers/atm/nicstar.c
2216
vcc->push(vcc, skb);
drivers/atm/nicstar.c
2322
vcc->push(vcc, hb);
drivers/atm/solos-pci.c
839
vcc->push(vcc, skb);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1101
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1116
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1120
PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1121
PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1151
struct nvif_push *push;
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1159
push = &chan->chan.push;
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1201
ret = PUSH_WAIT(push, 8);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1205
PUSH_NVSQ(push, NV05F, 0x012c, 0);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1206
PUSH_NVSQ(push, NV05F, 0x0134, head);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1207
PUSH_NVSQ(push, NV05F, 0x0100, 0);
drivers/gpu/drm/nouveau/dispnv04/crtc.c
1208
PUSH_NVSQ(push, NV05F, 0x0130, 0);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
121
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
124
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
127
PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
135
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
138
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
141
PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
161
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
164
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
167
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
174
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
177
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
180
PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
198
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
201
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
204
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
211
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
214
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
217
PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
38
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
41
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
44
PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
45
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
51
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
54
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
57
PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
61
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
68
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base507c.c
71
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/base507c.c
74
PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
78
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
81
PUSH_MTHD(push, NV507C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
88
PUSH_MTHD(push, NV507C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
96
PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
98
PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
drivers/gpu/drm/nouveau/dispnv50/base827c.c
31
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base827c.c
34
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/base827c.c
37
PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
41
PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/base827c.c
44
PUSH_MTHD(push, NV827C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
51
PUSH_MTHD(push, NV827C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
59
PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
102
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
159
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base907c.c
162
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
165
PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
173
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base907c.c
176
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
179
PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
31
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base907c.c
34
if ((ret = PUSH_WAIT(push, 10)))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
37
PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
42
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
44
PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
68
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base907c.c
71
if ((ret = PUSH_WAIT(push, 6)))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
74
PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
77
PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
80
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
87
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/base907c.c
90
if ((ret = PUSH_WAIT(push, 6)))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
93
PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
100
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
133
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/core507d.c
136
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/core507d.c
139
PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
140
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
36
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/core507d.c
39
if ((ret = PUSH_WAIT(push, (ntfy ? 2 : 0) + 3)))
drivers/gpu/drm/nouveau/dispnv50/core507d.c
43
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
49
PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |
drivers/gpu/drm/nouveau/dispnv50/core507d.c
58
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
83
struct nvif_push *push = &disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/core507d.c
86
ret = PUSH_WAIT(push, 6);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
90
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
95
PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
97
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
130
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
134
if ((ret = PUSH_WAIT(push, 2 + windows * 5)))
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
137
PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
140
PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
149
PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
157
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
36
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
40
if ((ret = PUSH_WAIT(push, windows * 2)))
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
44
PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
54
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
57
if ((ret = PUSH_WAIT(push, (ntfy ? 2 * 2 : 0) + 5)))
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
61
PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
67
PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
69
PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
74
PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
78
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
33
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
37
if ((ret = PUSH_WAIT(push, 2 + windows * 5)))
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
40
PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
43
PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
51
PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
59
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
21
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
24
ret = PUSH_WAIT(push, 5 + (ntfy ? 5 + 2 : 0));
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
29
PUSH_MTHD(push, NVCA7D, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
36
PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
41
PUSH_MTHD(push, NVCA7D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
44
PUSH_MTHD(push, NVCA7D, UPDATE,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
50
PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
54
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
60
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
64
ret = PUSH_WAIT(push, windows * 6 + heads * 6);
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
69
PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
77
PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
87
PUSH_MTHD(push, NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
93
PUSH_MTHD(push, NVCA7D, HEAD_SET_TILE_MASK(i), BIT(i));
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
95
PUSH_MTHD(push, NVCA7D, TILE_SET_TILE_SIZE(i), 0);
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
99
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
29
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
60
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
64
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
65
PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
67
PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
68
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
77
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
81
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
84
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
18
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
40
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
44
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
45
PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
47
PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
48
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
56
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
60
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
63
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
16
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
35
ret = PUSH_WAIT(push, 4);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
40
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
41
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
43
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
44
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
16
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
20
ret = PUSH_WAIT(push, ctx ? 3 : 2);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
28
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CRC(i), crc_hi,
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
35
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
46
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
51
ret = PUSH_WAIT(push, 1);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
55
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
75
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
79
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/dac507d.c
32
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/dac507d.c
41
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/dac507d.c
44
PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
drivers/gpu/drm/nouveau/dispnv50/dac907d.c
32
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/dac907d.c
35
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/dac907d.c
38
PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/disp.c
130
nvif_mem_dtor(&dmac->push.mem);
drivers/gpu/drm/nouveau/dispnv50/disp.c
134
nv50_dmac_kick(struct nvif_push *push)
drivers/gpu/drm/nouveau/dispnv50/disp.c
136
struct nv50_dmac *dmac = container_of(push, typeof(*dmac), push);
drivers/gpu/drm/nouveau/dispnv50/disp.c
138
dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/dispnv50/disp.c
143
if (dmac->push.mem.type & NVIF_MEM_VRAM) {
drivers/gpu/drm/nouveau/dispnv50/disp.c
156
push->bgn = push->cur;
drivers/gpu/drm/nouveau/dispnv50/disp.c
178
nv50_dmac_kick(&dmac->push);
drivers/gpu/drm/nouveau/dispnv50/disp.c
187
PUSH_RSVD(&dmac->push, PUSH_JUMP(&dmac->push, 0));
drivers/gpu/drm/nouveau/dispnv50/disp.c
193
nv50_dmac_wait(struct nvif_push *push, u32 size)
drivers/gpu/drm/nouveau/dispnv50/disp.c
195
struct nv50_dmac *dmac = container_of(push, typeof(*dmac), push);
drivers/gpu/drm/nouveau/dispnv50/disp.c
201
dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/dispnv50/disp.c
207
push->cur = dmac->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/dispnv50/disp.c
208
push->cur = push->cur + dmac->cur;
drivers/gpu/drm/nouveau/dispnv50/disp.c
209
nv50_dmac_kick(push);
drivers/gpu/drm/nouveau/dispnv50/disp.c
220
push->bgn = dmac->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/dispnv50/disp.c
221
push->bgn = push->bgn + dmac->cur;
drivers/gpu/drm/nouveau/dispnv50/disp.c
222
push->cur = push->bgn;
drivers/gpu/drm/nouveau/dispnv50/disp.c
223
push->end = push->cur + free;
drivers/gpu/drm/nouveau/dispnv50/disp.c
255
ret = nvif_mem_ctor_map(&drm->mmu, "kmsChanPush", type, 0x1000, &dmac->push.mem);
drivers/gpu/drm/nouveau/dispnv50/disp.c
259
dmac->push.wait = nv50_dmac_wait;
drivers/gpu/drm/nouveau/dispnv50/disp.c
260
dmac->push.kick = nv50_dmac_kick;
drivers/gpu/drm/nouveau/dispnv50/disp.c
261
dmac->push.bgn = dmac->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/dispnv50/disp.c
262
dmac->push.cur = dmac->push.bgn;
drivers/gpu/drm/nouveau/dispnv50/disp.c
263
dmac->push.end = dmac->push.bgn;
drivers/gpu/drm/nouveau/dispnv50/disp.c
272
args->pushbuf = nvif_handle(&dmac->push.mem.object);
drivers/gpu/drm/nouveau/dispnv50/disp.h
65
struct nvif_push push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
115
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
118
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
125
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
129
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
132
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
142
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
146
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
149
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
191
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
195
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
198
PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
205
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
209
if ((ret = PUSH_WAIT(push, 9)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
212
PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
215
PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
233
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
281
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
285
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
288
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
296
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
300
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
303
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
32
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
348
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
353
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
356
PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
36
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
365
PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
39
PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
393
PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
403
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
407
if ((ret = PUSH_WAIT(push, 7)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
410
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
416
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
420
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
51
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
55
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
58
PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
69
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
87
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head507d.c
90
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
97
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
104
PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
113
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
117
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/head827d.c
120
PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
123
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
130
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
134
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/head827d.c
137
PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
145
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
32
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
36
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/head827d.c
39
PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
44
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
51
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
55
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/head827d.c
58
PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
69
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
76
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head827d.c
80
if ((ret = PUSH_WAIT(push, 9)))
drivers/gpu/drm/nouveau/dispnv50/head827d.c
83
PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
86
PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
117
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
120
PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
127
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
145
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
148
PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
155
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
159
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
162
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
167
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
174
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
178
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
181
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
191
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
198
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
202
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
205
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
212
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
216
if ((ret = PUSH_WAIT(push, 9)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
219
PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
222
PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
240
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
249
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
253
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
256
PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
259
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
266
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
270
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
273
PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
281
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
325
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
330
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
333
PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
358
PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
363
PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
381
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
385
if ((ret = PUSH_WAIT(push, 8)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
388
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
39
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
394
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
398
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
43
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
46
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
60
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
64
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
67
PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
80
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head907d.c
84
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head907d.c
87
PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
98
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head917d.c
33
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head917d.c
37
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head917d.c
40
PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head917d.c
51
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head917d.c
70
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/head917d.c
73
PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head917d.c
80
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/head917d.c
84
ret = PUSH_WAIT(push, 5);
drivers/gpu/drm/nouveau/dispnv50/head917d.c
88
PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head917d.c
98
PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
107
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
111
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
114
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
118
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
125
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
129
if ((ret = PUSH_WAIT(push, 7)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
132
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
148
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
149
PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
164
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
168
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
171
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
178
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
182
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
185
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
212
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
217
if ((ret = PUSH_WAIT(push, 15)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
220
PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
237
PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
238
PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
240
PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
243
PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
247
PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
257
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
261
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
264
PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
268
PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
33
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
52
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
55
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
67
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
71
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
74
PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
88
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
92
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
95
PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
103
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
106
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
113
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
117
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
120
PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
204
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
209
if ((ret = PUSH_WAIT(push, 15)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
212
PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
229
PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
230
PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
232
PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
235
PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
239
PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
33
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
36
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
39
PUSH_NVSQ(push, NVC57D, 0x2020 + (head->base.index * 0x400), display_id);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
46
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
65
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
68
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
81
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
85
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
89
PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
99
struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
100
PUSH_MTHD(push, NVCA7D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
113
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
117
ret = PUSH_WAIT(push, 4);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
121
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
125
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
134
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
140
ret = PUSH_WAIT(push, 7);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
144
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(i, 0), curs_hi);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
146
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
151
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
16
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
172
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
176
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
180
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
189
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
195
ret = PUSH_WAIT(push, 6);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
199
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_OLUT(i), olut_hi,
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
20
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
206
PUSH_MTHD(push, NVCA7D, HEAD_SET_OLUT_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
220
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
225
ret = PUSH_WAIT(push, 11);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
229
PUSH_MTHD(push, NVCA7D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
24
PUSH_MTHD(push, NVCA7D, HEAD_SET_DISPLAY_ID(i, 0), display_id);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
245
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
248
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
251
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
260
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
264
ret = PUSH_WAIT(push, 4);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
268
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
272
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
32
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
55
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
59
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
73
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
77
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
81
PUSH_MTHD(push, NVCA7D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
92
struct nvif_push *push = &head->disp->core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
96
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
36
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
39
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
42
PUSH_MTHD(push, NV507E, SET_POINT_IN,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
58
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
61
if ((ret = PUSH_WAIT(push, 12)))
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
64
PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
68
PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
70
PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
73
PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
75
PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
35
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
38
if ((ret = PUSH_WAIT(push, 12)))
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
41
PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
45
PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
47
PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
50
PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
52
PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
32
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
35
if ((ret = PUSH_WAIT(push, 12)))
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
38
PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
42
PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
44
PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
47
PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
49
PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/pior507d.c
33
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/pior507d.c
42
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/pior507d.c
45
PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sor507d.c
33
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/sor507d.c
42
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/sor507d.c
45
PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sor907d.c
35
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/sor907d.c
38
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/sor907d.c
41
PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sorc37d.c
32
struct nvif_push *push = &core->chan.push;
drivers/gpu/drm/nouveau/dispnv50/sorc37d.c
35
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/sorc37d.c
38
PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
34
struct nvif_push *push = &wndw->wimm.push;
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
37
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
40
PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
43
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
49
struct nvif_push *push = &wndw->wimm.push;
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
52
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
55
PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
101
if ((ret = PUSH_WAIT(push, 8)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
104
PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
143
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
146
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
149
PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
153
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
160
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
163
if ((ret = PUSH_WAIT(push, 17)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
166
PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
171
PUSH_MTHD(push, NVC37E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
193
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
194
PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
196
PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
200
PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
204
PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
213
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
216
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
219
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
226
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
229
if ((ret = PUSH_WAIT(push, 3)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
232
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
243
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
246
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
249
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
256
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
259
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
262
PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
272
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
275
if ((ret = PUSH_WAIT(push, 5)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
278
PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
282
PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
286
return PUSH_KICK(push);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
43
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
46
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
49
PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
56
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
59
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
62
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
69
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
72
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
75
PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
98
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
102
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
105
if ((ret = PUSH_WAIT(push, 13)))
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
108
PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
115
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
118
if ((ret = PUSH_WAIT(push, 2)))
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
121
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
128
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
131
if ((ret = PUSH_WAIT(push, 4)))
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
134
PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
35
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
38
if ((ret = PUSH_WAIT(push, 17)))
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
41
PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
46
PUSH_MTHD(push, NVC57E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
64
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
65
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
67
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
71
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
75
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
84
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
92
if ((ret = PUSH_WAIT(push, 1 + ARRAY_SIZE(identity))))
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
95
PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
32
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
35
if ((ret = PUSH_WAIT(push, 17)))
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
38
PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
43
PUSH_MTHD(push, NVC57E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
60
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
61
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
63
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
67
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
71
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
102
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
106
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
117
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
120
ret = PUSH_WAIT(push, 5);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
124
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ILUT, ilut_hi,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
131
PUSH_MTHD(push, NVCA7E, SET_ILUT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
142
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
145
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
149
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
162
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
165
ret = PUSH_WAIT(push, 5);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
169
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
17
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
176
PUSH_MTHD(push, NVCA7E, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
20
ret = PUSH_WAIT(push, 4);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
24
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
28
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
39
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
47
ret = PUSH_WAIT(push, 17);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
51
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ISO(0), iso0_hi);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
53
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
59
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
64
PUSH_MTHD(push, NVCA7E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
81
PUSH_MTHD(push, NVCA7E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
85
PUSH_MTHD(push, NVCA7E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
89
PUSH_MTHD(push, NVCA7E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
99
struct nvif_push *push = &wndw->wndw.push;
drivers/gpu/drm/nouveau/gv100_fence.c
18
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/gv100_fence.c
21
ret = PUSH_WAIT(push, 13);
drivers/gpu/drm/nouveau/gv100_fence.c
25
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
drivers/gpu/drm/nouveau/gv100_fence.c
29
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
drivers/gpu/drm/nouveau/gv100_fence.c
35
PUSH_MTHD(push, NVC36F, MEM_OP_A, 0,
drivers/gpu/drm/nouveau/gv100_fence.c
40
PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
drivers/gpu/drm/nouveau/gv100_fence.c
42
PUSH_KICK(push);
drivers/gpu/drm/nouveau/gv100_fence.c
49
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/gv100_fence.c
52
ret = PUSH_WAIT(push, 6);
drivers/gpu/drm/nouveau/gv100_fence.c
56
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
drivers/gpu/drm/nouveau/gv100_fence.c
60
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
drivers/gpu/drm/nouveau/gv100_fence.c
65
PUSH_KICK(push);
drivers/gpu/drm/nouveau/include/nvif/chan.h
13
} push;
drivers/gpu/drm/nouveau/include/nvif/chan.h
17
void (*push)(struct nvif_chan *, bool main, u64 addr, u32 size,
drivers/gpu/drm/nouveau/include/nvif/chan.h
45
struct nvif_push push;
drivers/gpu/drm/nouveau/include/nvif/chan.h
54
void *push, u64 push_addr, u32 push_size, struct nvif_chan *);
drivers/gpu/drm/nouveau/include/nvif/chan.h
63
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
drivers/gpu/drm/nouveau/include/nvif/chan.h
70
void *push, u64 push_addr, u32 push_size);
drivers/gpu/drm/nouveau/include/nvif/chan.h
72
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr);
drivers/gpu/drm/nouveau/include/nvif/chan.h
74
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
drivers/gpu/drm/nouveau/include/nvif/push.h
30
int (*wait)(struct nvif_push *push, u32 size);
drivers/gpu/drm/nouveau/include/nvif/push.h
31
void (*kick)(struct nvif_push *push);
drivers/gpu/drm/nouveau/include/nvif/push.h
48
PUSH_WAIT(struct nvif_push *push, u32 size)
drivers/gpu/drm/nouveau/include/nvif/push.h
50
if (push->cur + size > push->end) {
drivers/gpu/drm/nouveau/include/nvif/push.h
51
int ret = push->wait(push, size);
drivers/gpu/drm/nouveau/include/nvif/push.h
56
push->seg = push->cur + size;
drivers/gpu/drm/nouveau/include/nvif/push.h
62
PUSH_KICK(struct nvif_push *push)
drivers/gpu/drm/nouveau/include/nvif/push.h
64
if (push->cur != push->bgn) {
drivers/gpu/drm/nouveau/include/nvif/push.h
65
push->kick(push);
drivers/gpu/drm/nouveau/include/nvif/push.h
66
push->bgn = push->cur;
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
20
struct nvkm_gpuobj *push;
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
288
return gsp->rm->api->rpc->push(gsp, argv, policy, repc);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
329
return object->client->gsp->rm->api->ctrl->push(object, argv, repc);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
387
void *repv = object->client->gsp->rm->api->alloc->push(object, argv);
drivers/gpu/drm/nouveau/nouveau_abi16.c
430
if (chan->chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM)
drivers/gpu/drm/nouveau/nouveau_bo0039.c
102
ret = PUSH_WAIT(push, 4);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
106
PUSH_MTHD(push, NV039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
107
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->cli->drm->ntfy.handle);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
50
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo0039.c
58
ret = PUSH_WAIT(push, 3);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
62
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
drivers/gpu/drm/nouveau/nouveau_bo0039.c
69
ret = PUSH_WAIT(push, 11);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
73
PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
drivers/gpu/drm/nouveau/nouveau_bo0039.c
86
PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
99
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo5039.c
102
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
106
PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
112
PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
drivers/gpu/drm/nouveau/nouveau_bo5039.c
126
PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
139
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo5039.c
142
ret = PUSH_WAIT(push, 6);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
146
PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
147
PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->cli->drm->ntfy.handle,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
43
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo5039.c
54
ret = PUSH_WAIT(push, 18 + 6 * (src_tiled + dst_tiled));
drivers/gpu/drm/nouveau/nouveau_bo5039.c
63
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
80
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
85
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo74c1.c
40
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo74c1.c
43
ret = PUSH_WAIT(push, 7);
drivers/gpu/drm/nouveau/nouveau_bo74c1.c
47
PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size,
drivers/gpu/drm/nouveau/nouveau_bo85b5.c
44
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo85b5.c
54
ret = PUSH_WAIT(push, 11);
drivers/gpu/drm/nouveau/nouveau_bo85b5.c
58
PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset),
drivers/gpu/drm/nouveau/nouveau_bo85b5.c
66
PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110);
drivers/gpu/drm/nouveau/nouveau_bo9039.c
41
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo9039.c
52
ret = PUSH_WAIT(push, 12);
drivers/gpu/drm/nouveau/nouveau_bo9039.c
56
PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
61
PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
70
PUSH_MTHD(push, NV9039, LAUNCH_DMA,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
89
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo9039.c
92
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/nouveau_bo9039.c
96
PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_bo90b5.c
37
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_bo90b5.c
47
ret = PUSH_WAIT(push, 10);
drivers/gpu/drm/nouveau/nouveau_bo90b5.c
51
PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset),
drivers/gpu/drm/nouveau/nouveau_bo90b5.c
59
PUSH_NVIM(push, NV90B5, 0x0300, 0x0110);
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
42
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
45
ret = PUSH_WAIT(push, 10);
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
49
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
63
PUSH_IMMD(push, NVA0B5, LAUNCH_DMA,
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
81
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
84
ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
88
PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff);
drivers/gpu/drm/nouveau/nouveau_chan.c
108
nvif_object_dtor(&chan->push.ctxdma);
drivers/gpu/drm/nouveau/nouveau_chan.c
109
nouveau_vma_del(&chan->push.vma);
drivers/gpu/drm/nouveau/nouveau_chan.c
110
nouveau_bo_unpin_del(&chan->push.buffer);
drivers/gpu/drm/nouveau/nouveau_chan.c
117
nouveau_channel_kick(struct nvif_push *push)
drivers/gpu/drm/nouveau/nouveau_chan.c
119
struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push);
drivers/gpu/drm/nouveau/nouveau_chan.c
120
chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn);
drivers/gpu/drm/nouveau/nouveau_chan.c
122
chan->chan.push.bgn = chan->chan.push.cur;
drivers/gpu/drm/nouveau/nouveau_chan.c
126
nouveau_channel_wait(struct nvif_push *push, u32 size)
drivers/gpu/drm/nouveau/nouveau_chan.c
128
struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push);
drivers/gpu/drm/nouveau/nouveau_chan.c
130
chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn);
drivers/gpu/drm/nouveau/nouveau_chan.c
133
chan->chan.push.bgn = chan->chan.push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/nouveau_chan.c
134
chan->chan.push.bgn = chan->chan.push.bgn + chan->dma.cur;
drivers/gpu/drm/nouveau/nouveau_chan.c
135
chan->chan.push.cur = chan->chan.push.bgn;
drivers/gpu/drm/nouveau/nouveau_chan.c
136
chan->chan.push.end = chan->chan.push.bgn + size;
drivers/gpu/drm/nouveau/nouveau_chan.c
165
ret = nouveau_bo_new_map(cli, target, size, &chan->push.buffer);
drivers/gpu/drm/nouveau/nouveau_chan.c
171
chan->chan.push.mem.object.parent = cli->base.object.parent;
drivers/gpu/drm/nouveau/nouveau_chan.c
172
chan->chan.push.mem.object.client = &cli->base;
drivers/gpu/drm/nouveau/nouveau_chan.c
173
chan->chan.push.mem.object.name = "chanPush";
drivers/gpu/drm/nouveau/nouveau_chan.c
174
chan->chan.push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
drivers/gpu/drm/nouveau/nouveau_chan.c
175
chan->chan.push.wait = nouveau_channel_wait;
drivers/gpu/drm/nouveau/nouveau_chan.c
176
chan->chan.push.kick = nouveau_channel_kick;
drivers/gpu/drm/nouveau/nouveau_chan.c
182
chan->push.addr = chan->push.buffer->offset;
drivers/gpu/drm/nouveau/nouveau_chan.c
185
ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
drivers/gpu/drm/nouveau/nouveau_chan.c
186
&chan->push.vma);
drivers/gpu/drm/nouveau/nouveau_chan.c
192
chan->push.addr = chan->push.vma->addr;
drivers/gpu/drm/nouveau/nouveau_chan.c
204
if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
drivers/gpu/drm/nouveau/nouveau_chan.c
238
&chan->push.ctxdma);
drivers/gpu/drm/nouveau/nouveau_chan.c
305
args->ctxdma = nvif_handle(&chan->push.ctxdma);
drivers/gpu/drm/nouveau/nouveau_chan.c
306
args->offset = chan->push.addr;
drivers/gpu/drm/nouveau/nouveau_chan.c
311
args->ctxdma = nvif_handle(&chan->push.ctxdma);
drivers/gpu/drm/nouveau/nouveau_chan.c
314
args->offset = ioffset + chan->push.addr;
drivers/gpu/drm/nouveau/nouveau_chan.c
440
(u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
drivers/gpu/drm/nouveau/nouveau_chan.c
441
chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000);
drivers/gpu/drm/nouveau/nouveau_chan.c
447
(u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
drivers/gpu/drm/nouveau/nouveau_chan.c
448
chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000,
drivers/gpu/drm/nouveau/nouveau_chan.c
454
(u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
drivers/gpu/drm/nouveau/nouveau_chan.c
455
chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000,
drivers/gpu/drm/nouveau/nouveau_chan.c
466
ret = PUSH_WAIT(&chan->chan.push, NOUVEAU_DMA_SKIPS);
drivers/gpu/drm/nouveau/nouveau_chan.c
471
PUSH_DATA(&chan->chan.push, 0x00000000);
drivers/gpu/drm/nouveau/nouveau_chan.c
481
ret = PUSH_WAIT(&chan->chan.push, 2);
drivers/gpu/drm/nouveau/nouveau_chan.c
485
PUSH_NVSQ(&chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
drivers/gpu/drm/nouveau/nouveau_chan.c
486
PUSH_KICK(&chan->chan.push);
drivers/gpu/drm/nouveau/nouveau_chan.h
32
} push;
drivers/gpu/drm/nouveau/nouveau_dma.c
114
OUT_RING(chan, chan->push.addr | 0x20000000);
drivers/gpu/drm/nouveau/nouveau_dma.c
62
if (val < chan->push.addr ||
drivers/gpu/drm/nouveau/nouveau_dma.c
63
val > chan->push.addr + (chan->dma.max << 2))
drivers/gpu/drm/nouveau/nouveau_dma.c
66
return (val - chan->push.addr) >> 2;
drivers/gpu/drm/nouveau/nouveau_dma.h
79
nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
drivers/gpu/drm/nouveau/nouveau_dma.h
84
nouveau_bo_rd32(chan->push.buffer, 0); \
drivers/gpu/drm/nouveau/nouveau_dma.h
85
nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
drivers/gpu/drm/nouveau/nouveau_dmem.c
558
struct nvif_push *push = &drm->dmem->migrate.chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_dmem.c
562
ret = PUSH_WAIT(push, 13);
drivers/gpu/drm/nouveau/nouveau_dmem.c
569
PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
573
PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
586
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
590
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
600
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_dmem.c
614
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
drivers/gpu/drm/nouveau/nouveau_dmem.c
631
struct nvif_push *push = &drm->dmem->migrate.chan->chan.push;
drivers/gpu/drm/nouveau/nouveau_dmem.c
635
ret = PUSH_WAIT(push, 12);
drivers/gpu/drm/nouveau/nouveau_dmem.c
641
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
645
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
drivers/gpu/drm/nouveau/nouveau_dmem.c
654
PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
drivers/gpu/drm/nouveau/nouveau_dmem.c
663
PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
drivers/gpu/drm/nouveau/nouveau_dmem.c
668
PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
drivers/gpu/drm/nouveau/nouveau_dmem.c
670
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
drivers/gpu/drm/nouveau/nouveau_drm.c
402
struct nvif_push *push = &drm->channel->chan.push;
drivers/gpu/drm/nouveau/nouveau_drm.c
404
ret = PUSH_WAIT(push, 8);
drivers/gpu/drm/nouveau/nouveau_drm.c
407
PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
drivers/gpu/drm/nouveau/nouveau_drm.c
408
PUSH_NVSQ(push, NV09F, 0x0120, 0,
drivers/gpu/drm/nouveau/nouveau_drm.c
412
PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
drivers/gpu/drm/nouveau/nouveau_exec.c
136
ret = nvif_chan_gpfifo_wait(&chan->chan, exec_job->push.count + 1, 16);
drivers/gpu/drm/nouveau/nouveau_exec.c
142
for (i = 0; i < exec_job->push.count; i++) {
drivers/gpu/drm/nouveau/nouveau_exec.c
143
struct drm_nouveau_exec_push *p = &exec_job->push.s[i];
drivers/gpu/drm/nouveau/nouveau_exec.c
176
kfree(exec_job->push.s);
drivers/gpu/drm/nouveau/nouveau_exec.c
211
for (i = 0; i < __args->push.count; i++) {
drivers/gpu/drm/nouveau/nouveau_exec.c
212
struct drm_nouveau_exec_push *p = &__args->push.s[i];
drivers/gpu/drm/nouveau/nouveau_exec.c
226
job->push.count = __args->push.count;
drivers/gpu/drm/nouveau/nouveau_exec.c
227
if (__args->push.count) {
drivers/gpu/drm/nouveau/nouveau_exec.c
228
job->push.s = kmemdup(__args->push.s,
drivers/gpu/drm/nouveau/nouveau_exec.c
229
sizeof(*__args->push.s) *
drivers/gpu/drm/nouveau/nouveau_exec.c
230
__args->push.count,
drivers/gpu/drm/nouveau/nouveau_exec.c
232
if (!job->push.s) {
drivers/gpu/drm/nouveau/nouveau_exec.c
243
args.credits = job->push.count + 1;
drivers/gpu/drm/nouveau/nouveau_exec.c
261
kfree(job->push.s);
drivers/gpu/drm/nouveau/nouveau_exec.c
304
args->push.count = pushc;
drivers/gpu/drm/nouveau/nouveau_exec.c
305
args->push.s = u_memcpya(pushs, pushc, sizeof(*args->push.s));
drivers/gpu/drm/nouveau/nouveau_exec.c
306
if (IS_ERR(args->push.s))
drivers/gpu/drm/nouveau/nouveau_exec.c
307
return PTR_ERR(args->push.s);
drivers/gpu/drm/nouveau/nouveau_exec.c
335
u_free(args->push.s);
drivers/gpu/drm/nouveau/nouveau_exec.c
344
u_free(args->push.s);
drivers/gpu/drm/nouveau/nouveau_exec.h
27
} push;
drivers/gpu/drm/nouveau/nouveau_exec.h
38
} push;
drivers/gpu/drm/nouveau/nouveau_gem.c
752
struct drm_nouveau_gem_pushbuf_push *push;
drivers/gpu/drm/nouveau/nouveau_gem.c
804
push = u_memcpya(req->push, req->nr_push, sizeof(*push));
drivers/gpu/drm/nouveau/nouveau_gem.c
805
if (IS_ERR(push))
drivers/gpu/drm/nouveau/nouveau_gem.c
806
return nouveau_abi16_put(abi16, PTR_ERR(push));
drivers/gpu/drm/nouveau/nouveau_gem.c
810
u_free(push);
drivers/gpu/drm/nouveau/nouveau_gem.c
816
if (push[i].bo_index >= req->nr_buffers) {
drivers/gpu/drm/nouveau/nouveau_gem.c
862
bo[push[i].bo_index].user_priv;
drivers/gpu/drm/nouveau/nouveau_gem.c
863
u64 addr = vma->addr + push[i].offset;
drivers/gpu/drm/nouveau/nouveau_gem.c
864
u32 length = push[i].length & ~NOUVEAU_GEM_PUSHBUF_NO_PREFETCH;
drivers/gpu/drm/nouveau/nouveau_gem.c
865
bool no_prefetch = push[i].length & NOUVEAU_GEM_PUSHBUF_NO_PREFETCH;
drivers/gpu/drm/nouveau/nouveau_gem.c
873
ret = PUSH_WAIT(&chan->chan.push, req->nr_push * 2);
drivers/gpu/drm/nouveau/nouveau_gem.c
881
bo[push[i].bo_index].user_priv;
drivers/gpu/drm/nouveau/nouveau_gem.c
883
PUSH_CALL(&chan->chan.push, nvbo->offset + push[i].offset);
drivers/gpu/drm/nouveau/nouveau_gem.c
884
PUSH_DATA(&chan->chan.push, 0);
drivers/gpu/drm/nouveau/nouveau_gem.c
887
ret = PUSH_WAIT(&chan->chan.push, req->nr_push * (2 + NOUVEAU_DMA_SKIPS));
drivers/gpu/drm/nouveau/nouveau_gem.c
895
bo[push[i].bo_index].user_priv;
drivers/gpu/drm/nouveau/nouveau_gem.c
898
cmd = chan->push.addr + ((chan->dma.cur + 2) << 2);
drivers/gpu/drm/nouveau/nouveau_gem.c
912
nouveau_bo_wr32(nvbo, (push[i].offset +
drivers/gpu/drm/nouveau/nouveau_gem.c
913
push[i].length - 8) / 4, cmd);
drivers/gpu/drm/nouveau/nouveau_gem.c
916
PUSH_JUMP(&chan->chan.push, nvbo->offset + push[i].offset);
drivers/gpu/drm/nouveau/nouveau_gem.c
917
PUSH_DATA(&chan->chan.push, 0);
drivers/gpu/drm/nouveau/nouveau_gem.c
919
PUSH_DATA(&chan->chan.push, 0);
drivers/gpu/drm/nouveau/nouveau_gem.c
960
u_free(push);
drivers/gpu/drm/nouveau/nouveau_gem.c
972
(chan->push.addr + ((chan->dma.cur + 2) << 2));
drivers/gpu/drm/nouveau/nv04_fence.c
42
struct nvif_push *push = &unrcu_pointer(fence->channel)->chan.push;
drivers/gpu/drm/nouveau/nv04_fence.c
43
int ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/nv04_fence.c
45
PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno);
drivers/gpu/drm/nouveau/nv04_fence.c
46
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nv10_fence.c
35
struct nvif_push *push = &fence->channel->chan.push;
drivers/gpu/drm/nouveau/nv10_fence.c
36
int ret = PUSH_WAIT(push, 2);
drivers/gpu/drm/nouveau/nv10_fence.c
38
PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
drivers/gpu/drm/nouveau/nv10_fence.c
39
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nv17_fence.c
42
struct nvif_push *ppush = &prev->chan.push;
drivers/gpu/drm/nouveau/nv17_fence.c
43
struct nvif_push *npush = &chan->chan.push;
drivers/gpu/drm/nouveau/nv84_fence.c
38
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nv84_fence.c
39
int ret = PUSH_WAIT(push, 8);
drivers/gpu/drm/nouveau/nv84_fence.c
41
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
drivers/gpu/drm/nouveau/nv84_fence.c
43
PUSH_MTHD(push, NV826F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nv84_fence.c
53
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nv84_fence.c
61
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nv84_fence.c
62
int ret = PUSH_WAIT(push, 7);
drivers/gpu/drm/nouveau/nv84_fence.c
64
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
drivers/gpu/drm/nouveau/nv84_fence.c
66
PUSH_MTHD(push, NV826F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nv84_fence.c
74
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nvc0_fence.c
37
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nvc0_fence.c
38
int ret = PUSH_WAIT(push, 6);
drivers/gpu/drm/nouveau/nvc0_fence.c
40
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvc0_fence.c
52
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nvc0_fence.c
60
struct nvif_push *push = &chan->chan.push;
drivers/gpu/drm/nouveau/nvc0_fence.c
61
int ret = PUSH_WAIT(push, 5);
drivers/gpu/drm/nouveau/nvc0_fence.c
63
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvc0_fence.c
72
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nvif/chan.c
10
struct nvif_chan *chan = container_of(push, typeof(*chan), push);
drivers/gpu/drm/nouveau/nvif/chan.c
107
chan->push.mem.object.map.ptr = push;
drivers/gpu/drm/nouveau/nvif/chan.c
108
chan->push.wait = nvif_chan_gpfifo_push_wait;
drivers/gpu/drm/nouveau/nvif/chan.c
109
chan->push.kick = nvif_chan_gpfifo_push_kick;
drivers/gpu/drm/nouveau/nvif/chan.c
11
u32 put = push->bgn - (u32 *)chan->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/nvif/chan.c
110
chan->push.addr = push_addr;
drivers/gpu/drm/nouveau/nvif/chan.c
111
chan->push.hw.max = push_size >> 2;
drivers/gpu/drm/nouveau/nvif/chan.c
112
chan->push.bgn = chan->push.cur = chan->push.end = push;
drivers/gpu/drm/nouveau/nvif/chan.c
118
struct nvif_push *push = &chan->push;
drivers/gpu/drm/nouveau/nvif/chan.c
119
u32 cur = push->cur - (u32 *)push->mem.object.map.ptr;
drivers/gpu/drm/nouveau/nvif/chan.c
125
u32 get = chan->func->push.read_get(chan);
drivers/gpu/drm/nouveau/nvif/chan.c
128
free = push->hw.max - cur;
drivers/gpu/drm/nouveau/nvif/chan.c
132
PUSH_KICK(push);
drivers/gpu/drm/nouveau/nvif/chan.c
135
get = chan->func->push.read_get(chan);
drivers/gpu/drm/nouveau/nvif/chan.c
15
if (push->end - push->cur < chan->func->gpfifo.post_size)
drivers/gpu/drm/nouveau/nvif/chan.c
155
push->bgn = (u32 *)push->mem.object.map.ptr + cur;
drivers/gpu/drm/nouveau/nvif/chan.c
156
push->cur = push->bgn;
drivers/gpu/drm/nouveau/nvif/chan.c
157
push->end = push->bgn + free - chan->func->gpfifo.post_size;
drivers/gpu/drm/nouveau/nvif/chan.c
16
push->end = push->cur + chan->func->gpfifo.post_size;
drivers/gpu/drm/nouveau/nvif/chan.c
21
cnt = push->cur - push->bgn;
drivers/gpu/drm/nouveau/nvif/chan.c
23
chan->func->gpfifo.push(chan, true, chan->push.addr + (put << 2), cnt << 2, false);
drivers/gpu/drm/nouveau/nvif/chan.c
28
nvif_chan_gpfifo_push_wait(struct nvif_push *push, u32 push_nr)
drivers/gpu/drm/nouveau/nvif/chan.c
30
struct nvif_chan *chan = container_of(push, typeof(*chan), push);
drivers/gpu/drm/nouveau/nvif/chan.c
38
const u32 *map = chan->push.mem.object.map.ptr;
drivers/gpu/drm/nouveau/nvif/chan.c
39
const u32 pbptr = (chan->push.cur - map) + chan->func->gpfifo.post_size;
drivers/gpu/drm/nouveau/nvif/chan.c
51
chan->func->gpfifo.push(chan, false, addr, size, no_prefetch);
drivers/gpu/drm/nouveau/nvif/chan.c
57
struct nvif_push *push = &chan->push;
drivers/gpu/drm/nouveau/nvif/chan.c
73
if (push->cur + push_nr > push->end) {
drivers/gpu/drm/nouveau/nvif/chan.c
8
nvif_chan_gpfifo_push_kick(struct nvif_push *push)
drivers/gpu/drm/nouveau/nvif/chan.c
97
void *push, u64 push_addr, u32 push_size, struct nvif_chan *chan)
drivers/gpu/drm/nouveau/nvif/chan506f.c
31
chan->push.end = chan->push.cur;
drivers/gpu/drm/nouveau/nvif/chan506f.c
45
struct nvif_push *push = &chan->push;
drivers/gpu/drm/nouveau/nvif/chan506f.c
51
push->hw.get = (tlget - push->addr) >> 2;
drivers/gpu/drm/nouveau/nvif/chan506f.c
54
return push->hw.get;
drivers/gpu/drm/nouveau/nvif/chan506f.c
59
.push.read_get = nvif_chan506f_read_get,
drivers/gpu/drm/nouveau/nvif/chan506f.c
61
.gpfifo.push = nvif_chan506f_gpfifo_push,
drivers/gpu/drm/nouveau/nvif/chan506f.c
67
void *push, u64 push_addr, u32 push_size)
drivers/gpu/drm/nouveau/nvif/chan506f.c
70
push, push_addr, push_size, chan);
drivers/gpu/drm/nouveau/nvif/chan906f.c
24
struct nvif_push *push = &chan->push;
drivers/gpu/drm/nouveau/nvif/chan906f.c
27
ret = PUSH_WAIT(push, NVIF_CHAN906F_SEM_RELEASE_SIZE);
drivers/gpu/drm/nouveau/nvif/chan906f.c
31
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvif/chan906f.c
67
.push.read_get = nvif_chan906f_read_get,
drivers/gpu/drm/nouveau/nvif/chan906f.c
69
.gpfifo.push = nvif_chan506f_gpfifo_push,
drivers/gpu/drm/nouveau/nvif/chan906f.c
78
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
drivers/gpu/drm/nouveau/nvif/chan906f.c
81
nvif_chan_gpfifo_ctor(func, userd, gpfifo, gpfifo_size, push, push_addr, push_size, chan);
drivers/gpu/drm/nouveau/nvif/chan906f.c
89
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr)
drivers/gpu/drm/nouveau/nvif/chan906f.c
92
push, push_addr, push_size, sema, sema_addr, chan);
drivers/gpu/drm/nouveau/nvif/chanc36f.c
29
struct nvif_push *push = &chan->push;
drivers/gpu/drm/nouveau/nvif/chanc36f.c
32
ret = PUSH_WAIT(push, NVIF_CHANC36F_SEM_RELEASE_SIZE);
drivers/gpu/drm/nouveau/nvif/chanc36f.c
36
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(addr),
drivers/gpu/drm/nouveau/nvif/chanc36f.c
42
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
drivers/gpu/drm/nouveau/nvif/chanc36f.c
53
.push.read_get = nvif_chan906f_read_get,
drivers/gpu/drm/nouveau/nvif/chanc36f.c
55
.gpfifo.push = nvif_chan506f_gpfifo_push,
drivers/gpu/drm/nouveau/nvif/chanc36f.c
64
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
drivers/gpu/drm/nouveau/nvif/chanc36f.c
70
push, push_addr, push_size, sema, sema_addr, chan);
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c
195
if (args->v0.id >= nr || !args->v0.pushbuf != !user->func->push)
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c
210
if (chan->func->push) {
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c
211
ret = chan->func->push(chan, args->v0.pushbuf);
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.h
22
u64 push;
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.h
36
int (*push)(struct nvkm_disp_chan *, u64 object);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
605
nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
627
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
972
nvkm_wr32(device, 0x610494, chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
994
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
109
nvkm_wr32(device, 0x611494, chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
131
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
42
nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
64
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
381
nvkm_wr32(device, 0x610b24 + poff, lower_32_bits(chan->push));
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
382
nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push));
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
403
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
529
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
765
nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push));
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
766
nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push));
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
778
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
663
nvkm_wr32(device, 0x610204 + (ctrl * 0x0010), chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
694
case NVKM_MEM_TARGET_VRAM: chan->push = 0x00000001; break;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
695
case NVKM_MEM_TARGET_NCOH: chan->push = 0x00000002; break;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
696
case NVKM_MEM_TARGET_HOST: chan->push = 0x00000003; break;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
701
chan->push |= nvkm_memory_addr(chan->memory) >> 8;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
707
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
975
nvkm_wr32(device, 0x610204, chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
997
.push = nv50_disp_dmac_push,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
289
nvkm_gpuobj_del(&chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
432
ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16, &chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
72
nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
126
nvkm_wo32(ramfc, base + 0x08, chan->push->addr >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
360
u32 push = nvkm_rd32(device, 0x003220);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
379
push);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
393
nv_dma_state_err(state), push);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
47
nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
48
nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
49
nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
105
nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/alloc.c
109
.push = r535_gsp_rpc_rm_alloc_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ctrl.c
91
.push = r535_gsp_rpc_rm_ctrl_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
210
.push = r535_dmac_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
220
.push = r535_dmac_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
250
.push = r535_dmac_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
702
.push = r535_gsp_rpc_push,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
46
void *(*push)(struct nvkm_gsp *gsp, void *argv,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
53
int (*push)(struct nvkm_gsp_object *, void **params, u32 repc);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
59
void *(*push)(struct nvkm_gsp_object *, void *params);
drivers/infiniband/ulp/srpt/ib_srpt.c
1695
goto push;
drivers/infiniband/ulp/srpt/ib_srpt.c
1707
goto push;
drivers/infiniband/ulp/srpt/ib_srpt.c
1746
push:
drivers/md/dm-cache-policy-smq.c
1483
push(mq, e);
drivers/md/dm-kcopyd.c
534
push(&kc->complete_jobs, job);
drivers/md/dm-kcopyd.c
541
push(&kc->complete_jobs, job);
drivers/md/dm-kcopyd.c
545
push(&kc->io_jobs, job);
drivers/md/dm-kcopyd.c
596
push(&job->kc->io_jobs, job);
drivers/md/dm-kcopyd.c
627
push(&kc->complete_jobs, job);
drivers/md/dm-kcopyd.c
685
push(&kc->callback_jobs, job);
drivers/md/dm-kcopyd.c
687
push(&kc->io_jobs, job);
drivers/md/dm-kcopyd.c
689
push(&kc->pages_jobs, job);
drivers/md/dm-kcopyd.c
757
push(&kc->complete_jobs, job);
drivers/md/dm-kcopyd.c
893
push(&kc->callback_jobs, job);
drivers/net/ethernet/netronome/nfp/flower/action.c
376
struct nfp_fl_push_geneve *push;
drivers/net/ethernet/netronome/nfp/flower/action.c
384
push = (struct nfp_fl_push_geneve *)&nfp_fl->action_data[len];
drivers/net/ethernet/netronome/nfp/flower/action.c
385
push->head.jump_id = NFP_FL_ACTION_OPCODE_PUSH_GENEVE;
drivers/net/ethernet/netronome/nfp/flower/action.c
386
push->head.len_lw = act_size >> NFP_FL_LW_SIZ;
drivers/net/ethernet/netronome/nfp/flower/action.c
387
push->reserved = 0;
drivers/net/ethernet/netronome/nfp/flower/action.c
388
push->class = opt->opt_class;
drivers/net/ethernet/netronome/nfp/flower/action.c
389
push->type = opt->type;
drivers/net/ethernet/netronome/nfp/flower/action.c
390
push->length = opt->length;
drivers/net/ethernet/netronome/nfp/flower/action.c
391
memcpy(&push->opt_data, opt->opt_data, opt->length * 4);
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
1576
bool push, timestamp;
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
1598
push = netxen_get_lro_sts_push_flag(sts_data0);
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
1623
th->psh = push;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1272
bool push, timestamp;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1292
push = qlcnic_get_lro_sts_push_flag(sts_data0);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1334
th->psh = push;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1793
bool push;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1814
push = qlcnic_83xx_is_psh_bit(sts_data[1]);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1856
th->psh = push;
drivers/net/geneve.c
1648
static void geneve_offload_rx_ports(struct net_device *dev, bool push)
drivers/net/geneve.c
1657
if (push) {
drivers/net/vxlan/vxlan_core.c
3319
static void vxlan_offload_rx_ports(struct net_device *dev, bool push)
drivers/net/vxlan/vxlan_core.c
3337
if (push)
drivers/rtc/sysfs.c
153
time64_t push = 0;
drivers/rtc/sysfs.c
172
push = 1;
drivers/rtc/sysfs.c
182
if (alarm > now || push) {
drivers/rtc/sysfs.c
191
if (push) {
drivers/rtc/sysfs.c
192
push = rtc_tm_to_time64(&alm.time);
drivers/rtc/sysfs.c
193
alarm += push;
drivers/rtc/sysfs.c
196
} else if (push)
drivers/tty/n_tty.c
103
unsigned char push:1;
drivers/tty/n_tty.c
1783
ldata->push = 0;
drivers/tty/n_tty.c
1787
ldata->push = 1;
drivers/tty/n_tty.c
2036
if (!ldata->push)
drivers/tty/n_tty.c
2039
ldata->push = 0;
drivers/tty/n_tty.c
320
ldata->push = 0;
drivers/tty/serial/ip22zilog.c
252
bool push = up->port.state != NULL;
drivers/tty/serial/ip22zilog.c
306
if (push)
drivers/tty/serial/ip22zilog.c
309
return push;
drivers/tty/serial/ip22zilog.c
428
bool push = false;
drivers/tty/serial/ip22zilog.c
443
push = ip22zilog_receive_chars(up, channel);
drivers/tty/serial/ip22zilog.c
451
if (push)
drivers/tty/serial/ip22zilog.c
457
push = false;
drivers/tty/serial/ip22zilog.c
466
push = ip22zilog_receive_chars(up, channel);
drivers/tty/serial/ip22zilog.c
474
if (push)
drivers/tty/serial/pmac_zilog.c
418
bool push;
drivers/tty/serial/pmac_zilog.c
428
push = false;
drivers/tty/serial/pmac_zilog.c
439
push = pmz_receive_chars(uap_a);
drivers/tty/serial/pmac_zilog.c
446
if (push)
drivers/tty/serial/pmac_zilog.c
453
push = false;
drivers/tty/serial/pmac_zilog.c
464
push = pmz_receive_chars(uap_b);
drivers/tty/serial/pmac_zilog.c
471
if (push)
drivers/usb/atm/usbatm.c
401
vcc->push(vcc, skb);
drivers/usb/gadget/function/u_serial.c
120
struct delayed_work push;
drivers/usb/gadget/function/u_serial.c
1229
INIT_DELAYED_WORK(&port->push, gs_rx_push);
drivers/usb/gadget/function/u_serial.c
1257
cancel_delayed_work_sync(&port->push);
drivers/usb/gadget/function/u_serial.c
367
struct gs_port *port = container_of(w, struct gs_port, push);
drivers/usb/gadget/function/u_serial.c
449
schedule_delayed_work(&port->push, 1);
drivers/usb/gadget/function/u_serial.c
465
schedule_delayed_work(&port->push, 0);
drivers/usb/gadget/function/u_serial.c
871
schedule_delayed_work(&port->push, 0);
drivers/usb/host/xhci-dbgcap.h
127
struct tasklet_struct push;
drivers/usb/host/xhci-dbgtty.c
194
tasklet_schedule(&port->push);
drivers/usb/host/xhci-dbgtty.c
387
tasklet_schedule(&port->push);
drivers/usb/host/xhci-dbgtty.c
409
struct dbc_port *port = from_tasklet(port, t, push);
drivers/usb/host/xhci-dbgtty.c
441
tasklet_schedule(&port->push);
drivers/usb/host/xhci-dbgtty.c
470
tasklet_setup(&port->push, dbc_rx_push);
drivers/usb/host/xhci-dbgtty.c
482
tasklet_kill(&port->push);
include/linux/atmdev.h
105
void (*push)(struct atm_vcc *vcc,struct sk_buff *skb);
include/linux/compiler_types.h
721
#define __diag_push() __diag(push)
include/uapi/drm/nouveau_drm.h
204
__u64 push;
net/atm/br2684.c
559
if (atmvcc->push == NULL) {
net/atm/br2684.c
593
brvcc->old_push = atmvcc->push;
net/atm/br2684.c
598
atmvcc->push = br2684_push;
net/atm/br2684.c
749
if (atmvcc->push != br2684_push)
net/atm/clip.c
430
if (!vcc->push)
net/atm/clip.c
446
clip_vcc->old_push = vcc->push;
net/atm/clip.c
448
vcc->push = clip_push;
net/atm/clip.c
465
if (vcc->push != clip_push) {
net/atm/clip.c
658
if (vcc->push == clip_push)
net/atm/clip.c
675
vcc->push = NULL;
net/atm/common.c
162
vcc->push = NULL;
net/atm/common.c
182
if (vcc->push)
net/atm/common.c
183
vcc->push(vcc, NULL); /* atmarpd has no push */
net/atm/common.c
240
vcc->push(vcc, skb);
net/atm/lec.c
1291
vcc->push = entry->old_push;
net/atm/lec.c
1304
entry->recv_vcc->push = entry->old_recv_push;
net/atm/lec.c
2173
to_add->old_push = vcc->push;
net/atm/lec.c
2174
vcc->push = lec_push;
net/atm/lec.c
729
&ioc_data, vcc, vcc->push);
net/atm/lec.c
731
vcc->push = lec_push;
net/atm/mpc.c
646
vcc->push = mpc_push;
net/atm/pppoatm.c
171
atmvcc->push = pvcc->old_push;
net/atm/pppoatm.c
191
atmvcc->push(atmvcc, NULL); /* Pass along bad news */
net/atm/pppoatm.c
407
pvcc->old_push = atmvcc->push;
net/atm/pppoatm.c
423
atmvcc->push = pppoatm_push;
net/atm/pppoatm.c
445
if (cmd != ATM_SETBACKEND && atmvcc->push != pppoatm_push)
net/atm/raw.c
64
vcc->push = atm_push_raw;
net/atm/raw.c
73
vcc->push = atm_push_raw;
net/atm/raw.c
85
vcc->push = atm_push_raw;
sound/core/pcm_native.c
1680
static int snd_pcm_pause(struct snd_pcm_substream *substream, bool push)
sound/core/pcm_native.c
1683
(__force snd_pcm_state_t)push);
sound/core/pcm_native.c
1687
bool push)
sound/core/pcm_native.c
1690
(__force snd_pcm_state_t)push);
sound/soc/dwc/dwc-pcm.c
101
if (push)
sound/soc/dwc/dwc-pcm.c
110
if (push) {
sound/soc/dwc/dwc-pcm.c
95
static void dw_pcm_transfer(struct dw_i2s_dev *dev, bool push)
tools/perf/ui/gtk/helpline.c
51
.push = gtk_helpline_push,
tools/perf/ui/helpline.c
27
.push = nop_helpline__push,
tools/perf/ui/helpline.c
40
helpline_fns->push(msg);
tools/perf/ui/helpline.h
10
void (*push)(const char *msg);
tools/perf/ui/tui/helpline.c
54
.push = tui_helpline__push,
tools/perf/util/mmap.c
321
int push(struct mmap *map, void *to, void *buf, size_t size))
tools/perf/util/mmap.c
340
if (push(md, to, buf, size) < 0) {
tools/perf/util/mmap.c
350
if (push(md, to, buf, size) < 0) {
tools/perf/util/mmap.h
58
int push(struct mmap *map, void *to, void *buf, size_t size));
tools/testing/selftests/bpf/benchs/bench_trigger.c
598
BENCH_TRIG_USERMODE(uprobe_push, push, "uprobe-push");
tools/testing/selftests/bpf/benchs/bench_trigger.c
601
BENCH_TRIG_USERMODE(uretprobe_push, push, "uretprobe-push");
tools/testing/selftests/bpf/benchs/bench_trigger.c
604
BENCH_TRIG_USERMODE(uprobe_multi_push, push, "uprobe-multi-push");
tools/testing/selftests/bpf/benchs/bench_trigger.c
607
BENCH_TRIG_USERMODE(uretprobe_multi_push, push, "uretprobe-multi-push");
tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
163
static void test_sockmap_ktls_tx_cork(int family, int sotype, bool push)
tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
198
if (push) {
tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
243
static void test_sockmap_ktls_tx_no_buf(int family, int sotype, bool push)
tools/testing/selftests/bpf/test_sockmap.c
553
int bytes_cnt = *bytes_cnt_p, check_cnt = *check_cnt_p, push = *push_p;
tools/testing/selftests/bpf/test_sockmap.c
574
if (push > 0 &&
tools/testing/selftests/bpf/test_sockmap.c
575
check_cnt == verify_push_start + verify_push_len - push) {
tools/testing/selftests/bpf/test_sockmap.c
578
skipped = push;
tools/testing/selftests/bpf/test_sockmap.c
579
if (j + push >= msg->msg_iov[i].iov_len)
tools/testing/selftests/bpf/test_sockmap.c
581
push -= skipped;
tools/testing/selftests/bpf/test_sockmap.c
597
push = verify_push_len;
tools/testing/selftests/bpf/test_sockmap.c
600
if (push > 0 &&
tools/testing/selftests/bpf/test_sockmap.c
601
check_cnt == verify_push_start + verify_push_len - push)
tools/testing/selftests/bpf/test_sockmap.c
617
push = verify_push_len;
tools/testing/selftests/bpf/test_sockmap.c
625
*push_p = push;
tools/testing/selftests/bpf/test_sockmap.c
685
int push = 0;
tools/testing/selftests/bpf/test_sockmap.c
713
push = verify_push_len;
tools/testing/selftests/bpf/test_sockmap.c
791
&check_cnt, &push);
tools/testing/selftests/bpf/test_sockmap.c
803
&push);
tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h
490
.machine push; \
tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h
511
.machine push; \
tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h
519
.machine push; \