drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10701

wb_info->writeback_source_plane = pipe->plane_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11176

struct drm_plane_state *plane_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11209

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11212

if (IS_ERR(plane_state)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11213

ret = PTR_ERR(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12148

static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12151

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12154

*src_w = plane_state->src_h >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12155

*src_h = plane_state->src_w >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12160

*src_w = plane_state->src_w >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12161

*src_h = plane_state->src_h >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12167

dm_get_plane_scale(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12172

dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12173

*out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12174

*out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12306

struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12332

for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12342

if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12343

drm_atomic_plane_disabling(old_plane_state, plane_state) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12344

old_plane_state->fb->format != plane_state->fb->format) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12349

dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12382

for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12390

if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12395

dm_get_plane_scale(plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12408

if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12409

plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12410

plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6070

fill_plane_color_attributes(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6079

if (plane_state->state && plane_state->state->plane_color_pipeline)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6086

full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6088

switch (plane_state->color_encoding) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6119

const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6125

const struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6127

to_amdgpu_framebuffer(plane_state->fb);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6188

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6210

plane_info->layer_index = plane_state->normalized_zpos;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6212

ret = fill_plane_color_attributes(plane_state, plane_info->format,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6227

plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6235

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6239

struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6244

ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6253

ret = fill_dc_plane_info_and_addr(adev, plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6283

plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1070

struct drm_plane_state *plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1083

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1105

struct drm_plane_state *plane_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1107

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1419

__set_dm_plane_degamma(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1423

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1496

__set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1502

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1523

__set_dm_plane_colorop_3x4_matrix(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1529

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1564

__set_dm_plane_colorop_multiplier(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1570

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1593

__set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1599

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1700

__set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1707

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1756

__set_dm_plane_colorop_blend(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1762

struct drm_atomic_state *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1823

amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1826

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1847

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1849

plane_state->plane->index);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1862

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1864

plane_state->plane->index);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1873

amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1876

struct drm_colorop *colorop = plane_state->color_pipeline;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1877

struct drm_device *dev = plane_state->plane->dev;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1886

ret = __set_dm_plane_colorop_degamma(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1897

ret = __set_dm_plane_colorop_multiplier(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1908

ret = __set_dm_plane_colorop_3x4_matrix(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1920

ret = __set_dm_plane_colorop_shaper(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1936

ret = __set_dm_plane_colorop_3dlut(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1948

ret = __set_dm_plane_colorop_blend(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1974

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1978

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1984

ret = amdgpu_dm_verify_lut3d_size(adev, plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2000

ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2056

if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2059

return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1004

struct dc_plane_state *plane_state =

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1008

adev, afb, plane_state->format, plane_state->rotation,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

101

void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1010

&plane_state->tiling_info, &plane_state->plane_size,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1011

&plane_state->dcc, &plane_state->address,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

111

if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

112

plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

123

uint32_t format = plane_state->fb->format->format;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

133

if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

137

if (plane_state->alpha < 0xffff) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

139

*global_alpha_value = plane_state->alpha >> 8;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

63

void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

231

__field(const struct drm_plane_state *, plane_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

260

__entry->plane_state = state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

293

__entry->plane_id, __entry->plane_type, __entry->plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

385

TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

389

TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

428

__entry->dst_x = plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

429

__entry->dst_y = plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

430

__entry->dst_w = plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

431

__entry->dst_h = plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

432

__entry->src_x = plane_state->src_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

433

__entry->src_y = plane_state->src_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

434

__entry->src_w = plane_state->src_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

435

__entry->src_h = plane_state->src_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

436

__entry->clip_x = plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

437

__entry->clip_y = plane_state->clip_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

438

__entry->clip_w = plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

439

__entry->clip_h = plane_state->clip_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

448

__entry->flip_immediate = plane_state->flip_immediate;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

449

__entry->surface_pitch = plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

450

__entry->format = plane_state->format;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

451

__entry->swizzle = plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

55

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

64

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

73

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

83

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

85

if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

86

&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

87

&& plane_state->input_csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

88

&& plane_state->coeff_reduction_factor.value != 0) {

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

90

dc_fixpt_mul(plane_state->coeff_reduction_factor,

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

40

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2806

ASSERT(pipe[i].plane_state);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2809

if (!pipe[i].plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2814

if (!pipe[i].plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2832

switch (pipe[i].plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2848

switch (pipe[i].plane_state->format) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2883

pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2890

switch (pipe[i].bottom_pipe->plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2927

if (pipe[i].plane_state) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2935

switch (pipe[i].plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2951

switch (pipe[i].plane_state->format) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

166

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

110

if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

493

int width = pipe->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

494

int height = pipe->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

498

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

499

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

584

if (curr_pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

586

disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

587

disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

398

int width = pipe->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

399

int height = pipe->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

403

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

404

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

487

if (curr_pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

489

disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

490

disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

1233

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

1243

memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/core/dc.c

1289

struct dc_plane_state *plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1310

plane_state = stream_status->plane_states[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1312

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

1318

if (pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1368

if (old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

1396

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2011

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

2013

return (pipe_ctx->plane_state == plane_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2538

if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))

drivers/gpu/drm/amd/display/dc/core/dc.c

2542

pipe->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

2544

if (pipe->plane_state->status.is_flip_pending)

drivers/gpu/drm/amd/display/dc/core/dc.c

2594

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2660

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

2667

if (plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3638

if (pipe_ctx->plane_state != surface)

drivers/gpu/drm/amd/display/dc/core/dc.c

3879

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

3901

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

3940

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

3962

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4028

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4036

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4040

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4104

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4114

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4119

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4121

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4124

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4127

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4129

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4205

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4354

pipe_ctx->stream && pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4366

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4371

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4373

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4375

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4378

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4380

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4385

plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4386

plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4399

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4418

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4425

ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4429

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4464

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4472

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4477

pipe_ctx->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/core/dc.c

4483

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4491

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4506

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4508

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4594

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4599

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4600

pipe_ctx->plane_state->skip_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

4794

if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

4795

pipe_ctx->plane_state->force_full_update = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4973

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6637

if (pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6639

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

6640

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

6641

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6644

if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6645

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6646

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6650

if (pipe_ctx->plane_state->src_rect.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6651

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6652

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6653

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

6654

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

6658

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6659

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6660

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

6663

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6664

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6665

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6666

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

6669

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6670

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6671

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6672

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6675

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6676

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6680

if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6682

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

6683

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

6684

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6685

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

6686

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

6687

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

6688

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

6775

if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6883

if (pipe_ctx->plane_state && pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6884

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

6887

state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6888

state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6889

state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6891

state->mpc.mpcc_global_alpha[i] = plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/core/dc.c

6892

state->mpc.mpcc_global_gain[i] = plane_state->global_alpha ? 255 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6905

if (plane_state->gamma_correction.type != GAMMA_CS_TFM_1D && plane_state->gamma_correction.num_entries > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1396

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1401

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1949

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1951

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1957

plane_state->format,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1959

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1960

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1969

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1970

struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2068

switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2136

if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2142

pipe->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2144

if (!pipe->plane_state->status.is_flip_pending)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2149

ASSERT(!pipe->plane_state->status.is_flip_pending);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

349

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

359

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

378

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

597

if (!pipe_ctx->plane_state->dcc.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

739

struct dc_plane_state *plane = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

796

if (current_mpc_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

797

if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

799

block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

803

if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

806

block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

810

if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

814

block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

826

if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

829

block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

834

if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

839

if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

844

if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

922

current_mpc_pipe->stream && current_mpc_pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

923

current_mpc_pipe->plane_state->update_flags.bits.addr_update &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

924

!current_mpc_pipe->plane_state->skip_manual_trigger) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

979

params->set_input_transfer_func_params.plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1153

&pipe_ctx->plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1182

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1184

struct rect surf_src = plane_state->src_rect;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1191

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1192

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1197

plane_state->dst_rect.width);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1200

plane_state->dst_rect.height);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1298

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1300

struct rect src = plane_state->src_rect;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1313

pipe_ctx, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1328

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1329

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1487

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1496

if (!plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1497

!plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1498

!plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1499

!plane_state->src_rect.width ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1500

!plane_state->src_rect.height) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1517

pipe_ctx->plane_state->format);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1524

if (plane_state->ctx->dce_version > DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1529

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1545

if (!res && plane_state->is_phantom)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1566

if (plane_state->ctx->dce_version > DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1571

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1581

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1585

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1593

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1597

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1608

&plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1614

&plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1618

if (!res && plane_state->is_phantom)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1632

if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1633

ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1664

plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1665

plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1666

plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1667

plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1668

plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1669

plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1670

plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1671

plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1672

plane_state->clip_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1673

plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1674

plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1675

plane_state->clip_rect.y);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1688

int cur_layer = pipe_ctx->plane_state->layer_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1704

if (!test_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1705

!test_pipe->plane_state->visible ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1706

test_pipe->plane_state->layer_index == cur_layer)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1720

if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1747

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1986

return pipe_ctx->plane_state && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1988

return !pipe_ctx->plane_state && !pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2061

if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2063

pipe->top_pipe->plane_state != plane)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2075

while (pipe && pipe->plane_state == plane) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2110

pri_dpp_pipe->top_pipe->plane_state == pri_dpp_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2121

while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2134

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2139

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2276

if (pipe_a->plane_state && !pipe_b->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2278

else if (!pipe_a->plane_state && pipe_b->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2284

if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2285

(pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2287

else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2288

(pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2433

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2440

dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2548

dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2564

if (pipe->stream == otg_master->stream && pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2587

if (pipe->plane_state == plane)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2604

split_pipe->top_pipe->plane_state == split_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2609

if (split_pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2954

ASSERT(otg_master->plane_state == NULL);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3017

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3023

if (opp_head_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3027

opp_head_pipe->plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3067

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3095

sec_pipe->plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3118

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3122

if (otg_master_pipe->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3124

plane_state, new_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3127

otg_master_pipe, plane_state, new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3132

plane_state, new_ctx, pool);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3135

pool, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3144

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3151

if (pipe_ctx->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3167

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3231

new_opp_head->plane_state = last_opp_head->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3243

new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3371

new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3500

dpp_pipes[0]->plane_state, new_ctx, pool);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4436

pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4437

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4438

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5193

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5198

if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5199

plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5204

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5692

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

465

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

483

plane_state, MAX_SURFACES);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

490

dc->current_state, pool, otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

500

otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

513

otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

521

plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

523

dc_plane_state_retain(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

533

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

540

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

555

state, pool, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

558

if (stream_status->plane_states[i] == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

926

if (pipe->plane_state && pipe->stream && dc_state_get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

418

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

511

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

112

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

119

if (!plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

120

!plane_state->ctx ||

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

121

!plane_state->ctx->dc) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

126

plane_status = &plane_state->status;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

127

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

137

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

140

if (pipe_ctx->plane_state && flags.bits.address)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

141

pipe_ctx->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

152

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

162

void dc_plane_state_retain(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

164

kref_get(&plane_state->refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

169

struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

170

dc_plane_destruct(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

171

kvfree(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

174

void dc_plane_state_release(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

176

kref_put(&plane_state->refcount, dc_plane_state_free);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

275

void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

281

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

284

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

296

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

40

void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

42

plane_state->ctx = ctx;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

44

plane_state->gamma_correction.is_identity = true;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

46

plane_state->in_transfer_func.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

48

plane_state->in_shaper_func.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

50

plane_state->lut3d_func.state.raw = 0;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

52

plane_state->blend_tf.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

54

plane_state->pre_multiplied_alpha = true;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

58

void dc_plane_destruct(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

68

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

73

for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

76

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

88

struct dc_plane_state *plane_state = kvzalloc_obj(*plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

91

if (NULL == plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

94

kref_init(&plane_state->refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

95

dc_plane_construct(dc->ctx, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

97

return plane_state;

drivers/gpu/drm/amd/display/dc/dc.h

1945

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1016

if (pipe_ctx->plane_state != NULL) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1017

if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1959

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1970

plane_state = srf_updates[plane_index].surface;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1971

address = &plane_state->address;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1987

cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1991

cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

822

reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/dc_plane.h

40

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_plane.h

42

void dc_plane_state_retain(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane.h

43

void dc_plane_state_release(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane.h

45

void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

31

void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

32

void dc_plane_destruct(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

33

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

102

populate_splrect_from_rect(&spl_in->basic_in.clip_rect, &plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

108

spl_in->basic_in.rotation = (enum spl_rotation_angle)plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

110

populate_splrect_from_rect(&spl_in->basic_in.src_rect, &plane_state->src_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

112

populate_splrect_from_rect(&spl_in->basic_in.dst_rect, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

114

spl_in->basic_in.horizontal_mirror = plane_state->horizontal_mirror;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

142

populate_spltaps_from_taps(&spl_in->scaling_quality, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

162

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_min = plane_state->sharpness_range.sdr_rgb_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

163

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_max = plane_state->sharpness_range.sdr_rgb_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

164

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_mid = plane_state->sharpness_range.sdr_rgb_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

165

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_min = plane_state->sharpness_range.sdr_yuv_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

166

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_max = plane_state->sharpness_range.sdr_yuv_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

167

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_mid = plane_state->sharpness_range.sdr_yuv_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

168

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_min = plane_state->sharpness_range.hdr_rgb_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

169

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_max = plane_state->sharpness_range.hdr_rgb_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

170

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_mid = plane_state->sharpness_range.hdr_rgb_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

177

} else if (!plane_state->adaptive_sharpness_en) {

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

182

spl_in->adaptive_sharpness.sharpness_level = plane_state->sharpness_level;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

189

spl_in->lls_pref = plane_state->linear_light_scaling;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

194

spl_in->basic_in.cositing = plane_state->cositing;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

196

spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

197

spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

202

spl_in->sharpen_policy = (enum sharpen_policy)plane_state->adaptive_sharpness_policy;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

211

spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

78

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

84

switch (plane_state->ctx->dce_version) {

drivers/gpu/drm/amd/display/dc/dc_state.h

53

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_state.h

59

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_trace.h

29

if (pipe_ctx->plane_state) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

30

trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1004

pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1008

pipe->plane_state->format);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1010

pipe->plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1025

v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1206

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1234

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1237

pipe->plane_state->update_flags.bits.full_update = 1;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1248

if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1267

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1272

hsplit_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

308

if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

309

pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

312

} else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

314

} else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

323

input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

334

dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

337

input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

339

input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

348

input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

350

switch (pipe->plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

365

switch (pipe->plane_state->format) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

519

pipe->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

530

if (!primary_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

717

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

718

(pipe->plane_state->dst_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

719

pipe->plane_state->dst_rect.height <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

720

pipe->plane_state->src_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

721

pipe->plane_state->src_rect.height <= 16)) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

899

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

915

if (!pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

946

if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

947

if (pipe->plane_state->rotation % 2 == 0) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

976

if (pipe->plane_state->rotation % 2 == 0) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

993

v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1064

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1182

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1425

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1426

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1430

while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1431

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1537

if (res_ctx->pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1538

(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1547

if (!res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1588

struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1592

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1593

|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1658

while (split_pipe && split_pipe->plane_state == pln) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1663

while (split_pipe && split_pipe->plane_state == pln) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2499

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

205

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

541

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

350

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

351

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

352

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

395

if (pipe_cnt == 1 && pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

396

&& pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

397

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

398

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

400

} else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1000

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1055

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1192

if (dpp_pipes[j]->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1194

dpp_pipes[j]->plane_state, 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1247

update_slice_table_for_plane(table, pipe, pipe->plane_state, -1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1259

pipe->plane_state, split[dc_pipe_idx] - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1703

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1726

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1741

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1743

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1863

if (odm && pri_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1865

if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1875

if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1931

ASSERT(pri_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2001

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2011

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2021

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2045

if (!pipe->plane_state && !odm)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2056

old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2059

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2081

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2100

old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2121

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2228

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2229

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2232

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3460

pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

348

if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3539

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

628

if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

635

!pipe->plane_state->address.tmz_surface &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

744

if (phantom && pipe->stream && pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

486

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

487

(pipe->plane_state->src_rect.height <

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

488

pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

489

pipe->plane_state->src_rect.width <

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

490

pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

533

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

534

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

535

&& pipe->plane_state->src_rect.width <= 1920 &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

536

pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

538

} else if (!is_dual_plane(pipe->plane_state->format) &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

539

pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

587

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

519

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

520

(pipe->plane_state->src_rect.height <

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

521

pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

522

pipe->plane_state->src_rect.width <

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

523

pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

566

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

567

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

568

&& pipe->plane_state->src_rect.width <= 1920 &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

569

pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

571

} else if (!is_dual_plane(pipe->plane_state->format) &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

572

pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

617

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

434

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

436

surface->plane0.pitch = plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

437

surface->plane1.pitch = plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

438

surface->plane0.height = plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

439

surface->plane0.width = plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

440

surface->plane1.height = plane_state->plane_size.chroma_size.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

441

surface->plane1.width = plane_state->plane_size.chroma_size.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

442

surface->dcc.enable = plane_state->dcc.enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

445

surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

446

surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_blks_c;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

447

surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

448

surface->dcc.plane1.pitch = plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

451

switch (plane_state->tiling_info.gfxversion) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

458

surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

461

surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

479

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

481

temp_pipe->plane_state = pipe->plane_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

497

struct dml2_plane_parameters *plane, const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

500

const struct scaler_data *scaler_data = get_scaler_data_for_plane(dml_ctx, plane_state, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

507

switch (plane_state->format) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

556

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

568

if (plane_state->ctx->dc->debug.always_scale == true) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

601

if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

604

switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

614

switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

630

plane->composition.scaler_info.rect_out_width = plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

631

plane->composition.rotation_angle = (enum dml2_rotation_angle) plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

636

plane->immediate_flip = plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

639

plane_state->dst_rect.height >= stream->src.height &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

170

if (dc_pipe->stream && dc_pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

172

dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

444

context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

481

context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

79

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

345

dc_main_pipes[0]->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

358

dc_phantom_pipes[0]->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

385

dc_main_pipes[0]->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

402

dc_phantom_pipes[0]->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1160

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

130

if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

151

if (!pipe->plane_state || !pipe->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

154

get_plane_id(ctx, state, pipe->plane_state, pipe->stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

158

&& (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

167

if (mpc_pipe->plane_state != pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

229

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

237

if (!pipe->plane_state && !pipe->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

707

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

121

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

129

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

139

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

157

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

256

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

375

if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

454

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

54

if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

540

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

56

bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

617

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

745

if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

751

curr_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

756

memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

757

memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

759

memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

760

memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

761

memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

762

memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

764

memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

766

memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

768

phantom_plane->format = curr_pipe->plane_state->format;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

769

phantom_plane->rotation = curr_pipe->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

770

phantom_plane->visible = curr_pipe->plane_state->visible;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

800

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

803

pipe->plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

850

if (pipe->plane_state && pipe->stream && ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

860

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

861

pipe->plane_state->is_phantom = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

87

if (pipe->plane_state->dcc.enable)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

894

if (!pipe_ctx->plane_state || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1210

if (!pipe || !pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

992

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

994

temp_pipe->plane_state = pipe->plane_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

305

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

347

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

349

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

522

if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

130

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

182

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

290

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

155

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

169

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

50

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2245

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2249

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2550

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

256

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2597

if (pipe_ctx->bottom_pipe->plane_state->visible) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2598

if (pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

260

switch (plane_state->format) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2603

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2606

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2635

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2637

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2642

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2643

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2645

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2650

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2652

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2655

plane_state->status.is_flip_pending =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2659

if (plane_state->status.is_flip_pending && !plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2662

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2665

plane_state->status.is_right_eye =\

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

285

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2914

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

295

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2957

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2958

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2959

&plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2960

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2964

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2969

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

297

dce110_prescale_params(&prescale_params, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2970

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2971

plane_state->rotation);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2974

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2975

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2976

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2977

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2979

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2989

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2990

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2991

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2992

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2993

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2994

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2995

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2996

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2997

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2998

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2999

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

300

if (!plane_state->gamma_correction.is_identity &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3000

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3001

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3002

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3003

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

301

dce_use_lut(plane_state->format))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

302

ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3124

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

.mirror = pipe_ctx->plane_state->horizontal_mirror

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3141

pos_cpy.x += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3142

pos_cpy.y += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3145

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3149

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

101

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

105

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

148

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

188

if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

274

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

318

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

319

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

320

&plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

321

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

330

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

331

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

332

plane_state->rotation);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

350

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

351

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

352

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

353

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

354

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

355

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

356

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

357

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

358

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

359

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

360

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

361

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

362

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

363

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

364

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1551

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1982

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1984

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1985

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1990

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1991

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1992

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1996

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1997

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1998

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1999

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2000

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2001

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2011

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2013

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2020

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2021

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2023

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2025

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2026

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2029

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2033

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2042

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2045

&& !plane_state->gamma_correction.is_identity

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2046

&& dce_use_lut(plane_state->format))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2047

dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

240

(!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2762

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2763

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2782

} else if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2787

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2796

if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2802

if (top->plane_state && top->plane_state->layer_index == 0 && !top->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2858

static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2864

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2866

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2867

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2871

build_prescale_params(&bns_params, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2891

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2906

&& pipe_ctx->plane_state->pre_multiplied_alpha);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2907

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2909

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2918

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2919

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2934

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2968

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2985

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2986

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2994

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3049

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3066

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3067

plane_state->update_flags.bits.bpp_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3068

dcn10_update_dpp(dpp, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3070

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3071

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3072

plane_state->update_flags.bits.global_alpha_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3075

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3076

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3077

plane_state->update_flags.bits.global_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3078

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3079

plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3083

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3084

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3085

plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3103

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3114

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3115

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3116

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3117

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3118

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3119

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3120

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3121

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3122

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3125

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3126

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3128

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3129

&plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3130

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3188

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3231

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3239

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3240

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3241

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3249

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3269

!pipe_ctx->stream || !pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3602

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3607

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3613

plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3616

plane_state->status.current_address = plane_state->status.requested_address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3618

if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3620

plane_state->status.is_right_eye =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3657

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3658

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3665

int x_plane = pipe_ctx->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3666

int y_plane = pipe_ctx->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3669

bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3673

? param.viewport.x : pipe_ctx->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3674

int clip_width = pipe_ctx->plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3677

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3678

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3701

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3702

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3703

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3704

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3706

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3707

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3708

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3709

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3710

clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3711

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3712

clip_width = clip_width * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3713

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3729

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3730

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3751

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4135

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4149

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

218

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

79

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1055

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1061

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1062

blend_lut = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1063

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1064

cm_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1065

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1075

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1081

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1082

shaper_lut = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1083

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1084

cm_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1085

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1091

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1093

&plane_state->lut3d_func.lut_3d);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1102

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1110

if (dpp_base == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1113

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1114

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1116

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1366

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1367

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1390

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1391

flip_immediate = pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1396

if (temp_pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1397

flip_immediate = temp_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1409

if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1431

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1432

flip_immediate = pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1436

if (temp_pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1437

flip_immediate = temp_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1441

if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1452

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1453

hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1459

} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1493

if (old_pipe->plane_state && !old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1494

new_pipe->plane_state && new_is_phantom) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1505

if (!old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1508

if (!old_pipe->plane_state && new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1541

if (old_pipe->plane_state && old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1542

new_pipe->plane_state && !new_is_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1545

if (old_pipe->plane_state && !new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1551

if (old_pipe->plane_state != new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1672

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1725

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1726

plane_state->update_flags.bits.input_csc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1727

plane_state->update_flags.bits.color_space_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1728

plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1729

struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1733

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1735

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1736

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1741

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1742

plane_state->cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1752

|| plane_state->update_flags.bits.global_alpha_change

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1753

|| plane_state->update_flags.bits.per_pixel_alpha_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1759

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1760

plane_state->update_flags.bits.position_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1761

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1763

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1771

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1772

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1804

|| plane_state->update_flags.bits.gamut_remap_change

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1820

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1821

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1822

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1823

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1824

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1825

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1826

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1827

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1828

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1833

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1834

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1836

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1837

&plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1838

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1845

plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1851

params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1928

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1929

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1960

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1961

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1966

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1970

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1971

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1972

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1974

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2006

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2051

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2052

ASSERT(!pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2055

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2061

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2063

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2120

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2152

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2178

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2301

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2490

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2692

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2694

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2695

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2700

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2701

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2702

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2707

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2708

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2709

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2710

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2711

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2712

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2721

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2723

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2729

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2733

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2734

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2736

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2738

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2739

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2742

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2925

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2935

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2936

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2938

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2947

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2948

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2958

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2973

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3068

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

731

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

34

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

36

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

46

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

140

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

144

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

147

uma = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

155

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

157

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

159

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

160

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

163

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

429

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

455

if (pipe_ctx->plane_state->global_alpha_value)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

456

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

488

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

543

if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

62

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

66

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

71

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

72

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

73

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

77

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

78

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

79

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

80

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

81

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

82

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1225

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

235

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

241

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

242

blend_lut = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

243

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

244

result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

245

&plane_state->blend_tf, &dpp_base->regamma_params, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

318

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

326

if (dpp_base == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

331

if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

332

tf = plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

336

if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

337

params = &plane_state->in_transfer_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

338

else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

339

cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

340

&plane_state->in_transfer_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

348

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

351

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

368

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

369

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

373

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

608

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

611

if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

60

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

64

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

635

if (!pipe_ctx_old->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1441

struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1448

if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1450

phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1451

phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1452

phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1453

phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1454

phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1456

phantom_pipe->plane_state->update_flags.bits.position_change = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

241

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

395

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

401

if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

403

top_pipe_to_program->plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

414

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

484

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

493

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

494

lut_params = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

495

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

496

result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

497

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

508

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

509

lut_params = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

510

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

512

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

513

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

521

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

522

result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

531

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

541

if (mpc == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

546

if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

547

tf = plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

551

if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

552

params = &plane_state->in_transfer_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

553

else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

554

cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

555

&plane_state->in_transfer_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

564

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

684

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

714

pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

715

!pipe->plane_state->address.tmz_surface ? 2 : 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

51

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

55

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1038

if ((!cur_pipe->plane_state && new_pipe->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1064

} else if (cur_pipe->plane_state == new_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

847

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

848

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

889

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

100

ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1000

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

107

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

108

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1093

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1094

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1111

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1112

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

112

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1154

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1155

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1265

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1364

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1365

pipe_ctx->plane_state->dcc.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1366

pipe_ctx->plane_state->flip_immediate &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1367

pipe_ctx->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1830

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1919

if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1921

&& mpc_pipe->plane_state->mcm_shaper_3dlut_setting

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2147

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2148

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2178

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2179

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2183

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2184

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2187

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2188

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2189

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2190

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2192

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2274

!pipe_ctx->plane_state || !pipe_ctx->plane_state->visible,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2325

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2326

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2333

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2334

pipe_ctx->plane_state->update_flags.bits.hdr_mult)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2339

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2340

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2341

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2342

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2345

hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2374

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2420

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2421

if (pipe->plane_state->triplebuffer_flips)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2426

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2432

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2434

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2491

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2523

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2549

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2597

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2638

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2718

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2779

if (old_pipe->plane_state && !old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2780

new_pipe->plane_state && new_is_phantom) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2791

if (!old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2794

if (!old_pipe->plane_state && new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2827

if (old_pipe->plane_state && old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2828

new_pipe->plane_state && !new_is_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2831

if (old_pipe->plane_state && !new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2837

if (old_pipe->plane_state != new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3225

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3228

if (pipe_ctx->plane_state == wb_info->writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3472

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3578

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3579

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3593

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3598

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3638

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3639

plane_state->update_flags.bits.input_csc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3640

plane_state->update_flags.bits.color_space_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3641

plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3646

hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3647

&plane_state->cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3658

plane_state->update_flags.bits.global_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3659

plane_state->update_flags.bits.per_pixel_alpha_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3668

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3669

plane_state->update_flags.bits.position_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3670

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3672

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3679

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3680

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3712

plane_state->update_flags.bits.gamut_remap_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3727

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3728

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3729

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3730

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3731

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3732

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3733

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3734

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3735

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3739

plane_state->format, &plane_state->tiling_info, size,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3740

plane_state->rotation, &plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3741

plane_state->horizontal_mirror, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3748

plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3753

&pipe_ctx->plane_state->address, pipe_ctx->subvp_index);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3781

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3784

per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3791

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3792

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3794

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3803

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3804

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3814

if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3821

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

390

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3915

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

392

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

393

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3943

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

395

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3972

pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3973

!pipe->plane_state->address.tmz_surface) ? 2 : 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

620

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

630

if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

631

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

636

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

638

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

639

lut_params = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

640

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

641

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

642

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

650

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

651

lut_params = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

652

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

654

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

655

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

663

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

664

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

99

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

40

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1038

void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1617

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

87

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

188

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

190

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

192

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

93

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

157

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

171

struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

449

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/inc/resource.h

158

struct dc_plane_state *const *plane_state,

drivers/gpu/drm/amd/display/dc/inc/resource.h

316

struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/resource.h

326

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

569

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

962

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

965

if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

42

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1043

static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1046

if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1047

((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

939

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

941

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1177

static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1179

if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1181

&& plane_state->src_rect.width > caps->max_video_width)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1245

static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1247

enum surface_pixel_format surf_pix_format = plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1257

plane_state->tiling_info.gfx9.swizzle = swizzle;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1547

if (prev_odm_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1596

ASSERT(primary_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1810

odm_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1823

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1832

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1838

hsplit_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1846

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1879

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1880

(pipe->plane_state->dst_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1881

pipe->plane_state->dst_rect.height <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1882

pipe->plane_state->src_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1883

pipe->plane_state->src_rect.height <= 16))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1888

(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1978

else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1986

pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2020

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2088

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2099

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2102

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2106

if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2111

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2136

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2233

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2235

enum surface_pixel_format surf_pix_format = plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2238

plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2240

plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

167

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1379

static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1381

if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1382

plane_state->dcc.enable = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1384

plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1387

return dcn20_patch_unknown_plane_state(plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

858

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

859

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

862

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

881

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

892

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

895

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

899

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

924

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1609

ASSERT(pri_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1743

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1746

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1770

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1779

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1789

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1812

if (!pipe->plane_state && !odm)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1823

old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1826

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1848

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1867

old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1888

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1693

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1694

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1695

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1735

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1736

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1737

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1739

} else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1684

(res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1685

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1686

res_ctx->pipe_ctx[i].plane_state->src_rect.height

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1687

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1690

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1742

split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1791

|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1821

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1822

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1823

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1827

} else if (!is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1828

&& pipe->plane_state->src_rect.width <= 5120

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1705

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1706

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1707

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1711

} else if (!is_dual_plane(pipe->plane_state->format)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1684

if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1687

phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1692

memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1693

memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1695

memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1696

memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1697

memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1698

memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1700

memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1702

memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1703

phantom_plane->format = curr_pipe->plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1704

phantom_plane->rotation = curr_pipe->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1705

phantom_plane->visible = curr_pipe->plane_state->visible;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1769

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1772

pipe->plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

127

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

135

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

145

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

164

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

206

if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

222

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

223

if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

224

pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

262

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

277

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

348

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

351

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

360

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

404

if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

405

if (!is_dual_plane(pipe->plane_state->format)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

408

if (pipe->plane_state->src_rect.width >= 5120 &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

409

pipe->plane_state->src_rect.height >= 2880)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

597

pipe->plane_state->src_rect.width == width &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

598

pipe->plane_state->src_rect.height == height &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

599

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

600

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1790

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1792

plane_state->tiling_info.gfxversion = DcGfxVersion9;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1793

dcn20_patch_unknown_plane_state(plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

38

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1667

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1669

plane_state->tiling_info.gfxversion = DcGfxAddr3;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1670

plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

23

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/armada/armada_overlay.c

266

struct drm_plane_state *plane_state;

drivers/gpu/drm/armada/armada_overlay.c

278

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/armada/armada_overlay.c

279

if (IS_ERR(plane_state)) {

drivers/gpu/drm/armada/armada_overlay.c

280

ret = PTR_ERR(plane_state);

drivers/gpu/drm/armada/armada_overlay.c

284

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/armada/armada_overlay.c

288

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/armada/armada_overlay.c

289

plane_state->crtc_x = crtc_x;

drivers/gpu/drm/armada/armada_overlay.c

290

plane_state->crtc_y = crtc_y;

drivers/gpu/drm/armada/armada_overlay.c

291

plane_state->crtc_h = crtc_h;

drivers/gpu/drm/armada/armada_overlay.c

292

plane_state->crtc_w = crtc_w;

drivers/gpu/drm/armada/armada_overlay.c

293

plane_state->src_x = src_x;

drivers/gpu/drm/armada/armada_overlay.c

294

plane_state->src_y = src_y;

drivers/gpu/drm/armada/armada_overlay.c

295

plane_state->src_h = src_h;

drivers/gpu/drm/armada/armada_overlay.c

296

plane_state->src_w = src_w;

drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c

144

struct drm_plane_state *plane_state)

drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c

164

struct drm_plane_state *plane_state)

drivers/gpu/drm/ast/ast_cursor.c

194

struct drm_plane_state *plane_state = &shadow_plane_state->base;

drivers/gpu/drm/ast/ast_cursor.c

195

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_cursor.c

251

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/ast/ast_cursor.c

252

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/ast/ast_cursor.c

253

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_cursor.c

269

if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) {

drivers/gpu/drm/ast/ast_cursor.c

284

writel(plane_state->crtc_x, sig + AST_HWC_SIGNATURE_X);

drivers/gpu/drm/ast/ast_cursor.c

285

writel(plane_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);

drivers/gpu/drm/ast/ast_cursor.c

290

if (plane_state->crtc_x < 0) {

drivers/gpu/drm/ast/ast_cursor.c

291

x_offset = (-plane_state->crtc_x) + offset_x;

drivers/gpu/drm/ast/ast_cursor.c

295

x = plane_state->crtc_x;

drivers/gpu/drm/ast/ast_cursor.c

297

if (plane_state->crtc_y < 0) {

drivers/gpu/drm/ast/ast_cursor.c

298

y_offset = (-plane_state->crtc_y) + offset_y;

drivers/gpu/drm/ast/ast_cursor.c

302

y = plane_state->crtc_y;

drivers/gpu/drm/ast/ast_mode.c

548

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/ast/ast_mode.c

549

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/ast/ast_mode.c

550

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_mode.c

554

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/ast/ast_mode.c

568

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

613

struct atmel_hlcdc_plane_state *plane_state;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

622

plane_state =

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

625

pixels = (plane_state->src_w * plane_state->src_h) -

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

626

(plane_state->disc_w * plane_state->disc_h);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

628

for (i = 0; i < plane_state->nplanes; i++)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

629

load += pixels * plane_state->bpp[i];

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

632

plane_state->ahb_id = 0;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

634

plane_state->ahb_id = 1;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

636

ahb_load[plane_state->ahb_id] += load;

drivers/gpu/drm/drm_atomic.c

1580

struct drm_plane_state *plane_state =

drivers/gpu/drm/drm_atomic.c

1583

if (IS_ERR(plane_state))

drivers/gpu/drm/drm_atomic.c

1584

return PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic.c

1810

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_atomic.c

1814

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic.c

1818

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic.c

1819

plane_state->crtc_x = 0;

drivers/gpu/drm/drm_atomic.c

1820

plane_state->crtc_y = 0;

drivers/gpu/drm/drm_atomic.c

1821

plane_state->crtc_w = 0;

drivers/gpu/drm/drm_atomic.c

1822

plane_state->crtc_h = 0;

drivers/gpu/drm/drm_atomic.c

1823

plane_state->src_x = 0;

drivers/gpu/drm/drm_atomic.c

1824

plane_state->src_y = 0;

drivers/gpu/drm/drm_atomic.c

1825

plane_state->src_w = 0;

drivers/gpu/drm/drm_atomic.c

1826

plane_state->src_h = 0;

drivers/gpu/drm/drm_atomic.c

2000

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic.c

2016

for_each_new_plane_in_state(state, plane, plane_state, i)

drivers/gpu/drm/drm_atomic.c

2017

drm_atomic_plane_print_state(p, plane_state);

drivers/gpu/drm/drm_atomic.c

550

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic.c

560

plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/drm_atomic.c

561

if (plane_state)

drivers/gpu/drm/drm_atomic.c

562

return plane_state;

drivers/gpu/drm/drm_atomic.c

568

plane_state = plane->funcs->atomic_duplicate_state(plane);

drivers/gpu/drm/drm_atomic.c

569

if (!plane_state)

drivers/gpu/drm/drm_atomic.c

572

state->planes[index].state_to_destroy = plane_state;

drivers/gpu/drm/drm_atomic.c

575

state->planes[index].new_state = plane_state;

drivers/gpu/drm/drm_atomic.c

576

plane_state->state = state;

drivers/gpu/drm/drm_atomic.c

579

plane->base.id, plane->name, plane_state, state);

drivers/gpu/drm/drm_atomic.c

581

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic.c

585

plane_state->crtc);

drivers/gpu/drm/drm_atomic.c

590

return plane_state;

drivers/gpu/drm/drm_atomic_helper.c

2196

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

2200

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/drm_atomic_helper.c

2201

struct drm_framebuffer *new_fb = plane_state->fb;

drivers/gpu/drm/drm_atomic_helper.c

2213

WARN_ON_ONCE(plane->state->crtc_x != plane_state->crtc_x);

drivers/gpu/drm/drm_atomic_helper.c

2214

WARN_ON_ONCE(plane->state->crtc_y != plane_state->crtc_y);

drivers/gpu/drm/drm_atomic_helper.c

2215

WARN_ON_ONCE(plane->state->src_x != plane_state->src_x);

drivers/gpu/drm/drm_atomic_helper.c

2216

WARN_ON_ONCE(plane->state->src_y != plane_state->src_y);

drivers/gpu/drm/drm_atomic_helper.c

2222

WARN_ON_ONCE(plane_state->fb != old_fb);

drivers/gpu/drm/drm_atomic_helper.c

3408

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3416

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3417

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3418

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3422

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3425

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/drm_atomic_helper.c

3426

plane_state->crtc_x = crtc_x;

drivers/gpu/drm/drm_atomic_helper.c

3427

plane_state->crtc_y = crtc_y;

drivers/gpu/drm/drm_atomic_helper.c

3428

plane_state->crtc_w = crtc_w;

drivers/gpu/drm/drm_atomic_helper.c

3429

plane_state->crtc_h = crtc_h;

drivers/gpu/drm/drm_atomic_helper.c

3430

plane_state->src_x = src_x;

drivers/gpu/drm/drm_atomic_helper.c

3431

plane_state->src_y = src_y;

drivers/gpu/drm/drm_atomic_helper.c

3432

plane_state->src_w = src_w;

drivers/gpu/drm/drm_atomic_helper.c

3433

plane_state->src_h = src_h;

drivers/gpu/drm/drm_atomic_helper.c

3459

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3467

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3468

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3469

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3473

if (plane_state->crtc && plane_state->crtc->cursor == plane)

drivers/gpu/drm/drm_atomic_helper.c

3474

plane_state->state->legacy_cursor_update = true;

drivers/gpu/drm/drm_atomic_helper.c

3476

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3560

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3600

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/drm_atomic_helper.c

3601

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic_helper.c

3605

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic_helper.c

3747

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3749

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3750

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3751

err = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3925

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3936

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3937

if (IS_ERR(plane_state))

drivers/gpu/drm/drm_atomic_helper.c

3938

return PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3940

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3943

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/drm_atomic_helper.c

82

struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_helper.c

893

int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_helper.c

900

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_atomic_helper.c

901

struct drm_rect *src = &plane_state->src;

drivers/gpu/drm/drm_atomic_helper.c

902

struct drm_rect *dst = &plane_state->dst;

drivers/gpu/drm/drm_atomic_helper.c

903

unsigned int rotation = plane_state->rotation;

drivers/gpu/drm/drm_atomic_helper.c

907

WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

909

*src = drm_plane_state_src(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

910

*dst = drm_plane_state_dest(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

913

plane_state->visible = false;

drivers/gpu/drm/drm_atomic_helper.c

918

if (WARN_ON(!plane_state->crtc)) {

drivers/gpu/drm/drm_atomic_helper.c

919

plane_state->visible = false;

drivers/gpu/drm/drm_atomic_helper.c

924

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

935

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

937

drm_rect_debug_print("src: ", &plane_state->src, true);

drivers/gpu/drm/drm_atomic_helper.c

938

drm_rect_debug_print("dst: ", &plane_state->dst, false);

drivers/gpu/drm/drm_atomic_helper.c

945

plane_state->visible = drm_rect_clip_scaled(src, dst, &clip);

drivers/gpu/drm/drm_atomic_helper.c

949

if (!plane_state->visible)

drivers/gpu/drm/drm_atomic_helper.c

960

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

97

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic_helper.c

98

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_atomic_state_helper.c

246

void __drm_atomic_helper_plane_state_reset(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_state_helper.c

251

plane_state->plane = plane;

drivers/gpu/drm/drm_atomic_state_helper.c

252

plane_state->rotation = DRM_MODE_ROTATE_0;

drivers/gpu/drm/drm_atomic_state_helper.c

254

plane_state->alpha = DRM_BLEND_ALPHA_OPAQUE;

drivers/gpu/drm/drm_atomic_state_helper.c

255

plane_state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;

drivers/gpu/drm/drm_atomic_state_helper.c

261

plane_state->color_encoding = val;

drivers/gpu/drm/drm_atomic_state_helper.c

268

plane_state->color_range = val;

drivers/gpu/drm/drm_atomic_state_helper.c

273

plane_state->color_pipeline = NULL;

drivers/gpu/drm/drm_atomic_state_helper.c

280

plane_state->zpos = val;

drivers/gpu/drm/drm_atomic_state_helper.c

281

plane_state->normalized_zpos = val;

drivers/gpu/drm/drm_atomic_state_helper.c

289

plane_state->hotspot_x = val;

drivers/gpu/drm/drm_atomic_state_helper.c

296

plane_state->hotspot_y = val;

drivers/gpu/drm/drm_atomic_state_helper.c

314

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_atomic_state_helper.c

316

if (plane_state)

drivers/gpu/drm/drm_atomic_state_helper.c

317

__drm_atomic_helper_plane_state_reset(plane_state, plane);

drivers/gpu/drm/drm_atomic_state_helper.c

319

plane->state = plane_state;

drivers/gpu/drm/drm_atomic_uapi.c

1230

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_uapi.c

1234

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_uapi.c

1235

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_uapi.c

1236

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

1242

ret = drm_atomic_plane_get_property(plane, plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

1268

plane_state, file_priv,

drivers/gpu/drm/drm_atomic_uapi.c

190

drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

193

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

196

if (plane_state->crtc == crtc)

drivers/gpu/drm/drm_atomic_uapi.c

198

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic_uapi.c

199

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

200

plane_state->crtc);

drivers/gpu/drm/drm_atomic_uapi.c

207

plane_state->crtc = crtc;

drivers/gpu/drm/drm_atomic_uapi.c

210

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

220

plane->base.id, plane->name, plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

225

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

242

drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

245

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

251

plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

255

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

257

drm_framebuffer_assign(&plane_state->fb, fb);

drivers/gpu/drm/drm_atomic_uapi.c

270

drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

273

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

279

plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

283

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

285

plane_state->color_pipeline = colorop;

drivers/gpu/drm/drm_blend.c

471

struct drm_plane_state *plane_state =

drivers/gpu/drm/drm_blend.c

473

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_blend.c

474

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_blend.c

477

states[n++] = plane_state;

drivers/gpu/drm/drm_blend.c

479

plane->base.id, plane->name, plane_state->zpos);

drivers/gpu/drm/drm_client_modeset.c

1054

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_client_modeset.c

1056

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_client_modeset.c

1057

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_client_modeset.c

1058

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_client_modeset.c

1062

plane_state->rotation = DRM_MODE_ROTATE_0;

drivers/gpu/drm/drm_client_modeset.c

1068

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

drivers/gpu/drm/drm_client_modeset.c

1078

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_client_modeset.c

1081

plane_state = drm_atomic_get_new_plane_state(state, primary);

drivers/gpu/drm/drm_client_modeset.c

1082

plane_state->rotation = rotation;

drivers/gpu/drm/drm_crtc_internal.h

249

struct drm_plane_state *plane_state);

drivers/gpu/drm/drm_damage_helper.c

162

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_damage_helper.c

173

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_damage_helper.c

174

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_damage_helper.c

175

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_damage_helper.c

179

drm_property_replace_blob(&plane_state->fb_damage_clips,

drivers/gpu/drm/drm_damage_helper.c

70

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_damage_helper.c

74

if (plane_state->crtc) {

drivers/gpu/drm/drm_damage_helper.c

76

plane_state->crtc);

drivers/gpu/drm/drm_damage_helper.c

82

drm_property_blob_put(plane_state->fb_damage_clips);

drivers/gpu/drm/drm_damage_helper.c

83

plane_state->fb_damage_clips = NULL;

drivers/gpu/drm/drm_framebuffer.c

1028

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_framebuffer.c

1037

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_framebuffer.c

1038

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_framebuffer.c

1039

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_framebuffer.c

1043

if (disable_crtcs && plane_state->crtc->primary == plane) {

drivers/gpu/drm/drm_framebuffer.c

1048

plane_state->crtc->base.id,

drivers/gpu/drm/drm_framebuffer.c

1049

plane_state->crtc->name, fb->base.id);

drivers/gpu/drm/drm_framebuffer.c

1051

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_framebuffer.c

1053

ret = drm_atomic_add_affected_connectors(state, plane_state->crtc);

drivers/gpu/drm/drm_framebuffer.c

1063

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_framebuffer.c

1064

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_gem_atomic_helper.c

222

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/drm_gem_atomic_helper.c

224

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

253

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/drm_gem_atomic_helper.c

256

if (!plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

292

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

295

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

360

int drm_gem_begin_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

362

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

363

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_gem_atomic_helper.c

382

void drm_gem_end_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

384

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

385

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_gem_atomic_helper.c

408

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

410

return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

426

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

428

drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

474

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

476

drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

386

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_mipi_dbi.c

388

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

389

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_mipi_dbi.c

474

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_mipi_dbi.c

476

return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

490

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_mipi_dbi.c

492

drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

538

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_mipi_dbi.c

540

drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);

drivers/gpu/drm/drm_plane_helper.c

107

struct drm_plane_state plane_state = {

drivers/gpu/drm/drm_plane_helper.c

128

ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,

drivers/gpu/drm/drm_plane_helper.c

135

*src = plane_state.src;

drivers/gpu/drm/drm_plane_helper.c

136

*dst = plane_state.dst;

drivers/gpu/drm/drm_plane_helper.c

137

*visible = plane_state.visible;

drivers/gpu/drm/drm_simple_kms_helper.c

219

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/drm_simple_kms_helper.c

229

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/drm_simple_kms_helper.c

236

if (!plane_state->visible)

drivers/gpu/drm/drm_simple_kms_helper.c

242

return pipe->funcs->check(pipe, plane_state, crtc_state);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

109

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

116

plane_state->fb->pitches[0]);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

141

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

143

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

144

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

151

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

158

if (!plane_state->visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

1252

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_plane.c

1256

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

1263

if (plane_config->base == plane_state->surf)

drivers/gpu/drm/i915/display/i9xx_plane.c

1267

intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

1269

intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

157

static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

159

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

160

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

161

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/i9xx_plane.c

228

int i9xx_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

230

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

231

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

232

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

237

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

241

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

244

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

245

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

246

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

256

intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

260

plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

279

while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) {

drivers/gpu/drm/i915/display/i9xx_plane.c

287

offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0,

drivers/gpu/drm/i915/display/i9xx_plane.c

296

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/i9xx_plane.c

301

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/i9xx_plane.c

302

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

303

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

320

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/i9xx_plane.c

321

plane_state->view.color_plane[0].x = src_x;

drivers/gpu/drm/i915/display/i9xx_plane.c

322

plane_state->view.color_plane[0].y = src_y;

drivers/gpu/drm/i915/display/i9xx_plane.c

329

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

331

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

334

ret = chv_plane_check_rotation(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

338

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

345

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

349

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

352

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

356

plane_state->ctl = i9xx_plane_ctl(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

361

static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

363

int x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/i9xx_plane.c

364

int y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/i9xx_plane.c

366

return intel_fb_xy_to_linear(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

369

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

371

return plane_state->view.color_plane[0].offset;

drivers/gpu/drm/i915/display/i9xx_plane.c

393

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

396

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

416

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

430

i9xx_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/i9xx_plane.c

442

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

448

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/i9xx_plane.c

451

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/i9xx_plane.c

452

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/i9xx_plane.c

453

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

454

int crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

471

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

475

int x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/i9xx_plane.c

476

int y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/i9xx_plane.c

479

dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

487

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/i9xx_plane.c

488

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/i9xx_plane.c

489

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

490

int crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

505

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/i9xx_plane.c

518

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

520

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

526

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

534

i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

535

i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

604

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

608

u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

615

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

622

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

628

intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.h

27

int i9xx_check_plane_surface(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.h

28

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.h

44

static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1000

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_wm.c

1060

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1064

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1067

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1072

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1083

wm = g4x_compute_wm(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1096

wm = ilk_compute_fbc_wm(crtc_state, plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1512

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1515

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1516

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1524

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1527

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

1530

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_wm.c

1683

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1686

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1691

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1698

int wm = vlv_compute_wm_level(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

2447

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2456

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2459

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2468

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2479

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2488

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2491

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2496

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2506

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2514

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2517

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2521

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2527

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2532

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2535

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2537

return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2929

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2938

intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2940

pristate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2942

sprstate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2944

curstate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3559

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3561

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

3562

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

3563

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3871

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3876

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_wm.c

4023

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

4028

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_wm.c

969

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

972

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

973

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

982

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

985

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/intel_color.c

2183

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_color.c

2188

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_color.c

2189

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/intel_color.c

2190

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3853

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

3855

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3856

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

3859

const struct drm_property_blob *blob = plane_state->hw.ctm;

drivers/gpu/drm/i915/display/intel_color.c

3948

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

3950

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3951

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

3954

const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;

drivers/gpu/drm/i915/display/intel_color.c

4001

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4003

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4004

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

4007

const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;

drivers/gpu/drm/i915/display/intel_color.c

4056

xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4058

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4059

xelpd_program_plane_pre_csc_lut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4061

if (plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4062

xelpd_program_plane_post_csc_lut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4241

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4243

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4244

struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

4247

glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_color.c

4252

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4254

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4257

display->funcs.color->load_plane_csc_matrix(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4262

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4264

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4267

display->funcs.color->load_plane_luts(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4281

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4283

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4284

struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

4287

glk_load_lut_3d(dsb, crtc, plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_color.c

4291

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4293

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_color.c

4294

intel_color_load_plane_csc_matrix(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4295

if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4296

intel_color_load_plane_luts(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4297

if (plane_state->hw.lut_3d)

drivers/gpu/drm/i915/display/intel_color.c

4298

intel_color_load_3dlut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

95

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.c

99

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.h

46

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.h

48

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

115

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

117

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

118

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

123

str_yes_no(plane_state->uapi.visible));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

130

fb->modifier, str_yes_no(plane_state->uapi.visible));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

132

plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

133

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

135

DRM_RECT_FP_ARG(&plane_state->uapi.src),

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

136

DRM_RECT_ARG(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

182

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

392

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

394

intel_dump_plane_state(&p, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

100

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

101

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

103

intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);

drivers/gpu/drm/i915/display/intel_cursor.c

105

plane_state, 0);

drivers/gpu/drm/i915/display/intel_cursor.c

118

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_cursor.c

123

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

124

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

125

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

130

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/intel_cursor.c

131

plane_state->view.color_plane[0].x = src_x;

drivers/gpu/drm/i915/display/intel_cursor.c

132

plane_state->view.color_plane[0].y = src_y;

drivers/gpu/drm/i915/display/intel_cursor.c

138

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

140

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

141

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

142

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

143

const struct drm_rect src = plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_cursor.c

144

const struct drm_rect dst = plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_cursor.c

153

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

161

plane_state->uapi.src = src;

drivers/gpu/drm/i915/display/intel_cursor.c

162

plane_state->uapi.dst = dst;

drivers/gpu/drm/i915/display/intel_cursor.c

165

drm_rect_translate(&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_cursor.c

169

ret = intel_cursor_check_surface(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

173

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_cursor.c

176

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

208

static u32 i845_cursor_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

212

CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_cursor.c

215

static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

217

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

223

return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);

drivers/gpu/drm/i915/display/intel_cursor.c

227

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

229

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

230

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

231

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

234

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

243

if (!i845_cursor_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_cursor.c

247

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_cursor.c

248

drm_rect_height(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

252

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

253

plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);

drivers/gpu/drm/i915/display/intel_cursor.c

268

plane_state->ctl = i845_cursor_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

277

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

282

if (plane_state && plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_cursor.c

283

unsigned int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

284

unsigned int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

286

cntl = plane_state->ctl |

drivers/gpu/drm/i915/display/intel_cursor.c

291

base = plane_state->surf;

drivers/gpu/drm/i915/display/intel_cursor.c

292

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

36

static u32 intel_cursor_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

38

return plane_state->view.color_plane[0].offset;

drivers/gpu/drm/i915/display/intel_cursor.c

400

static u32 i9xx_cursor_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

402

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

408

switch (drm_rect_width(&plane_state->uapi.dst)) {

drivers/gpu/drm/i915/display/intel_cursor.c

419

MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

42

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_cursor.c

423

if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)

drivers/gpu/drm/i915/display/intel_cursor.c

433

static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

435

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

436

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

437

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

439

if (!intel_cursor_size_ok(plane_state))

drivers/gpu/drm/i915/display/intel_cursor.c

45

int x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_cursor.c

459

plane_state->hw.rotation & DRM_MODE_ROTATE_0) {

drivers/gpu/drm/i915/display/intel_cursor.c

46

int y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_cursor.c

471

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

473

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

474

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

475

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

479

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

488

if (!i9xx_cursor_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_cursor.c

492

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_cursor.c

493

drm_rect_height(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

497

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

498

plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);

drivers/gpu/drm/i915/display/intel_cursor.c

501

drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {

drivers/gpu/drm/i915/display/intel_cursor.c

505

fb->pitches[0], drm_rect_width(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

520

plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {

drivers/gpu/drm/i915/display/intel_cursor.c

527

plane_state->ctl = i9xx_cursor_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

548

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

55

y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,

drivers/gpu/drm/i915/display/intel_cursor.c

551

u32 ctl = plane_state->ctl;

drivers/gpu/drm/i915/display/intel_cursor.c

567

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

575

if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {

drivers/gpu/drm/i915/display/intel_cursor.c

577

u32 val = intel_cursor_position(crtc_state, plane_state,

drivers/gpu/drm/i915/display/intel_cursor.c

583

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);

drivers/gpu/drm/i915/display/intel_cursor.c

587

wa_16021440873(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

652

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

658

if (plane_state && plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_cursor.c

659

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

660

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

662

cntl = plane_state->ctl |

drivers/gpu/drm/i915/display/intel_cursor.c

668

base = plane_state->surf;

drivers/gpu/drm/i915/display/intel_cursor.c

669

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

695

if (plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

696

i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

73

static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

76

&plane_state->uapi.plane->dev->mode_config;

drivers/gpu/drm/i915/display/intel_cursor.c

77

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

78

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

791

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_cursor.c

792

container_of(work, typeof(*plane_state), unpin_work);

drivers/gpu/drm/i915/display/intel_cursor.c

793

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

795

intel_plane_unpin_fb(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

796

intel_plane_destroy_state(&plane->base, &plane_state->uapi);

drivers/gpu/drm/i915/display/intel_cursor.c

84

static int intel_cursor_check_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

86

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

87

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

88

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_cursor.c

93

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

97

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_display.c

1085

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

1089

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

1102

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

1106

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

5518

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

5522

plane_state, i)

drivers/gpu/drm/i915/display/intel_display.c

5523

assert_plane(plane, plane_state->is_y_plane ||

drivers/gpu/drm/i915/display/intel_display.c

5524

plane_state->uapi.visible);

drivers/gpu/drm/i915/display/intel_display.c

585

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display.c

588

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_display.c

590

plane_state->uapi.visible = visible;

drivers/gpu/drm/i915/display/intel_display.c

624

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display.c

6240

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

6253

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

6254

crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_display.c

632

intel_plane_set_invisible(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_display.c

633

intel_set_plane_visible(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_display.c

669

intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_display.c

673

intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,

drivers/gpu/drm/i915/display/intel_display.c

674

plane_state->view.color_plane[0].offset, 0);

drivers/gpu/drm/i915/display/intel_display.c

7229

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

7232

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

7233

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_display.c

7261

&plane_state->ccval,

drivers/gpu/drm/i915/display/intel_display.c

7262

sizeof(plane_state->ccval));

drivers/gpu/drm/i915/display/intel_display.h

358

plane, plane_state, \

drivers/gpu/drm/i915/display/intel_display.h

362

for_each_if ((plane_state = \

drivers/gpu/drm/i915/display/intel_display.h

497

unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display.h

505

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

331

static const char *plane_visibility(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

333

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

336

if (plane_state->is_y_plane)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

344

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

346

const struct drm_framebuffer *fb = plane_state->uapi.fb;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

350

src = drm_plane_state_src(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

351

dst = drm_plane_state_dest(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

354

plane_state->uapi.rotation);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

364

", rotation=%s\n", plane_visibility(plane_state),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

367

if (plane_state->planar_linked_plane)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

369

plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

370

plane_state->is_y_plane ? "Y plane" : "UV plane");

drivers/gpu/drm/i915/display/intel_display_debugfs.c

375

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

377

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

384

plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

390

str_yes_no(plane_state->uapi.visible),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

391

DRM_RECT_FP_ARG(&plane_state->uapi.src),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

392

DRM_RECT_ARG(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_display_trace.h

411

TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

412

TP_ARGS(plane_state, crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

415

__string(dev, __dev_name_drm(plane_state->uapi.plane))

drivers/gpu/drm/i915/display/intel_display_trace.h

422

__string(name, plane_state->uapi.plane->name)

drivers/gpu/drm/i915/display/intel_display_trace.h

431

__entry->format = plane_state->hw.fb->format->format;

drivers/gpu/drm/i915/display/intel_display_trace.h

432

memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src));

drivers/gpu/drm/i915/display/intel_display_trace.h

433

memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst));

drivers/gpu/drm/i915/display/intel_display_trace.h

444

TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

445

TP_ARGS(plane_state, crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

448

__string(dev, __dev_name_drm(plane_state->uapi.plane))

drivers/gpu/drm/i915/display/intel_display_trace.h

455

__string(name, plane_state->uapi.plane->name)

drivers/gpu/drm/i915/display/intel_display_trace.h

464

__entry->format = plane_state->hw.fb->format->format;

drivers/gpu/drm/i915/display/intel_display_trace.h

465

memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src));

drivers/gpu/drm/i915/display/intel_display_trace.h

466

memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst));

drivers/gpu/drm/i915/display/intel_display_types.h

1616

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1621

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1631

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1632

u32 (*surf_offset)(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1634

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1638

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1654

#define to_intel_plane_state(plane_state) \

drivers/gpu/drm/i915/display/intel_display_types.h

1655

container_of_const((plane_state), struct intel_plane_state, uapi)

drivers/gpu/drm/i915/display/intel_fb.c

1053

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1057

return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane,

drivers/gpu/drm/i915/display/intel_fb.c

1058

plane_state->hw.rotation,

drivers/gpu/drm/i915/display/intel_fb.c

1059

plane_state->view.color_plane[color_plane].mapping_stride,

drivers/gpu/drm/i915/display/intel_fb.c

1133

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1136

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1137

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1138

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1139

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1140

unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

1239

static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1241

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1242

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1243

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1287

bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1289

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1290

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1293

(plane->fbc && !plane_state->no_fbc_reason &&

drivers/gpu/drm/i915/display/intel_fb.c

1294

plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);

drivers/gpu/drm/i915/display/intel_fb.c

1307

static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1309

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1310

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb.c

1311

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1318

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_fb.c

1321

if (!intel_plane_can_remap(plane_state))

drivers/gpu/drm/i915/display/intel_fb.c

1833

static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1835

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1836

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1838

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1844

intel_fb_view_init(display, &plane_state->view,

drivers/gpu/drm/i915/display/intel_fb.c

1848

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1849

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1850

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1851

src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1856

drm_rect_translate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

1861

drm_rect_rotate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

1891

&plane_state->view);

drivers/gpu/drm/i915/display/intel_fb.c

1949

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1952

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1954

unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

1965

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1969

*x += plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/intel_fb.c

1970

*y += plane_state->view.color_plane[color_plane].y;

drivers/gpu/drm/i915/display/intel_fb.c

2039

static int intel_plane_check_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

2041

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2042

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

2043

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

2044

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

2053

if (intel_plane_can_remap(plane_state) &&

drivers/gpu/drm/i915/display/intel_fb.c

2054

!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_fb.c

2058

stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

2073

int intel_plane_compute_gtt(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

2076

to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb.c

2077

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

2082

if (intel_plane_needs_remap(plane_state)) {

drivers/gpu/drm/i915/display/intel_fb.c

2083

intel_plane_remap_gtt(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2091

return intel_plane_check_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2094

intel_fb_fill_view(fb, rotation, &plane_state->view);

drivers/gpu/drm/i915/display/intel_fb.c

2098

drm_rect_rotate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

2102

return intel_plane_check_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

100

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

74

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

78

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

82

bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

94

int intel_plane_compute_gtt(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

97

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb_pin.c

236

intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb_pin.c

238

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb_pin.c

244

intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb_pin.c

246

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb_pin.c

247

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb_pin.c

256

intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb_pin.c

258

return intel_fb_view_vtd_guard(plane_state->hw.fb,

drivers/gpu/drm/i915/display/intel_fb_pin.c

259

&plane_state->view,

drivers/gpu/drm/i915/display/intel_fb_pin.c

260

plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_fb_pin.c

263

int intel_plane_pin_fb(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb_pin.c

266

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb_pin.c

267

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb_pin.c

269

to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb_pin.c

273

vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt,

drivers/gpu/drm/i915/display/intel_fb_pin.c

274

intel_plane_fb_min_alignment(plane_state),

drivers/gpu/drm/i915/display/intel_fb_pin.c

275

intel_plane_fb_min_phys_alignment(plane_state),

drivers/gpu/drm/i915/display/intel_fb_pin.c

276

intel_plane_fb_vtd_guard(plane_state),

drivers/gpu/drm/i915/display/intel_fb_pin.c

277

intel_plane_uses_fence(plane_state),

drivers/gpu/drm/i915/display/intel_fb_pin.c

278

&plane_state->flags);

drivers/gpu/drm/i915/display/intel_fb_pin.c

282

plane_state->ggtt_vma = vma;

drivers/gpu/drm/i915/display/intel_fb_pin.c

285

unsigned int alignment = intel_plane_fb_min_alignment(plane_state);

drivers/gpu/drm/i915/display/intel_fb_pin.c

291

plane_state->ggtt_vma = vma;

drivers/gpu/drm/i915/display/intel_fb_pin.c

293

vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt,

drivers/gpu/drm/i915/display/intel_fb_pin.c

294

alignment, &plane_state->flags,

drivers/gpu/drm/i915/display/intel_fb_pin.c

298

plane_state->ggtt_vma = NULL;

drivers/gpu/drm/i915/display/intel_fb_pin.c

302

plane_state->dpt_vma = vma;

drivers/gpu/drm/i915/display/intel_fb_pin.c

304

WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);

drivers/gpu/drm/i915/display/intel_fb_pin.c

310

drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma));

drivers/gpu/drm/i915/display/intel_fb_pin.c

322

plane_state->surf = i915_gem_object_get_dma_address(obj, 0) +

drivers/gpu/drm/i915/display/intel_fb_pin.c

323

plane->surf_offset(plane_state);

drivers/gpu/drm/i915/display/intel_fb_pin.c

325

plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) +

drivers/gpu/drm/i915/display/intel_fb_pin.c

326

plane->surf_offset(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1071

static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1073

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1074

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1080

static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1082

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1083

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1089

static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1094

static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1096

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1097

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1107

static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1112

static bool stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1114

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1117

return icl_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1119

return skl_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1121

return g4x_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1123

return i965_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1125

return i8xx_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1128

static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1130

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1131

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1148

static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1150

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1151

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1167

static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1169

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1184

xe3p_lpd_fbc_fp16_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1186

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1197

static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1199

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1201

if (lnl_fbc_pixel_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1204

if (xe3p_lpd_fbc_fp16_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1218

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1220

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1223

xe3p_lpd_fbc_fp16_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1229

static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1231

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1234

return xe3p_lpd_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1236

return lnl_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1238

return g4x_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1240

return i8xx_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1243

static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1245

return plane_state->hw.rotation == DRM_MODE_ROTATE_0;

drivers/gpu/drm/i915/display/intel_fbc.c

1248

static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1253

static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1255

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1256

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fbc.c

1265

static bool rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1267

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1270

return skl_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1272

return g4x_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1274

return i8xx_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1304

static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1306

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1311

effective_w = plane_state->view.color_plane[0].x +

drivers/gpu/drm/i915/display/intel_fbc.c

1312

(drm_rect_width(&plane_state->uapi.src) >> 16);

drivers/gpu/drm/i915/display/intel_fbc.c

1313

effective_h = plane_state->view.color_plane[0].y +

drivers/gpu/drm/i915/display/intel_fbc.c

1314

(drm_rect_height(&plane_state->uapi.src) >> 16);

drivers/gpu/drm/i915/display/intel_fbc.c

1337

static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1339

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1344

w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1345

h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1350

static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1352

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1357

static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1362

static bool tiling_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1364

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1367

return skl_fbc_tiling_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1369

return i8xx_fbc_tiling_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1426

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1435

drm_rect_fp_to_int(&src, &plane_state->uapi.src);

drivers/gpu/drm/i915/display/intel_fbc.c

144

static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1447

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

1452

WARN_ON(plane_state->no_fbc_reason);

drivers/gpu/drm/i915/display/intel_fbc.c

146

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1460

fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1462

drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE &&

drivers/gpu/drm/i915/display/intel_fbc.c

1465

if (plane_state->flags & PLANE_HAS_FENCE)

drivers/gpu/drm/i915/display/intel_fbc.c

1466

fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma);

drivers/gpu/drm/i915/display/intel_fbc.c

1470

fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1471

fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1472

fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1475

static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1477

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

149

stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_fbc.c

1492

(plane_state->flags & PLANE_HAS_FENCE &&

drivers/gpu/drm/i915/display/intel_fbc.c

1493

i915_vma_fence_id(plane_state->ggtt_vma) != -1);

drivers/gpu/drm/i915/display/intel_fbc.c

1496

static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1498

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1499

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fbc.c

150

if (!drm_rotation_90_or_270(plane_state->hw.rotation))

drivers/gpu/drm/i915/display/intel_fbc.c

1502

return intel_fbc_min_limit(plane_state) <= fbc->limit &&

drivers/gpu/drm/i915/display/intel_fbc.c

1503

intel_fbc_cfb_size(plane_state) <= fbc->limit *

drivers/gpu/drm/i915/display/intel_fbc.c

1507

static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1509

return !plane_state->no_fbc_reason &&

drivers/gpu/drm/i915/display/intel_fbc.c

1510

intel_fbc_is_fence_ok(plane_state) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1511

intel_fbc_is_cfb_ok(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1515

__intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fbc.c

1518

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fbc.c

1521

int width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1522

const struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/intel_fbc.c

1523

int y_offset = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_fbc.c

1528

!intel_fbc_is_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1547

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1554

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

156

static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1563

__intel_fbc_prepare_dirty_rect(plane_state,

drivers/gpu/drm/i915/display/intel_fbc.c

158

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1586

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

1588

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1589

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_fbc.c

1597

plane_state->no_fbc_reason = "stolen memory not initialised";

drivers/gpu/drm/i915/display/intel_fbc.c

1602

plane_state->no_fbc_reason = "VGPU active";

drivers/gpu/drm/i915/display/intel_fbc.c

1607

plane_state->no_fbc_reason = "disabled per module param or by default";

drivers/gpu/drm/i915/display/intel_fbc.c

1611

if (!plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_fbc.c

1612

plane_state->no_fbc_reason = "plane not visible";

drivers/gpu/drm/i915/display/intel_fbc.c

1617

plane_state->no_fbc_reason = "Wa_16023588340";

drivers/gpu/drm/i915/display/intel_fbc.c

1627

plane_state->no_fbc_reason = "Wa_15018326506";

drivers/gpu/drm/i915/display/intel_fbc.c

1634

plane_state->no_fbc_reason = "VT-d enabled";

drivers/gpu/drm/i915/display/intel_fbc.c

1641

plane_state->no_fbc_reason = "interlaced mode not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1646

plane_state->no_fbc_reason = "double wide pipe not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

165

static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1663

plane_state->no_fbc_reason = "Selective update enabled";

drivers/gpu/drm/i915/display/intel_fbc.c

167

unsigned int cpp = intel_fbc_cfb_cpp(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1671

plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";

drivers/gpu/drm/i915/display/intel_fbc.c

1675

if (!pixel_format_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1676

plane_state->no_fbc_reason = "pixel format not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1680

if (!tiling_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1681

plane_state->no_fbc_reason = "tiling not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1685

if (!rotation_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1686

plane_state->no_fbc_reason = "rotation not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

169

return intel_fbc_plane_stride(plane_state) * cpp;

drivers/gpu/drm/i915/display/intel_fbc.c

1690

if (!stride_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1691

plane_state->no_fbc_reason = "stride not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1696

plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&

drivers/gpu/drm/i915/display/intel_fbc.c

1698

plane_state->no_fbc_reason = "per-pixel alpha not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1702

if (!intel_fbc_plane_size_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1703

plane_state->no_fbc_reason = "plane size too big";

drivers/gpu/drm/i915/display/intel_fbc.c

1707

if (!intel_fbc_surface_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1708

plane_state->no_fbc_reason = "surface size too big";

drivers/gpu/drm/i915/display/intel_fbc.c

1718

plane_state->view.color_plane[0].y & 3) {

drivers/gpu/drm/i915/display/intel_fbc.c

1719

plane_state->no_fbc_reason = "plane start Y offset misaligned";

drivers/gpu/drm/i915/display/intel_fbc.c

1725

(plane_state->view.color_plane[0].y +

drivers/gpu/drm/i915/display/intel_fbc.c

1726

(drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {

drivers/gpu/drm/i915/display/intel_fbc.c

1727

plane_state->no_fbc_reason = "plane end Y offset misaligned";

drivers/gpu/drm/i915/display/intel_fbc.c

1732

plane_state->no_fbc_reason = "pixel rate too high";

drivers/gpu/drm/i915/display/intel_fbc.c

1736

plane_state->no_fbc_reason = NULL;

drivers/gpu/drm/i915/display/intel_fbc.c

1848

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1853

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

1909

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1913

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2008

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

2012

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2028

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

2038

if (intel_fbc_is_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

2048

fbc->no_fbc_reason = plane_state->no_fbc_reason;

drivers/gpu/drm/i915/display/intel_fbc.c

2052

if (!intel_fbc_is_fence_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

2062

if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),

drivers/gpu/drm/i915/display/intel_fbc.c

2063

intel_fbc_min_limit(plane_state))) {

drivers/gpu/drm/i915/display/intel_fbc.c

2075

intel_fbc_hw_intialize_dirty_rect(fbc, plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2112

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

2116

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2125

plane_state->no_fbc_reason) {

drivers/gpu/drm/i915/display/intel_fbc.c

216

static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

218

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

219

unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

220

unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

221

unsigned int cpp = intel_fbc_cfb_cpp(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2407

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

2416

plane_state->no_fbc_reason ?: "FBC possible");

drivers/gpu/drm/i915/display/intel_fbc.c

247

static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

249

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

250

unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

252

return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));

drivers/gpu/drm/i915/display/intel_fbc.c

255

static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

257

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

258

unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

259

unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

260

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

840

static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

842

return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;

drivers/gpu/drm/i915/display/intel_fbc.h

59

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fbdev.c

387

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

389

struct drm_gem_object *obj = intel_fb_bo(plane_state->uapi.fb);

drivers/gpu/drm/i915/display/intel_fbdev.c

409

fb = to_intel_framebuffer(plane_state->uapi.fb);

drivers/gpu/drm/i915/display/intel_fbdev.c

496

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

502

drm_WARN(display->drm, !plane_state->uapi.fb,

drivers/gpu/drm/i915/display/intel_initial_plane.c

104

plane_state->uapi.rotation = plane_config->rotation;

drivers/gpu/drm/i915/display/intel_initial_plane.c

106

plane_state->uapi.rotation, &plane_state->view);

drivers/gpu/drm/i915/display/intel_initial_plane.c

112

plane_state->uapi.src_x = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

113

plane_state->uapi.src_y = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

114

plane_state->uapi.src_w = fb->width << 16;

drivers/gpu/drm/i915/display/intel_initial_plane.c

115

plane_state->uapi.src_h = fb->height << 16;

drivers/gpu/drm/i915/display/intel_initial_plane.c

117

plane_state->uapi.crtc_x = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

118

plane_state->uapi.crtc_y = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

119

plane_state->uapi.crtc_w = fb->width;

drivers/gpu/drm/i915/display/intel_initial_plane.c

120

plane_state->uapi.crtc_h = fb->height;

drivers/gpu/drm/i915/display/intel_initial_plane.c

122

plane_state->uapi.fb = fb;

drivers/gpu/drm/i915/display/intel_initial_plane.c

125

plane_state->uapi.crtc = &crtc->base;

drivers/gpu/drm/i915/display/intel_initial_plane.c

126

intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);

drivers/gpu/drm/i915/display/intel_initial_plane.c

31

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_initial_plane.c

39

if (!plane_state->ggtt_vma)

drivers/gpu/drm/i915/display/intel_initial_plane.c

43

return plane_state;

drivers/gpu/drm/i915/display/intel_initial_plane.c

77

struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);

drivers/gpu/drm/i915/display/intel_load_detect.c

27

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_load_detect.c

34

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_load_detect.c

35

if (plane_state->crtc != crtc)

drivers/gpu/drm/i915/display/intel_load_detect.c

38

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/i915/display/intel_load_detect.c

42

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

479

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

482

if (plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

55

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

58

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

664

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

675

intel_set_plane_visible(crtc_state, plane_state, visible);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

840

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

847

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

854

if (plane_state->uapi.visible && plane->min_cdclk) {

drivers/gpu/drm/i915/display/intel_plane.c

1013

int intel_plane_check_clipping(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

1018

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1019

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1020

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

1021

struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_plane.c

1022

struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_plane.c

1024

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_plane.c

1028

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/intel_plane.c

1049

plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);

drivers/gpu/drm/i915/display/intel_plane.c

1053

if (!can_position && plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_plane.c

1068

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1070

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1071

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1072

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

1073

struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_plane.c

1075

bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_plane.c

1346

const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);

drivers/gpu/drm/i915/display/intel_plane.c

1347

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

1349

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1404

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1412

plane_state = to_intel_plane_state(plane->state);

drivers/gpu/drm/i915/display/intel_plane.c

1413

fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1516

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1518

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1519

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1521

if (!plane_state->planar_linked_plane)

drivers/gpu/drm/i915/display/intel_plane.c

1524

plane_state->planar_linked_plane = NULL;

drivers/gpu/drm/i915/display/intel_plane.c

1526

if (!plane_state->is_y_plane)

drivers/gpu/drm/i915/display/intel_plane.c

1529

drm_WARN_ON(display->drm, plane_state->uapi.visible);

drivers/gpu/drm/i915/display/intel_plane.c

1531

plane_state->is_y_plane = false;

drivers/gpu/drm/i915/display/intel_plane.c

1546

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1557

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

1561

unlink_nv12_plane(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1567

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

1599

link_nv12_planes(crtc_state, plane_state, y_plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1613

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1618

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_plane.c

1619

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/intel_plane.c

162

struct intel_plane_state *plane_state = to_intel_plane_state(state);

drivers/gpu/drm/i915/display/intel_plane.c

1620

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

164

drm_WARN_ON(plane->dev, plane_state->ggtt_vma);

drivers/gpu/drm/i915/display/intel_plane.c

165

drm_WARN_ON(plane->dev, plane_state->dpt_vma);

drivers/gpu/drm/i915/display/intel_plane.c

1650

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1655

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

1656

struct intel_plane *linked = plane_state->planar_linked_plane;

drivers/gpu/drm/i915/display/intel_plane.c

167

__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

168

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

169

drm_framebuffer_put(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

170

kfree(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1725

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1734

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

1771

for_each_new_intel_plane_in_state(state, plane, plane_state, i)

drivers/gpu/drm/i915/display/intel_plane.c

226

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

240

return intel_adjusted_rate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_plane.c

241

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_plane.c

246

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

249

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

251

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_plane.c

254

return intel_plane_pixel_rate(crtc_state, plane_state) *

drivers/gpu/drm/i915/display/intel_plane.c

260

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

263

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

264

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

271

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_plane.c

279

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

280

height = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

294

return intel_adjusted_rate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_plane.c

295

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_plane.c

302

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_plane.c

304

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

307

if (!plane_state->uapi.visible || !plane->min_cdclk)

drivers/gpu/drm/i915/display/intel_plane.c

313

plane->min_cdclk(new_crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

316

static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

318

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

319

drm_framebuffer_put(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

321

memset(&plane_state->hw, 0, sizeof(plane_state->hw));

drivers/gpu/drm/i915/display/intel_plane.c

344

intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

349

return drm_property_replace_blob(&plane_state->hw.ctm, blob);

drivers/gpu/drm/i915/display/intel_plane.c

351

return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);

drivers/gpu/drm/i915/display/intel_plane.c

353

return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);

drivers/gpu/drm/i915/display/intel_plane.c

355

return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);

drivers/gpu/drm/i915/display/intel_plane.c

361

intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

367

struct drm_atomic_state *state = plane_state->uapi.state;

drivers/gpu/drm/i915/display/intel_plane.c

376

iter_colorop = plane_state->uapi.color_pipeline;

drivers/gpu/drm/i915/display/intel_plane.c

383

changed |= intel_plane_colorop_replace_blob(plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

395

void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

399

intel_plane_clear_hw_state(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

407

plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;

drivers/gpu/drm/i915/display/intel_plane.c

409

plane_state->hw.fb = from_plane_state->uapi.fb;

drivers/gpu/drm/i915/display/intel_plane.c

410

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

411

drm_framebuffer_get(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

413

plane_state->hw.alpha = from_plane_state->uapi.alpha;

drivers/gpu/drm/i915/display/intel_plane.c

414

plane_state->hw.pixel_blend_mode =

drivers/gpu/drm/i915/display/intel_plane.c

416

plane_state->hw.rotation = from_plane_state->uapi.rotation;

drivers/gpu/drm/i915/display/intel_plane.c

417

plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;

drivers/gpu/drm/i915/display/intel_plane.c

418

plane_state->hw.color_range = from_plane_state->uapi.color_range;

drivers/gpu/drm/i915/display/intel_plane.c

419

plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;

drivers/gpu/drm/i915/display/intel_plane.c

421

plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

422

plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

424

intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

427

void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

430

intel_plane_clear_hw_state(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

432

memcpy(&plane_state->hw, &from_plane_state->hw,

drivers/gpu/drm/i915/display/intel_plane.c

433

sizeof(plane_state->hw));

drivers/gpu/drm/i915/display/intel_plane.c

435

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

436

drm_framebuffer_get(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

440

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

443

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

445

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

447

unlink_nv12_plane(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

460

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/intel_plane.c

463

static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

465

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

466

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

467

int dst_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_plane.c

468

int dst_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_plane.c

65

static void intel_plane_state_reset(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

68

memset(plane_state, 0, sizeof(*plane_state));

drivers/gpu/drm/i915/display/intel_plane.c

70

__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);

drivers/gpu/drm/i915/display/intel_plane.c

72

plane_state->scaler_id = -1;

drivers/gpu/drm/i915/display/intel_plane.c

77

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

822

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

829

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

84

plane_state = kzalloc_obj(*plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

85

if (!plane_state) {

drivers/gpu/drm/i915/display/intel_plane.c

858

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

862

trace_intel_plane_update_noarm(plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

868

plane->update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

874

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

880

plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);

drivers/gpu/drm/i915/display/intel_plane.c

886

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

891

intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);

drivers/gpu/drm/i915/display/intel_plane.c

895

trace_intel_plane_update_arm(plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

896

plane->update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

90

intel_plane_state_reset(plane_state, plane);

drivers/gpu/drm/i915/display/intel_plane.c

92

plane->base.state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_plane.h

32

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

35

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

37

void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

40

void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

45

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

50

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

54

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

74

int intel_plane_check_clipping(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

78

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

80

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_psr.c

2775

static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_psr.c

2777

if (plane_state->uapi.dst.y1 < 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2778

plane_state->uapi.dst.x1 < 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2779

plane_state->scaler_id >= 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2780

plane_state->hw.rotation != DRM_MODE_ROTATE_0)

drivers/gpu/drm/i915/display/intel_sprite.c

1009

static u32 g4x_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1011

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1012

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1013

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

1014

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

1058

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

1061

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/intel_sprite.c

1078

static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1080

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1081

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1082

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1108

static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1110

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1111

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1112

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1138

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1142

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

1143

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

1144

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

1145

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

1146

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

1147

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

1156

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

1168

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1172

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

1173

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

1174

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

1177

dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1187

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

1197

intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

1200

g4x_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1202

ilk_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1272

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1274

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1275

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1276

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_sprite.c

1277

const struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_sprite.c

1281

unsigned int stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_sprite.c

1338

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1340

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1345

if (g4x_fb_scalable(plane_state->hw.fb)) {

drivers/gpu/drm/i915/display/intel_sprite.c

1355

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1360

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1364

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_sprite.c

1367

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1371

ret = g4x_sprite_check_scaling(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1376

plane_state->ctl = ivb_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1378

plane_state->ctl = g4x_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1383

int chv_plane_check_rotation(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1385

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1386

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

140

vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1402

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1406

ret = chv_plane_check_rotation(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1410

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1417

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

142

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1421

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_sprite.c

1424

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1428

plane_state->ctl = vlv_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

143

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

144

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

150

plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {

drivers/gpu/drm/i915/display/intel_sprite.c

180

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

184

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

238

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

252

vlv_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

267

static u32 vlv_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

269

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

270

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

271

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

324

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

342

static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

344

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

345

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

346

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

369

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

374

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

375

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

376

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

377

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

380

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

391

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

396

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

397

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

398

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

401

sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

404

chv_sprite_update_csc(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

418

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

430

vlv_sprite_update_clrc(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

431

vlv_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

483

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

487

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

520

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

523

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

547

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

561

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

567

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

581

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

582

dst_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

585

ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

587

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

597

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

601

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

630

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

635

hsw_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

653

static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

655

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

656

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

662

static u32 ivb_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

664

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

665

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

666

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

667

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

68

chv_sprite_update_csc(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

70

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

71

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

711

if (!ivb_need_sprite_gamma(plane_state))

drivers/gpu/drm/i915/display/intel_sprite.c

714

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

717

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/intel_sprite.c

72

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

734

static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

759

static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

761

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

762

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

767

if (!ivb_need_sprite_gamma(plane_state))

drivers/gpu/drm/i915/display/intel_sprite.c

770

ivb_sprite_linear_gamma(plane_state, gamma);

drivers/gpu/drm/i915/display/intel_sprite.c

792

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

796

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

797

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

798

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

799

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

800

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

801

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

810

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

823

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

827

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

828

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

829

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

832

sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

848

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

859

intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

861

ivb_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

914

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

916

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

930

hscale = drm_rect_calc_hscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_sprite.c

931

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_sprite.c

98

const s16 *csc = csc_matrix[plane_state->hw.color_encoding];

drivers/gpu/drm/i915/display/intel_sprite.h

19

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

20

int chv_plane_check_rotation(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

23

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

25

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

27

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

106

plane_state = drm_atomic_get_plane_state(state,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

108

ret = PTR_ERR_OR_ZERO(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

110

intel_plane_set_ckey(to_intel_plane_state(plane_state), set);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

16

static void intel_plane_set_ckey(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

19

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

20

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

21

struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

48

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

92

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

93

ret = PTR_ERR_OR_ZERO(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

95

intel_plane_set_ckey(to_intel_plane_state(plane_state), set);

drivers/gpu/drm/i915/display/intel_wm.c

120

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_wm.c

122

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_wm.c

137

return plane_state->hw.fb != NULL;

drivers/gpu/drm/i915/display/intel_wm.c

139

return plane_state->uapi.visible;

drivers/gpu/drm/i915/display/intel_wm.h

30

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

301

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_scaler.c

303

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

304

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_scaler.c

305

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

306

bool force_detach = !fb || !plane_state->uapi.visible;

drivers/gpu/drm/i915/display/skl_scaler.c

316

&plane_state->scaler_id,

drivers/gpu/drm/i915/display/skl_scaler.c

317

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/skl_scaler.c

318

drm_rect_height(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/skl_scaler.c

319

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/skl_scaler.c

320

drm_rect_height(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/skl_scaler.c

328

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_scaler.c

338

if (!plane_state && casf_scaler && i != 1)

drivers/gpu/drm/i915/display/skl_scaler.c

390

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_scaler.c

400

*scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler);

drivers/gpu/drm/i915/display/skl_scaler.c

407

if (plane_state && plane_state->hw.fb &&

drivers/gpu/drm/i915/display/skl_scaler.c

408

plane_state->hw.fb->format->is_yuv &&

drivers/gpu/drm/i915/display/skl_scaler.c

409

plane_state->hw.fb->format->num_planes > 1) {

drivers/gpu/drm/i915/display/skl_scaler.c

410

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_scaler.c

423

plane_state->planar_linked_plane;

drivers/gpu/drm/i915/display/skl_scaler.c

446

if (plane_state && plane_state->hw.fb) {

drivers/gpu/drm/i915/display/skl_scaler.c

447

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

448

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/skl_scaler.c

449

const struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/skl_scaler.c

551

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_scaler.c

557

plane_state = intel_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_scaler.c

564

if (!plane_state && DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_scaler.c

567

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_scaler.c

568

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_scaler.c

569

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

574

plane_state, &plane_state->scaler_id,

drivers/gpu/drm/i915/display/skl_scaler.c

865

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_scaler.c

868

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

870

int scaler_id = plane_state->scaler_id;

drivers/gpu/drm/i915/display/skl_scaler.c

873

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_scaler.c

874

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_scaler.c

875

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

876

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

882

hscale = drm_rect_calc_hscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_scaler.c

883

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

885

vscale = drm_rect_calc_vscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_scaler.c

886

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

908

skl_scaler_get_filter_select(plane_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/skl_scaler.c

914

plane_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/skl_scaler.h

22

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_scaler.h

32

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1020

static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1022

if (!plane_state->hw.fb->format->has_alpha)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1025

switch (plane_state->hw.pixel_blend_mode) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1033

MISSING_CASE(plane_state->hw.pixel_blend_mode);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1038

static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1040

if (!plane_state->hw.fb->format->has_alpha)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1043

switch (plane_state->hw.pixel_blend_mode) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1051

MISSING_CASE(plane_state->hw.pixel_blend_mode);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1145

static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1147

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1185

static u32 skl_plane_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1187

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1188

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1189

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1190

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1196

plane_ctl |= skl_plane_ctl_alpha(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1199

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1202

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1221

plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1243

static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1245

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1246

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1247

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1251

plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1254

switch (plane_state->hw.color_encoding) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1266

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1270

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1274

if (plane_state->force_black)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1277

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1280

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1283

if (plane_state->hw.gamma_lut) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1285

if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1292

static u32 skl_surf_address(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1295

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1296

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1297

u32 offset = plane_state->view.color_plane[color_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1308

static int icl_plane_color_plane(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1310

if (plane_state->planar_linked_plane && !plane_state->is_y_plane)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1316

static u32 skl_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1318

int color_plane = icl_plane_color_plane(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1321

plane_surf = skl_surf_address(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1323

if (plane_state->decrypt)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1329

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1332

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1333

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1340

aux_dist = skl_surf_address(plane_state, aux_plane) -

drivers/gpu/drm/i915/display/skl_universal_plane.c

1341

skl_surf_address(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1344

aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1349

static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1351

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1356

static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1358

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1359

u8 alpha = plane_state->hw.alpha >> 8;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1364

static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1366

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1367

u8 alpha = plane_state->hw.alpha >> 8;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1407

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1412

u32 stride = skl_plane_stride(plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1413

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1414

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1415

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1416

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1419

if (plane_state->scaler_id >= 0) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1438

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1443

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1444

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1447

plane_ctl = plane_state->ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1456

plane_color_ctl = plane_state->color_ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1460

skl_plane_keyval(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1462

skl_plane_keymsk(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1464

skl_plane_keymax(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1470

skl_plane_aux_dist(plane_state, 0));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1473

PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1474

PLANE_OFFSET_X(plane_state->view.color_plane[1].x));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1487

if (plane_state->scaler_id >= 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1488

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1498

plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1504

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1516

clip = &plane_state->psr2_sel_fetch_area;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1519

y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1521

y = (clip->y1 + plane_state->uapi.dst.y1);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1523

val |= plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1526

x = plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1533

y = plane_state->view.color_plane[color_plane].y + clip->y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1535

y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1543

val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1551

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1556

int color_plane = icl_plane_color_plane(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1557

u32 stride = skl_plane_stride(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1558

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1559

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1560

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1561

int x = plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1562

int y = plane_state->view.color_plane[color_plane].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1563

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1564

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1567

plane_color_ctl = plane_state->color_ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1570

intel_color_plane_program_pipeline(dsb, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1573

if (plane_state->scaler_id >= 0) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1586

skl_plane_keyval(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1588

skl_plane_keymsk(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1590

skl_plane_keymax(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1597

lower_32_bits(plane_state->ccval));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1599

upper_32_bits(plane_state->ccval));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1605

skl_plane_aux_dist(plane_state, color_plane));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1609

plane_state->cus_ctl);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1615

icl_program_input_csc(dsb, plane, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1623

if (plane_state->force_black)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1626

icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1632

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1640

if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1651

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1658

plane_ctl = plane_state->ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1668

if (plane_state->scaler_id >= 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1669

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1671

icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1673

intel_color_plane_commit_arm(dsb, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1683

pixel_normalizer_value(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1693

plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1711

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1717

u32 plane_ctl = plane_state->ctl;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1718

u32 plane_surf = plane_state->surf;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1748

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1750

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1751

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1752

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1753

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1835

plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

1847

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1849

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1850

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1851

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1852

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1878

static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1880

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1881

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1882

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1883

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1884

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1958

skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1962

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1963

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1964

int aux_x = plane_state->view.color_plane[ccs_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1965

int aux_y = plane_state->view.color_plane[ccs_plane].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1966

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1984

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1995

plane_state->view.color_plane[ccs_plane].offset = aux_offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1996

plane_state->view.color_plane[ccs_plane].x = aux_x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1997

plane_state->view.color_plane[ccs_plane].y = aux_y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2003

int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2006

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2007

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2008

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2010

u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2012

int w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2014

intel_add_fb_offsets(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2015

*offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2025

*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2038

while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2046

*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2055

static int skl_check_main_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2057

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2058

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2059

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2060

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2061

int x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2062

int y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2063

int w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2064

int h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2082

ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2092

while (!skl_check_main_ccs_coordinates(plane_state, x, y,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2097

offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2101

if (x != plane_state->view.color_plane[aux_plane].x ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2102

y != plane_state->view.color_plane[aux_plane].y) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2115

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2116

plane_state->view.color_plane[0].x = x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2117

plane_state->view.color_plane[0].y = y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2123

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2129

static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2131

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2132

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2133

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2134

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2142

int x = plane_state->uapi.src.x1 >> 17;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2143

int y = plane_state->uapi.src.y1 >> 17;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2144

int w = drm_rect_width(&plane_state->uapi.src) >> 17;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2145

int h = drm_rect_height(&plane_state->uapi.src) >> 17;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2157

intel_add_fb_offsets(&x, &y, plane_state, uv_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2159

plane_state, uv_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2162

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2167

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2172

while (!skl_check_main_ccs_coordinates(plane_state, x, y,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2178

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2183

if (x != plane_state->view.color_plane[ccs_plane].x ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2184

y != plane_state->view.color_plane[ccs_plane].y) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2197

plane_state->view.color_plane[uv_plane].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2198

plane_state->view.color_plane[uv_plane].x = x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2199

plane_state->view.color_plane[uv_plane].y = y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2204

static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2206

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2207

int src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2208

int src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2229

intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2232

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2235

plane_state->view.color_plane[ccs_plane].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2236

plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2237

plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2243

static int skl_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2245

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2248

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2252

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2260

ret = skl_check_ccs_aux_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2267

ret = skl_check_nv12_aux_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2272

ret = skl_check_main_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2301

static void check_protection(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2303

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2304

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2310

plane_state->decrypt = intel_bo_key_check(obj) == 0;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2311

plane_state->force_black = intel_bo_is_protected(obj) &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

2312

!plane_state->decrypt;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2316

make_damage_viewport_relative(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2318

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2319

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2320

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2321

struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2326

if (!fb || !plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2327

plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2340

static void clip_damage(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2342

struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2348

drm_rect_fp_to_int(&src, &plane_state->uapi.src);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2354

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2356

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2357

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2358

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2363

ret = skl_plane_check_fb(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2368

if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2373

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2378

make_damage_viewport_relative(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2380

ret = skl_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2384

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2387

ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2391

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2395

clip_damage(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2397

ret = skl_plane_check_nv12_rotation(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2401

check_protection(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2404

if (!(plane_state->hw.alpha >> 8)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2405

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2406

plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2409

plane_state->ctl = skl_plane_ctl(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2412

plane_state->color_ctl = glk_plane_color_ctl(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2417

plane_state->cus_ctl = PLANE_CUS_ENABLE |

drivers/gpu/drm/i915/display/skl_universal_plane.c

2421

plane_state->cus_ctl = 0;

drivers/gpu/drm/i915/display/skl_universal_plane.c

267

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

269

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

276

glk_plane_ratio(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

279

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

291

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

293

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

296

glk_plane_ratio(plane_state, &num, &den);

drivers/gpu/drm/i915/display/skl_universal_plane.c

303

skl_plane_ratio(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

306

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

318

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

320

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3222

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/skl_universal_plane.c

3227

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

323

skl_plane_ratio(plane_state, &num, &den);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3234

if (plane_config->base == plane_state->surf)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3237

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

678

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

722

const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];

drivers/gpu/drm/i915/display/skl_universal_plane.c

766

static u32 skl_plane_stride(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

769

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

770

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

771

u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;

drivers/gpu/drm/i915/display/skl_universal_plane.c

901

static u32 pixel_normalizer_value(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

903

if (!intel_fbc_need_pixel_normalizer(plane_state))

drivers/gpu/drm/i915/display/skl_universal_plane.h

32

int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.h

43

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1748

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1751

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

1759

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_watermark.c

1763

plane_state->hw.rotation,

drivers/gpu/drm/i915/display/skl_watermark.c

1764

intel_plane_pixel_rate(crtc_state, plane_state),

drivers/gpu/drm/i915/display/skl_watermark.c

1766

plane_state->uapi.src.x1);

drivers/gpu/drm/i915/display/skl_watermark.c

2040

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2048

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2069

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2079

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2090

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2092

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2095

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

2100

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2103

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2109

ret = skl_build_plane_wm_uv(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2119

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2121

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2122

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2128

if (plane_state->is_y_plane)

drivers/gpu/drm/i915/display/skl_watermark.c

2133

if (plane_state->planar_linked_plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2134

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

2137

!intel_wm_plane_visible(crtc_state, plane_state));

drivers/gpu/drm/i915/display/skl_watermark.c

2141

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2142

plane_state->planar_linked_plane, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

2146

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2150

} else if (intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2151

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2335

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2339

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/skl_watermark.c

2349

ret = icl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2351

ret = skl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2437

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2452

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2453

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2454

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2799

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2822

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2823

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2824

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3810

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3815

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/i915_initial_plane.c

262

struct intel_plane_state *plane_state = to_intel_plane_state(_plane_state);

drivers/gpu/drm/i915/i915_initial_plane.c

266

plane_state->ggtt_vma = i915_vma_get(vma);

drivers/gpu/drm/i915/i915_initial_plane.c

267

if (intel_plane_uses_fence(plane_state) &&

drivers/gpu/drm/i915/i915_initial_plane.c

269

plane_state->flags |= PLANE_HAS_FENCE;

drivers/gpu/drm/i915/i915_initial_plane.c

271

plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);

drivers/gpu/drm/imx/dc/dc-plane.c

100

if (!plane_state->fb)

drivers/gpu/drm/imx/dc/dc-plane.c

103

if (!plane_state->crtc) {

drivers/gpu/drm/imx/dc/dc-plane.c

109

drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/imx/dc/dc-plane.c

113

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/imx/dc/dc-plane.c

122

ret = dc_plane_check_max_source_resolution(plane_state);

drivers/gpu/drm/imx/dc/dc-plane.c

126

return dc_plane_check_fb(plane_state);

drivers/gpu/drm/imx/dc/dc-plane.c

94

struct drm_plane_state *plane_state =

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

810

struct drm_plane_state *plane_state;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

832

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

833

ipu_state = to_ipu_plane_state(plane_state);

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

836

if (!plane_state->fb) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

841

if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

842

plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

849

plane_state->fb->format->format,

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

850

plane_state->fb->modifier))

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

857

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

858

ipu_state = to_ipu_plane_state(plane_state);

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

861

if (!plane_state->fb) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

866

if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

867

plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

871

plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

875

plane_state->fb->format->format,

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

876

plane_state->fb->modifier)) {

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

193

struct drm_plane_state *plane_state)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

210

bpp = imx_lcdc_get_format(plane_state->fb->format->format);

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

277

struct drm_plane_state *plane_state,

drivers/gpu/drm/mcde/mcde_display.c

1154

struct drm_plane_state *plane_state)

drivers/gpu/drm/mediatek/mtk_crtc.c

306

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

308

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

310

plane_state->pending.config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

318

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

320

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

322

plane_state->pending.async_config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

419

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

423

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

426

plane_state->pending.enable = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

430

plane_state, NULL);

drivers/gpu/drm/mediatek/mtk_crtc.c

512

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

514

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

516

if (!plane_state->pending.config)

drivers/gpu/drm/mediatek/mtk_crtc.c

523

plane_state,

drivers/gpu/drm/mediatek/mtk_crtc.c

526

plane_state->pending.config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

536

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

538

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

540

if (!plane_state->pending.async_config)

drivers/gpu/drm/mediatek/mtk_crtc.c

547

plane_state,

drivers/gpu/drm/mediatek/mtk_crtc.c

550

plane_state->pending.async_config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

580

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

582

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

583

if (plane_state->pending.dirty) {

drivers/gpu/drm/mediatek/mtk_crtc.c

584

plane_state->pending.config = true;

drivers/gpu/drm/mediatek/mtk_crtc.c

585

plane_state->pending.dirty = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

587

} else if (plane_state->pending.async_dirty) {

drivers/gpu/drm/mediatek/mtk_crtc.c

588

plane_state->pending.async_config = true;

drivers/gpu/drm/mediatek/mtk_crtc.c

589

plane_state->pending.async_dirty = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

737

struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

753

memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));

drivers/gpu/drm/mediatek/mtk_crtc.c

820

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

822

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

823

plane_state->pending.enable = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

824

plane_state->pending.config = true;

drivers/gpu/drm/mediatek/mtk_crtc.h

26

struct drm_atomic_state *plane_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

516

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/mgag200/mgag200_mode.c

518

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

519

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/mgag200/mgag200_mode.c

524

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1351

struct drm_plane_state *plane_state =

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1354

if (IS_ERR(plane_state)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1355

ret = PTR_ERR(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1359

states[plane_state->normalized_zpos] = plane_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1153

struct drm_plane_state *plane_state =

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1157

struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1161

if (IS_ERR(plane_state))

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1162

return PTR_ERR(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1164

if (plane_state->crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1166

plane_state->crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1168

ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1172

if (!plane_state->visible) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1189

old_plane_state->src_w != plane_state->src_w ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1190

old_plane_state->src_h != plane_state->src_h ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1191

old_plane_state->crtc_w != plane_state->crtc_w ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1192

old_plane_state->crtc_h != plane_state->crtc_h ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1194

msm_framebuffer_format(plane_state->fb))

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1202

struct drm_plane_state *plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1207

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1226

msm_framebuffer_format(plane_state->fb),

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1242

struct drm_plane_state *plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1246

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1255

if (plane_state->crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1257

plane_state->crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1259

pstate = to_dpu_plane_state(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1267

if (!plane_state->fb)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1270

fmt = msm_framebuffer_format(plane_state->fb);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1272

reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1273

(plane_state->src_h >> 16 != plane_state->crtc_h);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1275

reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1285

prev_adjacent_plane_state[i] = plane_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1290

plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1310

struct drm_plane_state *plane_state = states[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1312

if (!plane_state ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1313

!plane_state->visible)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1317

state, plane_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

655

struct plane_state *pa = (struct plane_state *)a;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

656

struct plane_state *pb = (struct plane_state *)b;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

702

struct plane_state pstates[STAGE_MAX + 1];

drivers/gpu/drm/mxsfb/lcdif_kms.c

163

struct drm_plane_state *plane_state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

167

const u32 format = plane_state->fb->format->format;

drivers/gpu/drm/mxsfb/lcdif_kms.c

278

lcdif_yuv2rgb_coeffs[plane_state->color_encoding]

drivers/gpu/drm/mxsfb/lcdif_kms.c

279

[plane_state->color_range];

drivers/gpu/drm/mxsfb/lcdif_kms.c

403

struct drm_plane_state *plane_state)

drivers/gpu/drm/mxsfb/lcdif_kms.c

419

lcdif_set_formats(lcdif, plane_state, lcdif_crtc_state->bus_format);

drivers/gpu/drm/mxsfb/lcdif_kms.c

669

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

677

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

525

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

533

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/omapdrm/omap_crtc.c

670

struct drm_plane_state *plane_state;

drivers/gpu/drm/omapdrm/omap_crtc.c

678

plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);

drivers/gpu/drm/omapdrm/omap_crtc.c

679

if (IS_ERR(plane_state))

drivers/gpu/drm/omapdrm/omap_crtc.c

680

return PTR_ERR(plane_state);

drivers/gpu/drm/omapdrm/omap_crtc.c

683

plane_state->rotation = val;

drivers/gpu/drm/omapdrm/omap_crtc.c

685

plane_state->zpos = val;

drivers/gpu/drm/omapdrm/omap_drv.c

166

struct drm_plane_state *plane_state =

drivers/gpu/drm/omapdrm/omap_drv.c

169

if (IS_ERR(plane_state)) {

drivers/gpu/drm/omapdrm/omap_drv.c

170

ret = PTR_ERR(plane_state);

drivers/gpu/drm/omapdrm/omap_drv.c

173

states[n++] = plane_state;

drivers/gpu/drm/pl111/pl111_display.c

122

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

514

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

516

struct qxl_crtc *qcrtc = to_qxl_crtc(plane_state->crtc);

drivers/gpu/drm/qxl/qxl_display.c

540

cmd->u.set.position.x = plane_state->crtc_x + plane_state->hotspot_x;

drivers/gpu/drm/qxl/qxl_display.c

541

cmd->u.set.position.y = plane_state->crtc_y + plane_state->hotspot_y;

drivers/gpu/drm/qxl/qxl_display.c

559

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

561

struct qxl_crtc *qcrtc = to_qxl_crtc(plane_state->crtc);

drivers/gpu/drm/qxl/qxl_display.c

583

cmd->u.position.x = plane_state->crtc_x + plane_state->hotspot_x;

drivers/gpu/drm/qxl/qxl_display.c

584

cmd->u.position.y = plane_state->crtc_y + plane_state->hotspot_y;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1524

struct drm_plane_state *plane_state;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1541

plane_state =

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1543

if (IS_ERR(plane_state)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1546

return PTR_ERR(plane_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1549

if (drm_is_afbc(plane_state->fb->modifier))

drivers/gpu/drm/sitronix/st7571.c

346

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7571.c

347

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7571.c

348

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7571.c

365

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sitronix/st7586.c

174

struct drm_plane_state *plane_state)

drivers/gpu/drm/sitronix/st7586.c

177

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7586.c

178

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7735r.c

132

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/sitronix/st7735r.c

62

struct drm_plane_state *plane_state)

drivers/gpu/drm/sitronix/st7920.c

345

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

346

struct st7920_plane_state *st7920_state = to_st7920_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

348

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/sitronix/st7920.c

357

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sitronix/st7920.c

363

else if (!plane_state->visible)

drivers/gpu/drm/sitronix/st7920.c

372

if (plane_state->fb->format != fi) {

drivers/gpu/drm/sitronix/st7920.c

392

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

394

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

395

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sitronix/st7920.c

397

struct st7920_plane_state *st7920_plane_state = to_st7920_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

398

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7920.c

410

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sitronix/st7920.c

412

dst_clip = plane_state->dst;

drivers/gpu/drm/sitronix/st7920.c

436

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

441

if (!plane_state->crtc)

drivers/gpu/drm/sitronix/st7920.c

444

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1081

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1082

struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1084

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1093

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1099

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1108

if (plane_state->fb->format != fi) {

drivers/gpu/drm/solomon/ssd130x.c

1130

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1131

struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1133

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1142

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1148

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1157

if (plane_state->fb->format != fi) {

drivers/gpu/drm/solomon/ssd130x.c

1177

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1178

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1185

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1191

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1200

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1202

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1203

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1205

struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1206

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1219

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1221

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1241

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1243

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1244

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1246

struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1247

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1260

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1262

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1282

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1284

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1285

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1287

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1300

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1302

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1323

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1328

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1331

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1347

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1352

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1355

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1371

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1376

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1379

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sprd/sprd_dpu.c

506

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/sprd/sprd_dpu.c

511

if (!plane_state->fb || !plane_state->crtc)

drivers/gpu/drm/sprd/sprd_dpu.c

514

fmt = drm_format_to_dpu(plane_state->fb);

drivers/gpu/drm/sprd/sprd_dpu.c

518

crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sprd/sprd_dpu.c

522

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sun4i/sun4i_backend.c

492

struct drm_plane_state *plane_state =

drivers/gpu/drm/sun4i/sun4i_backend.c

495

state_to_sun4i_layer_state(plane_state);

drivers/gpu/drm/sun4i/sun4i_backend.c

496

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sun4i/sun4i_backend.c

498

if (!sun4i_backend_plane_is_supported(plane_state,

drivers/gpu/drm/sun4i/sun4i_backend.c

515

if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))

drivers/gpu/drm/sun4i/sun4i_backend.c

519

plane_state->normalized_zpos);

drivers/gpu/drm/sun4i/sun4i_backend.c

522

plane_states[plane_state->normalized_zpos] = plane_state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

261

struct drm_plane_state *plane_state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

275

plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sun4i/sun8i_mixer.c

276

if (!plane_state)

drivers/gpu/drm/sun4i/sun8i_mixer.c

277

plane_state = plane->state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

279

enable = plane_state->crtc && plane_state->visible;

drivers/gpu/drm/sun4i/sun8i_mixer.c

280

zpos = plane_state->normalized_zpos;

drivers/gpu/drm/sun4i/sun8i_mixer.c

281

x = plane_state->dst.x1;

drivers/gpu/drm/sun4i/sun8i_mixer.c

282

y = plane_state->dst.y1;

drivers/gpu/drm/sun4i/sun8i_mixer.c

283

w = drm_rect_width(&plane_state->dst);

drivers/gpu/drm/sun4i/sun8i_mixer.c

284

h = drm_rect_height(&plane_state->dst);

drivers/gpu/drm/sysfb/drm_sysfb_helper.h

112

struct drm_plane_state *plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_helper.h

140

struct drm_plane_state *plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

242

struct drm_plane_state *plane_state)

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

245

struct drm_sysfb_plane_state *sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

246

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

252

ret = drm_gem_begin_shadow_fb_access(plane, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

261

crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

280

drm_gem_end_shadow_fb_access(plane, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

333

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

335

struct drm_sysfb_plane_state *sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

337

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

339

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

354

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

357

struct drm_rect dst_clip = plane_state->dst;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

379

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

388

plane_state->src_x >> 16, plane_state->src_y >> 16,

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

389

plane_state->src_w >> 16, plane_state->src_h >> 16);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

441

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

446

if (drm_WARN_ON(dev, !plane_state))

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

448

sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

463

struct drm_plane_state *plane_state)

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

465

drm_sysfb_plane_state_destroy(to_drm_sysfb_plane_state(plane_state));

drivers/gpu/drm/tegra/dc.c

2351

const struct drm_plane_state *plane_state)

drivers/gpu/drm/tegra/dc.c

2359

if (!plane_state->visible || !plane_state->fb)

drivers/gpu/drm/tegra/dc.c

2366

if (tegra_plane_is_cursor(plane_state))

drivers/gpu/drm/tegra/dc.c

2370

rect = plane_state->dst;

drivers/gpu/drm/tegra/dc.c

2399

const struct drm_plane_state *plane_state;

drivers/gpu/drm/tegra/dc.c

2427

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {

drivers/gpu/drm/tegra/dc.c

2428

tegra_state = to_const_tegra_plane_state(plane_state);

drivers/gpu/drm/tegra/dc.c

2435

mask = tegra_plane_overlap_mask(new_state, plane_state);

drivers/gpu/drm/tegra/dc.c

2457

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {

drivers/gpu/drm/tegra/dc.c

2466

tegra_state = to_const_tegra_plane_state(plane_state);

drivers/gpu/drm/tegra/dc.c

623

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/dc.c

628

struct tegra_bo_tiling *tiling = &plane_state->tiling;

drivers/gpu/drm/tegra/dc.c

633

plane_state->peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

634

plane_state->avg_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

638

plane_state->total_peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

643

&plane_state->format,

drivers/gpu/drm/tegra/dc.c

644

&plane_state->swap);

drivers/gpu/drm/tegra/dc.c

655

err = tegra_plane_setup_legacy_state(tegra, plane_state);

drivers/gpu/drm/tegra/dc.c

682

plane_state->reflect_x = true;

drivers/gpu/drm/tegra/dc.c

684

plane_state->reflect_x = false;

drivers/gpu/drm/tegra/dc.c

687

plane_state->reflect_y = true;

drivers/gpu/drm/tegra/dc.c

689

plane_state->reflect_y = false;

drivers/gpu/drm/tegra/dc.c

871

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/dc.c

875

plane_state->peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

876

plane_state->avg_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

880

plane_state->total_peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/hub.c

431

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/hub.c

433

struct tegra_bo_tiling *tiling = &plane_state->tiling;

drivers/gpu/drm/tegra/hub.c

442

&plane_state->format,

drivers/gpu/drm/tegra/hub.c

443

&plane_state->swap);

drivers/gpu/drm/tegra/plane.c

620

struct drm_plane_state *old, *plane_state;

drivers/gpu/drm/tegra/plane.c

638

plane_state = drm_atomic_get_plane_state(state->base.state,

drivers/gpu/drm/tegra/plane.c

640

if (IS_ERR(plane_state))

drivers/gpu/drm/tegra/plane.c

641

return PTR_ERR(plane_state);

drivers/gpu/drm/tests/drm_plane_helper_test.c

101

static void check_crtc_eq(struct kunit *test, struct drm_plane_state *plane_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

107

KUNIT_EXPECT_TRUE_MSG(test, drm_rect_equals(&plane_state->dst, &expected),

drivers/gpu/drm/tests/drm_plane_helper_test.c

109

DRM_RECT_ARG(&plane_state->dst), DRM_RECT_ARG(&expected));

drivers/gpu/drm/tests/drm_plane_helper_test.c

115

struct drm_plane_state *plane_state = test->priv;

drivers/gpu/drm/tests/drm_plane_helper_test.c

118

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

123

KUNIT_EXPECT_TRUE(test, plane_state->visible);

drivers/gpu/drm/tests/drm_plane_helper_test.c

124

check_src_eq(test, plane_state, params->src_expected.x, params->src_expected.y,

drivers/gpu/drm/tests/drm_plane_helper_test.c

126

check_crtc_eq(test, plane_state, params->crtc_expected.x, params->crtc_expected.y,

drivers/gpu/drm/tests/drm_plane_helper_test.c

257

struct drm_plane_state *plane_state = test->priv;

drivers/gpu/drm/tests/drm_plane_helper_test.c

260

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

82

static void check_src_eq(struct kunit *test, struct drm_plane_state *plane_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

88

KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0,

drivers/gpu/drm/tests/drm_plane_helper_test.c

90

plane_state->src.x1, DRM_RECT_FP_ARG(&plane_state->src));

drivers/gpu/drm/tests/drm_plane_helper_test.c

92

KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0,

drivers/gpu/drm/tests/drm_plane_helper_test.c

94

plane_state->src.y1, DRM_RECT_FP_ARG(&plane_state->src));

drivers/gpu/drm/tests/drm_plane_helper_test.c

96

KUNIT_EXPECT_TRUE_MSG(test, drm_rect_equals(&plane_state->src, &expected),

drivers/gpu/drm/tests/drm_plane_helper_test.c

98

DRM_RECT_FP_ARG(&plane_state->src), DRM_RECT_FP_ARG(&expected));

drivers/gpu/drm/tiny/appletbdrm.c

475

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/appletbdrm.c

482

appletbdrm_flush_damage(adev, old_plane_state, plane_state);

drivers/gpu/drm/tiny/arcpgu.c

199

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/bochs.c

449

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/bochs.c

451

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/bochs.c

452

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/bochs.c

459

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/tiny/bochs.c

469

plane_state->crtc_x,

drivers/gpu/drm/tiny/bochs.c

470

plane_state->crtc_y,

drivers/gpu/drm/tiny/cirrus-qemu.c

332

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/tiny/cirrus-qemu.c

333

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/cirrus-qemu.c

334

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/cirrus-qemu.c

353

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/tiny/gm12u320.c

561

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/gm12u320.c

565

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/gm12u320.c

568

gm12u320_fb_mark_dirty(plane_state->fb, &shadow_plane_state->data[0], &rect);

drivers/gpu/drm/tiny/hx8357d.c

180

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/hx8357d.c

51

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/ili9163.c

40

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/ili9163.c

99

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/ili9225.c

184

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/ili9225.c

187

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/ili9225.c

188

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/ili9341.c

136

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/ili9341.c

57

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/ili9486.c

158

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/ili9486.c

99

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/mi0283qt.c

140

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/mi0283qt.c

55

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/panel-mipi-dbi.c

238

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/panel-mipi-dbi.c

255

mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);

drivers/gpu/drm/tiny/pixpaper.c

863

struct drm_plane_state *plane_state =

drivers/gpu/drm/tiny/pixpaper.c

866

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/pixpaper.c

867

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/tiny/pixpaper.c

871

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/pixpaper.c

884

if (!fb || !plane_state->visible) {

drivers/gpu/drm/tiny/repaper.c

636

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/sharp-memory.c

228

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/tiny/sharp-memory.c

235

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/tiny/sharp-memory.c

245

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/sharp-memory.c

246

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/sharp-memory.c

254

if (drm_atomic_helper_damage_merged(old_state, plane_state, &rect))

drivers/gpu/drm/tiny/sharp-memory.c

255

sharp_memory_fb_dirty(plane_state->fb, shadow_plane_state->data,

drivers/gpu/drm/tve200/tve200_display.c

124

struct drm_plane_state *plane_state)

drivers/gpu/drm/udl/udl_modeset.c

285

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/udl/udl_modeset.c

286

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/udl/udl_modeset.c

287

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/udl/udl_modeset.c

303

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/vc4/vc4_hvs.c

798

const struct drm_plane_state *plane_state;

drivers/gpu/drm/vc4/vc4_hvs.c

808

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/vc4/vc4_hvs.c

809

u32 plane_dlist_count = vc4_plane_dlist_size(plane_state);

drivers/gpu/drm/vkms/vkms_composer.c

193

static void pre_blend_color_transform(const struct vkms_plane_state *plane_state,

drivers/gpu/drm/vkms/vkms_composer.c

199

struct drm_colorop *colorop = plane_state->base.base.color_pipeline;

drivers/gpu/drm/vkms/vkms_composer.c

526

struct vkms_plane_state **plane_state = crtc_state->active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

530

if (iosys_map_is_null(&plane_state[i]->frame_info->map[0]))

drivers/gpu/drm/vkms/vkms_crtc.c

119

struct drm_plane_state *plane_state;

drivers/gpu/drm/vkms/vkms_crtc.c

130

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_crtc.c

131

WARN_ON(!plane_state);

drivers/gpu/drm/vkms/vkms_crtc.c

133

if (!plane_state->visible)

drivers/gpu/drm/vkms/vkms_crtc.c

146

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_crtc.c

148

if (!plane_state->visible)

drivers/gpu/drm/vkms/vkms_crtc.c

152

to_vkms_plane_state(plane_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

903

struct drm_plane_state *plane_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

922

plane_state = du->primary.state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

923

if (plane_state->crtc != crtc)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

927

implicit_fb = plane_state->fb;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

928

else if (implicit_fb != plane_state->fb)

drivers/gpu/drm/xe/display/xe_initial_plane.c

163

struct intel_plane_state *plane_state = to_intel_plane_state(_plane_state);

drivers/gpu/drm/xe/display/xe_initial_plane.c

166

vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt,

drivers/gpu/drm/xe/display/xe_initial_plane.c

167

0, 0, 0, false, &plane_state->flags);

drivers/gpu/drm/xe/display/xe_initial_plane.c

171

plane_state->ggtt_vma = vma;

drivers/gpu/drm/xe/display/xe_initial_plane.c

173

plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);

drivers/gpu/drm/xen/xen_drm_front_kms.c

110

struct drm_plane_state *plane_state)

drivers/gpu/drm/xen/xen_drm_front_kms.c

115

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/xen/xen_drm_front_kms.c

183

struct drm_plane_state *plane_state =

drivers/gpu/drm/xen/xen_drm_front_kms.c

195

if (old_plane_state->fb && plane_state->fb) {

drivers/gpu/drm/xen/xen_drm_front_kms.c

206

xen_drm_front_fb_to_cookie(plane_state->fb));

drivers/gpu/drm/xen/xen_drm_front_kms.c

228

struct drm_plane_state *plane_state,

include/drm/drm_atomic.h

888

struct drm_plane_state *plane_state;

include/drm/drm_atomic.h

890

plane_state = drm_atomic_get_new_plane_state(state, plane);

include/drm/drm_atomic.h

891

if (plane_state)

include/drm/drm_atomic.h

892

return plane_state;

include/drm/drm_atomic_helper.h

231

#define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \

include/drm/drm_atomic_helper.h

233

for_each_if ((plane_state = \

include/drm/drm_atomic_helper.h

54

int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

49

drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

51

void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

53

void drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_damage_helper.h

68

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

100

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

114

int drm_gem_begin_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

115

void drm_gem_end_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

130

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

132

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

137

struct drm_plane_state *plane_state);

include/drm/drm_mipi_dbi.h

184

struct drm_plane_state *plane_state);

include/drm/drm_mipi_dbi.h

186

struct drm_plane_state *plane_state);

include/drm/drm_mipi_dbi.h

190

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

126

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

136

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

156

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

228

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

64

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

92

struct drm_plane_state *plane_state,

include/drm/intel/display_parent_interface.h

37

int (*setup)(struct drm_plane_state *plane_state, struct intel_initial_plane_config *plane_config,