arch/arm/mm/pmsa-v7.c

368

unsigned int subregions, bool need_flush)

arch/arm/mm/pmsa-v7.c

387

if (need_flush)

arch/arm/mm/pmsa-v7.c

441

bool need_flush = region == PMSAv7_RAM_REGION;

arch/arm/mm/pmsa-v7.c

448

xip[i].subreg, need_flush);

arch/arm64/kvm/hyp/pgtable.c

1153

bool need_flush = false;

arch/arm64/kvm/hyp/pgtable.c

1169

need_flush = !cpus_have_final_cap(ARM64_HAS_STAGE2_FWB);

arch/arm64/kvm/hyp/pgtable.c

1179

if (need_flush && mm_ops->dcache_clean_inval_poc)

arch/loongarch/include/asm/mmu_context.h

103

if (need_flush)

arch/loongarch/include/asm/mmu_context.h

151

bool need_flush = false;

arch/loongarch/include/asm/mmu_context.h

154

get_new_mmu_context(mm, cpu, &need_flush);

arch/loongarch/include/asm/mmu_context.h

157

if (need_flush)

arch/loongarch/include/asm/mmu_context.h

52

get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, bool *need_flush)

arch/loongarch/include/asm/mmu_context.h

57

*need_flush = true; /* start new asid cycle */

arch/loongarch/include/asm/mmu_context.h

91

bool need_flush = false;

arch/loongarch/include/asm/mmu_context.h

96

get_new_mmu_context(next, cpu, &need_flush);

arch/sparc/kernel/iommu-common.c

206

(n < pool->hint || need_flush(iommu))) {

arch/x86/kernel/amd_gart_64.c

104

need_flush = true;

arch/x86/kernel/amd_gart_64.c

113

need_flush = true;

arch/x86/kernel/amd_gart_64.c

117

need_flush = true;

arch/x86/kernel/amd_gart_64.c

142

if (need_flush) {

arch/x86/kernel/amd_gart_64.c

144

need_flush = false;

arch/x86/kernel/amd_gart_64.c

87

static bool need_flush; /* global flush state. set for each gart wrap */

arch/x86/mm/tlb.c

222

unsigned int need_flush : 1;

arch/x86/mm/tlb.c

232

ns.need_flush = 1;

arch/x86/mm/tlb.c

245

ns.need_flush = 0;

arch/x86/mm/tlb.c

259

ns.need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) < next_tlb_gen);

arch/x86/mm/tlb.c

272

ns.need_flush = true;

arch/x86/mm/tlb.c

566

bool need_flush)

arch/x86/mm/tlb.c

570

if (need_flush) {

arch/x86/mm/tlb.c

901

ns.need_flush = true;

arch/x86/mm/tlb.c

947

if (ns.need_flush) {

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

289

bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

307

if (need_flush || switch_context) {

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

314

if (need_flush) {

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

343

if (need_flush) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

480

unsigned int need_flush;

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

485

err = i915_gem_object_prepare_write(obj, &need_flush);

drivers/infiniband/hw/mlx4/cm.c

529

int need_flush = 0;

drivers/infiniband/hw/mlx4/cm.c

537

need_flush |= !cancel_delayed_work(&map->timeout);

drivers/infiniband/hw/mlx4/cm.c

543

if (need_flush)

drivers/md/dm-writecache.c

1070

need_flush = true;

drivers/md/dm-writecache.c

1091

need_flush = true;

drivers/md/dm-writecache.c

1098

if (need_flush) {

drivers/md/dm-writecache.c

999

bool need_flush = false;

drivers/md/raid10.c

4605

int need_flush = 0;

drivers/md/raid10.c

4646

need_flush = 1;

drivers/md/raid10.c

4668

need_flush = 1;

drivers/md/raid10.c

4678

if (need_flush ||

drivers/net/vmxnet3/vmxnet3_drv.c

1617

bool need_flush = false;

drivers/net/vmxnet3/vmxnet3_drv.c

1678

need_flush |= act == XDP_REDIRECT;

drivers/net/vmxnet3/vmxnet3_drv.c

1735

need_flush |= act == XDP_REDIRECT;

drivers/net/vmxnet3/vmxnet3_drv.c

2010

if (need_flush)

fs/ceph/caps.c

1476

if (capsnap->need_flush) {

fs/ceph/caps.c

1641

BUG_ON(!capsnap->need_flush);

fs/ceph/caps.c

3204

if (!capsnap->need_flush &&

fs/ceph/snap.c

583

capsnap->need_flush = true;

fs/ceph/snap.c

595

ceph_cap_string(dirty), capsnap->need_flush ? "" : "no_flush");

fs/ceph/super.h

274

bool need_flush;

mm/highmem.c

200

int need_flush = 0;

mm/highmem.c

233

need_flush = 1;

mm/highmem.c

235

if (need_flush)