arch/mips/sgi-ip30/ip30-smp.c

112

struct mpconf *mpc = (struct mpconf *)MPCONF(cpu);

arch/mips/sgi-ip30/ip30-smp.c

115

mpc->stackaddr = (void *)__KSTK_TOS(idle);

arch/mips/sgi-ip30/ip30-smp.c

118

mpc->lnch_parm = task_thread_info(idle);

arch/mips/sgi-ip30/ip30-smp.c

123

mpc->launch = smp_bootstrap;

arch/mips/sgi-ip30/ip30-smp.c

79

struct mpconf *mpc;

arch/mips/sgi-ip30/ip30-smp.c

85

mpc = (struct mpconf *)MPCONF(i);

arch/mips/sgi-ip30/ip30-smp.c

86

if (mpc->magic == MPCONF_MAGIC) {

arch/mips/sgi-ip30/ip30-smp.c

91

i, mpc->prid, mpc->physid, mpc->virtid);

arch/x86/include/asm/mpspec_def.h

162

char mpc[8];

arch/x86/kernel/mpparse.c

140

static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)

arch/x86/kernel/mpparse.c

143

if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {

arch/x86/kernel/mpparse.c

145

mpc->signature[0], mpc->signature[1],

arch/x86/kernel/mpparse.c

146

mpc->signature[2], mpc->signature[3]);

arch/x86/kernel/mpparse.c

149

if (mpf_checksum((unsigned char *)mpc, mpc->length)) {

arch/x86/kernel/mpparse.c

153

if (mpc->spec != 0x01 && mpc->spec != 0x04) {

arch/x86/kernel/mpparse.c

154

pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec);

arch/x86/kernel/mpparse.c

157

if (!mpc->lapic) {

arch/x86/kernel/mpparse.c

161

memcpy(oem, mpc->oem, 8);

arch/x86/kernel/mpparse.c

165

memcpy(str, mpc->productid, 12);

arch/x86/kernel/mpparse.c

170

pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic);

arch/x86/kernel/mpparse.c

181

static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)

arch/x86/kernel/mpparse.c

186

1, mpc, mpc->length, 1);

arch/x86/kernel/mpparse.c

189

static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)

arch/x86/kernel/mpparse.c

194

int count = sizeof(*mpc);

arch/x86/kernel/mpparse.c

195

unsigned char *mpt = ((unsigned char *)mpc) + count;

arch/x86/kernel/mpparse.c

197

if (!smp_check_mpc(mpc, oem, str))

arch/x86/kernel/mpparse.c

203

register_lapic_address(mpc->lapic);

arch/x86/kernel/mpparse.c

208

while (count < mpc->length) {

arch/x86/kernel/mpparse.c

234

smp_dump_mptable(mpc, mpt);

arch/x86/kernel/mpparse.c

235

count = mpc->length;

arch/x86/kernel/mpparse.c

414

struct mpc_table *mpc;

arch/x86/kernel/mpparse.c

417

mpc = early_memremap(physptr, PAGE_SIZE);

arch/x86/kernel/mpparse.c

418

size = mpc->length;

arch/x86/kernel/mpparse.c

419

early_memunmap(mpc, PAGE_SIZE);

arch/x86/kernel/mpparse.c

427

struct mpc_table *mpc;

arch/x86/kernel/mpparse.c

431

mpc = early_memremap(mpf->physptr, size);

arch/x86/kernel/mpparse.c

437

if (!smp_read_mpc(mpc, early)) {

arch/x86/kernel/mpparse.c

443

early_memunmap(mpc, size);

arch/x86/kernel/mpparse.c

446

early_memunmap(mpc, size);

arch/x86/kernel/mpparse.c

724

static int __init replace_intsrc_all(struct mpc_table *mpc,

arch/x86/kernel/mpparse.c

731

int count = sizeof(*mpc);

arch/x86/kernel/mpparse.c

733

unsigned char *mpt = ((unsigned char *)mpc) + count;

arch/x86/kernel/mpparse.c

735

pr_info("mpc_length %x\n", mpc->length);

arch/x86/kernel/mpparse.c

736

while (count < mpc->length) {

arch/x86/kernel/mpparse.c

756

smp_dump_mptable(mpc, mpt);

arch/x86/kernel/mpparse.c

784

mpc->length = count;

arch/x86/kernel/mpparse.c

792

mpc->checksum = 0;

arch/x86/kernel/mpparse.c

793

mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length);

arch/x86/kernel/mpparse.c

840

struct mpc_table *mpc, *mpc_new;

arch/x86/kernel/mpparse.c

865

mpc = early_memremap(mpf->physptr, size);

arch/x86/kernel/mpparse.c

866

if (!mpc) {

arch/x86/kernel/mpparse.c

871

if (!smp_check_mpc(mpc, oem, str))

arch/x86/kernel/mpparse.c

877

if (mpc_new_phys && mpc->length > mpc_new_length) {

arch/x86/kernel/mpparse.c

886

mpc->checksum = 0;

arch/x86/kernel/mpparse.c

887

old = mpf_checksum((unsigned char *)mpc, mpc->length);

arch/x86/kernel/mpparse.c

888

mpc->checksum = 0xff;

arch/x86/kernel/mpparse.c

889

new = mpf_checksum((unsigned char *)mpc, mpc->length);

arch/x86/kernel/mpparse.c

902

memcpy(mpc_new, mpc, mpc->length);

arch/x86/kernel/mpparse.c

903

early_memunmap(mpc, size);

arch/x86/kernel/mpparse.c

904

mpc = mpc_new;

arch/x86/kernel/mpparse.c

932

replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length);

arch/x86/kernel/mpparse.c

935

early_memunmap(mpc, size);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1146

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1747

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1917

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c

234

adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

497

if (adev->dm.dc->caps.color.mpc.ogam_ram)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1661

if (dm->dc->caps.color.mpc.gamut_remap)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1665

if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1681

if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7590

state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7591

state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7592

state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7593

state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */

drivers/gpu/drm/amd/display/dc/core/dc.c

7594

state->mpc.mpcc_global_alpha[i] = plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/core/dc.c

7595

state->mpc.mpcc_global_gain[i] = plane_state->global_alpha ? 255 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7596

state->mpc.mpcc_bg_bpc[i] = 8; /* Standard 8-bit background */

drivers/gpu/drm/amd/display/dc/core/dc.c

7597

state->mpc.mpcc_bot_gain_mode[i] = 0; /* Standard gain mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7601

state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

7603

state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */

drivers/gpu/drm/amd/display/dc/core/dc.c

7605

state->mpc.mpcc_top_sel[i] = pipe_ctx->pipe_idx; /* This pipe's DPP ID */

drivers/gpu/drm/amd/display/dc/core/dc.c

7609

state->mpc.mpcc_ogam_mode[i] = 1; /* Gamma enabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7610

state->mpc.mpcc_ogam_select[i] = 0; /* Bank A selection */

drivers/gpu/drm/amd/display/dc/core/dc.c

7611

state->mpc.mpcc_ogam_pwl_disable[i] = 0; /* PWL enabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7613

state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7614

state->mpc.mpcc_ogam_select[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7615

state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7620

state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7622

state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */

drivers/gpu/drm/amd/display/dc/core/dc.c

7626

state->mpc.mpcc_idle[i] = 0; /* Active pipe - not idle */

drivers/gpu/drm/amd/display/dc/core/dc.c

7627

state->mpc.mpcc_busy[i] = 1; /* Active pipe - busy processing */

drivers/gpu/drm/amd/display/dc/core/dc.c

7631

state->mpc.mpcc_mode[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7632

state->mpc.mpcc_alpha_blend_mode[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7633

state->mpc.mpcc_alpha_multiplied_mode[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7634

state->mpc.mpcc_blnd_active_overlap_only[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7635

state->mpc.mpcc_global_alpha[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7636

state->mpc.mpcc_global_gain[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7637

state->mpc.mpcc_bg_bpc[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7638

state->mpc.mpcc_bot_gain_mode[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7639

state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */

drivers/gpu/drm/amd/display/dc/core/dc.c

7640

state->mpc.mpcc_top_sel[i] = 0xF; /* No top connection */

drivers/gpu/drm/amd/display/dc/core/dc.c

7641

state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass */

drivers/gpu/drm/amd/display/dc/core/dc.c

7642

state->mpc.mpcc_ogam_select[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7643

state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7644

state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */

drivers/gpu/drm/amd/display/dc/core/dc.c

7645

state->mpc.mpcc_idle[i] = 1; /* Idle */

drivers/gpu/drm/amd/display/dc/core/dc.c

7646

state->mpc.mpcc_busy[i] = 0; /* Not busy */

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1122

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1129

block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1136

block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1835

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1840

seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1852

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1858

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1871

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1877

seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2356

struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2360

if (mpc->funcs->power_on_mpc_mem_pwr)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2361

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2366

struct mpc *mpc = params->set_output_csc_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2371

if (mpc->funcs->set_output_csc != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2372

mpc->funcs->set_output_csc(mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2380

struct mpc *mpc = params->set_ocsc_default_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2385

if (mpc->funcs->set_ocsc_default != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2386

mpc->funcs->set_ocsc_default(mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2577

dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2938

struct mpc *mpc = params->mpc_remove_mpcc_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2942

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3075

struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3079

if (mpc->funcs->set_dwb_mux)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3080

mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3085

struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3088

if (mpc->funcs->disable_dwb_mux)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3089

mpc->funcs->disable_dwb_mux(mpc, dwb_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3454

struct mpc *mpc = params->mpc_update_blending_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3458

if (mpc && mpc->funcs->update_blending)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3459

mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3464

struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3467

if (mpc && mpc->funcs->wait_for_idle)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3468

mpc->funcs->wait_for_idle(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3473

struct mpc *mpc = params->mpc_insert_plane_params.mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3481

if (mpc && mpc->funcs->insert_plane)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3482

mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3877

struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3881

seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3994

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4000

seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4011

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4021

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4036

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4041

seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4161

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4167

seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4175

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4180

seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4004

if (pool->mpc->funcs->read_mpcc_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4007

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4010

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4014

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4015

&pool->mpc->mpcc_array[s.bot_mpcc_id];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1003

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1047

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

drivers/gpu/drm/amd/display/dc/dc.h

326

struct mpc_color_caps mpc;

drivers/gpu/drm/amd/display/dc/dc.h

3305

} mpc;

drivers/gpu/drm/amd/display/dc/dc.h

857

bool mpc: 1;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

398

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

43

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

49

struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h

71

struct mpc base;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1492

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1498

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1504

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1681

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2308

dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2930

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2932

if (mpc->funcs->set_bg_color) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2933

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2944

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2985

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2991

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2994

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2997

mpc->funcs->assert_mpcc_idle_before_connect(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2998

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3001

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3629

res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

547

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

556

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

557

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

558

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

559

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

570

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

605

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1000

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1004

if (mpc->funcs->power_on_mpc_mem_pwr)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1005

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1008

if (mpc->funcs->set_output_csc != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1009

mpc->funcs->set_output_csc(mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1014

if (mpc->funcs->set_ocsc_default != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1015

mpc->funcs->set_ocsc_default(mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1026

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1035

if (mpc->funcs->power_on_mpc_mem_pwr)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1036

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1038

&& mpc->funcs->set_output_gamma) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1045

&mpc->blender_params, false))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1046

params = &mpc->blender_params;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1056

if (mpc->funcs->set_output_gamma)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1057

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

173

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

185

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

186

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

187

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

188

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2956

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3003

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3009

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3012

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3015

mpc->funcs->assert_mpcc_idle_before_connect(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3016

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3019

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3203

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

833

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

931

if (mpc->funcs->set_out_rate_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

933

mpc->funcs->set_out_rate_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

934

mpc, opp_inst[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

297

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

385

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

394

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

395

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

398

if (mpcc_to_remove != NULL && mpc->funcs->remove_mpcc_from_secondary) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

399

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

404

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

406

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

433

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

490

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

495

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

496

remove_mpcc = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

499

if (remove_mpcc != NULL && mpc->funcs->remove_mpcc_from_secondary)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

500

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, remove_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

503

remove_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

507

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, remove_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

510

mpc->funcs->assert_mpcc_idle_before_connect(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

511

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

515

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1312

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1332

if (mpc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1333

if (mpc->funcs->mpc_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1334

mpc->funcs->mpc_read_reg_state(mpc, i, out_data->mpc_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

186

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

187

mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

229

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

230

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

231

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

232

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

263

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

294

acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

299

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

304

result = mpc->funcs->program_shaper(mpc, shaper_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

311

mpc->funcs->release_rmu(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

364

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

392

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

400

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

408

if (ret == false && mpc->funcs->set_output_gamma) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

415

&mpc->blender_params, false))

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

416

params = &mpc->blender_params;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

423

if (mpc->funcs->set_output_gamma)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

424

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

447

dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

573

dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

95

if (dc->debug.enable_mem_low_power.bits.mpc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

96

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

97

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

181

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

195

if (mpc->funcs->set_out_rate_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

197

mpc->funcs->set_out_rate_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

198

mpc, opp_inst[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

452

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

471

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

475

result = mpc->funcs->program_shaper(mpc, shaper_lut, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

488

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

504

mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

518

mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

522

result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

524

result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

534

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

541

if (mpc == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

575

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

583

if (ret == false && mpc->funcs->set_output_gamma) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

590

&mpc->blender_params, false))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

591

params = &mpc->blender_params;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

598

if (mpc->funcs->set_output_gamma)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

599

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

101

if (dc->debug.enable_mem_low_power.bits.mpc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

102

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

103

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

439

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

456

if (mpc->funcs->set_out_rate_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

458

mpc->funcs->set_out_rate_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

459

mpc, opp_inst[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

706

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

707

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

116

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

122

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

138

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3192

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3198

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3205

hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3392

hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3416

hwss_add_mpc_disable_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3884

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3931

hwss_add_mpc_update_blending(seq_state, mpc, blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3939

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3943

hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, new_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3947

hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3951

hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3993

hwss_add_mpc_assert_idle_mpcc(seq_state, res_pool->mpc, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

415

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

422

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

449

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

472

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

478

if (mpc->funcs->populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

479

mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

481

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

482

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

492

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

498

if (mpc->funcs->mcm.populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

499

mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

500

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

501

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

514

if (mpc->funcs->populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

515

mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

516

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

517

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

524

if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

539

if (mpc->funcs->mcm.is_config_supported &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

540

!mpc->funcs->mcm.is_config_supported(width))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

543

if (mpc->funcs->program_lut_read_write_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

544

mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

545

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

546

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

551

if (mpc->funcs->mcm.program_bit_depth)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

552

mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

592

mpc->funcs->mcm.program_bias_scale) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

593

mpc->funcs->mcm.program_bias_scale(mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

619

if (mpc->funcs->mcm.program_lut_read_write_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

620

mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

622

if (mpc->funcs->mcm.program_3dlut_size)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

623

mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

625

if (mpc->funcs->update_3dlut_fast_load_select)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

626

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

631

if (mpc->funcs->program_lut_mode) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

632

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

633

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

634

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

658

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

668

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

679

result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

692

result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

695

if (mpc->funcs->program_3dlut) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

697

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

699

result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

711

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

719

if (ret == false && mpc->funcs->set_output_gamma) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

726

&mpc->blender_params, false))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

727

params = &mpc->blender_params;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

734

if (mpc->funcs->set_output_gamma)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

735

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

97

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

305

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

353

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

359

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

362

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

365

mpc->funcs->assert_mpcc_idle_before_connect(

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

366

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

369

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

458

static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

460

if (mpc->funcs->rmcm.power_on_shaper_3dlut &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

461

mpc->funcs->rmcm.fl_3dlut_configure &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

470

if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

473

return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 != 0u;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

475

return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 != 0u;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

481

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

487

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

500

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

507

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

563

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

611

if (mpc->funcs->rmcm.populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

612

mpc->funcs->rmcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

613

if (mpc->funcs->rmcm.program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

614

mpc->funcs->rmcm.program_lut_mode(mpc, !bypass_rmcm_shaper, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

635

if (!dc_is_rmcm_3dlut_supported(hubp, mpc) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

636

!mpc->funcs->rmcm.is_config_supported(

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

676

mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

679

mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

684

mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

702

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

734

mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

745

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

751

if (mpc->funcs->populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

752

mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

754

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

755

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

765

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

771

if (mpc->funcs->mcm.populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

772

mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

773

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

774

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

787

if (mpc->funcs->populate_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

788

mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

789

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

790

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

811

if (mpc->funcs->mcm.is_config_supported &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

812

!mpc->funcs->mcm.is_config_supported(width))

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

815

if (mpc->funcs->program_lut_read_write_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

816

mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

817

if (mpc->funcs->program_lut_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

818

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

823

if (mpc->funcs->mcm.program_bit_depth)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

824

mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

847

mpc->funcs->mcm.program_bias_scale) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

848

mpc->funcs->mcm.program_bias_scale(mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

871

if (mpc->funcs->mcm.program_lut_read_write_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

872

mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

874

if (mpc->funcs->mcm.program_3dlut_size)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

875

mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

877

if (mpc->funcs->update_3dlut_fast_load_select)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

878

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

883

if (mpc->funcs->program_lut_mode) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

884

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

885

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

886

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

899

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

909

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

920

result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

933

result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

936

if (mpc->funcs->program_3dlut) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

938

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

940

result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

31

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

112

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

113

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

147

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

153

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

160

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1950

struct mpc *mpc, int mpcc_id, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1953

struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1956

struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2048

struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2113

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2118

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2283

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2288

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2292

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

420

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

426

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

431

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

441

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

504

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

510

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

259

struct mpc *mpc;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1010

void (*set_mpc_mem_lp_mode)(struct mpc *mpc);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1026

void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1042

void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1060

void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1078

void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1096

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1114

void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1123

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1124

void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1125

void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1127

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1130

void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1140

void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1141

void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1142

void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1143

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1145

void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1147

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1148

void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1149

void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1152

void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

1153

void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

381

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

399

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

426

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

450

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

467

void (*mpc_init)(struct mpc *mpc);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

479

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

498

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

519

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

547

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

571

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

624

void (*wait_for_idle)(struct mpc *mpc, int id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

639

void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

656

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

674

void (*set_denorm)(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

693

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

713

void (*set_output_csc)(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

735

void (*set_ocsc_default)(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

756

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

776

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

795

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

814

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

832

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

852

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

873

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

890

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

909

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

927

uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

942

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

959

int (*release_rmu)(struct mpc *mpc, int mpcc_id);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

975

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

993

void (*set_bg_color)(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

109

void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

111

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

119

struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

121

ASSERT(mpcc_id < TO_DCN10_MPC(mpc)->num_mpcc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

122

return &(mpc->mpcc_array[mpcc_id]);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

143

void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

145

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

178

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

186

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

205

new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

245

mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

250

mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

270

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

274

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

353

void mpc1_mpc_init(struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

355

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

366

mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

375

void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

377

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

387

mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

395

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

398

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

40

void mpc1_set_bg_color(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

419

mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

430

struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

44

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

441

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

445

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

45

struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

458

void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

460

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

465

unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

467

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

77

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

81

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

82

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

95

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

99

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

125

struct mpc base;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

142

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

151

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

156

struct mpc *mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

159

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

163

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

167

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

172

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

177

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

181

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

185

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

193

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

197

void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

199

unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

110

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

114

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

130

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

136

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

184

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

190

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

243

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

246

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

271

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

274

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

282

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

285

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

294

static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

298

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

320

static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

323

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

326

mpc2_ogam_get_reg_field(mpc, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

347

static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

350

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

353

mpc2_ogam_get_reg_field(mpc, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

375

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

380

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

404

static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

408

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

410

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

415

if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

429

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

435

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

437

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

447

current_mode = mpc20_get_ogam_current(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

453

mpc20_power_on_ogam_lut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

454

mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

457

mpc2_program_luta(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

459

mpc2_program_lutb(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

461

apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

464

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

469

void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

47

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

471

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

484

void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

486

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

51

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

53

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

542

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

546

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

72

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

76

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

261

struct mpc base;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

278

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

283

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

288

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

293

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

299

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

305

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

309

void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

310

void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

311

void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

100

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1003

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1028

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

103

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1034

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

110

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1126

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1130

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

119

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1198

void mpc3_get_gamut_remap(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1202

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1219

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1234

mpc3_set_3dlut_mode(mpc, LUT_BYPASS, false, false, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1237

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1239

mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1268

mpc3_select_3dlut_ram(mpc, mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1270

mpc3_select_3dlut_ram_mask(mpc, 0x1, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1272

mpc3_set3dlut_ram12(mpc, lut0, lut_size0, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1274

mpc3_set3dlut_ram10(mpc, lut0, lut_size0, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1276

mpc3_select_3dlut_ram_mask(mpc, 0x2, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1278

mpc3_set3dlut_ram12(mpc, lut1, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1280

mpc3_set3dlut_ram10(mpc, lut1, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1282

mpc3_select_3dlut_ram_mask(mpc, 0x4, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1284

mpc3_set3dlut_ram12(mpc, lut2, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1286

mpc3_set3dlut_ram10(mpc, lut2, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1288

mpc3_select_3dlut_ram_mask(mpc, 0x8, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

129

enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1290

mpc3_set3dlut_ram12(mpc, lut3, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1292

mpc3_set3dlut_ram10(mpc, lut3, lut_size, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1294

mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1297

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1298

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1304

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1309

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1343

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1348

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

137

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1387

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1391

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1401

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1405

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1415

uint32_t mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1420

rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1426

mpc3_set_rmu_mux(mpc, rmu_idx, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1434

static int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1436

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1442

rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1444

mpc3_set_rmu_mux(mpc, rmu_idx, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1453

static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1455

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1458

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1472

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1476

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1518

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1521

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

168

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

171

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

188

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

191

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

201

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

204

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

234

static void mpc3_program_luta(struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

237

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

240

mpc3_ogam_get_reg_field(mpc, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

267

static void mpc3_program_lutb(struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

270

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

273

mpc3_ogam_get_reg_field(mpc, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

302

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

307

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

341

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

347

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

349

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

361

current_mode = mpc3_get_ogam_current(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

369

mpc3_power_on_ogam_lut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

370

mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

373

mpc3_program_luta(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

375

mpc3_program_lutb(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

378

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

384

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

385

mpc3_power_on_ogam_lut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

389

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

393

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

428

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

43

void mpc3_mpc_init(struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

432

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

446

static enum dc_lut_mode mpc3_get_shaper_current(struct mpc *mpc, uint32_t rmu_idx)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

45

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

450

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

473

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

477

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

48

mpc1_mpc_init(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

487

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

492

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

58

void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

60

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

62

mpc1_mpc_init_single_inst(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

636

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

641

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

74

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

77

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

787

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

796

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

820

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

826

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

833

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

844

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

863

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

870

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

877

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

878

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

880

current_mode = mpc3_get_shaper_current(mpc, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

887

mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

89

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

890

mpc3_program_shaper_luta_settings(mpc, params, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

892

mpc3_program_shaper_lutb_settings(mpc, params, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

895

mpc, params->rgb_resulted, params->hw_points_num, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

898

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

904

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

912

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

927

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

93

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

934

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

972

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

977

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

985

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

989

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

997

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1011

struct mpc *mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1014

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1018

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1023

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1027

uint32_t mpcc3_acquire_rmu(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1031

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1036

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1041

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1047

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1053

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1058

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1062

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1066

void mpc3_get_gamut_remap(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1071

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1076

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1081

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1085

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1089

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1096

struct mpc *mpc, int mpcc_id,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1100

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1107

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

992

struct mpc base;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

125

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

129

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

140

struct dcn30_mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

143

reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

144

reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

145

reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

146

reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

147

reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

148

reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

149

reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

150

reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

152

reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

153

reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

154

reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

155

reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

156

reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

157

reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

158

reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

159

reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

160

reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

161

reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

162

reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

163

reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

168

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

172

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

192

cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

197

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

201

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

221

cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

225

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

231

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

262

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

268

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

272

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

273

mpc32_power_on_blnd_lut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

277

current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

283

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

284

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

287

mpc32_program_post1dluta_settings(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

289

mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

292

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

301

static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

305

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

329

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

333

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

344

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

349

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

45

void mpc32_mpc_init(struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

47

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

496

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

50

mpc3_mpc_init(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

501

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

52

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

649

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

658

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

68

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

683

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

689

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

695

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

713

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

72

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

720

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

727

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

729

current_mode = mpc32_get_shaper_current(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

736

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

739

mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

741

mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

744

mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

747

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

754

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

76

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

761

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

80

} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

800

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

805

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

814

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

818

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

827

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

833

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

859

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

865

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

881

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

889

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

909

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

92

static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

924

mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

927

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

929

mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

958

mpc32_select_3dlut_ram(mpc, mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

960

mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

962

mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

964

mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

966

mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

968

mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

970

mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

972

mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

974

mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

976

mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

978

mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

98

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

980

mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

982

mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

984

mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

987

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

988

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

311

void mpc32_mpc_init(struct mpc *mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

313

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

317

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

321

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

334

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

338

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

343

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

347

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

351

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

355

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

360

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

364

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

368

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

372

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

376

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

381

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

386

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

390

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

396

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

121

void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

141

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

142

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

145

mpc32_program_post1dluta_settings(mpc, mpcc_id, lut1d);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

147

mpc32_program_post1dlutb_settings(mpc, mpcc_id, lut1d);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

150

mpc, mpcc_id, lut1d->rgb_resulted, lut1d->hw_points_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

156

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

157

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

159

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

162

mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

164

mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

167

mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

169

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

175

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

177

get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

201

mpc32_select_3dlut_ram(mpc, next_mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

203

mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

205

mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

207

mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

209

mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

211

mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

213

mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

215

mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

217

mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

219

mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

221

mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

223

mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

225

mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

227

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

228

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

236

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

242

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

282

void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

284

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

288

mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

292

mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

295

mpc32_configure_post1dlut(mpc, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

301

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

308

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

338

mpc->ctx,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

372

mpc->ctx,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

407

mpc->ctx,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

422

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

426

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

43

void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

432

mpc_program_gamut_remap(mpc, mpcc_id, NULL,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

45

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

466

mpc_program_gamut_remap(mpc, mpcc_id, arr_reg_val,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

471

void mpc_read_gamut_remap(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

478

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

50

void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

52

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

562

void mpc401_get_gamut_remap(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

569

mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

60

void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

62

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

77

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

84

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

191

struct mpc base;

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

208

void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

209

void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

213

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

220

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

226

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

231

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

236

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

241

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

247

void mpc_read_gamut_remap(struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

254

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

261

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

103

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

119

void mpc42_program_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

121

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

133

void mpc42_program_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

135

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

150

void mpc42_program_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

152

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

170

void mpc42_populate_lut(struct mpc *mpc, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

178

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

179

mpc42_power_on_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

181

mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

184

mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

186

mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

189

mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

191

mpc42_power_on_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

194

void mpc42_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

197

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

207

mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

216

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

222

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

230

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

247

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

251

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

267

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

272

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

41

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

419

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

424

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

45

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

47

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

570

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

579

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

601

void mpc42_enable_3dlut_fl(struct mpc *mpc, bool enable, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

603

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

613

void mpc42_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

615

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

622

void mpc42_populate_rmcm_lut(struct mpc *mpc, const union mcm_lut_params params,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

630

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

631

mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, true);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

633

mpc42_configure_rmcm_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

636

mpc42_program_rmcm_shaper_luta_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

638

mpc42_program_rmcm_shaper_lutb_settings(mpc, lut_shaper, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

641

mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

643

mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, false);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

646

void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

649

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

677

void mpc42_program_lut_mode(struct mpc *mpc, const enum MCM_LUT_XABLE xable,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

68

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

680

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

692

void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

694

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

705

void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

707

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

722

void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

724

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

74

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

743

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

747

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

82

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

979

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

983

struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

985

mpc1_read_mpcc_state(mpc, mpcc_inst, s);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

99

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

1003

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

868

struct mpc base;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

888

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

892

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

896

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

900

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

904

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

908

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

913

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

917

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

922

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

932

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

937

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

941

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

945

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

949

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

953

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

957

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

961

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

966

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

972

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

977

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

981

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

986

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

993

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

998

struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1433

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1434

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1435

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1436

dc->caps.color.mpc.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1437

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1438

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1439

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1440

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1441

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1442

dc->caps.color.mpc.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1686

pool->base.mpc = dcn10_mpc_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1687

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

699

static struct mpc *dcn10_mpc_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

941

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

942

kfree(TO_DCN10_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

943

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1128

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1129

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1130

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2516

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2517

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2518

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2519

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2520

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2521

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2522

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2523

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2524

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2525

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2734

pool->base.mpc = dcn20_mpc_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2735

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

867

struct mpc *dcn20_mpc_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

111

struct mpc *dcn20_mpc_create(struct dc_context *ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1179

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1180

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1181

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1182

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1183

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1184

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1185

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1186

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1187

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1188

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1301

pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1302

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

728

static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

951

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

952

kfree(TO_DCN201_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

953

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1096

static struct mpc *dcn21_mpc_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1492

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1493

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1494

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1495

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1496

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1497

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1498

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1499

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1500

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1501

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1686

pool->base.mpc = dcn21_mpc_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1687

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

692

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

693

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

694

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1242

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1243

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1244

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2510

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2511

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2512

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2513

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2514

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2515

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2516

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2517

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2518

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2703

pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2704

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

884

static struct mpc *dcn30_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1091

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1092

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1093

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1510

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1511

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1512

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1513

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1514

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1515

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1516

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1517

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1518

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1694

pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1695

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

798

static struct mpc *dcn301_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1150

if (pool->mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1151

kfree(TO_DCN20_MPC(pool->mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1152

pool->mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1411

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1412

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1413

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1414

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1415

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1416

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1417

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1418

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1419

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1582

pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1583

if (pool->mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

768

static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1094

if (pool->mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1095

kfree(TO_DCN20_MPC(pool->mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1096

pool->mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1355

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1356

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1357

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1358

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1359

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1360

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1361

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1362

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1363

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1514

pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1515

if (pool->mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

732

static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1063

static struct mpc *dcn31_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1544

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1545

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1546

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2116

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2117

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2118

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2119

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2120

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2121

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2122

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2123

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2124

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2314

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2315

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

942

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1120

static struct mpc *dcn31_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1604

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1605

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1606

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2043

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2044

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2045

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2046

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2049

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2050

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2051

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2232

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2233

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

962

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1062

static struct mpc *dcn31_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1546

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1547

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1548

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2088

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2089

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2090

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2091

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2092

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2093

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2094

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2095

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2096

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2266

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2267

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

942

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1055

static struct mpc *dcn31_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1539

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1540

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1541

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1962

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1963

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1964

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1965

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1966

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1967

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1968

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1969

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1970

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2130

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2131

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

937

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1020

static struct mpc *dcn32_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1560

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1561

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1562

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2442

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2443

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2444

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2445

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2446

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2447

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2448

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2449

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2450

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2451

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2627

pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2628

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

770

.mpc = false,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1008

static struct mpc *dcn321_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1535

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1536

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1537

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1933

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1934

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1935

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1936

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1937

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1938

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1939

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1940

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1941

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1942

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2115

pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2116

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

760

.mpc = false,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1002

static struct mpc *dcn35_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1609

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1610

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1611

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2071

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2072

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2073

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2074

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2075

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2076

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2077

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2078

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2079

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2080

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2282

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2283

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

794

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1589

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1590

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1591

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2044

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2045

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2046

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2049

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2050

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2051

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2052

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2053

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2254

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2255

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

774

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

982

static struct mpc *dcn35_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1596

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1597

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1598

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2041

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2042

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2043

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2044

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2045

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2046

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2049

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2050

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2252

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2253

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

781

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

989

static struct mpc *dcn35_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1010

static struct mpc *dcn401_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1550

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1551

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1552

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2123

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2124

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2125

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2126

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2127

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2128

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2129

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2130

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2131

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2132

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2322

pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2323

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

758

.mpc = false,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1043

static struct mpc *dcn42_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1543

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1544

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1545

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2074

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2076

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2077

dc->caps.color.mpc.num_rmcm_3dluts = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2078

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2079

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2080

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2081

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2082

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2083

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2084

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2085

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2086

dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2087

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2088

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2089

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2090

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2091

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2092

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2093

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2094

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2095

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2096

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2097

dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2098

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2099

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2100

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2101

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2102

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2103

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2104

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2105

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2106

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2107

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2319

pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2321

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

757

.mpc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1078

static struct mpc *dcn42b_mpc_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1507

if (pool->base.mpc != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1508

kfree(TO_DCN20_MPC(pool->base.mpc));

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1509

pool->base.mpc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2035

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2037

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2038

dc->caps.color.mpc.num_rmcm_3dluts = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2039

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2040

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2041

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2042

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2043

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2044

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2045

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2046

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2047

dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2048

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2049

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2050

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2051

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2052

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2053

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2054

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2055

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2056

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2057

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2058

dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2059

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2060

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2061

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2062

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2063

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2064

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2065

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2066

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2067

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2068

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2273

pool->base.mpc = dcn42b_mpc_create(ctx, pool->base.mpcc_count,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2275

if (pool->base.mpc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

785

.mpc = true,

drivers/infiniband/hw/mana/main.c

12

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/main.c

16

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/main.c

24

mana_destroy_eq(mpc);

drivers/infiniband/hw/mana/main.c

25

mana_uncfg_vport(mpc);

drivers/infiniband/hw/mana/main.c

34

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/main.c

39

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/main.c

65

err = mana_cfg_vport(mpc, pd->pdn, doorbell_id, true);

drivers/infiniband/hw/mana/main.c

75

err = mana_create_eq(mpc);

drivers/infiniband/hw/mana/main.c

77

mana_uncfg_vport(mpc);

drivers/infiniband/hw/mana/main.c

80

pd->tx_shortform_allowed = mpc->tx_shortform_allowed;

drivers/infiniband/hw/mana/main.c

81

pd->tx_vp_offset = mpc->tx_vp_offset;

drivers/infiniband/hw/mana/main.c

88

mpc->port_handle, pd->pdn, doorbell_id);

drivers/infiniband/hw/mana/qp.c

146

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

15

struct mana_port_context *mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

205

eq = &mpc->eqs[cq->comp_vector % mpc->num_queues];

drivers/infiniband/hw/mana/qp.c

208

ret = mana_create_wq_obj(mpc, mpc->port_handle, GDMA_RQ,

drivers/infiniband/hw/mana/qp.c

232

mana_destroy_wq_obj(mpc, GDMA_RQ, wq->rx_object);

drivers/infiniband/hw/mana/qp.c

255

mana_disable_vport_rx(mpc);

drivers/infiniband/hw/mana/qp.c

264

mana_destroy_wq_obj(mpc, GDMA_RQ, wq->rx_object);

drivers/infiniband/hw/mana/qp.c

296

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/qp.c

331

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

332

ibdev_dbg(&mdev->ib_dev, "port %u ndev %p mpc %p\n", port, ndev, mpc);

drivers/infiniband/hw/mana/qp.c

358

if (!mpc->eqs) {

drivers/infiniband/hw/mana/qp.c

365

eq = &mpc->eqs[eq_vec % mpc->num_queues];

drivers/infiniband/hw/mana/qp.c

368

err = mana_create_wq_obj(mpc, mpc->port_handle, GDMA_SQ, &wq_spec,

drivers/infiniband/hw/mana/qp.c

37

req->vport = mpc->port_handle;

drivers/infiniband/hw/mana/qp.c

407

mana_destroy_wq_obj(mpc, GDMA_SQ, qp->qp_handle);

drivers/infiniband/hw/mana/qp.c

746

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/qp.c

778

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

779

copy_in_reverse(req.ah_attr.src_mac, mpc->mac_addr, ETH_ALEN);

drivers/infiniband/hw/mana/qp.c

824

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/qp.c

832

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

848

mana_disable_vport_rx(mpc);

drivers/infiniband/hw/mana/qp.c

855

mana_destroy_wq_obj(mpc, GDMA_RQ, wq->rx_object);

drivers/infiniband/hw/mana/qp.c

872

struct mana_port_context *mpc;

drivers/infiniband/hw/mana/qp.c

877

mpc = netdev_priv(ndev);

drivers/infiniband/hw/mana/qp.c

880

mana_destroy_wq_obj(mpc, GDMA_SQ, qp->qp_handle);

drivers/infiniband/hw/mana/qp.c

90

struct mana_port_context *mpc;

drivers/net/ethernet/apple/mace.c

646

dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */

drivers/net/ethernet/apple/mace.h

36

REG(mpc); /* missed packet count (clears when read) */

drivers/net/ethernet/apple/macmace.c

542

dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

45

{ "rx_missed_errors", E1000_STAT(stats.mpc) },

drivers/net/ethernet/intel/e1000/e1000_hw.h

1255

u64 mpc;

drivers/net/ethernet/intel/e1000/e1000_main.c

3632

adapter->stats.mpc += er32(MPC);

drivers/net/ethernet/intel/e1000/e1000_main.c

3701

netdev->stats.rx_missed_errors = adapter->stats.mpc;

drivers/net/ethernet/intel/e1000e/ethtool.c

65

E1000_STAT("rx_missed_errors", stats.mpc),

drivers/net/ethernet/intel/e1000e/hw.h

383

u64 mpc;

drivers/net/ethernet/intel/e1000e/netdev.c

4986

adapter->stats.mpc += er32(MPC);

drivers/net/ethernet/intel/e1000e/netdev.c

5048

netdev->stats.rx_missed_errors = adapter->stats.mpc;

drivers/net/ethernet/intel/e1000e/netdev.c

6032

stats->rx_missed_errors = adapter->stats.mpc;

drivers/net/ethernet/intel/igb/e1000_hw.h

172

u64 mpc;

drivers/net/ethernet/intel/igb/igb_ethtool.c

45

IGB_STAT("rx_missed_errors", stats.mpc),

drivers/net/ethernet/intel/igb/igb_ethtool.c

557

regs_buff[58] = adapter->stats.mpc;

drivers/net/ethernet/intel/igb/igb_main.c

6761

u32 reg, mpc;

drivers/net/ethernet/intel/igb/igb_main.c

6836

mpc = rd32(E1000_MPC);

drivers/net/ethernet/intel/igb/igb_main.c

6837

adapter->stats.mpc += mpc;

drivers/net/ethernet/intel/igb/igb_main.c

6838

net_stats->rx_fifo_errors += mpc;

drivers/net/ethernet/intel/igb/igb_main.c

6916

net_stats->rx_missed_errors = adapter->stats.mpc;

drivers/net/ethernet/intel/igc/igc_ethtool.c

239

regs_buff[34] = adapter->stats.mpc;

drivers/net/ethernet/intel/igc/igc_ethtool.c

39

IGC_STAT("rx_missed_errors", stats.mpc),

drivers/net/ethernet/intel/igc/igc_hw.h

209

u64 mpc;

drivers/net/ethernet/intel/igc/igc_main.c

5157

u32 mpc;

drivers/net/ethernet/intel/igc/igc_main.c

5232

mpc = rd32(IGC_MPC);

drivers/net/ethernet/intel/igc/igc_main.c

5233

adapter->stats.mpc += mpc;

drivers/net/ethernet/intel/igc/igc_main.c

5234

net_stats->rx_fifo_errors += mpc;

drivers/net/ethernet/intel/igc/igc_main.c

5294

net_stats->rx_missed_errors = adapter->stats.mpc;

drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

884

regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

7686

u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

7761

mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

7762

missed_rx += mpc;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

7763

hwstats->mpc[i] += mpc;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

7764

total_mpc += hwstats->mpc[i];

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

3402

u64 mpc[8];

drivers/net/ethernet/microsoft/mana/mana_en.c

2691

struct mana_port_context *mpc = netdev_priv(rxq->ndev);

drivers/net/ethernet/microsoft/mana/mana_en.c

2698

if (mpc->rxbufs_pre)

drivers/net/ethernet/microsoft/mana/mana_en.c

2782

struct mana_port_context *mpc = netdev_priv(rxq->ndev);

drivers/net/ethernet/microsoft/mana/mana_en.c

2786

pprm.pool_size = mpc->rx_queue_size / rxq->frag_count + 1;

drivers/net/ethernet/microsoft/mana/mana_en.c

679

void mana_pre_dealloc_rxbufs(struct mana_port_context *mpc)

drivers/net/ethernet/microsoft/mana/mana_en.c

684

dev = mpc->ac->gdma_dev->gdma_context->dev;

drivers/net/ethernet/microsoft/mana/mana_en.c

686

if (!mpc->rxbufs_pre)

drivers/net/ethernet/microsoft/mana/mana_en.c

689

if (!mpc->das_pre)

drivers/net/ethernet/microsoft/mana/mana_en.c

692

while (mpc->rxbpre_total) {

drivers/net/ethernet/microsoft/mana/mana_en.c

693

i = --mpc->rxbpre_total;

drivers/net/ethernet/microsoft/mana/mana_en.c

694

dma_unmap_single(dev, mpc->das_pre[i], mpc->rxbpre_datasize,

drivers/net/ethernet/microsoft/mana/mana_en.c

696

put_page(virt_to_head_page(mpc->rxbufs_pre[i]));

drivers/net/ethernet/microsoft/mana/mana_en.c

699

kvfree(mpc->das_pre);

drivers/net/ethernet/microsoft/mana/mana_en.c

700

mpc->das_pre = NULL;

drivers/net/ethernet/microsoft/mana/mana_en.c

703

kvfree(mpc->rxbufs_pre);

drivers/net/ethernet/microsoft/mana/mana_en.c

704

mpc->rxbufs_pre = NULL;

drivers/net/ethernet/microsoft/mana/mana_en.c

707

mpc->rxbpre_datasize = 0;

drivers/net/ethernet/microsoft/mana/mana_en.c

708

mpc->rxbpre_alloc_size = 0;

drivers/net/ethernet/microsoft/mana/mana_en.c

709

mpc->rxbpre_headroom = 0;

drivers/net/ethernet/microsoft/mana/mana_en.c

716

struct mana_port_context *mpc;

drivers/net/ethernet/microsoft/mana/mana_en.c

719

mpc = netdev_priv(ndev);

drivers/net/ethernet/microsoft/mana/mana_en.c

721

if (!mpc->rxbufs_pre || !mpc->das_pre || !mpc->rxbpre_total) {

drivers/net/ethernet/microsoft/mana/mana_en.c

727

if (mpc->rxbpre_datasize != rxq->datasize) {

drivers/net/ethernet/microsoft/mana/mana_en.c

729

mpc->rxbpre_datasize, rxq->datasize);

drivers/net/ethernet/microsoft/mana/mana_en.c

733

if (mpc->rxbpre_alloc_size != rxq->alloc_size) {

drivers/net/ethernet/microsoft/mana/mana_en.c

735

mpc->rxbpre_alloc_size, rxq->alloc_size);

drivers/net/ethernet/microsoft/mana/mana_en.c

739

if (mpc->rxbpre_headroom != rxq->headroom) {

drivers/net/ethernet/microsoft/mana/mana_en.c

741

mpc->rxbpre_headroom, rxq->headroom);

drivers/net/ethernet/microsoft/mana/mana_en.c

745

mpc->rxbpre_total--;

drivers/net/ethernet/microsoft/mana/mana_en.c

747

*da = mpc->das_pre[mpc->rxbpre_total];

drivers/net/ethernet/microsoft/mana/mana_en.c

748

va = mpc->rxbufs_pre[mpc->rxbpre_total];

drivers/net/ethernet/microsoft/mana/mana_en.c

749

mpc->rxbufs_pre[mpc->rxbpre_total] = NULL;

drivers/net/ethernet/microsoft/mana/mana_en.c

752

if (!mpc->rxbpre_total)

drivers/net/ethernet/microsoft/mana/mana_en.c

753

mana_pre_dealloc_rxbufs(mpc);

drivers/net/ethernet/microsoft/mana/mana_en.c

802

int mana_pre_alloc_rxbufs(struct mana_port_context *mpc, int new_mtu, int num_queues)

drivers/net/ethernet/microsoft/mana/mana_en.c

811

mana_get_rxbuf_cfg(mpc, new_mtu, &mpc->rxbpre_datasize,

drivers/net/ethernet/microsoft/mana/mana_en.c

812

&mpc->rxbpre_alloc_size, &mpc->rxbpre_headroom,

drivers/net/ethernet/microsoft/mana/mana_en.c

813

&mpc->rxbpre_frag_count);

drivers/net/ethernet/microsoft/mana/mana_en.c

815

dev = mpc->ac->gdma_dev->gdma_context->dev;

drivers/net/ethernet/microsoft/mana/mana_en.c

817

num_rxb = num_queues * mpc->rx_queue_size;

drivers/net/ethernet/microsoft/mana/mana_en.c

819

WARN(mpc->rxbufs_pre, "mana rxbufs_pre exists\n");

drivers/net/ethernet/microsoft/mana/mana_en.c

820

mpc->rxbufs_pre = kvmalloc_array(num_rxb, sizeof(void *), GFP_KERNEL);

drivers/net/ethernet/microsoft/mana/mana_en.c

821

if (!mpc->rxbufs_pre)

drivers/net/ethernet/microsoft/mana/mana_en.c

824

mpc->das_pre = kvmalloc_objs(dma_addr_t, num_rxb);

drivers/net/ethernet/microsoft/mana/mana_en.c

825

if (!mpc->das_pre)

drivers/net/ethernet/microsoft/mana/mana_en.c

828

mpc->rxbpre_total = 0;

drivers/net/ethernet/microsoft/mana/mana_en.c

831

page = dev_alloc_pages(get_order(mpc->rxbpre_alloc_size));

drivers/net/ethernet/microsoft/mana/mana_en.c

837

da = dma_map_single(dev, va + mpc->rxbpre_headroom,

drivers/net/ethernet/microsoft/mana/mana_en.c

838

mpc->rxbpre_datasize, DMA_FROM_DEVICE);

drivers/net/ethernet/microsoft/mana/mana_en.c

844

mpc->rxbufs_pre[i] = va;

drivers/net/ethernet/microsoft/mana/mana_en.c

845

mpc->das_pre[i] = da;

drivers/net/ethernet/microsoft/mana/mana_en.c

846

mpc->rxbpre_total = i + 1;

drivers/net/ethernet/microsoft/mana/mana_en.c

852

netdev_err(mpc->ndev, "Failed to pre-allocate RX buffers for %d queues\n", num_queues);

drivers/net/ethernet/microsoft/mana/mana_en.c

853

mana_pre_dealloc_rxbufs(mpc);

drivers/net/ethernet/microsoft/mana/mana_en.c

859

struct mana_port_context *mpc = netdev_priv(ndev);

drivers/net/ethernet/microsoft/mana/mana_en.c

864

err = mana_pre_alloc_rxbufs(mpc, new_mtu, mpc->num_queues);

drivers/net/ethernet/microsoft/mana/mana_en.c

885

mana_pre_dealloc_rxbufs(mpc);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c

1025

static void brcmf_scan_config_mpc(struct brcmf_if *ifp, int mpc)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c

1028

brcmf_set_mpc(ifp, mpc);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c

1031

void brcmf_set_mpc(struct brcmf_if *ifp, int mpc)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c

1037

err = brcmf_fil_iovar_int_set(ifp, "mpc", mpc);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c

1042

brcmf_dbg(INFO, "MPC : %d\n", mpc);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.h

493

void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);

drivers/pci/quirks.c

5352

u32 mpc;

drivers/pci/quirks.c

5360

pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);

drivers/pci/quirks.c

5361

if (!(mpc & INTEL_MPC_REG_IRBNCE)) {

drivers/pci/quirks.c

5363

mpc |= INTEL_MPC_REG_IRBNCE;

drivers/pci/quirks.c

5364

pci_write_config_word(dev, INTEL_MPC_REG, mpc);

sound/soc/mediatek/common/mtk-soundcard-driver.c

137

const struct mtk_pcm_constraints_data *mpc = &soc_card->card_data->pcm_constraints[ctype];

sound/soc/mediatek/common/mtk-soundcard-driver.c

140

if (unlikely(!mpc))

sound/soc/mediatek/common/mtk-soundcard-driver.c

145

mpc->rates);

sound/soc/mediatek/common/mtk-soundcard-driver.c

153

mpc->channels);