max3
l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
return max3(bfqq->soft_rt_next_start,
bdi->ra_pages = max3(bdi->ra_pages,
if (max3(alg->maxauthsize, alg->ivsize, alg->chunksize) >
size = max3(ddata->offsets[SYSC_REVISION],
max3(sizeof(struct gpu_metrics_v2_2),
#define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
max_ctf = max3(pptable->CTFLimitMID, pptable->CTFLimitXCD,
max_thm = max3(pptable->ThermalLimitMID, pptable->ThermalLimitXCD,
vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
*(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
vco_min = max3(vco_min, vclk, dclk);
high = max3(tbuf[1], tbuf[2], tbuf[3]);
high = max3(g15->transfer_buf[1], g15->transfer_buf[2],
ipoib_sendq_size = max3(ipoib_sendq_size, 2 * MAX_SEND_CQE, IPOIB_MIN_QUEUE_SIZE);
if (max3(FIELD_GET(RISCV_IOMMU_ICVEC_CIV, iommu->icvec),
return max3(new_setpoint, new_min, 0);
max_rgb = max3(r, g, b);
vp9_top_lb += max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES) *
return max3(vpp_cycles, vsp_cycles, fw_cycles);
return max3(x, y, z);
return max3(x, y, z);
return max3(x, y, z);
dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr);
timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
timeps = max3(timeps, conf->timings.sdr.tDH_min,
cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
last_subpart = max3(trx->offset[0], trx->offset[1],
rx_size = max3(BNGE_DEFAULT_RX_COPYBREAK,
rx_size = max3(BNXT_MIN_RX_HDR_BUF,
pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues,
return max3(NFP_NET_DEFAULT_MTU,
return max3(ath11k_mac_max_ht_nss(ht_mcs_mask),
mac_nss = max(max3(ath12k_mac_max_ht_nss(ht_mcs_mask),
mac_nss = max3(ath12k_mac_max_ht_nss(ht_mcs_mask),
pwr = max3(pwr80, pwr40, pwr20);
mphy->txpower_cur = max3(mphy->txpower_cur, pwr160, pwr);
pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
pkt_stat->signal_power = max3(power_a, power_b, min_rx_power);
ALIGN(max3(RTW89_RADIOTAP_ROOM_VHT, RTW89_RADIOTAP_ROOM_HE, \
u8 hue = 0, max = max3(c->r, c->g, c->b);
bits_per_pixel = max(max3(si->red_size + si->red_pos,
bufsize = 1024 + max3(nlmsvc_version1.vs_xdrsize,
unwrite_start = max3(start,
const unsigned int per_intent = max(max3(tx0, tx1, tx2),
max3(tx3, tx4, relog));
*step_size = max(f4, max3(f1, f2, f3));
return XFS_DQUOT_LOGRES + max3(t1, t2, t3);
return XFS_DQUOT_LOGRES + max(t4, max3(t1, t2, t3));
return XFS_DQUOT_LOGRES + max3(t1, t2, t3);
return XFS_DQUOT_LOGRES + max(t4, max3(t1, t2, t3));
return overhead + max3(t1, t2, t3);
return overhead + max3(t1, t2, t3);
return overhead + max3(t1, t2, t3);
return overhead + max3(t1, t2, t3);
const unsigned int step_size = max3(f1, f2, f3);
const unsigned int step_size = max3(f1, f2, f3);
const unsigned int step_size = max3(f1, f2, f3);
start = max3(addr_start, pt_start, vma->vm_start);
x = max3(wb->balanced_dirty_ratelimit,
pcp->high = max3(pcp->count - (batch << CONFIG_PCP_BATCH_SCALE_MAX),
*start = max3(left, vma->vm_start, faddr & PMD_MASK);
return max3(va_size(va),
return max3(2U, ca->shadow_wnd, tcp_snd_cwnd(tp) >> 1);