irq_pending
unsigned long irq_pending;
clear_bit(irq, &vcpu->arch.irq_pending);
set_bit(irq, &vcpu->arch.irq_pending);
return test_bit(INT_TI, &vcpu->arch.irq_pending);
clear_bit(priority, &vcpu->arch.irq_pending);
unsigned long *pending = &vcpu->arch.irq_pending;
return !!(vcpu->arch.irq_pending) &&
kvm_debug("\tExceptions: %08lx\n", vcpu->arch.irq_pending);
memset(&vcpu->arch.irq_pending, 0, sizeof(vcpu->arch.irq_pending));
__u16 irq_pending; /* [0x202-0x203] pending interrupts bits */
events = oss->irq_pending & OSS_IP_NUBUS;
u32 irq_pending;
irq_pending = gfpic_read(pic, GFPIC_REG_IRQ_PENDING);
if (irq_pending & 1)
irq_pending >>= 1;
} while (irq_pending);
u8 irq_pending; /* Used by XIVE to signal pending guest irqs */
return vcpu->arch.irq_pending || vcpu->arch.xive_saved_state.pipr <
vcpu->arch.irq_pending = 0;
vcpu->arch.irq_pending = 1;
} while (machine_is_lpar() && irq_pending(regs));
int (*irq_pending)(unsigned int irq);
if (legacy_pic->irq_pending(irq))
.irq_pending = legacy_pic_irq_pending_noop,
.irq_pending = i8259A_irq_pending,
bool irq_pending;
if (READ_ONCE(ring->irq_pending))
} else if (ring->intmodt && !READ_ONCE(ring->irq_pending)) {
WRITE_ONCE(ring->irq_pending, true);
WRITE_ONCE(ring->irq_pending, false);
return pvr_dev->fw_dev.defs->irq_pending(pvr_dev);
bool (*irq_pending)(struct pvr_device *pvr_dev);
.irq_pending = pvr_meta_irq_pending,
.irq_pending = pvr_mips_irq_pending,
.irq_pending = pvr_riscv_irq_pending,
bool irq_pending = xe_device_uses_memirq(gt_to_xe(gt)) &&
if (irq_pending || READ_ONCE(gt->sriov.vf.migration.ggtt_need_fixes))
u32 irq_pending = axi_ioread(ADI_REG_IRQ_PENDING, ctl);
if (irq_pending & ADI_IRQ_SRC_TEMP_INCREASE)
if (irq_pending & ADI_IRQ_SRC_PWM_CHANGED) {
if (irq_pending & ADI_IRQ_SRC_NEW_MEASUR) {
if (irq_pending & ADI_IRQ_SRC_TACH_ERR)
clear_mask = irq_pending & ADI_IRQ_SRC_MASK;
u16 irq_pending = dib3000mc_read_word(state, 511);
if (irq_pending & 0x1) // failed
if (irq_pending & 0x2) // succeeded
u16 irq_pending = dib7000m_read_word(state, reg);
if (irq_pending & 0x1) { // failed
if (irq_pending & 0x2) { // succeeded
u16 irq_pending = dib7000p_read_word(state, 1284);
if (irq_pending & 0x1)
if (irq_pending & 0x2)
u16 irq_pending = dib8000_read_word(state, 1284);
if (irq_pending & 0x1) {
if (irq_pending & 0x1) { /* failed */
if (irq_pending & 0x2) { /* succeeded */
ep->irq_pending |= BIT(intx);
ep->irq_pending &= ~BIT(intx);
if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
u8 irq_pending;
ep->irq_pending |= BIT(intx);
ep->irq_pending &= ~BIT(intx);
u8 irq_pending;
bool irq_pending;
irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
if (mask != irq_pending) {
.irq_pending = pci_esp_irq_pending,
if (esp->ops->irq_pending(esp))
if (esp->ops->irq_pending(esp)) {
if (esp->ops->irq_pending(esp)) {
if (esp->ops->irq_pending(esp))
int (*irq_pending)(struct esp *esp);
.irq_pending = jazz_esp_irq_pending,
.irq_pending = mac_esp_irq_pending,
.irq_pending = sun3x_esp_irq_pending,
.irq_pending = sbus_esp_irq_pending,
.irq_pending = zorro_esp_irq_pending,
.irq_pending = zorro_esp_irq_pending,
.irq_pending = zorro_esp_irq_pending,
.irq_pending = cyber_esp_irq_pending,
.irq_pending = zorro_esp_irq_pending,
.irq_pending = fastlane_esp_irq_pending,
temp = readl(&pdev->ir_set->irq_pending);
writel(IMAN_IE_SET(temp), &pdev->ir_set->irq_pending);
temp = readl(&pdev->ir_set->irq_pending);
writel(IMAN_IE_CLEAR(temp), &pdev->ir_set->irq_pending);
temp = readl(&pdev->ir_set->irq_pending);
writel(temp, &pdev->ir_set->irq_pending);
__le32 irq_pending;
u32 irq_pending;
irq_pending = readl(&pdev->ir_set->irq_pending);
irq_pending |= IMAN_IP;
writel(irq_pending, &pdev->ir_set->irq_pending);
unsigned int irq_pending:1;
azx_dev->irq_pending = 0;
azx_dev->irq_pending = 1;
if (!azx_dev->irq_pending ||
azx_dev->irq_pending = 0;
azx_dev->irq_pending = 0;