iidr
info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR);
void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
if (quirks->iidr != (quirks->mask & iidr))
u32 iidr;
void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
.iidr = 0xa100034c, /* ThunderX pass 1.x */
.iidr = 0xa100034c, /* ThunderX pass 1.x */
.iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
.iidr = 0x0001143b,
.iidr = 0x00000004,
.iidr = 0x00051736,
.iidr = 0x0201743b,
.iidr = 0x0201743b,
u32 iidr = readl_relaxed(its->base + GITS_IIDR);
gic_enable_quirks(iidr, its_quirks, its);
.iidr = 0x0204043b,
.iidr = 0x00000000,
.iidr = 0xa000034c,
.iidr = 0x0402043b,
.iidr = 0x0400043b,
.iidr = 0x0402043b,
.iidr = 0x0000043b,
struct iidr_t iidr;
struct iidr_t iidr;
struct iidr iidr;
mhu->implem = readl_relaxed_bitmask(&mhu->ctrl->iidr, implementer);
mhu->rev = readl_relaxed_bitmask(&mhu->ctrl->iidr, revision);
mhu->var = readl_relaxed_bitmask(&mhu->ctrl->iidr, variant);
mhu->prod_id = readl_relaxed_bitmask(&mhu->ctrl->iidr, product_id);
u32 iidr;
return sysfs_emit(page, "0x%08x\n", smmu_pmu->iidr);
if (!smmu_pmu->iidr)
u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
if (!iidr && smmu_pmu_coresight_id_regs(smmu_pmu)) {
iidr = FIELD_PREP(SMMU_PMCG_IIDR_PRODUCTID, productid) |
smmu_pmu->iidr = iidr;
int iidr, ver, impl;
iidr = readl(gwdt->control_base + SBSA_GWDT_W_IIDR);
ver = (iidr >> SBSA_GWDT_VERSION_SHIFT) & SBSA_GWDT_VERSION_MASK;
impl = (iidr >> SBSA_GWDT_IMPL_SHIFT) & SBSA_GWDT_IMPL_MASK;
__u32 iidr;