drivers/gpu/drm/amd/display/dc/core/dc.c

2512

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

4360

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/core/dc.c

4451

cur_pipe->plane_res.hubp->funcs->validate_dml_output(

drivers/gpu/drm/amd/display/dc/core/dc.c

4452

cur_pipe->plane_res.hubp, dc->ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

5789

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

5804

hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

5805

hubp->funcs->set_blank_regs(hubp, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

5819

hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

5820

hubp->funcs->set_blank_regs(hubp, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

6624

state->hubp[i].valid_stream = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

6628

state->hubp[i].valid_stream = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

6632

state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6634

state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6636

state->hubp[i].valid_plane_state = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

6638

state->hubp[i].valid_plane_state = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

6639

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

6640

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

6641

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6645

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6646

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6651

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6652

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6653

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

6654

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

6658

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6659

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6660

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

6663

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6664

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6665

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6666

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

6669

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6670

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6671

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6672

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6675

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6676

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6679

state->hubp[i].min_dc_gfx_version9 = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

6681

state->hubp[i].min_dc_gfx_version9 = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

6682

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

6683

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

6684

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6685

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

6686

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

6687

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

6688

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

6694

state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6695

state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6696

state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6697

state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6698

state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6699

state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6700

state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6701

state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

6706

state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6707

state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6708

state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6709

state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6710

state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6711

state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6712

state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6713

state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

6717

state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6718

state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6719

state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6720

state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6723

state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

6724

state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

6725

state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6726

state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6729

state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6730

state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6731

state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

6734

state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

6735

state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

6736

state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6737

state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1038

params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1039

params->hubp_wait_pipe_read_start_params.hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1347

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1351

seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1587

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1590

seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1768

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1772

seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1907

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1912

seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2026

struct hubp *hubp = params->program_surface_config_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2035

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2036

hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2045

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2050

struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2053

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2163

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2181

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2182

if (!hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2185

mpcc_inst = hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2543

struct hubp *hubp = params->hubp_disconnect_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2545

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2546

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2592

struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2598

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2734

struct hubp *hubp = params->hubp_update_mall_sel_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2738

if (hubp && hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2739

hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2744

struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2747

if (hubp && hubp->funcs->hubp_prepare_subvp_buffering)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2748

hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2753

struct hubp *hubp = params->hubp_set_blank_en_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2756

if (hubp && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2757

hubp->funcs->set_hubp_blank_en(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2762

struct hubp *hubp = params->hubp_disable_control_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2765

if (hubp && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2766

hubp->funcs->hubp_disable_control(hubp, disable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2780

struct hubp *hubp = params->hubp_clk_cntl_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2783

if (hubp && hubp->funcs->hubp_clk_cntl) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2784

hubp->funcs->hubp_clk_cntl(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2785

hubp->power_gated = !enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2791

struct hubp *hubp = params->hubp_init_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2793

if (hubp && hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2794

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2799

struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2806

if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2807

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2812

struct hubp *hubp = params->hubp_set_flip_int_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2814

if (hubp && hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2815

hubp->funcs->hubp_set_flip_int(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2907

struct hubp *hubp = params->hubp_reset_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2909

if (hubp && hubp->funcs->hubp_reset)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2910

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2953

struct hubp *hubp = params->hubp_vtg_sel_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2956

if (hubp && hubp->funcs->hubp_vtg_sel)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2957

hubp->funcs->hubp_vtg_sel(hubp, otg_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2962

struct hubp *hubp = params->hubp_setup2_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2967

if (hubp && hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2968

hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2973

struct hubp *hubp = params->hubp_setup_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2979

if (hubp && hubp->funcs->hubp_setup)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2980

hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2985

struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2988

if (hubp && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2989

hubp->funcs->set_unbounded_requesting(hubp, unbounded_req);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2994

struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2997

if (hubp && hubp->funcs->hubp_setup_interdependent2)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2998

hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3003

struct hubp *hubp = params->hubp_setup_interdependent_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3007

if (hubp && hubp->funcs->hubp_setup_interdependent)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3008

hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3076

struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3080

if (hubp && hubp->funcs->mem_program_viewport)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3081

hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3134

struct hubp *hubp = params->hubp_set_blank_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3137

if (hubp && hubp->funcs->set_blank)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3138

hubp->funcs->set_blank(hubp, blank);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3143

struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3145

if (hubp && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3146

hubp->funcs->phantom_hubp_post_enable(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3198

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3202

seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3348

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3353

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3518

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3524

seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3532

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3537

seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3544

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3549

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3556

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3561

seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3582

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3587

seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3712

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3716

seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3722

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3726

seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3754

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3761

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3770

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3774

seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3794

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3799

seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3806

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3813

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3822

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3830

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3840

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3845

seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3852

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3857

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3864

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3870

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3878

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3889

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3938

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3944

seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4018

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4022

seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

798

block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

861

block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

867

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

963

params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

964

params->set_flip_control_gsl_params.hubp,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2614

split_pipe->plane_res.hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3787

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3932

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5556

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

417

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

513

pipe_ctx->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

829

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

849

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

850

if (hubp == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

859

if (hubp->funcs->dmdata_set_attributes != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

861

hubp->funcs->dmdata_set_attributes(hubp, attr);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

76

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

77

pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc.h

2957

} hubp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1038

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1045

if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1054

payload->cursor_rect.x = hubp->cur_rect.x;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1055

payload->cursor_rect.y = hubp->cur_rect.y;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1057

payload->cursor_rect.width = hubp->cur_rect.w;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1058

payload->cursor_rect.height = hubp->cur_rect.h;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1060

payload->enable = hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1068

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1071

pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1072

pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1073

pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1074

pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1083

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1086

pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1087

pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1088

pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1089

pl_A->aHubp.size.raw = hubp->att.size.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1090

pl_A->aHubp.settings.raw = hubp->att.settings.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1138

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1148

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

436

fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

441

fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

856

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

858

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

135

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

136

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

138

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

145

hubp->inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

164

hubp->inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

514

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

515

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

517

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

520

hubp->funcs->hubp_clear_underflow(hubp);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

537

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1888

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

276

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

277

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

316

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

317

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

103

void hubp1_clear_underflow(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

105

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1093

void hubp1_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1095

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1099

hubp1_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

110

static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

112

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1167

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1170

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1175

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

118

void hubp1_vready_workaround(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1199

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1203

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1210

int cursor_height = (int)hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1211

int cursor_width = (int)hubp->curs_attr.width;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1215

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

122

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1224

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1273

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1299

void hubp1_clk_cntl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1301

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1307

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1309

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1314

bool hubp1_in_blank(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1317

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1323

void hubp1_soft_reset(struct hubp *hubp, bool reset)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1325

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1335

void hubp1_set_flip_int(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1337

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1350

static void hubp1_wait_pipe_read_start(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1352

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1359

void hubp1_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1361

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

142

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

146

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

164

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

169

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

204

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

208

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

237

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

240

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

350

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

354

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

41

void hubp1_set_blank(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

43

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

516

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

521

void hubp1_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

523

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

535

void hubp1_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

540

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

549

void hubp_reset(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

551

memset(&hubp->pos, 0, sizeof(hubp->pos));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

552

memset(&hubp->att, 0, sizeof(hubp->att));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

553

hubp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

557

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

566

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

567

hubp1_program_tiling(hubp, tiling_info, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

568

hubp1_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

569

hubp1_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

570

hubp1_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

574

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

577

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

608

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

612

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

65

hubp->mpcc_id = 0xf;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

66

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

696

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

70

static void hubp1_disconnect(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

705

hubp1_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

706

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

707

hubp1_vready_workaround(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

711

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

715

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

72

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

752

bool hubp1_is_flip_pending(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

755

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

758

if (hubp && hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

773

if (hubp &&

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

774

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

783

static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

786

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

81

static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

812

static void hubp1_set_vm_context0_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

815

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

83

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

848

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

852

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

889

void hubp1_read_state_common(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

891

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

90

static unsigned int hubp1_get_underflow_status(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

93

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

30

#define TO_DCN10_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

31

container_of(hubp, struct dcn10_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

853

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

861

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

871

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

876

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

880

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

884

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

890

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

895

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

899

void hubp1_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

903

void hubp_reset(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

906

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

910

bool hubp1_is_flip_pending(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

913

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

917

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

921

void hubp1_set_blank(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

923

void min_set_viewport(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

927

void hubp1_clk_cntl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

928

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

938

void hubp1_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

939

void hubp1_clear_underflow(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

943

void hubp1_vready_workaround(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

946

void hubp1_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

947

void hubp1_read_state_common(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

948

bool hubp1_in_blank(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

949

void hubp1_soft_reset(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

951

void hubp1_set_flip_int(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

953

void hubp1_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1001

int cursor_height = (int)hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1002

int cursor_width = (int)hubp->curs_attr.width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1006

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1015

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1063

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1064

bool cursor_not_programmed = hubp->att.SURFACE_ADDR == 0 && hubp->att.SURFACE_ADDR_HIGH == 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1067

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1069

if (!hubp->cursor_offload)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1073

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1088

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1089

hubp->pos.position.bits.x_pos = pos->x;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1090

hubp->pos.position.bits.y_pos = pos->y;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1091

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1092

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1093

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1106

hubp->cur_rect.x = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1107

hubp->cur_rect.y = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1108

hubp->cur_rect.w = param->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1109

hubp->cur_rect.h = param->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1111

hubp->cur_rect.x = src_x_offset + param->viewport.x;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1112

hubp->cur_rect.y = src_y_offset + param->viewport.y;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1116

void hubp2_clk_cntl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1118

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1124

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1126

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1131

void hubp2_clear_underflow(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1133

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1138

void hubp2_read_state_common(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1140

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1330

void hubp2_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1332

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1336

hubp2_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1366

static void hubp2_validate_dml_output(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1372

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

172

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

176

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

197

static void hubp2_program_requestor(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

200

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

230

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

240

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

241

hubp2_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

242

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

247

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

251

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

329

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

334

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

377

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

381

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

409

void hubp2_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

411

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

423

void hubp2_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

428

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

438

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

441

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

47

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

50

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

551

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

560

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

562

hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

564

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

565

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

566

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

606

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

609

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

614

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

616

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

639

hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

640

hubp->att.SURFACE_ADDR = attr->address.low_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

641

hubp->att.size.bits.width = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

642

hubp->att.size.bits.height = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

643

hubp->att.cur_ctl.bits.mode = attr->color_format;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

645

hubp->cur_rect.w = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

646

hubp->cur_rect.h = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

648

hubp->att.cur_ctl.bits.pitch = hw_pitch;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

649

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

650

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

651

hubp->att.settings.bits.dst_y_offset = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

652

hubp->att.settings.bits.chunk_hdl_adjust = 3;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

656

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

659

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

696

hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

707

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

712

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

719

bool hubp2_dmdata_status_done(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

722

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

729

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

733

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

82

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

86

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

886

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

892

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

895

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

908

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

910

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

918

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

920

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

925

bool hubp2_is_flip_pending(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

928

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

931

if (hubp && hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

946

if (hubp &&

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

947

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

953

void hubp2_set_blank(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

955

hubp2_set_blank_regs(hubp, blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

958

hubp->mpcc_id = 0xf;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

959

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

963

void hubp2_set_blank_regs(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

965

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

990

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

994

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

304

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

31

#define TO_DCN20_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

32

container_of(hubp, struct dcn20_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

320

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

324

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

328

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

331

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

339

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

343

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

347

bool hubp2_dmdata_status_done(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

350

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

354

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

356

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

359

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

364

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

368

void hubp2_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

372

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

378

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

383

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

387

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

396

bool hubp2_is_flip_pending(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

398

void hubp2_set_blank(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

399

void hubp2_set_blank_regs(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

402

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

406

void hubp2_clk_cntl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

408

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

410

void hubp2_clear_underflow(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

412

void hubp2_read_state_common(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

414

void hubp2_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

416

void hubp2_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

107

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

108

hubp201_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

109

hubp201_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

43

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

52

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

53

hubp1_program_tiling(hubp, tiling_info, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

54

hubp1_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

55

hubp1_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

59

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

63

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

66

static void hubp201_program_requestor(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

69

struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

97

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

117

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

32

#define TO_DCN201_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

33

container_of(hubp, struct dcn201_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

128

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

132

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

134

apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

138

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

141

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

170

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

180

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

181

hubp21_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

182

hubp21_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

187

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

191

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

228

static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

231

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

251

static void hubp21_validate_dml_output(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

257

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

594

static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

596

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

667

static void dmcub_PLAT_54186_wa(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

670

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

686

cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

692

dc_wake_and_execute_dmub_cmd(hubp->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

697

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

78

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

794

if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

795

dmcub_PLAT_54186_wa(hubp, &flip_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

797

program_surface_flip_and_addr(hubp, &flip_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

799

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

804

static void hubp21_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

809

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

81

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

813

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

106

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

123

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

127

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

132

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

32

#define TO_DCN21_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

33

container_of(hubp, struct dcn21_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

314

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

337

void hubp3_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

339

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

353

void hubp3_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

357

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

366

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

369

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

381

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

384

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

412

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

421

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

423

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

425

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

426

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

427

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

431

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

435

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

437

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

442

void hubp3_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

444

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

448

hubp2_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

45

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

479

void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

48

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

481

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

600

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

609

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

610

hubp21_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

611

hubp3_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

614

void hubp3_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

619

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

625

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

69

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

73

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

257

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

261

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

266

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

276

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

287

void hubp3_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

290

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

294

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

297

void hubp3_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

299

void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

301

void hubp3_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

303

void hubp3_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

305

uint32_t hubp3_get_current_read_line(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

307

uint32_t hubp3_get_underflow_status(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

42

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

50

void hubp31_soft_reset(struct hubp *hubp, bool reset)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

57

static void hubp31_program_extended_blank(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

60

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

66

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

68

hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

71

uint32_t hubp31_get_det_config_error(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

74

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

244

void hubp31_soft_reset(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

246

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

249

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

251

uint32_t hubp31_get_det_config_error(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

109

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

112

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

141

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

143

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

167

hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

168

hubp->att.SURFACE_ADDR = attr->address.low_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

169

hubp->att.size.bits.width = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

170

hubp->att.size.bits.height = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

171

hubp->att.cur_ctl.bits.mode = attr->color_format;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

173

hubp->cur_rect.w = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

174

hubp->cur_rect.h = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

176

hubp->att.cur_ctl.bits.pitch = hw_pitch;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

177

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

178

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

179

hubp->att.settings.bits.dst_y_offset = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

180

hubp->att.settings.bits.chunk_hdl_adjust = 3;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

181

hubp->use_mall_for_cursor = use_mall_for_cursor;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

183

void hubp32_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

185

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

42

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

50

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

59

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

68

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

70

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

86

void hubp32_phantom_hubp_post_enable(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

89

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

47

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

49

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

51

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

53

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

55

void hubp32_phantom_hubp_post_enable(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

57

void hubp32_cursor_set_attributes(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

60

void hubp32_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

173

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

182

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

184

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

186

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

187

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

188

hubp35_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

41

void hubp35_set_fgcg(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

43

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

48

void hubp35_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

50

hubp3_init(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

58

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

59

void hubp35_set_fgcg(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

62

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

66

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

75

void hubp35_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

101

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1014

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1016

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

109

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

111

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

116

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

118

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

123

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

125

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

131

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

134

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

167

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

169

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

179

void hubp401_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

181

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

184

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

198

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

221

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

224

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

249

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

253

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

347

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

355

hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

356

hubp401_program_requestor(hubp, &pipe_regs->rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

357

hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

361

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

364

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

410

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

414

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

43

void hubp401_program_3dlut_fl_addr(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

46

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

52

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

54

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

555

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

560

void hubp401_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

562

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

572

void hubp401_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

575

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

59

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

596

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

601

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

630

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

639

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

641

hubp401_dcc_control(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

643

hubp401_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

644

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

645

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

649

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

653

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

66

int hubp401_get_3dlut_fl_done(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

68

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

691

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

694

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

710

void hubp401_set_flip_int(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

712

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

720

bool hubp401_in_blank(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

722

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

731

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

735

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

743

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

75

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

760

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

768

(1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

77

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

780

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

782

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

784

if (!hubp->cursor_offload)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

789

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

802

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

803

hubp->pos.position.bits.x_pos = pos->x;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

804

hubp->pos.position.bits.y_pos = pos->y;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

805

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

806

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

807

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

818

hubp->cur_rect.x = rec_x_offset + param->recout.x;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

819

hubp->cur_rect.y = rec_y_offset + param->recout.y;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

82

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

822

void hubp401_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

824

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

84

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

89

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

91

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

96

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

259

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

262

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

268

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

272

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

276

void hubp401_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

285

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

291

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

300

void hubp401_set_viewport(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

304

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

306

void hubp401_set_flip_int(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

308

bool hubp401_in_blank(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

311

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

315

void hubp401_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

325

void hubp401_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

327

int hubp401_get_3dlut_fl_done(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

329

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

331

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

333

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

338

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

340

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

342

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

344

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

346

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

348

void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

350

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

352

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

355

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

358

void hubp401_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

360

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

365

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

369

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1037

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1042

hubp->funcs->set_blank(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1057

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1080

hubp->funcs->set_hubp_blank_en(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1352

struct hubp *hubp ;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1371

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1373

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1374

hubp->funcs->set_hubp_blank_en(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1384

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1386

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1387

hubp->funcs->hubp_disable_control(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1394

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1396

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1397

hubp->funcs->hubp_disable_control(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1406

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1408

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1409

hubp->funcs->set_hubp_blank_en(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1446

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1468

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1469

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1490

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1503

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1505

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1511

"Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1524

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1526

int opp_id = hubp->opp_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1530

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1539

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1544

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1559

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1614

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1620

if (hubbub && hubp) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1622

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1624

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1642

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1659

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1667

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1673

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1676

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1677

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1678

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1693

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2018

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2019

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2717

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2719

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2726

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2727

hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2744

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2755

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2765

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2931

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2956

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2962

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2983

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

304

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

305

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3052

hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3053

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3058

hubp->funcs->hubp_setup_interdependent(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3059

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

307

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3086

hubp->funcs->mem_program_viewport(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3087

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

311

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3123

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3124

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3134

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3139

hubp->funcs->set_blank(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3546

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3575

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3581

hubp->funcs->set_blank(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3610

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3611

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3649

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3866

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3874

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3875

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4114

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4115

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4117

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4138

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4140

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4144

if (clear_tiling && hubp->funcs->hubp_clear_tiling)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4145

hubp->funcs->hubp_clear_tiling(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4148

hubp->funcs->hubp_program_surface_flip_and_addr(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

816

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

824

if (hubp->funcs->hubp_get_underflow_status(hubp)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

825

hubp->funcs->hubp_clear_underflow(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

200

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1017

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1286

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1293

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1306

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1309

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1362

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1368

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1369

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1411

if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1670

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1689

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1691

if (hubp->funcs->hubp_setup2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1693

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1698

hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1699

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1707

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1708

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1711

if (hubp->funcs->hubp_setup_interdependent2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1712

hubp->funcs->hubp_setup_interdependent2(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1713

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1716

hubp->funcs->hubp_setup_interdependent(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1717

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1775

hubp->funcs->mem_program_viewport(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1776

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1782

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1783

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1814

hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1831

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1832

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1840

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1859

hubp->funcs->set_blank(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1861

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

hubp->funcs->phantom_hubp_post_enable(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1953

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1957

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2125

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2128

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2187

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2190

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2263

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2267

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2463

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2466

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2514

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2515

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2592

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2594

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2596

return hubp->funcs->dmdata_status_done(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2632

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2646

hubp->funcs->dmdata_set_attributes(hubp, &attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2729

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2731

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2732

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2923

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2970

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2996

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3001

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3002

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

302

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

304

pipe_ctx->plane_res.hubp, flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3096

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3109

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3116

hubp->inst, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3186

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3192

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3195

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3196

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3197

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3200

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3227

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

382

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

383

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

384

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

698

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

709

if (hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

710

hubp->funcs->hubp_update_mall_sel(hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

714

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

718

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

722

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

742

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

994

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

152

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

153

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

310

struct hubp *hubp = res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

320

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

321

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

324

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

349

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

383

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

418

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

419

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

427

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

484

dpp_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

524

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

525

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

566

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

574

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

591

hubp->funcs->dmdata_set_attributes(hubp, &attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1249

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1257

if (hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1258

if (hubp->funcs->hubp_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1259

hubp->funcs->hubp_read_reg_state(hubp, out_data->hubp_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

260

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

362

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

398

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

902

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

909

hubp->inst, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

639

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

642

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

450

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

487

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

573

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

617

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

625

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

626

hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

627

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

628

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

637

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

662

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

663

hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

664

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

665

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

682

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

684

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

685

int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

687

switch (hubp->curs_attr.color_format) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

708

hubp->funcs->hubp_update_mall_sel(hubp, 1, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

711

hubp->funcs->hubp_update_mall_sel(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

742

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

744

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

751

hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1043

if (j == PG_HUBP && new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1044

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1069

cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1070

new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1071

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1129

if (new_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1130

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1636

if (pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1637

pipe->plane_res.hubp->cursor_offload = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1650

if (pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1651

pipe->plane_res.hubp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1676

const struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1681

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1690

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1691

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1692

p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1693

p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1694

p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1695

p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1696

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1697

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1698

p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1699

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1700

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1701

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1702

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1703

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1714

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1715

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

666

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

672

if (hubbub && hubp) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

674

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

676

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

694

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

711

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

719

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

725

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

728

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

729

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

730

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

745

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

822

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

825

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

842

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

849

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

850

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

858

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

875

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

879

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

902

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

951

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

952

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

954

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

955

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

967

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1084

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1179

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1180

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1200

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1201

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1223

if (recout_x_pos + (int)hubp->curs_attr.width <= 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1226

if (recout_y_pos + (int)hubp->curs_attr.height <= 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1232

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1233

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1480

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1483

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1838

dpp_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1840

hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1843

if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1844

hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1933

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1934

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1942

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1943

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2172

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2175

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2316

pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2321

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2496

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2499

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2558

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2561

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2599

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2603

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2742

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2743

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2744

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2952

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2970

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2972

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2980

"Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2990

const struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2995

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3004

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3005

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3006

p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3007

p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3008

p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3009

p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3010

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3011

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3012

p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3013

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3014

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3015

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3016

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3017

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3035

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3036

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3037

p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3044

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3063

hwss_add_hubp_pg_control(seq_state, hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3066

hwss_add_hubp_reset(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3075

DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3087

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3115

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3116

hwss_add_hubp_disconnect(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3434

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3448

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3449

hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3452

hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3455

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3463

pipe_ctx->plane_res.hubp, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3532

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3552

hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3559

if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3560

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3563

if (pipe_ctx->plane_res.hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3564

hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3571

if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3572

hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3580

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3581

hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3591

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3598

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3611

hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3614

if (hubp->funcs->hubp_setup2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3615

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3617

} else if (hubp->funcs->hubp_setup) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3618

hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3624

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3625

hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3629

if (hubp->funcs->hubp_setup_interdependent2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3630

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3631

else if (hubp->funcs->hubp_setup_interdependent)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3632

hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3682

hwss_add_hubp_mem_program_viewport(seq_state, hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3688

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3689

hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3720

pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3738

hwss_add_hubp_program_surface_config(seq_state, hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3742

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3762

hwss_add_hubp_set_blank(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3765

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3766

hwss_add_phantom_hubp_post_enable(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3773

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3781

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3818

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3845

hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3851

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3852

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3855

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

388

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3883

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3890

if (hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3891

hwss_add_hubp_set_blank(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3941

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3943

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3944

int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3946

switch (hubp->curs_attr.color_format) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3967

hwss_add_hubp_update_mall_sel(seq_state, hubp, 1, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3974

hwss_add_hubp_update_mall_sel(seq_state, hubp, mall_sel, cache_cursor);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3982

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3984

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3986

hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4008

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4019

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4020

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4021

hwss_add_hubp_set_blank_en(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4033

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4034

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4035

hwss_add_hubp_disable_control(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4044

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4045

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4046

hwss_add_hubp_disable_control(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4058

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4059

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4060

hwss_add_hubp_set_blank_en(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

419

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

420

int mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

481

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

482

hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

516

if (hubp->funcs->hubp_program_3dlut_fl_addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

517

hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

540

if (hubp->funcs->hubp_program_3dlut_fl_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

541

hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

543

if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

544

hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

557

if (hubp->funcs->hubp_program_3dlut_fl_format)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

558

hubp->funcs->hubp_program_3dlut_fl_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

559

if (hubp->funcs->hubp_update_3dlut_fl_bias_scale &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

565

hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

581

if (hubp->funcs->hubp_program_3dlut_fl_crossbar)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

582

hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

594

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

596

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

597

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

612

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

614

if (hubp->funcs->hubp_enable_3dlut_fl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

615

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

623

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

676

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

119

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

122

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1608

struct hubp *hubp, bool flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

162

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1653

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1692

struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1718

struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

173

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1736

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1815

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1820

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1824

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1828

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

183

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1837

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1882

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1886

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1889

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1899

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1905

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1913

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1917

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1923

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1930

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1934

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1938

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1942

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1982

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2010

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

430

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

444

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

520

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

526

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

531

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

536

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

547

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

552

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

556

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

564

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

590

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

637

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

642

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

649

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

657

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

662

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

667

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

689

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

69

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

695

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

728

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

733

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

127

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

130

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

67

struct hubp;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

246

struct hubp *hubps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

379

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

160

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

167

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

173

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

178

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

181

void (*dcc_control)(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

184

void (*hubp_reset)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

187

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

192

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

197

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

203

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

207

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

211

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

220

bool (*hubp_is_flip_pending)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

222

void (*set_blank)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

223

void (*set_blank_regs)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

224

void (*phantom_hubp_post_enable)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

225

void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

228

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

232

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

236

void (*hubp_disconnect)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

238

void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

239

void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

240

void (*hubp_read_state)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

241

void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

242

void (*hubp_clear_underflow)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

243

void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

244

unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

245

void (*hubp_init)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

248

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

252

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

255

bool (*dmdata_status_done)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

257

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

261

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

264

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

268

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

274

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

276

bool (*hubp_in_blank)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

277

void (*hubp_soft_reset)(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

279

void (*hubp_set_flip_int)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

281

void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

282

void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

283

void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

284

void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

285

void (*hubp_surface_update_lock)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

288

void (*program_extended_blank)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

291

void (*hubp_wait_pipe_read_start)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

292

void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

293

void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

294

void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

296

void (*hubp_program_3dlut_fl_format)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

298

void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

300

void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

301

void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

302

void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

303

void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

304

void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

305

void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

309

int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

310

void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

311

void (*hubp_clear_tiling)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

312

uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

313

uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1013

static struct hubp *dcn10_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1136

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1231

struct hubp *dcn20_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1526

next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1582

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2199

sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

105

struct hubp *dcn20_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1015

static struct hubp *dcn201_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1055

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1005

static struct hubp *dcn21_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1231

static struct hubp *dcn30_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1567

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1193

static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

535

static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

516

static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1527

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1585

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1528

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1520

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2807

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2866

free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2898

free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

920

static struct hubp *dcn32_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

44

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

45

uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

914

static struct hubp *dcn321_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1603

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1583

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1590

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

916

static struct hubp *dcn401_hubp_create(