flush_icache_range
void flush_icache_range(unsigned long kstart, unsigned long kend);
flush_icache_range(entry->code, entry->code + JUMP_LABEL_NOP_SIZE);
flush_icache_range(address, address + BREAK_INSTR_SIZE);
flush_icache_range(single_step_data.address[i],
flush_icache_range((unsigned long)p->ainsn.t1_addr,
flush_icache_range((unsigned long)p->ainsn.t2_addr,
flush_icache_range((unsigned long)p->addr,
flush_icache_range((unsigned long)p->ainsn.t1_addr,
flush_icache_range((unsigned long)p->ainsn.t2_addr,
flush_icache_range((unsigned long)p->addr,
flush_icache_range((unsigned long)p->addr,
flush_icache_range((unsigned long)p->ainsn.t1_addr,
flush_icache_range((unsigned long)p->ainsn.t2_addr,
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range((unsigned long)ctx->bpf_header,
flush_icache_range((unsigned long)(dest_buf), \
flush_icache_range((unsigned long)base + offset,
flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length);
flush_icache_range((uintptr_t)(addr),
flush_icache_range(fn_addr, fn_addr + 8);
flush_icache_range(fn_addr, fn_addr + 8);
flush_icache_range((unsigned long)rc,
flush_icache_range(ptr, ptr + PAGE_SIZE);
flush_icache_range(start, end);
flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
flush_icache_range((unsigned long)TEMP_IRAM_AREA,
flush_icache_range(to, to + len);
flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
flush_icache_range((unsigned long)(addr), \
flush_icache_range((unsigned long)code,
#define flush_icache_range flush_icache_range
flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);
flush_icache_range((unsigned long)start, (unsigned long)end);
flush_icache_range(hook_pos, hook_pos + MCOUNT_INSN_SIZE);
flush_icache_range(addr, addr + 4);
extern void flush_icache_range(unsigned long start, unsigned long end);
#define flush_icache_range flush_icache_range
flush_icache_range((unsigned long) dst,
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range((unsigned long)p->addr, \
flush_icache_range((unsigned long)insn, (unsigned long)(insn + nr));
flush_icache_range((unsigned long)tp,
flush_icache_range((unsigned long)copy->dst, (unsigned long)copy->dst + copy->len);
flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
flush_icache_range(stepped_address, stepped_address + BREAK_INSTR_SIZE);
flush_icache_range((unsigned long)dst, (unsigned long)dst + len);
flush_icache_range((unsigned long)addr, (unsigned long)addr + kvm_exception_size + kvm_enter_guest_size);
flush_icache_range((unsigned long)start, (unsigned long)end);
extern void flush_icache_range(unsigned long address, unsigned long endaddr);
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range(regs->r16, regs->r16 + 0x4);
flush_icache_range((u32)parent, (u32)parent + 4);
flush_icache_range(addr, addr + 4);
extern void (*flush_icache_range)(unsigned long start, unsigned long end);
flush_icache_range((unsigned long)p->addr, \
flush_icache_range(ip, ip + 8);
flush_icache_range(ip, ip + 8);
flush_icache_range(ip, ip + 8);
flush_icache_range((unsigned long)insn_p,
flush_icache_range((unsigned long)gp,
flush_icache_range(kstart, kstart + len);
flush_icache_range((unsigned long)v->load_addr,
flush_icache_range((unsigned long)gebase,
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
flush_icache_range = octeon_flush_icache_range;
flush_icache_range = r3k_flush_icache_range;
flush_icache_range = r4k_flush_icache_range;
flush_icache_range = (void *)b5k_instruction_hazard;
void (*flush_icache_range)(unsigned long start, unsigned long end);
EXPORT_SYMBOL_GPL(flush_icache_range);
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
flush_icache_range((unsigned long)header,
extern void flush_icache_range(unsigned long start, unsigned long end);
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range(start, start + folio_size(folio));
flush_icache_range(vpage, vpage + KUSER_SIZE);
flush_icache_range((unsigned long)&(p)->ainsn.insn[0], \
flush_icache_range(init_begin, init_end);
flush_icache_range((unsigned long)start, (unsigned long)end);
void flush_icache_range(unsigned long start, unsigned long stop);
#define flush_icache_range flush_icache_range
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtmsrd_len * 4);
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtmsr_len * 4);
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrtee_len * 4);
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrteei_0_len * 4);
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtsrin_len * 4);
flush_icache_range((ulong)inst, (ulong)inst + 4);
flush_icache_range((unsigned long)buff, (unsigned long)(&buff[TMPL_END_IDX]));
flush_icache_range((unsigned long) &tramp[0],
flush_icache_range(reboot_code_buffer,
flush_icache_range((unsigned long)__va(ranges[i].mem),
flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
flush_icache_range(start, start + len);
flush_icache_range((unsigned long)maddr, (unsigned long)maddr + len);
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range(kernstart_virt_addr, kernstart_virt_addr + kernel_sz);
flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
#define flush_icache_range flush_icache_range
flush_icache_range(va, va + 4 * insns);
flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
flush_icache_range(stepped_address,
flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);
flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);
flush_icache_range(start, start + len);
flush_icache_range(addr, addr + sizeof(frame->sigreturn_code));
flush_icache_range((unsigned long)start, (unsigned long)end);
flush_icache_range((unsigned long)chan->sar, chan->count);
extern void flush_icache_range(unsigned long start, unsigned long end);
#define flush_icache_user_range flush_icache_range
flush_icache_range(ip, ip + MCOUNT_INSN_SIZE);
flush_icache_range(addr, addr + instruction_size(op));
flush_icache_range((long)addr, (long)addr +
flush_icache_range(stepped_address, stepped_address + 2);
flush_icache_range((unsigned long)p->addr,
flush_icache_range((unsigned long)p->addr,
flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
flush_icache_range((unsigned long)&stack_start,
flush_icache_range(addr, addr+len);
EXPORT_SYMBOL(flush_icache_range);
void flush_icache_range(unsigned long start, unsigned long end);
EXPORT_SYMBOL(flush_icache_range);
void flush_icache_range(unsigned long start, unsigned long end);
#define flush_icache_range flush_icache_range
#define flush_icache_user_range flush_icache_range
EXPORT_SYMBOL(flush_icache_range);
flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
flush_icache_range((unsigned long)ptr, (unsigned long)(ptr + size));
flush_icache_range((unsigned long)dst,
flush_icache_range(start, end);
#ifndef flush_icache_range
#define flush_icache_user_range flush_icache_range
flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
flush_icache_range(addr, addr + length);
flush_icache_range((unsigned long)mod_mem->base,
flush_icache_range((unsigned long)d->unc,
flush_icache_range((unsigned long)page_address(page),