arch/alpha/include/asm/core_titan.h

75

titan_64 dsc;

arch/alpha/include/asm/core_tsunami.h

68

tsunami_64 dsc;

arch/alpha/kernel/core_titan.c

382

printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);

arch/alpha/kernel/core_tsunami.c

406

printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);

arch/mips/include/asm/octeon/cvmx-pciercx-defs.h

361

__BITFIELD_FIELD(uint32_t dsc:1,

arch/mips/mm/cerr-sb1.c

466

struct dc_state *dsc = dc_states;

arch/mips/mm/cerr-sb1.c

467

while (dsc->val != 0xff) {

arch/mips/mm/cerr-sb1.c

468

if (dsc->val == state)

arch/mips/mm/cerr-sb1.c

470

dsc++;

arch/mips/mm/cerr-sb1.c

472

return dsc->name;

arch/mips/pci/pcie-octeon.c

1320

pciercx_cfg515.s.dsc = 1;

drivers/acpi/scan.c

1092

unsigned long long dsc = ACPI_STATE_D0;

drivers/acpi/scan.c

1114

acpi_evaluate_integer(device->handle, "_DSC", NULL, &dsc);

drivers/acpi/scan.c

1115

device->power.state_for_enumeration = dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7496

!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1570

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1591

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1592

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1593

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1756

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1777

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1778

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1779

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1940

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1961

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1962

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1963

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2120

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2141

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2142

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2143

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2295

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2316

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2317

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2318

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2349

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2370

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2371

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2372

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2418

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2439

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2440

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2441

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2487

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2508

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2509

if (dsc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2510

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1325

panel_config->dsc.disable_dsc_edp = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1326

panel_config->dsc.force_dsc_edp_policy = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1337

link->panel_config.dsc.disable_dsc_edp = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

1930

struct display_stream_compressor *dsc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1935

dsc = dc->res_pool->dscs[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc.c

1938

if (!dsc || !dsc->funcs->dsc_read_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1944

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

3966

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3978

if (!stream->timing.flags.DSC || !dsc)

drivers/gpu/drm/amd/display/dc/core/dc.c

4010

hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst,

drivers/gpu/drm/amd/display/dc/core/dc.c

4014

hwss_add_dsc_set_config(seq_state, dsc, dsc_cfg, dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/core/dc.c

4018

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc.c

4048

if (dsc->funcs->dsc_get_packed_pps) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4049

dsc->funcs->dsc_get_packed_pps(dsc, &dsc_pps_cfg, dsc_packed_pps);

drivers/gpu/drm/amd/display/dc/core/dc.c

7560

state->dsc[i].dsc_clock_enable = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7564

state->dsc[i].dsc_num_slices_h = dsc_cfg->num_slices_h;

drivers/gpu/drm/amd/display/dc/core/dc.c

7565

state->dsc[i].dsc_num_slices_v = dsc_cfg->num_slices_v;

drivers/gpu/drm/amd/display/dc/core/dc.c

7566

state->dsc[i].dsc_bits_per_pixel = dsc_cfg->bits_per_pixel;

drivers/gpu/drm/amd/display/dc/core/dc.c

7570

state->dsc[i].dscrm_dsc_forward_enable = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7571

state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7573

state->dsc[i].dscrm_dsc_forward_enable = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7574

state->dsc[i].dscrm_dsc_opp_pipe_source = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7578

memset(&state->dsc[i], 0, sizeof(state->dsc[i]));

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2649

struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2653

if (dsc && dsc->funcs->dsc_set_config)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2654

dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2659

struct display_stream_compressor *dsc = params->dsc_enable_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2662

if (dsc && dsc->funcs->dsc_enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2663

dsc->funcs->dsc_enable(dsc, opp_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2690

struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2692

if (dsc && dsc->funcs->dsc_disconnect)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2693

dsc->funcs->dsc_disconnect(dsc);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2698

struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2701

if (dsc && dsc->funcs->dsc_read_state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2702

dsc->funcs->dsc_read_state(dsc, dsc_state);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2712

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2715

if (!dsc || !enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2735

if (dsc->funcs->dsc_set_config)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2736

dsc->funcs->dsc_set_config(dsc, &dsc_cfg,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2743

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2745

if (dsc && dsc->funcs->dsc_enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2746

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3268

struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3275

if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3276

dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3281

struct display_stream_compressor *dsc = params->dsc_disable_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3288

if (dsc && dsc->funcs->dsc_disable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3289

dsc->funcs->dsc_disable(dsc);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3844

struct display_stream_compressor *dsc = params->dsc_set_config_simple_params.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3848

if (dsc && dsc->funcs && dsc->funcs->dsc_set_config)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3849

dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3933

struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3937

seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4349

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4354

seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4361

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4366

seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4943

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4949

seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5305

if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5872

sec_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5880

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5882

ASSERT(sec_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5883

if (sec_pipe->stream_res.dsc == NULL)

drivers/gpu/drm/amd/display/dc/dc.h

3274

} dsc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

868

bool dsc: 1;

drivers/gpu/drm/amd/display/dc/dc.h

896

bool dsc : 1; /* Display stream compression */

drivers/gpu/drm/amd/display/dc/dc_dsc.h

106

void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

108

void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

80

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

90

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dc_types.h

1344

} dsc;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

360

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

404

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

142

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2093

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2101

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2109

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2117

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

399

!link->panel_config.dsc.disable_dsc_edp &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

184

!link->panel_config.dsc.disable_dsc_edp &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1863

sec_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1887

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1888

ASSERT(sec_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1889

if (sec_pipe->stream_res.dsc == NULL)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1976

if (pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1977

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

160

timing->dsc.enable = dml2_dsc_enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

161

timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

162

timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

164

timing->dsc.enable = dml2_dsc_disable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h

280

} dsc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

162

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

178

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

179

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

184

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8435

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8436

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8438

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8439

mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8517

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8555

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8565

DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8742

if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

341

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

357

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

358

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

364

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

125

if (pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

126

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

141

void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1054

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1064

if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1067

dc = dsc->ctx->dc;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1075

dsc->funcs->dsc_get_single_enc_caps(&single_dsc_enc_caps, max_dscclk_khz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1104

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1112

if (dsc && dsc->ctx->dc) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1113

if (dsc->ctx->dc->clk_mgr &&

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1114

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1116

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1136

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1142

if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1146

if (dsc->funcs->dsc_get_enc_caps) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1147

dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1149

build_dsc_enc_caps(dsc, dsc_enc_caps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1993

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2004

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2006

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

316

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

337

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

37

dsc->ctx->logger

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

927

const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

947

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

949

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

965

void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

970

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

984

void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

143

void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

145

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

159

void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

161

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

167

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

170

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

180

void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

191

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

195

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

197

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

198

dsc_config_log(dsc, dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

202

dsc_log_pps(dsc, &dsc20->reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

203

dsc_write_to_registers(dsc, &dsc20->reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

207

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

217

dsc_config_log(dsc, dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

222

dsc_log_pps(dsc, &dsc_reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

228

void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

230

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

235

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

240

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

253

void dsc2_disable(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

255

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

258

DC_LOG_DSC("disable DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

262

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

272

void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

274

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

279

void dsc2_disconnect(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

281

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

283

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

290

void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

33

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

587

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

59

dsc->ctx->logger

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

590

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

63

void dsc2_construct(struct dcn20_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

70

dsc->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

71

dsc->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

72

dsc->base.funcs = &dcn20_dsc_funcs;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

74

dsc->dsc_regs = dsc_regs;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

75

dsc->dsc_shift = dsc_shift;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

76

dsc->dsc_mask = dsc_mask;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

78

dsc->max_image_width = 5184;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

31

#define TO_DCN20_DSC(dsc)\

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

32

container_of(dsc, struct dcn20_dsc, base)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

572

void dsc_config_log(struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

575

void dsc_log_pps(struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

594

void dsc2_construct(struct dcn20_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

604

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

608

void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

609

void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

610

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

611

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

613

void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

614

void dsc2_disable(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

615

void dsc2_disconnect(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

616

void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

30

static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

59

dsc->ctx->logger

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

61

void dsc35_construct(struct dcn20_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

68

dsc->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

69

dsc->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

70

dsc->base.funcs = &dcn35_dsc_funcs;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

72

dsc->dsc_regs = dsc_regs;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

73

dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

74

dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

76

dsc->max_image_width = 5184;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

79

static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

81

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

86

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

99

DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

50

void dsc35_construct(struct dcn20_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

118

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

12

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

121

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

130

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

134

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

136

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

137

dsc_config_log(dsc, dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

141

dsc_log_pps(dsc, &dsc401->reg_vals.pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

142

dsc_write_to_registers(dsc, &dsc401->reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

145

void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

147

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

152

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

157

DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

170

void dsc401_disable(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

172

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

175

DC_LOG_DSC("disable DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

179

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

189

void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

191

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

196

void dsc401_disconnect(struct display_stream_compressor *dsc)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

198

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

200

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

206

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

209

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

43

dsc->ctx->logger

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

48

void dsc401_construct(struct dcn401_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

55

dsc->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

56

dsc->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

57

dsc->base.funcs = &dcn401_dsc_funcs;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

59

dsc->dsc_regs = dsc_regs;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

60

dsc->dsc_shift = dsc_shift;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

61

dsc->dsc_mask = dsc_mask;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

63

dsc->max_image_width = 5184;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

96

void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

98

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

13

#define TO_DCN401_DSC(dsc)\

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

14

container_of(dsc, struct dcn401_dsc, base)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

328

void dsc401_construct(struct dcn401_dsc *dsc,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

337

void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

338

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

339

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

341

void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

342

void dsc401_disable(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

343

void dsc401_disconnect(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

344

void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

116

void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

117

void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

118

bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

119

void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

121

bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

123

void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

124

void (*dsc_disable)(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

125

void (*dsc_disconnect)(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

126

void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

128

void (*set_fgcg)(struct display_stream_compressor *dsc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1956

struct display_stream_compressor *dsc = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1970

dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1971

dsc->funcs->dsc_read_state(dsc, &s);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1989

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1990

dsc->funcs->dsc_disable(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1994

pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

693

struct display_stream_compressor *dsc = pool->dscs[j];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

696

dsc->funcs->dsc_read_state(dsc, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

698

dsc->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2213

struct display_stream_compressor *dsc = opp_head->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2222

if (dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2226

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2235

dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2236

dsc->funcs->dsc_disable(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2238

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2617

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2622

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2632

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2635

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2637

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1305

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1322

if (dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1323

if (dsc->funcs->dsc_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1324

dsc->funcs->dsc_read_reg_state(dsc, out_data->dsc_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

293

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

114

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

116

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

140

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

142

ASSERT(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

143

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

211

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

218

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

219

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

221

dsc->funcs->dsc_disconnect(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

235

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

74

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

79

ASSERT(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

89

if (!dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

94

if (dsc->funcs->dsc_read_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

95

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1028

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1046

ASSERT(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1056

if (!dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1061

if (dsc->funcs->dsc_read_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1062

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1082

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1083

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1084

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1086

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1110

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1112

ASSERT(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1113

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1175

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1182

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1183

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1186

dsc->funcs->dsc_disconnect(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1547

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1548

bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1552

hws->funcs.dsc_pg_control(hws, dsc->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1556

hws->funcs.dsc_pg_control(hws, dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1003

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1091

if (j == PG_DSC && new_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1092

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1123

cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1124

new_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1125

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1170

if (new_pipe->stream_res.dsc && !new_pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1171

update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1172

update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1173

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1177

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

331

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

338

ASSERT(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

348

if (!dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

353

if (dsc->funcs->dsc_read_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

354

dsc->funcs->dsc_read_state(dsc, &dsc_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

371

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

372

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

374

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

398

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

400

ASSERT(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

401

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

473

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

480

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

481

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

483

dsc->funcs->dsc_disconnect(dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

995

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

996

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

998

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

999

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1637

if (otg_master->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1640

if (old_otg_master && old_otg_master->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1644

if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1645

old_pipe->stream_res.dsc->funcs->dsc_disconnect(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1646

old_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1717

if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1734

otg_master->stream_res.dsc->inst, num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1746

if (!odm_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1752

odm_pipe->stream_res.dsc->inst, num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1766

} else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1770

hwss_add_dsc_disconnect(seq_state, otg_master->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1774

if (old_otg_master && old_otg_master->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1780

if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1782

hwss_add_dsc_disconnect(seq_state, old_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3589

struct display_stream_compressor *dsc = opp_head->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3598

if (dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3602

hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3611

hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3614

hwss_add_dsc_disable(seq_state, dsc, is_ungated);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3618

hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1014

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1015

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1017

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1018

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1138

if (j == PG_DSC && new_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1139

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1170

cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1171

new_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1172

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2060

struct display_stream_compressor *dsc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2177

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2181

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2412

struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

255

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

261

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

272

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

276

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

643

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

648

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

830

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

358

struct display_stream_compressor *dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

664

static void dsc_optc_config_log(struct display_stream_compressor *dsc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

671

DC_LOGGER_INIT(dsc->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

721

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

738

DC_LOGGER_INIT(dsc->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

761

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

762

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

763

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

765

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

781

dsc_optc_config_log(dsc, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

795

dsc_optc_config_log(dsc, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

802

dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

809

dsc_optc_config_log(dsc, &dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

843

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

865

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

867

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

883

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

889

if (!dsc)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

892

DC_LOGGER_INIT(dsc->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

910

dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

958

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

963

if (!dsc)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

982

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

986

if (!dsc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1002

if (link->panel_config.dsc.force_dsc_edp_policy) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

371

|| link->panel_config.dsc.disable_dsc_edp

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

850

policy = link->panel_config.dsc.force_dsc_edp_policy;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1093

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1096

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1101

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1102

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1105

void dcn20_dsc_destroy(struct display_stream_compressor **dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1107

kfree(container_of(*dsc, struct dcn20_dsc, base));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1108

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1364

struct display_stream_compressor **dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1369

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1371

ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1372

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1376

*dsc = pool->dscs[pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1383

*dsc = dsc_old;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1391

*dsc = pool->dscs[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1399

struct display_stream_compressor **dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1404

if (pool->dscs[i] == *dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1406

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1430

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1433

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1436

if (!pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1458

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1459

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1533

next_odm_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1561

dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1562

ASSERT(next_odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1563

if (next_odm_pipe->stream_res.dsc == NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1590

secondary_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1712

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1821

if (odm_pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1822

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2269

if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2270

dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

103

void dcn20_dsc_destroy(struct display_stream_compressor **dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

134

struct display_stream_compressor **dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

148

struct display_stream_compressor **dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1125

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1128

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1133

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1134

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1425

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1428

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1433

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1434

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1698

sec_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1721

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1722

ASSERT(sec_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1723

if (sec_pipe->stream_res.dsc == NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1903

if (pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1904

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1263

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1266

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1271

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1272

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

801

struct dcn20_dsc *dsc = kzalloc_obj(struct dcn20_dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

803

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

808

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

809

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

762

struct dcn20_dsc *dsc = kzalloc_obj(struct dcn20_dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

764

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

769

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

770

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1722

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1725

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1730

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1731

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1781

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1784

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1789

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1790

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

972

.dsc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1724

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1727

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1732

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1733

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1714

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1717

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1722

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1723

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1732

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1735

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1747

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1749

dsc->max_image_width = 6016;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1751

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3034

free_pipe->stream_res.dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3046

&free_pipe->stream_res.dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3048

ASSERT(free_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3049

if (free_pipe->stream_res.dsc == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

132

if (pipe->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

133

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1706

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1709

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1721

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1723

dsc->max_image_width = 6016;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1725

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1824

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1827

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1839

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1840

dsc35_set_fgcg(dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1841

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1842

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

803

.dsc = true,/*dscclk and dsc pg*/

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1804

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1807

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1819

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1820

dsc35_set_fgcg(dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1821

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1822

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

783

.dsc = true,/*dscclk and dsc pg*/

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1811

struct dcn20_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1814

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1826

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1827

dsc35_set_fgcg(dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1828

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1829

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

790

.dsc = true,/*dscclk and dsc pg*/

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1483

static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1485

kfree(container_of(*dsc, struct dcn401_dsc, base));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1486

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1724

struct dcn401_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1727

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1739

dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1740

dsc401_set_fgcg(dsc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1741

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1744

dsc->max_image_width = 5760;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1746

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1476

static void dcn42_dsc_destroy(struct display_stream_compressor **dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1478

kfree(container_of(*dsc, struct dcn401_dsc, base));

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1479

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1789

struct dcn401_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1792

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1804

dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1805

dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1807

dsc->max_image_width = 5760;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1809

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

764

.dsc = true,/*dscclk and dsc pg*/

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1455

static void dcn42b_dsc_destroy(struct display_stream_compressor **dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1457

kfree(container_of(*dsc, struct dcn401_dsc, base));

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1458

*dsc = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1754

struct dcn401_dsc *dsc =

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1757

if (!dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1769

dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1770

dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1772

dsc->max_image_width = 5760;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1774

return &dsc->base;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

792

.dsc = false,/*dscclk and dsc pg*/

drivers/gpu/drm/amd/display/modules/power/power_psr.c

642

link->panel_config.dsc.disable_dsc_edp ||

drivers/gpu/drm/display/drm_dsc_helper.c

1460

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)

drivers/gpu/drm/display/drm_dsc_helper.c

1462

return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);

drivers/gpu/drm/display/drm_dsc_helper.c

1472

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc)

drivers/gpu/drm/display/drm_dsc_helper.c

1474

return 2 << (dsc->bits_per_component - 8);

drivers/gpu/drm/i915/display/icl_dsi.c

1512

if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {

drivers/gpu/drm/i915/display/icl_dsi.c

1513

int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

1621

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/icl_dsi.c

1768

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/icl_dsi.c

350

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/icl_dsi.c

351

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

752

if (pipe_config->dsc.compression_enable) {

drivers/gpu/drm/i915/display/icl_dsi.c

898

if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/icl_dsi.c

899

mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

922

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/icl_dsi.c

923

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/intel_audio.c

459

vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_audio.c

526

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_bios.c

2201

devdata->dsc = kmemdup(&params->data[index],

drivers/gpu/drm/i915/display/intel_bios.c

2202

sizeof(*devdata->dsc), GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_bios.c

2765

devdata->dsc != NULL);

drivers/gpu/drm/i915/display/intel_bios.c

3373

kfree(devdata->dsc);

drivers/gpu/drm/i915/display/intel_bios.c

3572

struct dsc_compression_parameters_entry *dsc,

drivers/gpu/drm/i915/display/intel_bios.c

3576

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_bios.c

3580

vdsc_cfg->dsc_version_major = dsc->version_major;

drivers/gpu/drm/i915/display/intel_bios.c

3581

vdsc_cfg->dsc_version_minor = dsc->version_minor;

drivers/gpu/drm/i915/display/intel_bios.c

3583

if (dsc->support_12bpc && dsc_max_bpc >= 12)

drivers/gpu/drm/i915/display/intel_bios.c

3585

else if (dsc->support_10bpc && dsc_max_bpc >= 10)

drivers/gpu/drm/i915/display/intel_bios.c

3587

else if (dsc->support_8bpc && dsc_max_bpc >= 8)

drivers/gpu/drm/i915/display/intel_bios.c

3595

crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,

drivers/gpu/drm/i915/display/intel_bios.c

3596

VBT_DSC_MAX_BPP(dsc->max_bpp)));

drivers/gpu/drm/i915/display/intel_bios.c

3606

if (dsc->slices_per_line & BIT(2)) {

drivers/gpu/drm/i915/display/intel_bios.c

3608

} else if (dsc->slices_per_line & BIT(1)) {

drivers/gpu/drm/i915/display/intel_bios.c

3612

if (!(dsc->slices_per_line & BIT(0)))

drivers/gpu/drm/i915/display/intel_bios.c

3621

&crtc_state->dsc.slice_config)))

drivers/gpu/drm/i915/display/intel_bios.c

3625

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config) != 0)

drivers/gpu/drm/i915/display/intel_bios.c

3629

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_bios.c

3635

vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,

drivers/gpu/drm/i915/display/intel_bios.c

3636

dsc->rc_buffer_size);

drivers/gpu/drm/i915/display/intel_bios.c

3639

vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);

drivers/gpu/drm/i915/display/intel_bios.c

3641

vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;

drivers/gpu/drm/i915/display/intel_bios.c

3643

vdsc_cfg->slice_height = dsc->slice_height;

drivers/gpu/drm/i915/display/intel_bios.c

3663

if (!devdata->dsc)

drivers/gpu/drm/i915/display/intel_bios.c

3666

return fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);

drivers/gpu/drm/i915/display/intel_bios.c

76

struct dsc_compression_parameters_entry *dsc;

drivers/gpu/drm/i915/display/intel_display.c

2000

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_display.c

4715

crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);

drivers/gpu/drm/i915/display/intel_display.c

479

new_crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_display.c

533

old_crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_display.c

5445

PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);

drivers/gpu/drm/i915/display/intel_display.c

5446

PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);

drivers/gpu/drm/i915/display/intel_display.c

5447

PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);

drivers/gpu/drm/i915/display/intel_display.c

5448

PIPE_CONF_CHECK_BOOL(dsc.config.native_422);

drivers/gpu/drm/i915/display/intel_display.c

5449

PIPE_CONF_CHECK_BOOL(dsc.config.native_420);

drivers/gpu/drm/i915/display/intel_display.c

5450

PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);

drivers/gpu/drm/i915/display/intel_display.c

5451

PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);

drivers/gpu/drm/i915/display/intel_display.c

5452

PIPE_CONF_CHECK_I(dsc.config.bits_per_component);

drivers/gpu/drm/i915/display/intel_display.c

5453

PIPE_CONF_CHECK_I(dsc.config.pic_width);

drivers/gpu/drm/i915/display/intel_display.c

5454

PIPE_CONF_CHECK_I(dsc.config.pic_height);

drivers/gpu/drm/i915/display/intel_display.c

5455

PIPE_CONF_CHECK_I(dsc.config.slice_width);

drivers/gpu/drm/i915/display/intel_display.c

5456

PIPE_CONF_CHECK_I(dsc.config.slice_height);

drivers/gpu/drm/i915/display/intel_display.c

5457

PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);

drivers/gpu/drm/i915/display/intel_display.c

5458

PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);

drivers/gpu/drm/i915/display/intel_display.c

5459

PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);

drivers/gpu/drm/i915/display/intel_display.c

5460

PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);

drivers/gpu/drm/i915/display/intel_display.c

5461

PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);

drivers/gpu/drm/i915/display/intel_display.c

5462

PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);

drivers/gpu/drm/i915/display/intel_display.c

5463

PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);

drivers/gpu/drm/i915/display/intel_display.c

5464

PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);

drivers/gpu/drm/i915/display/intel_display.c

5465

PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);

drivers/gpu/drm/i915/display/intel_display.c

5466

PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);

drivers/gpu/drm/i915/display/intel_display.c

5467

PIPE_CONF_CHECK_I(dsc.config.initial_offset);

drivers/gpu/drm/i915/display/intel_display.c

5468

PIPE_CONF_CHECK_I(dsc.config.final_offset);

drivers/gpu/drm/i915/display/intel_display.c

5469

PIPE_CONF_CHECK_I(dsc.config.rc_model_size);

drivers/gpu/drm/i915/display/intel_display.c

5470

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);

drivers/gpu/drm/i915/display/intel_display.c

5471

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);

drivers/gpu/drm/i915/display/intel_display.c

5472

PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);

drivers/gpu/drm/i915/display/intel_display.c

5473

PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);

drivers/gpu/drm/i915/display/intel_display.c

5474

PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);

drivers/gpu/drm/i915/display/intel_display.c

5476

PIPE_CONF_CHECK_BOOL(dsc.compression_enable);

drivers/gpu/drm/i915/display/intel_display.c

5477

PIPE_CONF_CHECK_I(dsc.slice_config.streams_per_pipe);

drivers/gpu/drm/i915/display/intel_display.c

5478

PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1038

seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

942

str_yes_no(crtc_state->dsc.compression_enable));

drivers/gpu/drm/i915/display/intel_display_types.h

1348

} dsc;

drivers/gpu/drm/i915/display/intel_dp.c

1494

bool dsc = false;

drivers/gpu/drm/i915/display/intel_dp.c

1552

dsc = dsc_max_compressed_bpp && dsc_slice_count;

drivers/gpu/drm/i915/display/intel_dp.c

1559

dsc = intel_dp_mode_valid_with_dsc(connector,

drivers/gpu/drm/i915/display/intel_dp.c

1568

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {

drivers/gpu/drm/i915/display/intel_dp.c

1573

if (mode_rate > max_rate && !dsc) {

drivers/gpu/drm/i915/display/intel_dp.c

1582

if (!dsc)

drivers/gpu/drm/i915/display/intel_dp.c

2055

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_dp.c

2187

intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);

drivers/gpu/drm/i915/display/intel_dp.c

2387

pipe_config->dsc.compressed_bpp_x16 = max_bpp_x16;

drivers/gpu/drm/i915/display/intel_dp.c

2402

pipe_config->dsc.compressed_bpp_x16 = bpp_x16;

drivers/gpu/drm/i915/display/intel_dp.c

2504

crtc_state->dsc.compression_enable = false;

drivers/gpu/drm/i915/display/intel_dp.c

2505

crtc_state->dsc.compressed_bpp_x16 = 0;

drivers/gpu/drm/i915/display/intel_dp.c

2507

memset(&crtc_state->dsc.slice_config, 0, sizeof(crtc_state->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_dp.c

2508

memset(&crtc_state->dsc.config, 0, sizeof(crtc_state->dsc.config));

drivers/gpu/drm/i915/display/intel_dp.c

2551

&pipe_config->dsc.slice_config))

drivers/gpu/drm/i915/display/intel_dp.c

2560

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));

drivers/gpu/drm/i915/display/intel_dp.c

2569

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),

drivers/gpu/drm/i915/display/intel_dp.c

2570

intel_dsc_line_slice_count(&pipe_config->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_dp.c

2705

bool dsc,

drivers/gpu/drm/i915/display/intel_dp.c

2719

if (!dsc) {

drivers/gpu/drm/i915/display/intel_dp.c

2748

str_on_off(dsc),

drivers/gpu/drm/i915/display/intel_dp.c

2797

bool dsc,

drivers/gpu/drm/i915/display/intel_dp.c

2829

if (!dsc && intel_dp_in_hdr_mode(conn_state)) {

drivers/gpu/drm/i915/display/intel_dp.c

2851

if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits))

drivers/gpu/drm/i915/display/intel_dp.c

2865

if (dsc)

drivers/gpu/drm/i915/display/intel_dp.c

2895

dsc,

drivers/gpu/drm/i915/display/intel_dp.c

2903

int link_bpp_x16 = crtc_state->dsc.compression_enable ?

drivers/gpu/drm/i915/display/intel_dp.c

2904

crtc_state->dsc.compressed_bpp_x16 :

drivers/gpu/drm/i915/display/intel_dp.c

3000

dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);

drivers/gpu/drm/i915/display/intel_dp.c

3014

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),

drivers/gpu/drm/i915/display/intel_dp.c

3587

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

3598

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

3599

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_dp.c

3635

(crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_dp.c

3637

crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));

drivers/gpu/drm/i915/display/intel_dp.c

3704

if (pipe_config->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

3705

link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_dp.c

3955

if (!new_crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

3986

if (!old_crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

4161

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

6795

if (crtc_state && crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

7617

crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.h

204

bool dsc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

144

bool dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1481

bool dsc = false;

drivers/gpu/drm/i915/display/intel_dp_mst.c

150

if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1569

dsc = intel_dp_mode_valid_with_dsc(connector,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1577

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1582

if (mode_rate > max_rate && !dsc) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1592

if (!dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2110

if (old_crtc_state->dsc.compression_enable ==

drivers/gpu/drm/i915/display/intel_dp_mst.c

2111

new_crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp_mst.c

251

int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

266

drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||

drivers/gpu/drm/i915/display/intel_dp_mst.c

292

crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

300

if (crtc_state->fec_enable && dsc &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

304

max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));

drivers/gpu/drm/i915/display/intel_dp_mst.c

314

if (dsc) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

331

if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

337

link_bpp_x16 = dsc ? bpp_x16 :

drivers/gpu/drm/i915/display/intel_dp_mst.c

431

if (!dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

434

crtc_state->dsc.compressed_bpp_x16 = bpp_x16;

drivers/gpu/drm/i915/display/intel_dp_mst.c

437

slots, FXP_Q4_ARGS(bpp_x16), dsc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

522

bool dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

531

if (!dsc) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

581

bool dsc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

588

crtc_state, false, dsc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

596

dsc);

drivers/gpu/drm/i915/display/intel_dp_mst.h

37

int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc);

drivers/gpu/drm/i915/display/intel_link_bw.c

123

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_link_bw.c

124

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_psr.c

1345

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_psr.c

1387

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_psr.c

1645

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_psr.c

2699

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_psr.c

2777

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_psr.c

2782

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_vdsc.c

1093

crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;

drivers/gpu/drm/i915/display/intel_vdsc.c

1094

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1099

crtc_state->dsc.slice_config.streams_per_pipe = 3;

drivers/gpu/drm/i915/display/intel_vdsc.c

1101

crtc_state->dsc.slice_config.streams_per_pipe = 2;

drivers/gpu/drm/i915/display/intel_vdsc.c

1103

crtc_state->dsc.slice_config.streams_per_pipe = 1;

drivers/gpu/drm/i915/display/intel_vdsc.c

1115

FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),

drivers/gpu/drm/i915/display/intel_vdsc.c

1116

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config),

drivers/gpu/drm/i915/display/intel_vdsc.c

1117

crtc_state->dsc.slice_config.streams_per_pipe);

drivers/gpu/drm/i915/display/intel_vdsc.c

1123

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1127

drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);

drivers/gpu/drm/i915/display/intel_vdsc.c

1151

int dsc_slices = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);

drivers/gpu/drm/i915/display/intel_vdsc.c

1155

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1191

int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *

drivers/gpu/drm/i915/display/intel_vdsc.c

1202

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

317

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

327

struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

328

u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/intel_vdsc.c

335

intel_dsc_line_slice_count(&pipe_config->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_vdsc.c

360

vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_vdsc.c

430

crtc_state->dsc.compression_enabled_on_link = true;

drivers/gpu/drm/i915/display/intel_vdsc.c

431

crtc_state->dsc.compression_enable = true;

drivers/gpu/drm/i915/display/intel_vdsc.c

438

drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_vdsc.c

439

!crtc_state->dsc.compression_enabled_on_link);

drivers/gpu/drm/i915/display/intel_vdsc.c

441

return crtc_state->dsc.compression_enabled_on_link;

drivers/gpu/drm/i915/display/intel_vdsc.c

472

return crtc_state->dsc.slice_config.streams_per_pipe;

drivers/gpu/drm/i915/display/intel_vdsc.c

527

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

783

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

789

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

806

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

809

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

828

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

864

if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_vdsc.c

883

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

921

if (old_crtc_state->dsc.compression_enable ||

drivers/gpu/drm/i915/display/intel_vdsc.c

972

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

996

crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;

drivers/gpu/drm/i915/display/skl_prefill.c

38

ctx->prefill.dsc = intel_vdsc_prefill_lines(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

76

prefill += ctx->prefill.dsc;

drivers/gpu/drm/i915/display/skl_prefill.h

20

unsigned int dsc;

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

438

.dsc = sm8650_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h

266

.dsc = milos_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

479

.dsc = sm8750_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

526

.dsc = glymur_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

350

.dsc = eliza_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

477

.dsc = kaanapali_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h

320

.dsc = msm8996_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

305

.dsc = msm8998_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h

269

.dsc = sdm660_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

325

.dsc = sdm845_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h

144

.dsc = sdm670_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

374

.dsc = sm8150_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

398

.dsc = sc8180x_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

306

.dsc = sm7150_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

373

.dsc = sm8250_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

224

.dsc = sm6350_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h

153

.dsc = sm6375_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

387

.dsc = sm8350_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

260

.dsc = sc7280_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

418

.dsc = sc8280xp_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

400

.dsc = sm8450_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

439

.dsc = sa8775p_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

395

.dsc = sm8550_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

395

.dsc = sar2130p_dsc,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

435

.dsc = x1e80100_dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1345

dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1967

dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1972

soft_slice_per_enc = enc_ip_width / dsc->slice_width;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1984

ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1985

total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1988

return DIV_ROUND_UP(total_pixels, dsc->slice_width);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1994

struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1999

hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2002

hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2018

struct drm_dsc_config *dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2042

pic_width = dsc->pic_width;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2052

this_frame_slices = pic_width / dsc->slice_width;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2053

intf_ip_w = this_frame_slices * dsc->slice_width;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2056

initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2060

dsc, dsc_common_mode, initial_lines);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2102

if (dpu_enc->dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2103

dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

217

struct drm_dsc_config *dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2322

if (dpu_enc->dsc) {

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2324

dpu_enc->dsc = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2329

intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

303

return dpu_enc->dsc ? true : false;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

668

struct drm_dsc_config *dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

676

dsc = dpu_encoder_get_dsc_config(drm_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

679

if (dsc) {

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

68

intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

78

if (intf_cfg.dsc != 0)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

131

struct drm_dsc_config *dsc =

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

137

timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

138

(dsc->bits_per_component * 3);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

140

timing->dce_bytes_per_line = msm_dsc_get_bytes_per_line(dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

312

intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

738

const struct dpu_dsc_cfg *dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

606

if (cfg->dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

607

dsc_active |= cfg->dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

724

if (cfg->dsc) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

726

dsc_active &= ~cfg->dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

59

unsigned int dsc;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

100

data = dsc->first_line_bpg_offset;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

103

data = dsc->nfl_bpg_offset << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

104

data |= dsc->slice_bpg_offset;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

107

data = dsc->initial_offset << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

108

data |= dsc->final_offset;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

111

det_thresh_flatness = drm_dsc_flatness_det_thresh(dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

113

data |= dsc->flatness_max_qp << 5;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

114

data |= dsc->flatness_min_qp;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

117

data = dsc->rc_model_size;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

120

data = dsc->rc_tgt_offset_low << 18;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

121

data |= dsc->rc_tgt_offset_high << 14;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

122

data |= dsc->rc_quant_incr_limit1 << 9;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

123

data |= dsc->rc_quant_incr_limit0 << 4;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

124

data |= dsc->rc_edge_factor;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

129

struct drm_dsc_config *dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

131

struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

138

DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

38

static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

40

struct dpu_hw_blk_reg_map *c = &dsc->hw;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

46

struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

55

bool input_10_bits = dsc->bits_per_component == 10;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

62

slice_last_group_size = (dsc->slice_width + 2) % 3;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

67

data |= (dsc->bits_per_pixel << 8);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

68

data |= (dsc->block_pred_enable << 7);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

69

data |= (dsc->line_buf_depth << 3);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

70

data |= (dsc->simple_422 << 2);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

71

data |= (dsc->convert_rgb << 1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

76

data = dsc->pic_width << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

77

data |= dsc->pic_height;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

80

data = dsc->slice_width << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

81

data |= dsc->slice_height;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

84

data = dsc->slice_chunk_size << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

87

data = dsc->initial_dec_delay << 16;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

88

data |= dsc->initial_xmit_delay;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

91

data = dsc->initial_scale_value;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

94

data = dsc->scale_decrement_interval;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

97

data = dsc->scale_increment_interval;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

37

struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

47

struct drm_dsc_config *dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

112

num_active_slice_per_enc = dsc->slice_count;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

114

num_active_slice_per_enc = dsc->slice_count / 2;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

129

data = (dsc->dsc_version_minor & 0xf) << 28;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

130

if (dsc->dsc_version_minor == 0x2) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

131

if (dsc->native_422)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

133

if (dsc->native_420)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

137

bpp = dsc->bits_per_pixel;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

141

if (dsc->native_422 || dsc->native_420)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

146

if (dsc->block_pred_enable)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

149

if (dsc->convert_rgb)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

152

data |= (dsc->line_buf_depth & 0xf) << 6;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

153

data |= dsc->bits_per_component & 0xf;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

157

data = (dsc->pic_width & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

158

((dsc->pic_height & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

162

data = (dsc->slice_width & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

163

((dsc->slice_height & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

168

(dsc->slice_chunk_size) & 0xffff);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

170

data = (dsc->initial_xmit_delay & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

171

((dsc->initial_dec_delay & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

176

dsc->initial_scale_value & 0x3f);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

178

data = (dsc->scale_increment_interval & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

179

((dsc->scale_decrement_interval & 0x7ff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

183

data = (dsc->first_line_bpg_offset & 0x1f) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

184

((dsc->second_line_bpg_offset & 0x1f) << 5);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

188

data = (dsc->nfl_bpg_offset & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

189

((dsc->slice_bpg_offset & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

193

data = (dsc->initial_offset & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

194

((dsc->final_offset & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

198

data = (dsc->nsl_bpg_offset & 0xffff) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

199

((dsc->second_line_offset_adj & 0xffff) << 16);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

203

det_thresh_flatness = drm_dsc_flatness_det_thresh(dsc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

204

data = (dsc->flatness_min_qp & 0x1f) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

205

((dsc->flatness_max_qp & 0x1f) << 5) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

211

(dsc->rc_model_size) & 0xffff);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

213

data = dsc->rc_edge_factor & 0xf;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

214

data |= (dsc->rc_quant_incr_limit0 & 0x1f) << 8;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

215

data |= (dsc->rc_quant_incr_limit1 & 0x1f) << 13;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

216

data |= (dsc->rc_tgt_offset_high & 0xf) << 20;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

217

data |= (dsc->rc_tgt_offset_low & 0xf) << 24;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

223

if (dsc->native_422)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

225

else if (dsc->native_420)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

227

if (!dsc->convert_rgb)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

229

if (dsc->bits_per_component == 8)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

242

struct drm_dsc_config *dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

248

if (!hw_dsc || !dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

255

rc = dsc->rc_range_params;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

263

(dsc->rc_buf_thresh[0] << 0) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

264

(dsc->rc_buf_thresh[1] << 8) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

265

(dsc->rc_buf_thresh[2] << 16) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

266

(dsc->rc_buf_thresh[3] << 24));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

268

(dsc->rc_buf_thresh[4] << 0) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

269

(dsc->rc_buf_thresh[5] << 8) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

270

(dsc->rc_buf_thresh[6] << 16) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

271

(dsc->rc_buf_thresh[7] << 24));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

273

(dsc->rc_buf_thresh[8] << 0) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

274

(dsc->rc_buf_thresh[9] << 8) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

275

(dsc->rc_buf_thresh[10] << 16) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

276

(dsc->rc_buf_thresh[11] << 24));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

278

(dsc->rc_buf_thresh[12] << 0) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

279

(dsc->rc_buf_thresh[13] << 8));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

88

struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

99

if (!hw_dsc || !dsc)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1040

base = dpu_kms->mmio + cat->dsc[i].base;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1041

msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1042

"%s", cat->dsc[i].name);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1045

struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1046

struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1049

cat->dsc[i].name, enc.name);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1051

cat->dsc[i].name, ctl.name);

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

169

const struct dpu_dsc_cfg *dsc = &cat->dsc[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

172

hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

174

hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

181

rm->dsc_blks[dsc->id - DSC_0] = &hw->base;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

629

.dsc = {

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

732

.dsc = {

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h

109

struct mdp5_sub_block dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

1022

if (msm_host->dsc) {

drivers/gpu/drm/msm/dsi/dsi_host.c

1023

struct drm_dsc_config *dsc = msm_host->dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

1027

if (!dsc || !mode->hdisplay || !mode->vdisplay) {

drivers/gpu/drm/msm/dsi/dsi_host.c

1033

dsc->pic_width = mode->hdisplay;

drivers/gpu/drm/msm/dsi/dsi_host.c

1034

dsc->pic_height = mode->vdisplay;

drivers/gpu/drm/msm/dsi/dsi_host.c

1035

DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);

drivers/gpu/drm/msm/dsi/dsi_host.c

1040

ret = dsi_populate_dsc_params(msm_host, dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

1063

bits_per_pclk = dsc->bits_per_component * 3;

drivers/gpu/drm/msm/dsi/dsi_host.c

1070

hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8, bits_per_pclk);

drivers/gpu/drm/msm/dsi/dsi_host.c

1077

if (msm_host->dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

1098

if (msm_host->dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

1102

if (!msm_host->dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

1112

wc = msm_host->dsc->slice_chunk_size + 1;

drivers/gpu/drm/msm/dsi/dsi_host.c

168

struct drm_dsc_config *dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

1721

if (dsi->dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

1722

msm_host->dsc = dsi->dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

1737

if (msm_host->dsc &&

drivers/gpu/drm/msm/dsi/dsi_host.c

1869

static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

1873

if (dsc->bits_per_pixel & 0xf) {

drivers/gpu/drm/msm/dsi/dsi_host.c

1878

switch (dsc->bits_per_component) {

drivers/gpu/drm/msm/dsi/dsi_host.c

1891

dsc->bits_per_component);

drivers/gpu/drm/msm/dsi/dsi_host.c

1895

dsc->simple_422 = 0;

drivers/gpu/drm/msm/dsi/dsi_host.c

1896

dsc->convert_rgb = 1;

drivers/gpu/drm/msm/dsi/dsi_host.c

1897

dsc->vbr_enable = 0;

drivers/gpu/drm/msm/dsi/dsi_host.c

1899

drm_dsc_set_const_params(dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

1900

drm_dsc_set_rc_buf_thresh(dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

1903

ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);

drivers/gpu/drm/msm/dsi/dsi_host.c

1909

dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

1910

dsc->line_buf_depth = dsc->bits_per_component + 1;

drivers/gpu/drm/msm/dsi/dsi_host.c

1912

return drm_dsc_compute_rc_parameters(dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

2599

struct drm_dsc_config *dsc = msm_host->dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

2603

if (!msm_host->dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

2606

if (pic_width % dsc->slice_width) {

drivers/gpu/drm/msm/dsi/dsi_host.c

2608

pic_width, dsc->slice_width);

drivers/gpu/drm/msm/dsi/dsi_host.c

2612

if (pic_height % dsc->slice_height) {

drivers/gpu/drm/msm/dsi/dsi_host.c

2614

pic_height, dsc->slice_height);

drivers/gpu/drm/msm/dsi/dsi_host.c

2703

return msm_host->dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

37

static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);

drivers/gpu/drm/msm/dsi/dsi_host.c

590

const struct drm_dsc_config *dsc,

drivers/gpu/drm/msm/dsi/dsi_host.c

605

new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc),

drivers/gpu/drm/msm/dsi/dsi_host.c

606

dsc->bits_per_component * 3);

drivers/gpu/drm/msm/dsi/dsi_host.c

617

const struct drm_dsc_config *dsc, bool is_bonded_dsi)

drivers/gpu/drm/msm/dsi/dsi_host.c

623

if (dsc)

drivers/gpu/drm/msm/dsi/dsi_host.c

624

pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi);

drivers/gpu/drm/msm/dsi/dsi_host.c

644

unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);

drivers/gpu/drm/msm/dsi/dsi_host.c

663

msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi);

drivers/gpu/drm/msm/dsi/dsi_host.c

800

return msm_host->dsc &&

drivers/gpu/drm/msm/dsi/dsi_host.c

928

struct drm_dsc_config *dsc = msm_host->dsc;

drivers/gpu/drm/msm/dsi/dsi_host.c

938

slice_per_intf = dsc->slice_count;

drivers/gpu/drm/msm/dsi/dsi_host.c

940

total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;

drivers/gpu/drm/msm/dsi/dsi_host.c

941

bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */

drivers/gpu/drm/msm/dsi/dsi_host.c

978

reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);

drivers/gpu/drm/msm/msm_dsc_helper.h

22

static inline u32 msm_dsc_get_bytes_per_line(const struct drm_dsc_config *dsc)

drivers/gpu/drm/msm/msm_dsc_helper.h

24

return dsc->slice_count * dsc->slice_chunk_size;

drivers/gpu/drm/panel/panel-himax-hx83121a.c

115

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-himax-hx83121a.c

33

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-himax-hx83121a.c

616

ctx->dsc = *desc->dsc_cfg;

drivers/gpu/drm/panel/panel-himax-hx83121a.c

664

ctx->dsi[i]->dsc = enable_dsc ? &ctx->dsc : NULL;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

30

const struct drm_dsc_config *dsc;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

61

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

714

.dsc = &tianma_il79900a_dsc,

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

835

if (desc->dsc) {

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

836

ili->dsc = *desc->dsc;

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

837

dsi->dsc = &ili->dsc;

drivers/gpu/drm/panel/panel-lg-sw43408.c

111

drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc);

drivers/gpu/drm/panel/panel-lg-sw43408.c

284

ctx->dsc.dsc_version_major = 0x1;

drivers/gpu/drm/panel/panel-lg-sw43408.c

285

ctx->dsc.dsc_version_minor = 0x1;

drivers/gpu/drm/panel/panel-lg-sw43408.c

288

ctx->dsc.slice_height = 16;

drivers/gpu/drm/panel/panel-lg-sw43408.c

289

ctx->dsc.slice_width = 540;

drivers/gpu/drm/panel/panel-lg-sw43408.c

290

ctx->dsc.slice_count = 2;

drivers/gpu/drm/panel/panel-lg-sw43408.c

291

ctx->dsc.bits_per_component = 8;

drivers/gpu/drm/panel/panel-lg-sw43408.c

292

ctx->dsc.bits_per_pixel = 8 << 4;

drivers/gpu/drm/panel/panel-lg-sw43408.c

293

ctx->dsc.block_pred_enable = true;

drivers/gpu/drm/panel/panel-lg-sw43408.c

295

dsi->dsc = &ctx->dsc;

drivers/gpu/drm/panel/panel-lg-sw43408.c

38

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

145

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-novatek-nt37801.c

22

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

290

dsi->dsc = &ctx->dsc;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

291

ctx->dsc.dsc_version_major = 1;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

292

ctx->dsc.dsc_version_minor = 1;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

293

ctx->dsc.slice_height = 40;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

294

ctx->dsc.slice_width = 720;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

295

ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

296

ctx->dsc.bits_per_component = 8;

drivers/gpu/drm/panel/panel-novatek-nt37801.c

297

ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */

drivers/gpu/drm/panel/panel-novatek-nt37801.c

298

ctx->dsc.block_pred_enable = true;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

154

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

23

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

321

dsi->dsc = &ctx->dsc;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

324

ctx->dsc.dsc_version_major = 1;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

325

ctx->dsc.dsc_version_minor = 1;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

326

ctx->dsc.slice_height = 60;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

327

ctx->dsc.slice_width = 1224;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

329

ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

330

ctx->dsc.bits_per_component = 8;

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

331

ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */

drivers/gpu/drm/panel/panel-raydium-rm692e5.c

332

ctx->dsc.block_pred_enable = true;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

201

drm_dsc_pps_payload_pack(&pps, &priv->dsc);

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

22

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

289

dsi->dsc = &priv->dsc;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

291

priv->dsc.dsc_version_major = 1;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

292

priv->dsc.dsc_version_minor = 1;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

294

priv->dsc.slice_height = 40;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

295

priv->dsc.slice_width = 720;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

296

WARN_ON(1440 % priv->dsc.slice_width);

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

297

priv->dsc.slice_count = 1440 / priv->dsc.slice_width;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

298

priv->dsc.bits_per_component = 8;

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

299

priv->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c

300

priv->dsc.block_pred_enable = true;

drivers/gpu/drm/panel/panel-visionox-r66451.c

178

if (!dsi->dsc) {

drivers/gpu/drm/panel/panel-visionox-r66451.c

183

drm_dsc_pps_payload_pack(&pps, dsi->dsc);

drivers/gpu/drm/panel/panel-visionox-r66451.c

255

struct drm_dsc_config *dsc;

drivers/gpu/drm/panel/panel-visionox-r66451.c

264

dsc = devm_kzalloc(dev, sizeof(*dsc), GFP_KERNEL);

drivers/gpu/drm/panel/panel-visionox-r66451.c

265

if (!dsc)

drivers/gpu/drm/panel/panel-visionox-r66451.c

269

dsc->dsc_version_major = 0x1;

drivers/gpu/drm/panel/panel-visionox-r66451.c

270

dsc->dsc_version_minor = 0x2;

drivers/gpu/drm/panel/panel-visionox-r66451.c

272

dsc->slice_height = 20;

drivers/gpu/drm/panel/panel-visionox-r66451.c

273

dsc->slice_width = 540;

drivers/gpu/drm/panel/panel-visionox-r66451.c

274

dsc->slice_count = 2;

drivers/gpu/drm/panel/panel-visionox-r66451.c

275

dsc->bits_per_component = 8;

drivers/gpu/drm/panel/panel-visionox-r66451.c

276

dsc->bits_per_pixel = 8 << 4;

drivers/gpu/drm/panel/panel-visionox-r66451.c

277

dsc->block_pred_enable = true;

drivers/gpu/drm/panel/panel-visionox-r66451.c

279

dsi->dsc = dsc;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

209

drm_dsc_pps_payload_pack(&pps, &ctx->dsc);

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

27

struct drm_dsc_config dsc;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

396

dsi->dsc = &ctx->dsc;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

397

ctx->dsc.dsc_version_major = 1;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

398

ctx->dsc.dsc_version_minor = 1;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

399

ctx->dsc.slice_height = 20;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

400

ctx->dsc.slice_width = 540;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

401

ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

402

ctx->dsc.bits_per_component = 10;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

403

ctx->dsc.bits_per_pixel = 8 << 4;

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

404

ctx->dsc.block_pred_enable = true;

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

18

const bool dsc;

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

26

.dsc = false,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

32

.dsc = false,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

38

.dsc = false,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

44

.dsc = true,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

50

.dsc = true,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

65

sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled");

drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c

1542

.dsc = DESC_BUF_SIZE,

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h

209

unsigned int dsc;

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h

703

struct s5p_mfc_priv_buf dsc;

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

350

mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

351

mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

40

ctx->dsc.size = buf_size->dsc;

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

41

ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->dsc);

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

47

BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

48

memset(ctx->dsc.virt, 0, ctx->dsc.size);

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c

57

s5p_mfc_release_priv_buf(ctx->dev, &ctx->dsc);

drivers/net/ethernet/broadcom/sb1250-mac.c

1056

struct sbdmadscr *dsc;

drivers/net/ethernet/broadcom/sb1250-mac.c

1082

dsc = d->sbdma_remptr;

drivers/net/ethernet/broadcom/sb1250-mac.c

1083

curidx = dsc - d->sbdma_dscrtable;

drivers/net/ethernet/broadcom/sb1250-mac.c

1085

prefetch(dsc);

drivers/net/ethernet/broadcom/sb1250-mac.c

1108

len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;

drivers/net/ethernet/broadcom/sb1250-mac.c

1116

if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {

drivers/net/ethernet/broadcom/sb1250-mac.c

1147

if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&

drivers/net/ethernet/broadcom/sb1250-mac.c

1148

!((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {

drivers/net/ethernet/broadcom/sb1250-mac.c

1221

struct sbdmadscr *dsc;

drivers/net/ethernet/broadcom/sb1250-mac.c

1261

dsc = &(d->sbdma_dscrtable[curidx]);

drivers/net/ethernet/broadcom/sb1250-mac.c

773

struct sbdmadscr *dsc;

drivers/net/ethernet/broadcom/sb1250-mac.c

780

dsc = d->sbdma_addptr;

drivers/net/ethernet/broadcom/sb1250-mac.c

837

dsc->dscr_a = virt_to_phys(sb_new->data) |

drivers/net/ethernet/broadcom/sb1250-mac.c

840

dsc->dscr_a = virt_to_phys(sb_new->data) |

drivers/net/ethernet/broadcom/sb1250-mac.c

846

dsc->dscr_b = 0;

drivers/net/ethernet/broadcom/sb1250-mac.c

852

d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;

drivers/net/ethernet/broadcom/sb1250-mac.c

887

struct sbdmadscr *dsc;

drivers/net/ethernet/broadcom/sb1250-mac.c

895

dsc = d->sbdma_addptr;

drivers/net/ethernet/broadcom/sb1250-mac.c

926

dsc->dscr_a = phys |

drivers/net/ethernet/broadcom/sb1250-mac.c

935

dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |

drivers/net/ethernet/broadcom/sb1250-mac.c

942

d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c

61

#define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c

62

atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_stats.c

50

#define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_stats.c

51

atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

36

#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

37

(*(u64 *)((char *)ptr + dsc[i].offset))

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

38

#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

39

be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

40

#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

41

(*(u32 *)((char *)ptr + dsc[i].offset))

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

42

#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

43

be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))

drivers/scsi/qla2xxx/qla_mid.c

1136

int qla_get_buf(struct scsi_qla_host *vha, struct qla_qpair *qp, struct qla_buf_dsc *dsc)

drivers/scsi/qla2xxx/qla_mid.c

1143

dsc->tag = TAG_FREED;

drivers/scsi/qla2xxx/qla_mid.c

1170

dsc->buf = qp->buf_pool.buf_array[tag] = buf;

drivers/scsi/qla2xxx/qla_mid.c

1171

dsc->buf_dma = qp->buf_pool.dma_array[tag] = buf_dma;

drivers/scsi/qla2xxx/qla_mid.c

1174

dsc->buf = qp->buf_pool.buf_array[tag];

drivers/scsi/qla2xxx/qla_mid.c

1175

dsc->buf_dma = qp->buf_pool.dma_array[tag];

drivers/scsi/qla2xxx/qla_mid.c

1176

memset(dsc->buf, 0, FCP_CMND_DMA_POOL_SIZE);

drivers/scsi/qla2xxx/qla_mid.c

1183

dsc->tag = tag;

drivers/scsi/qla2xxx/qla_mid.c

1242

void qla_put_buf(struct qla_qpair *qp, struct qla_buf_dsc *dsc)

drivers/scsi/qla2xxx/qla_mid.c

1244

if (dsc->tag == TAG_FREED)

drivers/scsi/qla2xxx/qla_mid.c

1248

clear_bit(dsc->tag, qp->buf_pool.buf_map);

drivers/scsi/qla2xxx/qla_mid.c

1250

dsc->tag = TAG_FREED;

drivers/usb/atm/ueagle-atm.c

1946

struct cmv_dsc_e1 *dsc = &sc->cmv_dsc.e1;

drivers/usb/atm/ueagle-atm.c

1958

if (cmv->bFunction != dsc->function) {

drivers/usb/atm/ueagle-atm.c

1961

cmv->wIndex = cpu_to_le16(dsc->idx);

drivers/usb/atm/ueagle-atm.c

1962

put_unaligned_le32(dsc->address,

drivers/usb/atm/ueagle-atm.c

1964

cmv->wOffsetAddress = cpu_to_le16(dsc->offset);

drivers/usb/atm/ueagle-atm.c

1976

if (le16_to_cpu(cmv->wIndex) != dsc->idx ||

drivers/usb/atm/ueagle-atm.c

1977

get_unaligned_le32(&cmv->dwSymbolicAddress) != dsc->address ||

drivers/usb/atm/ueagle-atm.c

1978

le16_to_cpu(cmv->wOffsetAddress) != dsc->offset)

drivers/usb/atm/ueagle-atm.c

2003

struct cmv_dsc_e4 *dsc = &sc->cmv_dsc.e4;

drivers/usb/atm/ueagle-atm.c

2011

if (be16_to_cpu(cmv->wFunction) != dsc->function)

drivers/usb/atm/ueagle-atm.c

2021

if (be16_to_cpu(cmv->wOffset) != dsc->offset ||

drivers/usb/atm/ueagle-atm.c

2022

be16_to_cpu(cmv->wGroup) != dsc->group ||

drivers/usb/atm/ueagle-atm.c

2023

be16_to_cpu(cmv->wAddress) != dsc->address)

include/drm/display/drm_dsc_helper.h

30

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);

include/drm/display/drm_dsc_helper.h

31

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);

include/drm/drm_mipi_dsi.h

197

struct drm_dsc_config *dsc;

sound/pci/ctxfi/ctdaio.c

446

struct daio_desc dsc = {0};

sound/pci/ctxfi/ctdaio.c

448

dsc.type = dao->daio.type;

sound/pci/ctxfi/ctdaio.c

449

dsc.msr = desc->msr;

sound/pci/ctxfi/ctdaio.c

450

dsc.passthru = desc->passthru;

sound/pci/ctxfi/ctdaio.c

451

dsc.output = dao->daio.output;

sound/pci/ctxfi/ctdaio.c

453

return dao_rsc_init(dao, &dsc, mgr);

tools/perf/util/dlfilter.c

593

const char *dsc;

tools/perf/util/dlfilter.c

596

dsc = desc_fn(&long_dsc);

tools/perf/util/dlfilter.c

597

if (dsc)

tools/perf/util/dlfilter.c

598

*desc = strdup(dsc);