drmm_add_action_or_reset
ret = drmm_add_action_or_reset(dev, qaicm_wq_release, wq);
return drmm_add_action_or_reset(dev, qaicm_srcu_release, lock);
ret = drmm_add_action_or_reset(drm, qaicm_pci_release, NULL);
ret = drmm_add_action_or_reset(dev, ast_ddc_release, ddc);
ret = drmm_add_action_or_reset(drm, drmm_drm_panel_bridge_release,
return drmm_add_action_or_reset(connector->dev,
return drmm_add_action_or_reset(connector->dev,
ret = drmm_add_action_or_reset(dev, drm_connector_cleanup_action,
ret = drmm_add_action_or_reset(dev, drmm_crtc_init_with_planes_cleanup,
r = drmm_add_action_or_reset(dev, drm_minor_alloc_release, minor);
ret = drmm_add_action_or_reset(dev, drm_dev_init_release, NULL);
ret = drmm_add_action_or_reset(dev, drmm_cg_unregister_region, region);
ret = drmm_add_action_or_reset(dev, drmm_encoder_alloc_release, encoder);
return drmm_add_action_or_reset(dev, drm_gem_huge_mnt_free, NULL);
return drmm_add_action_or_reset(dev, drm_vram_mm_release, NULL);
return drmm_add_action_or_reset(dev, drm_mode_config_init_release,
ret = drmm_add_action_or_reset(dev, drmm_universal_plane_alloc_release,
ret = drmm_add_action_or_reset(dev, drm_kms_helper_poll_init_release, dev);
ret = drmm_add_action_or_reset(dev, drm_vblank_init_release,
ret = drmm_add_action_or_reset(dev, drm_writeback_connector_cleanup,
ret = drmm_add_action_or_reset(&dev_priv->drm,
return drmm_add_action_or_reset(&i915->drm, i915_gmch_bridge_release,
return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio,
ret = drmm_add_action_or_reset(dev, ipu_put_resources, ipu_crtc);
ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini,
return drmm_add_action_or_reset(ddev, loongson_gfxpll_fini, this);
ret = drmm_add_action_or_reset(ddev, lsdc_destroy_i2c, li2c);
return drmm_add_action_or_reset(this->ddev, lsdc_pixel_pll_free, this);
return drmm_add_action_or_reset(ddev, lsdc_ttm_fini, ldev);
ret = drmm_add_action_or_reset(dev, mgag200_ddc_release, ddc);
ret = drmm_add_action_or_reset(dev, mdp4_crtc_flip_cleanup, mdp4_crtc);
ret = drmm_add_action_or_reset(dev, mdp5_crtc_flip_cleanup, mdp5_crtc);
ret = drmm_add_action_or_reset(&ptdev->base, panthor_device_free_page,
ret = drmm_add_action_or_reset(&ptdev->base, panthor_device_reset_cleanup, NULL);
return drmm_add_action_or_reset(&ptdev->base, panthor_mmu_release_wq, mmu->vm.wq);
ret = drmm_add_action_or_reset(&ptdev->base, panthor_sched_fini, sched);
ret = drmm_add_action_or_reset(&rcdu->ddev, rcar_du_vsp_cleanup, vsp);
ret = drmm_add_action_or_reset(&rcdu->ddev, rzg2l_du_vsp_cleanup, vsp);
ret = drmm_add_action_or_reset(priv->drm, drm_action, priv);
ret = drmm_add_action_or_reset(priv->drm, drm_action, priv);
if (drmm_add_action_or_reset(bo->base.dev, ttm_bo_release_dummy_page,
return drmm_add_action_or_reset(dev, vc4_bo_cache_destroy, NULL);
ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
return drmm_add_action_or_reset(dev, vc4_gem_destroy, NULL);
ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
err = drmm_add_action_or_reset(&xe->drm, display_device_remove, display);
err = drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe);
if (drmm_add_action_or_reset(dev, barrier_release_dummy_page, page))
err = drmm_add_action_or_reset(&xe->drm, xe_device_destroy, NULL);
err = drmm_add_action_or_reset(&xe->drm, ggtt_fini_early, ggtt);
return drmm_add_action_or_reset(&xe->drm, control_fini_action, gt);
err = drmm_add_action_or_reset(&xe->drm, guc_ct_fini, ct);
ret = drmm_add_action_or_reset(&dbm_to_xe(dbm)->drm, __fini_dbm, dbm);
ret = drmm_add_action_or_reset(&idm_to_xe(idm)->drm, __fini_idm, idm);
return drmm_add_action_or_reset(&xe->drm, __fini_relay, relay);
err = drmm_add_action_or_reset(&xe->drm, guc_submit_sw_fini, guc);
err = drmm_add_action_or_reset(&xe->drm, __drmm_workqueue_release, group->resume_wq);
return drmm_add_action_or_reset(&xe->drm, fini_lmtt, lmtt);
if (drmm_add_action_or_reset(dev, xe_mmio_gem_release_dummy_page, page))
return drmm_add_action_or_reset(&xe->drm, reg_sr_fini, sr);
ret = drmm_add_action_or_reset(&xe->drm, xe_sa_bo_manager_fini,
return drmm_add_action_or_reset(&xe->drm, xe_shrinker_fini, shrinker);
return drmm_add_action_or_reset(&xe->drm, fini_sriov, xe);
return drmm_add_action_or_reset(&xe->drm, cleanup_ggtt, tile);
return drmm_add_action_or_reset(&xe->drm, tlb_inval_fini, tlb_inval);
return drmm_add_action_or_reset(&xe->drm, xe_ttm_sys_mgr_fini, xe);
return drmm_add_action_or_reset(&xe->drm, xe_ttm_vram_mgr_fini, mgr);
err = drmm_add_action_or_reset(&xe->drm, uc_fw_fini, uc_fw);
drmm_add_action_or_reset(dev, __drmm_mutex_release, lock); \
int ret = drmm_add_action_or_reset(dev, __drmm_workqueue_release, wq); \