devm_reset_control_get_optional_exclusive
hpriv->rsts = devm_reset_control_get_optional_exclusive(&pdev->dev,
plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
apb->prst = devm_reset_control_get_optional_exclusive(apb->dev, "prst");
axi->arst = devm_reset_control_get_optional_exclusive(axi->dev, "arst");
priv->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
dsi->dsi_p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
reset = devm_reset_control_get_optional_exclusive(drm_dev->dev, NULL);
priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL);
dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst");
pvt->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
info->reset = devm_reset_control_get_optional_exclusive(dev, "saradc-apb");
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
rst = devm_reset_control_get_optional_exclusive(dev, NULL);
csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
devm_reset_control_get_optional_exclusive(&pdev->dev,
dev->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev,
rc_dev->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
priv->rst = devm_reset_control_get_optional_exclusive(priv->dev, NULL);
pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge");
pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit");
pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
port->reset = devm_reset_control_get_optional_exclusive(dev, name);
rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
phy->phy_reset = devm_reset_control_get_optional_exclusive(dev, NULL);
qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
wcss->wcss_q6_bcr_reset = devm_reset_control_get_optional_exclusive(dev,
ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
priv->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
rst = devm_reset_control_get_optional_exclusive(&adev->dev, NULL);
return devm_reset_control_get_optional_exclusive(dev, id);
rk3308->reset = devm_reset_control_get_optional_exclusive(dev, "codec");
xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
formatter->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m");
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);