drivers/acpi/acpi_tad.c

570

static DEVICE_ATTR_RW(dc_status);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13132

enum dc_status status;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3370

static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3393

enum dc_status res;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3489

enum dc_status res;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8361

static enum dc_status dm_validate_stream_and_context(struct dc *dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8364

enum dc_status dc_result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8435

enum dc_status dc_result = DC_OK;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1935

enum dc_status dm_dp_mst_is_port_support_mode(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

93

enum dc_status dm_dp_mst_is_port_support_mode(

drivers/gpu/drm/amd/display/dc/core/dc.c

2204

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2207

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/core/dc.c

2447

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)

drivers/gpu/drm/amd/display/dc/core/dc.c

2451

enum dc_status res = DC_OK;

drivers/gpu/drm/amd/display/dc/core/dc.c

5546

enum dc_status ret = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/core/dc.c

6284

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)

drivers/gpu/drm/amd/display/dc/core/dc.c

6908

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

214

char *dc_status_to_str(enum dc_status status)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

423

enum dc_status dc_link_dp_read_hpd_rx_irq_data(

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

586

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1774

enum dc_status resource_build_scaling_params_for_context(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3129

enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4163

enum dc_status resource_map_pool_resources(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4406

enum dc_status dc_validate_with_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4416

enum dc_status res = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4699

enum dc_status dc_validate_global_state(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4704

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5226

enum dc_status resource_map_clock_resources(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5468

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5475

enum dc_status res = DC_OK;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5499

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5501

enum dc_status res = DC_OK;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5894

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

407

enum dc_status dc_state_add_stream(

drivers/gpu/drm/amd/display/dc/core/dc_state.c

413

enum dc_status res;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

437

enum dc_status dc_state_remove_stream(

drivers/gpu/drm/amd/display/dc/core/dc_state.c

821

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

828

enum dc_status res = dc_state_add_stream(dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

856

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

920

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2075

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc.h

2077

enum dc_status dc_validate_with_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2086

enum dc_status dc_validate_global_state(

drivers/gpu/drm/amd/display/dc/dc.h

2114

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);

drivers/gpu/drm/amd/display/dc/dc.h

2341

enum dc_status dc_link_dp_read_hpd_rx_irq_data(

drivers/gpu/drm/amd/display/dc/dc.h

2777

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/dc.h

2910

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);

drivers/gpu/drm/amd/display/dc/dc.h

2980

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

41

enum dc_status dc_state_add_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

45

enum dc_status dc_state_remove_stream(

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

63

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

67

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

467

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

477

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

96

enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

123

enum dc_status (*add_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

132

enum dc_status (*remove_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

236

enum dc_status status;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1610

static enum dc_status dce110_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1676

enum dc_status dce110_apply_single_controller_ctx_to_hw(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2626

enum dc_status dce110_apply_ctx_to_hw(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2632

enum dc_status status;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

38

enum dc_status dce110_apply_ctx_to_hw(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

42

enum dc_status dce110_apply_single_controller_ctx_to_hw(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1223

enum dc_status dcn10_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4112

enum dc_status dcn10_set_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

115

enum dc_status dce110_apply_ctx_to_hw(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

189

enum dc_status dcn10_set_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

43

enum dc_status dcn10_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

819

enum dc_status dcn20_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

82

enum dc_status dcn20_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

936

enum dc_status dcn30_setup_hdmi_frl_link(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

942

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

75

enum dc_status dcn30_setup_hdmi_frl_link(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1598

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

803

enum dc_status dcn401_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

48

enum dc_status dcn401_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1240

enum dc_status (*apply_ctx_to_hw)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1372

enum dc_status (*set_clock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1432

enum dc_status (*setup_hdmi_frl_link)(

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

111

enum dc_status (*enable_stream_timing)(

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

212

enum dc_status (*apply_single_controller_ctx_to_hw)(

drivers/gpu/drm/amd/display/dc/inc/core_status.h

68

char *dc_status_to_str(enum dc_status status);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

139

enum dc_status (*validate_global)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

159

enum dc_status (*validate_plane)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

163

enum dc_status (*add_stream_to_ctx)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

168

enum dc_status (*remove_stream_from_ctx)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

173

enum dc_status (*patch_unknown_plane_state)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

208

enum dc_status (*add_dsc_to_stream_resource)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

233

enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

88

enum dc_status (*validate_bandwidth)(

drivers/gpu/drm/amd/display/dc/inc/link_service.h

137

enum dc_status (*validate_mode_timing)(

drivers/gpu/drm/amd/display/dc/inc/link_service.h

144

enum dc_status (*validate_dp_tunnel_bandwidth)(

drivers/gpu/drm/amd/display/dc/inc/link_service.h

164

enum dc_status (*increase_mst_payload)(

drivers/gpu/drm/amd/display/dc/inc/link_service.h

166

enum dc_status (*reduce_mst_payload)(

drivers/gpu/drm/amd/display/dc/inc/link_service.h

244

enum dc_status (*dp_read_hpd_rx_irq_data)(

drivers/gpu/drm/amd/display/dc/inc/resource.h

117

enum dc_status resource_map_pool_resources(

drivers/gpu/drm/amd/display/dc/inc/resource.h

128

enum dc_status resource_build_scaling_params_for_context(

drivers/gpu/drm/amd/display/dc/inc/resource.h

301

enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

586

enum dc_status resource_map_clock_resources(

drivers/gpu/drm/amd/display/dc/inc/resource.h

591

enum dc_status resource_map_phy_clock_resources(

drivers/gpu/drm/amd/display/dc/inc/resource.h

647

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

39

static enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

528

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

110

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1298

static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1376

static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1582

static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1665

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1732

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1927

static enum dc_status enable_link_hdmi_frl(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1930

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2030

static enum dc_status enable_link_dp(struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2034

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2153

static enum dc_status enable_link_edp(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2179

static enum dc_status enable_link_dp_mst(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2208

static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2218

static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2230

static enum dc_status enable_link(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2234

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2484

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

87

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

43

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

44

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_validation.c

604

enum dc_status link_validate_mode_timing(

drivers/gpu/drm/amd/display/dc/link/link_validation.c

692

enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/link/link_validation.c

697

enum dc_status result = DC_OK;

drivers/gpu/drm/amd/display/dc/link/link_validation.h

31

enum dc_status link_validate_mode_timing(

drivers/gpu/drm/amd/display/dc/link/link_validation.h

35

enum dc_status link_validate_dp_tunnel_bandwidth(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1079

static enum dc_status wake_up_aux_channel(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1081

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1353

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1414

enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1546

enum dc_status st = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1636

enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1639

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1755

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

46

enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

49

enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

51

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h

35

enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

354

enum dc_status retval;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

378

enum dc_status retval;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

395

enum dc_status dp_read_hpd_rx_irq_data(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

399

static enum dc_status retval;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

479

enum dc_status result;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

53

enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h

35

enum dc_status dp_read_hpd_rx_irq_data(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

138

enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

146

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h

52

enum dc_status dp_set_fec_ready(struct dc_link *link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1020

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1048

enum dc_status dpcd_configure_channel_coding(struct dc_link *link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1054

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1069

enum dc_status dpcd_set_training_pattern(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1073

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1094

enum dc_status dpcd_set_link_settings(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1099

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1184

enum dc_status dpcd_set_lane_settings(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1190

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

548

enum dc_status status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

595

enum dc_status dp_get_lane_status_and_lane_adjust(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

608

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

904

enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

915

static enum dc_status configure_lttpr_mode_non_transparent(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

924

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

982

enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

984

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

199

enum dc_status status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

58

enum dc_status dpcd_set_training_pattern(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

63

enum dc_status dpcd_set_lane_settings(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

69

enum dc_status dpcd_set_link_settings(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

80

enum dc_status dp_get_lane_status_and_lane_adjust(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

88

enum dc_status dpcd_configure_lttpr_mode(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

92

enum dc_status configure_lttpr_mode_transparent(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

94

enum dc_status dpcd_configure_channel_coding(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

163

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

39

static enum dc_status dpcd_128b_132b_set_lane_settings(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

43

enum dc_status status = core_link_write_dpcd(link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

82

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

226

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

346

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

103

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

147

static enum dc_status core_link_send_set_config(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

204

static enum dc_status convert_trng_ptn_to_trng_stg(enum dc_dp_training_pattern tps, enum dpia_set_config_ts *ts)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

206

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

235

static enum dc_status dpcd_set_lt_pattern(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

242

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

297

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

464

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

595

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

740

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

831

static enum dc_status dpcd_clear_lt_pattern(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

837

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

871

enum dc_status status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

198

enum dc_status core_link_read_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

210

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

231

enum dc_status core_link_write_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

239

enum dc_status status = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

44

static enum dc_status internal_link_read_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

59

static enum dc_status internal_link_write_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h

31

enum dc_status core_link_read_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h

37

enum dc_status core_link_write_dpcd(

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

456

enum dc_status result = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

480

enum dc_status result = DC_OK;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

58

enum dc_status result;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

848

static enum dc_status build_mapped_resource(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

866

enum dc_status dce100_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

928

enum dc_status dce100_validate_global(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

939

enum dc_status dce100_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

944

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

966

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

42

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

44

enum dc_status dce100_validate_global(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

48

enum dc_status dce100_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

53

enum dc_status dce100_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1045

static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1101

static enum dc_status dce110_validate_global(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1112

static enum dc_status dce110_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1117

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

947

static enum dc_status build_mapped_resource(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

970

static enum dc_status dce110_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1024

enum dc_status dce112_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1029

enum dc_status result;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1043

static enum dc_status dce112_validate_global(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

875

static enum dc_status build_mapped_resource(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

893

enum dc_status dce112_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

966

enum dc_status resource_map_phy_clock_resources(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

38

enum dc_status dce112_validate_with_context(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

45

enum dc_status dce112_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

50

enum dc_status dce112_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1081

static enum dc_status build_mapped_resource(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1096

static enum dc_status dcn10_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1101

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1166

static enum dc_status dcn10_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1180

static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1191

static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1249

static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1327

static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1346

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1349

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1413

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1417

enum dc_status result = DC_OK;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1447

static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1470

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1472

enum dc_status result = DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1490

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1492

enum dc_status result = DC_OK;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2180

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2253

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

122

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

163

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

164

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

165

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

166

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

167

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1387

static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

960

static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1437

enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2200

enum dc_status dcn30_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

59

enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

96

enum dc_status dcn30_add_stream_to_ctx(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1914

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2417

enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

40

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

69

enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1856

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

42

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1982

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1987

enum dc_status status;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

101

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1888

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1910

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

38

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1868

static enum dc_status dcn351_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1875

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1788

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1795

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1800

enum dc_status status = DC_OK;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

23

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

25

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1839

enum dc_status dcn42_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

592

enum dc_status dcn42_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1805

enum dc_status dcn42b_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

552

enum dc_status dcn42b_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/arm/malidp_hw.c

1175

u32 status, mask, dc_status;

drivers/gpu/drm/arm/malidp_hw.c

1191

dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);

drivers/gpu/drm/arm/malidp_hw.c

1192

if (dc_status & hw->map.dc_irq_map.vsync_irq) {

drivers/gpu/drm/arm/malidp_hw.c

1193

malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);