drivers/accel/amdxdna/aie2_pci.c

517

ndev->priv = xdna->dev_info->dev_priv;

drivers/accel/amdxdna/amdxdna_pci_drv.h

82

const struct amdxdna_dev_priv *dev_priv;

drivers/accel/amdxdna/npu1_regs.c

122

.dev_priv = &npu1_dev_priv,

drivers/accel/amdxdna/npu4_regs.c

148

.dev_priv = &npu4_dev_priv,

drivers/accel/amdxdna/npu5_regs.c

113

.dev_priv = &npu5_dev_priv,

drivers/accel/amdxdna/npu6_regs.c

114

.dev_priv = &npu6_dev_priv,

drivers/bus/stm32_rifsc.c

403

bool dev_priv;

drivers/bus/stm32_rifsc.c

480

dbg_entry->dev_priv = priv_cfgr & BIT(reg_offset) ? true : false;

drivers/bus/stm32_rifsc.c

536

seq_printf(s, "| %-12s |", d_dbg_entry.dev_priv ? "PRIV" : "NPRIV");

drivers/gpu/drm/gma500/backlight.c

100

dev_priv->backlight_device =

drivers/gpu/drm/gma500/backlight.c

101

backlight_device_register(dev_priv->ops->backlight_name,

drivers/gpu/drm/gma500/backlight.c

104

if (IS_ERR(dev_priv->backlight_device))

drivers/gpu/drm/gma500/backlight.c

105

return PTR_ERR(dev_priv->backlight_device);

drivers/gpu/drm/gma500/backlight.c

114

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

116

if (dev_priv->backlight_device)

drivers/gpu/drm/gma500/backlight.c

117

backlight_device_unregister(dev_priv->backlight_device);

drivers/gpu/drm/gma500/backlight.c

24

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

26

dev_priv->backlight_enabled = true;

drivers/gpu/drm/gma500/backlight.c

27

dev_priv->ops->backlight_set(dev, dev_priv->backlight_level);

drivers/gpu/drm/gma500/backlight.c

32

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

34

dev_priv->backlight_enabled = false;

drivers/gpu/drm/gma500/backlight.c

35

dev_priv->ops->backlight_set(dev, 0);

drivers/gpu/drm/gma500/backlight.c

40

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

42

dev_priv->backlight_level = v;

drivers/gpu/drm/gma500/backlight.c

43

if (dev_priv->backlight_enabled)

drivers/gpu/drm/gma500/backlight.c

44

dev_priv->ops->backlight_set(dev, v);

drivers/gpu/drm/gma500/backlight.c

50

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

52

if (dev_priv->ops->backlight_get)

drivers/gpu/drm/gma500/backlight.c

53

return dev_priv->ops->backlight_get(dev);

drivers/gpu/drm/gma500/backlight.c

55

return dev_priv->backlight_level;

drivers/gpu/drm/gma500/backlight.c

78

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/backlight.c

82

dev_priv->backlight_enabled = true;

drivers/gpu/drm/gma500/backlight.c

83

dev_priv->backlight_level = 100;

drivers/gpu/drm/gma500/backlight.c

85

ret = dev_priv->ops->backlight_init(dev);

drivers/gpu/drm/gma500/backlight.c

91

dev_priv->ops->backlight_name);

drivers/gpu/drm/gma500/backlight.c

96

props.brightness = dev_priv->backlight_level;

drivers/gpu/drm/gma500/cdv_device.c

132

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

134

dev_priv->backlight_level = cdv_get_brightness(dev);

drivers/gpu/drm/gma500/cdv_device.c

135

cdv_set_brightness(dev, dev_priv->backlight_level);

drivers/gpu/drm/gma500/cdv_device.c

178

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

184

dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,

drivers/gpu/drm/gma500/cdv_device.c

186

dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,

drivers/gpu/drm/gma500/cdv_device.c

190

pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

195

outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

199

u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);

drivers/gpu/drm/gma500/cdv_device.c

231

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

233

struct psb_save_area *regs = &dev_priv->regs;

drivers/gpu/drm/gma500/cdv_device.c

289

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

291

struct psb_save_area *regs = &dev_priv->regs;

drivers/gpu/drm/gma500/cdv_device.c

361

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

365

pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

370

outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

373

pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);

drivers/gpu/drm/gma500/cdv_device.c

383

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

387

pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

392

outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

drivers/gpu/drm/gma500/cdv_device.c

395

pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);

drivers/gpu/drm/gma500/cdv_device.c

405

struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,

drivers/gpu/drm/gma500/cdv_device.c

407

struct drm_device *dev = &dev_priv->dev;

drivers/gpu/drm/gma500/cdv_device.c

418

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

419

schedule_work(&dev_priv->hotplug_work);

drivers/gpu/drm/gma500/cdv_device.c

42

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

446

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

450

prop = dev_priv->force_audio_property;

drivers/gpu/drm/gma500/cdv_device.c

461

dev_priv->force_audio_property = prop;

drivers/gpu/drm/gma500/cdv_device.c

475

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

479

prop = dev_priv->broadcast_rgb_property;

drivers/gpu/drm/gma500/cdv_device.c

48

cdv_intel_crt_init(dev, &dev_priv->mode_dev);

drivers/gpu/drm/gma500/cdv_device.c

49

cdv_intel_lvds_init(dev, &dev_priv->mode_dev);

drivers/gpu/drm/gma500/cdv_device.c

490

dev_priv->broadcast_rgb_property = prop;

drivers/gpu/drm/gma500/cdv_device.c

53

cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);

drivers/gpu/drm/gma500/cdv_device.c

55

cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);

drivers/gpu/drm/gma500/cdv_device.c

552

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_device.c

553

INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);

drivers/gpu/drm/gma500/cdv_device.c

555

dev_priv->use_msi = true;

drivers/gpu/drm/gma500/cdv_device.c

556

dev_priv->regmap = cdv_regmap;

drivers/gpu/drm/gma500/cdv_device.c

59

cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);

drivers/gpu/drm/gma500/cdv_device.c

61

cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);

drivers/gpu/drm/gma500/cdv_intel_display.c

460

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

463

crtc = dev_priv->pipe_to_crtc_mapping[pipe];

drivers/gpu/drm/gma500/cdv_intel_display.c

494

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

552

dev_priv->ops->disable_sr(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

579

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

582

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/cdv_intel_display.c

628

if (dev_priv->dplla_96mhz)

drivers/gpu/drm/gma500/cdv_intel_display.c

649

if (is_lvds && dev_priv->lvds_use_ssc) {

drivers/gpu/drm/gma500/cdv_intel_display.c

650

refclk = dev_priv->lvds_ssc_freq * 1000;

drivers/gpu/drm/gma500/cdv_intel_display.c

651

DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);

drivers/gpu/drm/gma500/cdv_intel_display.c

689

switch (dev_priv->edp.bpp) {

drivers/gpu/drm/gma500/cdv_intel_display.c

839

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

842

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/cdv_intel_display.c

847

struct psb_pipe *p = &dev_priv->regs.pipe[pipe];

drivers/gpu/drm/gma500/cdv_intel_display.c

865

(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);

drivers/gpu/drm/gma500/cdv_intel_display.c

920

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_display.c

921

struct psb_pipe *p = &dev_priv->regs.pipe[pipe];

drivers/gpu/drm/gma500/cdv_intel_display.c

922

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/cdv_intel_dp.c

1005

intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1011

bpp = dev_priv->edp.bpp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1041

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1107

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1169

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1230

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1275

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1334

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1358

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1382

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1401

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1467

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1560

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1643

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1666

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1693

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1727

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1742

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1760

if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1762

drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1783

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1807

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1809

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1816

if (property == dev_priv->force_audio_property) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1837

if (property == dev_priv->broadcast_rgb_property) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1863

struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1906

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1910

if (!dev_priv->child_dev_num)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1913

for (i = 0; i < dev_priv->child_dev_num; i++) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1914

p_child = dev_priv->child_dev + i;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1983

gma_encoder->dev_priv=intel_dp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

324

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

342

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

380

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

415

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

443

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

494

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

512

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

515

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/cdv_intel_dp.c

527

(cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)

drivers/gpu/drm/gma500/cdv_intel_dp.c

571

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

848

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

894

struct drm_psb_private *dev_priv = to_drm_psb_private(encoder->dev);

drivers/gpu/drm/gma500/cdv_intel_dp.c

896

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

907

bpp = dev_priv->edp.bpp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

986

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

112

struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

121

struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

131

struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

341

gma_encoder->dev_priv = hdmi_priv;

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

68

struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

96

struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

100

dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |

drivers/gpu/drm/gma500/cdv_intel_lvds.c

111

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

125

dev_priv->mode_dev.backlight_duty_cycle);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

160

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

162

dev_priv->mode_dev.panel_fixed_mode;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

186

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

187

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

233

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

234

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

251

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

252

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

266

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

291

if (dev_priv->lvds_dither)

drivers/gpu/drm/gma500/cdv_intel_lvds.c

303

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

304

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

430

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

433

if (!dev_priv->child_dev_num)

drivers/gpu/drm/gma500/cdv_intel_lvds.c

436

for (i = 0; i < dev_priv->child_dev_num; i++) {

drivers/gpu/drm/gma500/cdv_intel_lvds.c

437

struct child_device_config *child = dev_priv->child_dev + i;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

463

if (dev_priv->opregion.vbt)

drivers/gpu/drm/gma500/cdv_intel_lvds.c

488

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

495

if (!dev_priv->lvds_enabled_in_vbt)

drivers/gpu/drm/gma500/cdv_intel_lvds.c

516

gma_encoder->dev_priv = lvds_priv;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

557

dev_priv->backlight_property,

drivers/gpu/drm/gma500/cdv_intel_lvds.c

571

dev_priv->lvds_i2c_bus = gma_encoder->i2c_bus;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

599

if (dev_priv->lfp_lvds_vbt_mode) {

drivers/gpu/drm/gma500/cdv_intel_lvds.c

601

drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

63

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

73

retval = ((dev_priv->regs.saveBLC_PWM_CTL &

drivers/gpu/drm/gma500/cdv_intel_lvds.c

87

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

98

blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &

drivers/gpu/drm/gma500/fbdev.c

109

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/fbdev.c

137

if (size > dev_priv->vram_stolen_size) {

drivers/gpu/drm/gma500/fbdev.c

173

info->screen_base = dev_priv->vram_addr + backing->offset;

drivers/gpu/drm/gma500/fbdev.c

178

info->fix.smem_start = dev_priv->stolen_base + backing->offset;

drivers/gpu/drm/gma500/framebuffer.c

128

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/framebuffer.c

135

if (!dev_priv->backlight_property)

drivers/gpu/drm/gma500/framebuffer.c

136

dev_priv->backlight_property = drm_property_create_range(dev, 0,

drivers/gpu/drm/gma500/framebuffer.c

138

dev_priv->ops->output_init(dev);

drivers/gpu/drm/gma500/framebuffer.c

153

crtc_mask = dev_priv->ops->sdvo_mask;

drivers/gpu/drm/gma500/framebuffer.c

157

crtc_mask = dev_priv->ops->lvds_mask;

drivers/gpu/drm/gma500/framebuffer.c

169

crtc_mask = dev_priv->ops->hdmi_mask;

drivers/gpu/drm/gma500/framebuffer.c

189

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/framebuffer.c

190

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/framebuffer.c

202

for (i = 0; i < dev_priv->num_pipe; i++)

drivers/gpu/drm/gma500/framebuffer.c

210

if (dev_priv->ops->errata)

drivers/gpu/drm/gma500/framebuffer.c

211

dev_priv->ops->errata(dev);

drivers/gpu/drm/gma500/framebuffer.c

213

dev_priv->modeset = true;

drivers/gpu/drm/gma500/framebuffer.c

218

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/framebuffer.c

219

if (dev_priv->modeset) {

drivers/gpu/drm/gma500/gem.c

142

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

156

ret = psb_gtt_allocate_resource(dev_priv, &pobj->resource, name, size, align, stolen,

drivers/gpu/drm/gma500/gem.c

265

struct drm_psb_private *dev_priv;

drivers/gpu/drm/gma500/gem.c

269

dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

275

mutex_lock(&dev_priv->mmap_mutex);

drivers/gpu/drm/gma500/gem.c

295

pfn = (dev_priv->stolen_base + pobj->offset) >> PAGE_SHIFT;

drivers/gpu/drm/gma500/gem.c

300

mutex_unlock(&dev_priv->mmap_mutex);

drivers/gpu/drm/gma500/gem.c

33

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

333

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

339

mutex_init(&dev_priv->mmap_mutex);

drivers/gpu/drm/gma500/gem.c

34

u32 gpu_base = dev_priv->gtt.gatt_start;

drivers/gpu/drm/gma500/gem.c

341

pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/gem.c

343

pci_read_config_dword(pdev, PSB_BSM, &dev_priv->stolen_base);

drivers/gpu/drm/gma500/gem.c

344

vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base - PAGE_SIZE;

drivers/gpu/drm/gma500/gem.c

349

dev_priv->stolen_base, vram_stolen_size / 1024);

drivers/gpu/drm/gma500/gem.c

352

dev_priv->vram_stolen_size = vram_stolen_size;

drivers/gpu/drm/gma500/gem.c

354

dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, stolen_size);

drivers/gpu/drm/gma500/gem.c

355

if (!dev_priv->vram_addr) {

drivers/gpu/drm/gma500/gem.c

361

psb_gem_mm_populate_stolen(dev_priv);

drivers/gpu/drm/gma500/gem.c

366

mutex_destroy(&dev_priv->mmap_mutex);

drivers/gpu/drm/gma500/gem.c

372

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

374

iounmap(dev_priv->vram_addr);

drivers/gpu/drm/gma500/gem.c

376

mutex_destroy(&dev_priv->mmap_mutex);

drivers/gpu/drm/gma500/gem.c

408

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

413

pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/gem.c

415

pci_read_config_dword(pdev, PSB_BSM, &dev_priv->stolen_base);

drivers/gpu/drm/gma500/gem.c

416

vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base - PAGE_SIZE;

drivers/gpu/drm/gma500/gem.c

420

dev_dbg(dev->dev, "Stolen memory base 0x%x, size %luK\n", dev_priv->stolen_base,

drivers/gpu/drm/gma500/gem.c

428

psb_gem_mm_populate_stolen(dev_priv);

drivers/gpu/drm/gma500/gem.c

429

psb_gem_mm_populate_resources(dev_priv);

drivers/gpu/drm/gma500/gem.c

56

psb_gtt_insert_pages(dev_priv, &pobj->resource, pages);

drivers/gpu/drm/gma500/gem.c

57

psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu), pages,

drivers/gpu/drm/gma500/gem.c

78

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gem.c

79

u32 gpu_base = dev_priv->gtt.gatt_start;

drivers/gpu/drm/gma500/gem.c

96

psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu),

drivers/gpu/drm/gma500/gem.c

98

psb_gtt_remove_pages(dev_priv, &pobj->resource);

drivers/gpu/drm/gma500/gma_device.c

18

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_device.c

29

dev_priv->core_freq = 100;

drivers/gpu/drm/gma500/gma_device.c

32

dev_priv->core_freq = 133;

drivers/gpu/drm/gma500/gma_device.c

35

dev_priv->core_freq = 150;

drivers/gpu/drm/gma500/gma_device.c

38

dev_priv->core_freq = 178;

drivers/gpu/drm/gma500/gma_device.c

41

dev_priv->core_freq = 200;

drivers/gpu/drm/gma500/gma_device.c

46

dev_priv->core_freq = 266;

drivers/gpu/drm/gma500/gma_device.c

49

dev_priv->core_freq = 0;

drivers/gpu/drm/gma500/gma_display.c

147

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

149

const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];

drivers/gpu/drm/gma500/gma_display.c

173

dev_priv->regs.pipe[0].palette[i] =

drivers/gpu/drm/gma500/gma_display.c

200

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

203

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/gma_display.c

211

dev_priv->ops->disable_sr(dev);

drivers/gpu/drm/gma500/gma_display.c

323

dev_priv->ops->update_wm(dev, crtc);

drivers/gpu/drm/gma500/gma_display.c

334

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

393

if (dev_priv->ops->cursor_needs_phys) {

drivers/gpu/drm/gma500/gma_display.c

405

tmp_dst = dev_priv->vram_addr + cursor_pobj->offset;

drivers/gpu/drm/gma500/gma_display.c

578

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

581

const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];

drivers/gpu/drm/gma500/gma_display.c

62

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

621

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gma_display.c

624

const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];

drivers/gpu/drm/gma500/gma_display.c

67

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/gtt.c

128

static int psb_gtt_enable(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/gtt.c

130

struct drm_device *dev = &dev_priv->dev;

drivers/gpu/drm/gma500/gtt.c

134

ret = pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);

drivers/gpu/drm/gma500/gtt.c

137

ret = pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);

drivers/gpu/drm/gma500/gtt.c

141

dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);

drivers/gpu/drm/gma500/gtt.c

142

PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);

drivers/gpu/drm/gma500/gtt.c

149

static void psb_gtt_disable(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/gtt.c

151

struct drm_device *dev = &dev_priv->dev;

drivers/gpu/drm/gma500/gtt.c

154

pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl);

drivers/gpu/drm/gma500/gtt.c

155

PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);

drivers/gpu/drm/gma500/gtt.c

162

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gtt.c

164

iounmap(dev_priv->gtt_map);

drivers/gpu/drm/gma500/gtt.c

165

psb_gtt_disable(dev_priv);

drivers/gpu/drm/gma500/gtt.c

166

mutex_destroy(&dev_priv->gtt_mutex);

drivers/gpu/drm/gma500/gtt.c

185

static void psb_gtt_init_ranges(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/gtt.c

187

struct drm_device *dev = &dev_priv->dev;

drivers/gpu/drm/gma500/gtt.c

189

struct psb_gtt *pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/gtt.c

195

gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;

drivers/gpu/drm/gma500/gtt.c

212

gtt_start = dev_priv->pge_ctl;

drivers/gpu/drm/gma500/gtt.c

252

dev_priv->gtt_mem = gtt_mem;

drivers/gpu/drm/gma500/gtt.c

257

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gtt.c

258

struct psb_gtt *pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/gtt.c

261

mutex_init(&dev_priv->gtt_mutex);

drivers/gpu/drm/gma500/gtt.c

263

ret = psb_gtt_enable(dev_priv);

drivers/gpu/drm/gma500/gtt.c

267

psb_gtt_init_ranges(dev_priv);

drivers/gpu/drm/gma500/gtt.c

269

dev_priv->gtt_map = ioremap(pg->gtt_phys_start, pg->gtt_pages << PAGE_SHIFT);

drivers/gpu/drm/gma500/gtt.c

270

if (!dev_priv->gtt_map) {

drivers/gpu/drm/gma500/gtt.c

276

psb_gtt_clear(dev_priv);

drivers/gpu/drm/gma500/gtt.c

281

psb_gtt_disable(dev_priv);

drivers/gpu/drm/gma500/gtt.c

283

mutex_destroy(&dev_priv->gtt_mutex);

drivers/gpu/drm/gma500/gtt.c

289

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/gtt.c

290

struct psb_gtt *pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/gtt.c

295

ret = psb_gtt_enable(dev_priv);

drivers/gpu/drm/gma500/gtt.c

299

psb_gtt_init_ranges(dev_priv);

drivers/gpu/drm/gma500/gtt.c

307

psb_gtt_clear(dev_priv);

drivers/gpu/drm/gma500/gtt.c

310

psb_gtt_disable(dev_priv);

drivers/gpu/drm/gma500/intel_bios.c

100

dev_priv->edp.lanes = 4;

drivers/gpu/drm/gma500/intel_bios.c

104

dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp);

drivers/gpu/drm/gma500/intel_bios.c

108

dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;

drivers/gpu/drm/gma500/intel_bios.c

111

dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;

drivers/gpu/drm/gma500/intel_bios.c

114

dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;

drivers/gpu/drm/gma500/intel_bios.c

117

dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;

drivers/gpu/drm/gma500/intel_bios.c

122

dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;

drivers/gpu/drm/gma500/intel_bios.c

125

dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;

drivers/gpu/drm/gma500/intel_bios.c

128

dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;

drivers/gpu/drm/gma500/intel_bios.c

131

dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;

drivers/gpu/drm/gma500/intel_bios.c

135

dev_priv->edp.vswing, dev_priv->edp.preemphasis);

drivers/gpu/drm/gma500/intel_bios.c

190

static void parse_backlight_data(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

200

dev_priv->lvds_bl = NULL;

drivers/gpu/drm/gma500/intel_bios.c

212

dev_err(dev_priv->dev.dev, "out of memory for backlight data\n");

drivers/gpu/drm/gma500/intel_bios.c

215

dev_priv->lvds_bl = lvds_bl;

drivers/gpu/drm/gma500/intel_bios.c

219

static void parse_lfp_panel_data(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

229

dev_priv->lvds_dither = 0;

drivers/gpu/drm/gma500/intel_bios.c

230

dev_priv->lvds_vbt = 0;

drivers/gpu/drm/gma500/intel_bios.c

236

dev_priv->lvds_dither = lvds_options->pixel_dither;

drivers/gpu/drm/gma500/intel_bios.c

237

dev_priv->panel_type = lvds_options->panel_type;

drivers/gpu/drm/gma500/intel_bios.c

252

dev_err(dev_priv->dev.dev, "out of memory for fixed panel mode\n");

drivers/gpu/drm/gma500/intel_bios.c

256

dev_priv->lvds_vbt = 1;

drivers/gpu/drm/gma500/intel_bios.c

260

dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;

drivers/gpu/drm/gma500/intel_bios.c

263

dev_dbg(dev_priv->dev.dev, "ignoring invalid LVDS VBT\n");

drivers/gpu/drm/gma500/intel_bios.c

264

dev_priv->lvds_vbt = 0;

drivers/gpu/drm/gma500/intel_bios.c

271

static void parse_sdvo_panel_data(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

278

dev_priv->sdvo_lvds_vbt_mode = NULL;

drivers/gpu/drm/gma500/intel_bios.c

296

dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;

drivers/gpu/drm/gma500/intel_bios.c

301

static void parse_general_features(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

307

dev_priv->int_tv_support = 1;

drivers/gpu/drm/gma500/intel_bios.c

308

dev_priv->int_crt_support = 1;

drivers/gpu/drm/gma500/intel_bios.c

312

dev_priv->int_tv_support = general->int_tv_support;

drivers/gpu/drm/gma500/intel_bios.c

313

dev_priv->int_crt_support = general->int_crt_support;

drivers/gpu/drm/gma500/intel_bios.c

314

dev_priv->lvds_use_ssc = general->enable_ssc;

drivers/gpu/drm/gma500/intel_bios.c

316

if (dev_priv->lvds_use_ssc) {

drivers/gpu/drm/gma500/intel_bios.c

317

dev_priv->lvds_ssc_freq

drivers/gpu/drm/gma500/intel_bios.c

324

parse_sdvo_device_mapping(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

379

p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);

drivers/gpu/drm/gma500/intel_bios.c

415

parse_driver_features(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

425

dev_priv->edp.support = 1;

drivers/gpu/drm/gma500/intel_bios.c

427

dev_priv->lvds_enabled_in_vbt = driver->lvds_config != 0;

drivers/gpu/drm/gma500/intel_bios.c

432

dev_priv->dplla_96mhz = true;

drivers/gpu/drm/gma500/intel_bios.c

434

dev_priv->dplla_96mhz = false;

drivers/gpu/drm/gma500/intel_bios.c

438

parse_device_mapping(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_bios.c

47

parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb)

drivers/gpu/drm/gma500/intel_bios.c

480

dev_priv->child_dev = kzalloc_objs(*p_child, count);

drivers/gpu/drm/gma500/intel_bios.c

481

if (!dev_priv->child_dev) {

drivers/gpu/drm/gma500/intel_bios.c

486

dev_priv->child_dev_num = count;

drivers/gpu/drm/gma500/intel_bios.c

494

child_dev_ptr = dev_priv->child_dev + count;

drivers/gpu/drm/gma500/intel_bios.c

519

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/intel_bios.c

528

dev_priv->panel_type = 0xff;

drivers/gpu/drm/gma500/intel_bios.c

531

if (dev_priv->opregion.vbt) {

drivers/gpu/drm/gma500/intel_bios.c

532

struct vbt_header *vbt = dev_priv->opregion.vbt;

drivers/gpu/drm/gma500/intel_bios.c

538

dev_priv->opregion.vbt = NULL;

drivers/gpu/drm/gma500/intel_bios.c

56

dev_priv->edp.bpp = 18;

drivers/gpu/drm/gma500/intel_bios.c

563

parse_general_features(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

564

parse_driver_features(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

565

parse_lfp_panel_data(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

566

parse_sdvo_panel_data(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

567

parse_sdvo_device_mapping(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

568

parse_device_mapping(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

569

parse_backlight_data(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

570

parse_edp(dev_priv, bdb);

drivers/gpu/drm/gma500/intel_bios.c

58

if (dev_priv->edp.support) {

drivers/gpu/drm/gma500/intel_bios.c

583

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/intel_bios.c

585

kfree(dev_priv->sdvo_lvds_vbt_mode);

drivers/gpu/drm/gma500/intel_bios.c

586

kfree(dev_priv->lfp_lvds_vbt_mode);

drivers/gpu/drm/gma500/intel_bios.c

587

kfree(dev_priv->lvds_bl);

drivers/gpu/drm/gma500/intel_bios.c

60

dev_priv->edp.bpp);

drivers/gpu/drm/gma500/intel_bios.c

65

panel_type = dev_priv->panel_type;

drivers/gpu/drm/gma500/intel_bios.c

68

dev_priv->edp.bpp = 18;

drivers/gpu/drm/gma500/intel_bios.c

71

dev_priv->edp.bpp = 24;

drivers/gpu/drm/gma500/intel_bios.c

74

dev_priv->edp.bpp = 30;

drivers/gpu/drm/gma500/intel_bios.c

82

dev_priv->edp.pps = *edp_pps;

drivers/gpu/drm/gma500/intel_bios.c

85

dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,

drivers/gpu/drm/gma500/intel_bios.c

86

dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,

drivers/gpu/drm/gma500/intel_bios.c

87

dev_priv->edp.pps.t11_t12);

drivers/gpu/drm/gma500/intel_bios.c

89

dev_priv->edp.rate = edp_link_params->rate ? DP_LINK_BW_2_7 :

drivers/gpu/drm/gma500/intel_bios.c

93

dev_priv->edp.lanes = 1;

drivers/gpu/drm/gma500/intel_bios.c

96

dev_priv->edp.lanes = 2;

drivers/gpu/drm/gma500/intel_gmbus.c

107

struct drm_psb_private *dev_priv = gpio->dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

121

struct drm_psb_private *dev_priv = gpio->dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

131

struct drm_psb_private *dev_priv = gpio->dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

141

struct drm_psb_private *dev_priv = gpio->dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

158

struct drm_psb_private *dev_priv = gpio->dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

173

intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)

drivers/gpu/drm/gma500/intel_gmbus.c

195

gpio->dev_priv = dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

201

gpio->adapter.dev.parent = dev_priv->dev.dev;

drivers/gpu/drm/gma500/intel_gmbus.c

221

intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/intel_gmbus.c

231

gma_intel_i2c_reset(&dev_priv->dev);

drivers/gpu/drm/gma500/intel_gmbus.c

233

intel_i2c_quirk_set(dev_priv, true);

drivers/gpu/drm/gma500/intel_gmbus.c

242

intel_i2c_quirk_set(dev_priv, false);

drivers/gpu/drm/gma500/intel_gmbus.c

255

struct drm_psb_private *dev_priv = adapter->algo_data;

drivers/gpu/drm/gma500/intel_gmbus.c

259

return intel_i2c_quirk_xfer(dev_priv,

drivers/gpu/drm/gma500/intel_gmbus.c

356

bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);

drivers/gpu/drm/gma500/intel_gmbus.c

360

return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);

drivers/gpu/drm/gma500/intel_gmbus.c

399

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/intel_gmbus.c

402

dev_priv->gmbus = kzalloc_objs(struct intel_gmbus, GMBUS_NUM_PORTS);

drivers/gpu/drm/gma500/intel_gmbus.c

403

if (dev_priv->gmbus == NULL)

drivers/gpu/drm/gma500/intel_gmbus.c

407

dev_priv->gmbus_reg = dev_priv->aux_reg;

drivers/gpu/drm/gma500/intel_gmbus.c

409

dev_priv->gmbus_reg = dev_priv->vdc_reg;

drivers/gpu/drm/gma500/intel_gmbus.c

412

struct intel_gmbus *bus = &dev_priv->gmbus[i];

drivers/gpu/drm/gma500/intel_gmbus.c

421

bus->adapter.algo_data = dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

432

bus->force_bit = intel_gpio_create(dev_priv, i);

drivers/gpu/drm/gma500/intel_gmbus.c

435

gma_intel_i2c_reset(&dev_priv->dev);

drivers/gpu/drm/gma500/intel_gmbus.c

441

struct intel_gmbus *bus = &dev_priv->gmbus[i];

drivers/gpu/drm/gma500/intel_gmbus.c

444

kfree(dev_priv->gmbus);

drivers/gpu/drm/gma500/intel_gmbus.c

445

dev_priv->gmbus = NULL;

drivers/gpu/drm/gma500/intel_gmbus.c

468

struct drm_psb_private *dev_priv = adapter->algo_data;

drivers/gpu/drm/gma500/intel_gmbus.c

469

bus->force_bit = intel_gpio_create(dev_priv,

drivers/gpu/drm/gma500/intel_gmbus.c

483

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/intel_gmbus.c

486

if (dev_priv->gmbus == NULL)

drivers/gpu/drm/gma500/intel_gmbus.c

490

struct intel_gmbus *bus = &dev_priv->gmbus[i];

drivers/gpu/drm/gma500/intel_gmbus.c

498

dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */

drivers/gpu/drm/gma500/intel_gmbus.c

499

kfree(dev_priv->gmbus);

drivers/gpu/drm/gma500/intel_gmbus.c

500

dev_priv->gmbus = NULL;

drivers/gpu/drm/gma500/intel_gmbus.c

57

#define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))

drivers/gpu/drm/gma500/intel_gmbus.c

58

#define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))

drivers/gpu/drm/gma500/intel_gmbus.c

73

struct drm_psb_private *dev_priv;

drivers/gpu/drm/gma500/intel_gmbus.c

80

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/intel_gmbus.c

84

static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)

drivers/gpu/drm/gma500/mid_bios.c

108

dev_priv->platform_rev_id = (uint8_t) platform_rev_id;

drivers/gpu/drm/gma500/mid_bios.c

110

dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id);

drivers/gpu/drm/gma500/mid_bios.c

163

static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)

drivers/gpu/drm/gma500/mid_bios.c

180

dev_priv->gct_data.bpi = bpi;

drivers/gpu/drm/gma500/mid_bios.c

181

dev_priv->gct_data.pt = gct.PD.PanelType;

drivers/gpu/drm/gma500/mid_bios.c

182

dev_priv->gct_data.DTD = gct.panel[bpi].DTD;

drivers/gpu/drm/gma500/mid_bios.c

183

dev_priv->gct_data.Panel_Port_Control =

drivers/gpu/drm/gma500/mid_bios.c

185

dev_priv->gct_data.Panel_MIPI_Display_Descriptor =

drivers/gpu/drm/gma500/mid_bios.c

191

static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)

drivers/gpu/drm/gma500/mid_bios.c

208

dev_priv->gct_data.bpi = bpi;

drivers/gpu/drm/gma500/mid_bios.c

209

dev_priv->gct_data.pt = gct.PD.PanelType;

drivers/gpu/drm/gma500/mid_bios.c

210

dev_priv->gct_data.DTD = gct.panel[bpi].DTD;

drivers/gpu/drm/gma500/mid_bios.c

211

dev_priv->gct_data.Panel_Port_Control =

drivers/gpu/drm/gma500/mid_bios.c

213

dev_priv->gct_data.Panel_MIPI_Display_Descriptor =

drivers/gpu/drm/gma500/mid_bios.c

219

static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)

drivers/gpu/drm/gma500/mid_bios.c

22

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mid_bios.c

224

struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;

drivers/gpu/drm/gma500/mid_bios.c

242

dev_priv->gct_data.bpi = vbt.primary_panel_idx;

drivers/gpu/drm/gma500/mid_bios.c

243

dev_priv->gct_data.Panel_MIPI_Display_Descriptor =

drivers/gpu/drm/gma500/mid_bios.c

271

static void mid_get_vbt_data(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/mid_bios.c

273

struct drm_device *dev = &dev_priv->dev;

drivers/gpu/drm/gma500/mid_bios.c

312

ret = mid_get_vbt_data_r0(dev_priv, addr);

drivers/gpu/drm/gma500/mid_bios.c

315

ret = mid_get_vbt_data_r1(dev_priv, addr);

drivers/gpu/drm/gma500/mid_bios.c

318

ret = mid_get_vbt_data_r10(dev_priv, addr);

drivers/gpu/drm/gma500/mid_bios.c

328

dev_priv->has_gct = true;

drivers/gpu/drm/gma500/mid_bios.c

333

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mid_bios.c

335

mid_get_vbt_data(dev_priv);

drivers/gpu/drm/gma500/mid_bios.c

336

mid_get_pci_revID(dev_priv);

drivers/gpu/drm/gma500/mid_bios.c

49

dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;

drivers/gpu/drm/gma500/mid_bios.c

52

dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");

drivers/gpu/drm/gma500/mid_bios.c

55

if (dev_priv->iLVDS_enable) {

drivers/gpu/drm/gma500/mid_bios.c

56

dev_priv->is_lvds_on = true;

drivers/gpu/drm/gma500/mid_bios.c

57

dev_priv->is_mipi_on = false;

drivers/gpu/drm/gma500/mid_bios.c

59

dev_priv->is_mipi_on = true;

drivers/gpu/drm/gma500/mid_bios.c

60

dev_priv->is_lvds_on = false;

drivers/gpu/drm/gma500/mid_bios.c

63

dev_priv->video_device_fuse = fuse_value;

drivers/gpu/drm/gma500/mid_bios.c

71

dev_priv->fuse_reg_value = fuse_value;

drivers/gpu/drm/gma500/mid_bios.c

75

dev_priv->core_freq = 200;

drivers/gpu/drm/gma500/mid_bios.c

78

dev_priv->core_freq = 100;

drivers/gpu/drm/gma500/mid_bios.c

81

dev_priv->core_freq = 166;

drivers/gpu/drm/gma500/mid_bios.c

86

dev_priv->core_freq = 0;

drivers/gpu/drm/gma500/mid_bios.c

88

dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);

drivers/gpu/drm/gma500/mid_bios.c

95

static void mid_get_pci_revID(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/mid_bios.c

98

struct pci_dev *pdev = to_pci_dev(dev_priv->dev.dev);

drivers/gpu/drm/gma500/mmu.c

124

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mmu.c

234

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mmu.c

413

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mmu.c

426

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mmu.c

70

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/mmu.c

98

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_crtc.c

221

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_crtc.c

224

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/oaktrail_crtc.c

368

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_crtc.c

370

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/oaktrail_crtc.c

506

refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;

drivers/gpu/drm/gma500/oaktrail_crtc.c

597

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_crtc.c

601

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/oaktrail_crtc.c

89

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_crtc.c

93

switch (dev_priv->core_freq) {

drivers/gpu/drm/gma500/oaktrail_device.c

123

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

124

struct psb_save_area *regs = &dev_priv->regs;

drivers/gpu/drm/gma500/oaktrail_device.c

168

if (dev_priv->hdmi_priv)

drivers/gpu/drm/gma500/oaktrail_device.c

202

if (dev_priv->iLVDS_enable) {

drivers/gpu/drm/gma500/oaktrail_device.c

22

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

23

if (dev_priv->iLVDS_enable)

drivers/gpu/drm/gma500/oaktrail_device.c

237

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

238

struct psb_save_area *regs = &dev_priv->regs;

drivers/gpu/drm/gma500/oaktrail_device.c

24

oaktrail_lvds_init(dev, &dev_priv->mode_dev);

drivers/gpu/drm/gma500/oaktrail_device.c

27

if (dev_priv->hdmi_priv)

drivers/gpu/drm/gma500/oaktrail_device.c

278

if (dev_priv->iLVDS_enable)

drivers/gpu/drm/gma500/oaktrail_device.c

28

oaktrail_hdmi_init(dev, &dev_priv->mode_dev);

drivers/gpu/drm/gma500/oaktrail_device.c

299

if (dev_priv->hdmi_priv)

drivers/gpu/drm/gma500/oaktrail_device.c

302

if (dev_priv->iLVDS_enable) {

drivers/gpu/drm/gma500/oaktrail_device.c

352

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

357

outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);

drivers/gpu/drm/gma500/oaktrail_device.c

360

pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);

drivers/gpu/drm/gma500/oaktrail_device.c

376

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

380

pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);

drivers/gpu/drm/gma500/oaktrail_device.c

382

outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));

drivers/gpu/drm/gma500/oaktrail_device.c

385

pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);

drivers/gpu/drm/gma500/oaktrail_device.c

448

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

451

dev_priv->use_msi = true;

drivers/gpu/drm/gma500/oaktrail_device.c

452

dev_priv->regmap = oaktrail_regmap;

drivers/gpu/drm/gma500/oaktrail_device.c

457

if (!dev_priv->has_gct) {

drivers/gpu/drm/gma500/oaktrail_device.c

469

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

47

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

473

if (!dev_priv->has_gct)

drivers/gpu/drm/gma500/oaktrail_device.c

59

blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;

drivers/gpu/drm/gma500/oaktrail_device.c

65

blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;

drivers/gpu/drm/gma500/oaktrail_device.c

77

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_device.c

83

dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;

drivers/gpu/drm/gma500/oaktrail_device.c

84

dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;

drivers/gpu/drm/gma500/oaktrail_device.c

89

core_clock = dev_priv->core_freq;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

137

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

138

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

152

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

153

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

271

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

272

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

501

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

502

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

536

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

537

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

671

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

709

dev_priv->hdmi_priv = hdmi_dev;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

724

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

725

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

741

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

742

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

743

struct psb_state *regs = &dev_priv->regs.psb;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

744

struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];

drivers/gpu/drm/gma500/oaktrail_hdmi.c

794

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

795

struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

796

struct psb_state *regs = &dev_priv->regs.psb;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

797

struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];

drivers/gpu/drm/gma500/oaktrail_lvds.c

109

if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)

drivers/gpu/drm/gma500/oaktrail_lvds.c

159

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

161

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/oaktrail_lvds.c

175

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

185

ret = ((dev_priv->regs.saveBLC_PWM_CTL &

drivers/gpu/drm/gma500/oaktrail_lvds.c

195

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

197

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/oaktrail_lvds.c

219

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

220

struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;

drivers/gpu/drm/gma500/oaktrail_lvds.c

225

if (dev_priv->has_gct) {

drivers/gpu/drm/gma500/oaktrail_lvds.c

270

if (dev_priv->lfp_lvds_vbt_mode)

drivers/gpu/drm/gma500/oaktrail_lvds.c

273

dev_priv->lfp_lvds_vbt_mode);

drivers/gpu/drm/gma500/oaktrail_lvds.c

299

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

315

dev_priv->is_lvds_on = true;

drivers/gpu/drm/gma500/oaktrail_lvds.c

340

dev_priv->backlight_property,

drivers/gpu/drm/gma500/oaktrail_lvds.c

344

if (dev_priv->has_gct)

drivers/gpu/drm/gma500/oaktrail_lvds.c

345

mode_dev->panel_wants_dither = (dev_priv->gct_data.

drivers/gpu/drm/gma500/oaktrail_lvds.c

347

if (dev_priv->lvds_dither)

drivers/gpu/drm/gma500/oaktrail_lvds.c

363

i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);

drivers/gpu/drm/gma500/oaktrail_lvds.c

367

if (edid == NULL && dev_priv->lpc_gpio_base) {

drivers/gpu/drm/gma500/oaktrail_lvds.c

41

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

52

dev_priv->is_lvds_on = true;

drivers/gpu/drm/gma500/oaktrail_lvds.c

53

if (dev_priv->ops->lvds_bl_power)

drivers/gpu/drm/gma500/oaktrail_lvds.c

54

dev_priv->ops->lvds_bl_power(dev, true);

drivers/gpu/drm/gma500/oaktrail_lvds.c

56

if (dev_priv->ops->lvds_bl_power)

drivers/gpu/drm/gma500/oaktrail_lvds.c

57

dev_priv->ops->lvds_bl_power(dev, false);

drivers/gpu/drm/gma500/oaktrail_lvds.c

63

dev_priv->is_lvds_on = false;

drivers/gpu/drm/gma500/oaktrail_lvds.c

86

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds.c

87

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c

134

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c

143

chan->reg = dev_priv->lpc_gpio_base;

drivers/gpu/drm/gma500/opregion.c

154

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

155

struct opregion_asle *asle = dev_priv->opregion.asle;

drivers/gpu/drm/gma500/opregion.c

177

struct drm_psb_private *dev_priv =

drivers/gpu/drm/gma500/opregion.c

193

asle_stat |= asle_set_backlight(&dev_priv->dev, asle->bclp);

drivers/gpu/drm/gma500/opregion.c

201

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

203

if (dev_priv->opregion.asle)

drivers/gpu/drm/gma500/opregion.c

204

schedule_work(&dev_priv->opregion.asle_work);

drivers/gpu/drm/gma500/opregion.c

214

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

215

struct opregion_asle *asle = dev_priv->opregion.asle;

drivers/gpu/drm/gma500/opregion.c

220

gma_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);

drivers/gpu/drm/gma500/opregion.c

221

gma_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);

drivers/gpu/drm/gma500/opregion.c

261

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

262

struct psb_intel_opregion *opregion = &dev_priv->opregion;

drivers/gpu/drm/gma500/opregion.c

281

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

282

struct psb_intel_opregion *opregion = &dev_priv->opregion;

drivers/gpu/drm/gma500/opregion.c

307

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/opregion.c

309

struct psb_intel_opregion *opregion = &dev_priv->opregion;

drivers/gpu/drm/gma500/power.c

100

dev_priv->ops->power_down(dev);

drivers/gpu/drm/gma500/power.c

113

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

116

dev_priv->ops->power_up(dev);

drivers/gpu/drm/gma500/power.c

118

PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);

drivers/gpu/drm/gma500/power.c

120

dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);

drivers/gpu/drm/gma500/power.c

125

dev_priv->ops->restore_regs(dev);

drivers/gpu/drm/gma500/power.c

137

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

142

dev_priv->regs.saveBSM = bsm;

drivers/gpu/drm/gma500/power.c

144

dev_priv->regs.saveVBT = vbt;

drivers/gpu/drm/gma500/power.c

160

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

164

pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM);

drivers/gpu/drm/gma500/power.c

165

pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT);

drivers/gpu/drm/gma500/power.c

48

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

51

dev_priv->apm_base = dev_priv->apm_reg & 0xffff;

drivers/gpu/drm/gma500/power.c

52

dev_priv->ospm_base &= 0xffff;

drivers/gpu/drm/gma500/power.c

54

if (dev_priv->ops->init_pm)

drivers/gpu/drm/gma500/power.c

55

dev_priv->ops->init_pm(dev);

drivers/gpu/drm/gma500/power.c

70

dev_priv->pm_initialized = true;

drivers/gpu/drm/gma500/power.c

81

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

83

if (!dev_priv->pm_initialized)

drivers/gpu/drm/gma500/power.c

97

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/power.c

99

dev_priv->ops->save_regs(dev);

drivers/gpu/drm/gma500/psb_device.c

105

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_device.c

110

struct psb_state *regs = &dev_priv->regs.psb;

drivers/gpu/drm/gma500/psb_device.c

126

dev_priv->ops->save_crtc(crtc);

drivers/gpu/drm/gma500/psb_device.c

149

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_device.c

154

struct psb_state *regs = &dev_priv->regs.psb;

drivers/gpu/drm/gma500/psb_device.c

172

dev_priv->ops->restore_crtc(crtc);

drivers/gpu/drm/gma500/psb_device.c

20

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_device.c

21

psb_intel_lvds_init(dev, &dev_priv->mode_dev);

drivers/gpu/drm/gma500/psb_device.c

250

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_device.c

251

dev_priv->regmap = psb_regmap;

drivers/gpu/drm/gma500/psb_device.c

43

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_device.c

52

if (!dev_priv->lvds_bl) {

drivers/gpu/drm/gma500/psb_device.c

56

bl_max_freq = dev_priv->lvds_bl->freq;

drivers/gpu/drm/gma500/psb_device.c

59

core_clock = dev_priv->core_freq;

drivers/gpu/drm/gma500/psb_device.c

87

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.c

104

static void psb_spank(struct drm_psb_private *dev_priv)

drivers/gpu/drm/gma500/psb_drv.c

125

PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);

drivers/gpu/drm/gma500/psb_drv.c

130

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.c

131

struct psb_gtt *pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/psb_drv.c

144

dev_priv->gatt_free_offset = pg->mmu_gatt_start +

drivers/gpu/drm/gma500/psb_drv.c

147

spin_lock_init(&dev_priv->irqmask_lock);

drivers/gpu/drm/gma500/psb_drv.c

158

psb_spank(dev_priv);

drivers/gpu/drm/gma500/psb_drv.c

169

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.c

178

if (dev_priv->ops->chip_teardown)

drivers/gpu/drm/gma500/psb_drv.c

179

dev_priv->ops->chip_teardown(dev);

drivers/gpu/drm/gma500/psb_drv.c

183

if (dev_priv->pf_pd) {

drivers/gpu/drm/gma500/psb_drv.c

184

psb_mmu_free_pagedir(dev_priv->pf_pd);

drivers/gpu/drm/gma500/psb_drv.c

185

dev_priv->pf_pd = NULL;

drivers/gpu/drm/gma500/psb_drv.c

187

if (dev_priv->mmu) {

drivers/gpu/drm/gma500/psb_drv.c

188

struct psb_gtt *pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/psb_drv.c

192

(dev_priv->mmu),

drivers/gpu/drm/gma500/psb_drv.c

194

dev_priv->vram_stolen_size >> PAGE_SHIFT);

drivers/gpu/drm/gma500/psb_drv.c

195

psb_mmu_driver_takedown(dev_priv->mmu);

drivers/gpu/drm/gma500/psb_drv.c

196

dev_priv->mmu = NULL;

drivers/gpu/drm/gma500/psb_drv.c

200

if (dev_priv->scratch_page) {

drivers/gpu/drm/gma500/psb_drv.c

201

set_pages_wb(dev_priv->scratch_page, 1);

drivers/gpu/drm/gma500/psb_drv.c

202

__free_page(dev_priv->scratch_page);

drivers/gpu/drm/gma500/psb_drv.c

203

dev_priv->scratch_page = NULL;

drivers/gpu/drm/gma500/psb_drv.c

205

if (dev_priv->vdc_reg) {

drivers/gpu/drm/gma500/psb_drv.c

206

iounmap(dev_priv->vdc_reg);

drivers/gpu/drm/gma500/psb_drv.c

207

dev_priv->vdc_reg = NULL;

drivers/gpu/drm/gma500/psb_drv.c

209

if (dev_priv->sgx_reg) {

drivers/gpu/drm/gma500/psb_drv.c

210

iounmap(dev_priv->sgx_reg);

drivers/gpu/drm/gma500/psb_drv.c

211

dev_priv->sgx_reg = NULL;

drivers/gpu/drm/gma500/psb_drv.c

213

if (dev_priv->aux_reg) {

drivers/gpu/drm/gma500/psb_drv.c

214

iounmap(dev_priv->aux_reg);

drivers/gpu/drm/gma500/psb_drv.c

215

dev_priv->aux_reg = NULL;

drivers/gpu/drm/gma500/psb_drv.c

217

pci_dev_put(dev_priv->aux_pdev);

drivers/gpu/drm/gma500/psb_drv.c

218

pci_dev_put(dev_priv->lpc_pdev);

drivers/gpu/drm/gma500/psb_drv.c

236

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.c

247

dev_priv->ops = (struct psb_ops *)flags;

drivers/gpu/drm/gma500/psb_drv.c

249

pg = &dev_priv->gtt;

drivers/gpu/drm/gma500/psb_drv.c

253

dev_priv->num_pipe = dev_priv->ops->pipes;

drivers/gpu/drm/gma500/psb_drv.c

257

dev_priv->vdc_reg =

drivers/gpu/drm/gma500/psb_drv.c

259

if (!dev_priv->vdc_reg)

drivers/gpu/drm/gma500/psb_drv.c

262

dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,

drivers/gpu/drm/gma500/psb_drv.c

264

if (!dev_priv->sgx_reg)

drivers/gpu/drm/gma500/psb_drv.c

270

dev_priv->aux_pdev =

drivers/gpu/drm/gma500/psb_drv.c

274

if (dev_priv->aux_pdev) {

drivers/gpu/drm/gma500/psb_drv.c

275

resource_start = pci_resource_start(dev_priv->aux_pdev,

drivers/gpu/drm/gma500/psb_drv.c

277

resource_len = pci_resource_len(dev_priv->aux_pdev,

drivers/gpu/drm/gma500/psb_drv.c

279

dev_priv->aux_reg = ioremap(resource_start,

drivers/gpu/drm/gma500/psb_drv.c

281

if (!dev_priv->aux_reg)

drivers/gpu/drm/gma500/psb_drv.c

287

dev_priv->aux_reg = dev_priv->vdc_reg;

drivers/gpu/drm/gma500/psb_drv.c

290

dev_priv->gmbus_reg = dev_priv->aux_reg;

drivers/gpu/drm/gma500/psb_drv.c

292

dev_priv->lpc_pdev =

drivers/gpu/drm/gma500/psb_drv.c

295

if (dev_priv->lpc_pdev) {

drivers/gpu/drm/gma500/psb_drv.c

296

pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,

drivers/gpu/drm/gma500/psb_drv.c

297

&dev_priv->lpc_gpio_base);

drivers/gpu/drm/gma500/psb_drv.c

298

pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA,

drivers/gpu/drm/gma500/psb_drv.c

299

(u32)dev_priv->lpc_gpio_base | (1L<<31));

drivers/gpu/drm/gma500/psb_drv.c

300

pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,

drivers/gpu/drm/gma500/psb_drv.c

301

&dev_priv->lpc_gpio_base);

drivers/gpu/drm/gma500/psb_drv.c

302

dev_priv->lpc_gpio_base &= 0xffc0;

drivers/gpu/drm/gma500/psb_drv.c

303

if (dev_priv->lpc_gpio_base)

drivers/gpu/drm/gma500/psb_drv.c

305

dev_priv->lpc_gpio_base);

drivers/gpu/drm/gma500/psb_drv.c

307

pci_dev_put(dev_priv->lpc_pdev);

drivers/gpu/drm/gma500/psb_drv.c

308

dev_priv->lpc_pdev = NULL;

drivers/gpu/drm/gma500/psb_drv.c

312

dev_priv->gmbus_reg = dev_priv->vdc_reg;

drivers/gpu/drm/gma500/psb_drv.c

317

ret = dev_priv->ops->chip_setup(dev);

drivers/gpu/drm/gma500/psb_drv.c

326

dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);

drivers/gpu/drm/gma500/psb_drv.c

327

if (!dev_priv->scratch_page)

drivers/gpu/drm/gma500/psb_drv.c

330

set_pages_uc(dev_priv->scratch_page, 1);

drivers/gpu/drm/gma500/psb_drv.c

341

dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, NULL);

drivers/gpu/drm/gma500/psb_drv.c

342

if (!dev_priv->mmu)

drivers/gpu/drm/gma500/psb_drv.c

345

dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);

drivers/gpu/drm/gma500/psb_drv.c

346

if (!dev_priv->pf_pd)

drivers/gpu/drm/gma500/psb_drv.c

354

ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu),

drivers/gpu/drm/gma500/psb_drv.c

355

dev_priv->stolen_base >> PAGE_SHIFT,

drivers/gpu/drm/gma500/psb_drv.c

359

psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);

drivers/gpu/drm/gma500/psb_drv.c

360

psb_mmu_set_pd_context(dev_priv->pf_pd, 1);

drivers/gpu/drm/gma500/psb_drv.c

368

ret = drm_vblank_init(dev, dev_priv->num_pipe);

drivers/gpu/drm/gma500/psb_drv.c

376

dev_priv->vdc_irq_mask = 0;

drivers/gpu/drm/gma500/psb_drv.c

377

dev_priv->pipestat[0] = 0;

drivers/gpu/drm/gma500/psb_drv.c

378

dev_priv->pipestat[1] = 0;

drivers/gpu/drm/gma500/psb_drv.c

379

dev_priv->pipestat[2] = 0;

drivers/gpu/drm/gma500/psb_drv.c

380

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_drv.c

384

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_drv.c

453

struct drm_psb_private *dev_priv;

drivers/gpu/drm/gma500/psb_drv.c

465

dev_priv = devm_drm_dev_alloc(&pdev->dev, &driver, struct drm_psb_private, dev);

drivers/gpu/drm/gma500/psb_drv.c

466

if (IS_ERR(dev_priv))

drivers/gpu/drm/gma500/psb_drv.c

467

return PTR_ERR(dev_priv);

drivers/gpu/drm/gma500/psb_drv.c

468

dev = &dev_priv->dev;

drivers/gpu/drm/gma500/psb_drv.h

650

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

651

return ioread32(dev_priv->vdc_reg + reg);

drivers/gpu/drm/gma500/psb_drv.h

656

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

657

return ioread32(dev_priv->aux_reg + reg);

drivers/gpu/drm/gma500/psb_drv.h

682

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

683

iowrite32((val), dev_priv->vdc_reg + (reg));

drivers/gpu/drm/gma500/psb_drv.h

689

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

690

iowrite32((val), dev_priv->aux_reg + (reg));

drivers/gpu/drm/gma500/psb_drv.h

710

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

711

iowrite16((val), dev_priv->vdc_reg + (reg));

drivers/gpu/drm/gma500/psb_drv.h

719

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_drv.h

720

iowrite8((val), dev_priv->vdc_reg + (reg));

drivers/gpu/drm/gma500/psb_drv.h

725

#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))

drivers/gpu/drm/gma500/psb_drv.h

726

#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))

drivers/gpu/drm/gma500/psb_drv.h

728

#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))

drivers/gpu/drm/gma500/psb_drv.h

729

#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))

drivers/gpu/drm/gma500/psb_drv.h

731

#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))

drivers/gpu/drm/gma500/psb_drv.h

732

#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))

drivers/gpu/drm/gma500/psb_intel_display.c

101

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_display.c

105

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/psb_intel_display.c

308

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_display.c

310

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/psb_intel_display.c

315

struct psb_pipe *p = &dev_priv->regs.pipe[pipe];

drivers/gpu/drm/gma500/psb_intel_display.c

333

is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &

drivers/gpu/drm/gma500/psb_intel_display.c

390

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_display.c

391

struct psb_pipe *p = &dev_priv->regs.pipe[pipe];

drivers/gpu/drm/gma500/psb_intel_display.c

392

const struct psb_offset *map = &dev_priv->regmap[pipe];

drivers/gpu/drm/gma500/psb_intel_display.c

449

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_display.c

454

if (dev_priv->ops->cursor_needs_phys) {

drivers/gpu/drm/gma500/psb_intel_display.c

464

gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset;

drivers/gpu/drm/gma500/psb_intel_display.c

477

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_display.c

500

gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;

drivers/gpu/drm/gma500/psb_intel_display.c

513

dev_priv->ops->crtc_helper);

drivers/gpu/drm/gma500/psb_intel_display.c

517

BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||

drivers/gpu/drm/gma500/psb_intel_display.c

518

dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);

drivers/gpu/drm/gma500/psb_intel_display.c

519

dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;

drivers/gpu/drm/gma500/psb_intel_display.c

520

dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;

drivers/gpu/drm/gma500/psb_intel_drv.h

102

void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */

drivers/gpu/drm/gma500/psb_intel_lvds.c

112

if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)

drivers/gpu/drm/gma500/psb_intel_lvds.c

115

out_buf[0] = dev_priv->lvds_bl->brightnesscmd;

drivers/gpu/drm/gma500/psb_intel_lvds.c

120

dev_priv->lvds_bl->brightnesscmd,

drivers/gpu/drm/gma500/psb_intel_lvds.c

132

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

144

if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)

drivers/gpu/drm/gma500/psb_intel_lvds.c

164

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

168

if (!dev_priv->lvds_bl) {

drivers/gpu/drm/gma500/psb_intel_lvds.c

173

if (dev_priv->lvds_bl->type == BLC_I2C_TYPE)

drivers/gpu/drm/gma500/psb_intel_lvds.c

186

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

195

dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |

drivers/gpu/drm/gma500/psb_intel_lvds.c

199

blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &

drivers/gpu/drm/gma500/psb_intel_lvds.c

201

dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |

drivers/gpu/drm/gma500/psb_intel_lvds.c

211

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

212

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/psb_intel_lvds.c

257

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

260

(struct psb_intel_lvds_priv *)gma_encoder->dev_priv;

drivers/gpu/drm/gma500/psb_intel_lvds.c

273

dev_priv->backlight_duty_cycle = (dev_priv->regs.saveBLC_PWM_CTL &

drivers/gpu/drm/gma500/psb_intel_lvds.c

280

if (dev_priv->backlight_duty_cycle == 0)

drivers/gpu/drm/gma500/psb_intel_lvds.c

281

dev_priv->backlight_duty_cycle =

drivers/gpu/drm/gma500/psb_intel_lvds.c

299

(struct psb_intel_lvds_priv *)gma_encoder->dev_priv;

drivers/gpu/drm/gma500/psb_intel_lvds.c

337

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

340

dev_priv->mode_dev.panel_fixed_mode;

drivers/gpu/drm/gma500/psb_intel_lvds.c

343

fixed_mode = dev_priv->mode_dev.panel_fixed_mode2;

drivers/gpu/drm/gma500/psb_intel_lvds.c

367

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

368

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/psb_intel_lvds.c

428

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

429

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/psb_intel_lvds.c

446

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

447

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/psb_intel_lvds.c

461

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

483

if (dev_priv->lvds_dither)

drivers/gpu/drm/gma500/psb_intel_lvds.c

495

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

496

struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;

drivers/gpu/drm/gma500/psb_intel_lvds.c

636

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

64

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

661

gma_encoder->dev_priv = lvds_priv;

drivers/gpu/drm/gma500/psb_intel_lvds.c

701

dev_priv->backlight_property,

drivers/gpu/drm/gma500/psb_intel_lvds.c

71

ret = dev_priv->regs.saveBLC_PWM_CTL;

drivers/gpu/drm/gma500/psb_intel_lvds.c

715

dev_priv->lvds_i2c_bus = lvds_priv->i2c_bus;

drivers/gpu/drm/gma500/psb_intel_lvds.c

744

if (dev_priv->lfp_lvds_vbt_mode) {

drivers/gpu/drm/gma500/psb_intel_lvds.c

746

drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);

drivers/gpu/drm/gma500/psb_intel_lvds.c

80

REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

93

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_lvds.c

95

struct gma_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1243

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1246

&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1512

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1525

if (dev_priv->sdvo_lvds_vbt_mode != NULL) {

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1527

dev_priv->sdvo_lvds_vbt_mode);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1597

struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1606

if (property == dev_priv->force_audio_property) {

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1627

if (property == dev_priv->broadcast_rgb_property) {

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1853

psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1859

mapping = &(dev_priv->sdvo_mappings[0]);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1861

mapping = &(dev_priv->sdvo_mappings[1]);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1870

psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1877

mapping = &dev_priv->sdvo_mappings[0];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1879

mapping = &dev_priv->sdvo_mappings[1];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1889

sdvo->i2c = &dev_priv->gmbus[pin].adapter;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1893

sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1905

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1909

my_mapping = &dev_priv->sdvo_mappings[0];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1910

other_mapping = &dev_priv->sdvo_mappings[1];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1912

my_mapping = &dev_priv->sdvo_mappings[1];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1913

other_mapping = &dev_priv->sdvo_mappings[0];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2440

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2451

psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2475

dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2477

dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2492

psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);

drivers/gpu/drm/gma500/psb_irq.c

153

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

201

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

206

spin_lock(&dev_priv->irqmask_lock);

drivers/gpu/drm/gma500/psb_irq.c

218

vdc_stat &= dev_priv->vdc_irq_mask;

drivers/gpu/drm/gma500/psb_irq.c

219

spin_unlock(&dev_priv->irqmask_lock);

drivers/gpu/drm/gma500/psb_irq.c

235

if (hotplug_int && dev_priv->ops->hotplug) {

drivers/gpu/drm/gma500/psb_irq.c

236

handled = dev_priv->ops->hotplug(dev);

drivers/gpu/drm/gma500/psb_irq.c

252

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

255

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

264

dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

266

dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

269

if (dev_priv->ops->hotplug)

drivers/gpu/drm/gma500/psb_irq.c

270

dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;

drivers/gpu/drm/gma500/psb_irq.c

271

dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

274

PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);

drivers/gpu/drm/gma500/psb_irq.c

275

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

280

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

284

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

292

PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);

drivers/gpu/drm/gma500/psb_irq.c

297

gma_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);

drivers/gpu/drm/gma500/psb_irq.c

299

gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);

drivers/gpu/drm/gma500/psb_irq.c

302

if (dev_priv->ops->hotplug_enable)

drivers/gpu/drm/gma500/psb_irq.c

303

dev_priv->ops->hotplug_enable(dev, true);

drivers/gpu/drm/gma500/psb_irq.c

305

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

310

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

314

if (dev_priv->use_msi && pci_enable_msi(pdev)) {

drivers/gpu/drm/gma500/psb_irq.c

316

dev_priv->use_msi = false;

drivers/gpu/drm/gma500/psb_irq.c

331

dev_priv->irq_enabled = true;

drivers/gpu/drm/gma500/psb_irq.c

338

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

343

if (!dev_priv->irq_enabled)

drivers/gpu/drm/gma500/psb_irq.c

346

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

348

if (dev_priv->ops->hotplug_enable)

drivers/gpu/drm/gma500/psb_irq.c

349

dev_priv->ops->hotplug_enable(dev, false);

drivers/gpu/drm/gma500/psb_irq.c

355

gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);

drivers/gpu/drm/gma500/psb_irq.c

358

dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |

drivers/gpu/drm/gma500/psb_irq.c

363

PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);

drivers/gpu/drm/gma500/psb_irq.c

364

PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);

drivers/gpu/drm/gma500/psb_irq.c

370

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

373

if (dev_priv->use_msi)

drivers/gpu/drm/gma500/psb_irq.c

381

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

394

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

397

dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

399

dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

401

PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);

drivers/gpu/drm/gma500/psb_irq.c

402

PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);

drivers/gpu/drm/gma500/psb_irq.c

403

gma_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);

drivers/gpu/drm/gma500/psb_irq.c

405

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

414

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

417

spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

420

dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

422

dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;

drivers/gpu/drm/gma500/psb_irq.c

424

PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);

drivers/gpu/drm/gma500/psb_irq.c

425

PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);

drivers/gpu/drm/gma500/psb_irq.c

426

gma_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);

drivers/gpu/drm/gma500/psb_irq.c

428

spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);

drivers/gpu/drm/gma500/psb_irq.c

47

void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)

drivers/gpu/drm/gma500/psb_irq.c

49

if ((dev_priv->pipestat[pipe] & mask) != mask) {

drivers/gpu/drm/gma500/psb_irq.c

51

dev_priv->pipestat[pipe] |= mask;

drivers/gpu/drm/gma500/psb_irq.c

53

if (gma_power_begin(&dev_priv->dev, false)) {

drivers/gpu/drm/gma500/psb_irq.c

58

gma_power_end(&dev_priv->dev);

drivers/gpu/drm/gma500/psb_irq.c

63

void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)

drivers/gpu/drm/gma500/psb_irq.c

65

if ((dev_priv->pipestat[pipe] & mask) != 0) {

drivers/gpu/drm/gma500/psb_irq.c

67

dev_priv->pipestat[pipe] &= ~mask;

drivers/gpu/drm/gma500/psb_irq.c

68

if (gma_power_begin(&dev_priv->dev, false)) {

drivers/gpu/drm/gma500/psb_irq.c

73

gma_power_end(&dev_priv->dev);

drivers/gpu/drm/gma500/psb_irq.c

83

struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

drivers/gpu/drm/gma500/psb_irq.c

87

uint32_t pipe_enable = dev_priv->pipestat[pipe];

drivers/gpu/drm/gma500/psb_irq.c

88

uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;

drivers/gpu/drm/gma500/psb_irq.c

92

spin_lock(&dev_priv->irqmask_lock);

drivers/gpu/drm/gma500/psb_irq.c

98

spin_unlock(&dev_priv->irqmask_lock);

drivers/gpu/drm/gma500/psb_irq.h

26

void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);

drivers/gpu/drm/gma500/psb_irq.h

27

void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);

drivers/gpu/drm/i915/display/dvo_ch7017.c

215

dvo->dev_priv = priv;

drivers/gpu/drm/i915/display/dvo_ch7017.c

400

struct ch7017_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ch7017.c

404

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

151

struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

189

struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

226

dvo->dev_priv = ch7xxx;

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

370

struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

374

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_ivch.c

196

struct ivch_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

239

struct ivch_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

277

dvo->dev_priv = priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

333

struct ivch_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

403

struct ivch_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

488

struct ivch_priv *priv = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ivch.c

492

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_ns2501.c

395

struct ns2501_priv *ns = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ns2501.c

440

struct ns2501_priv *ns = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ns2501.c

484

dvo->dev_priv = ns;

drivers/gpu/drm/i915/display/dvo_ns2501.c

554

struct ns2501_priv *ns = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ns2501.c

658

struct ns2501_priv *ns = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ns2501.c

694

struct ns2501_priv *ns = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_ns2501.c

698

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_sil164.c

114

struct sil164_priv *sil = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_sil164.c

151

dvo->dev_priv = sil;

drivers/gpu/drm/i915/display/dvo_sil164.c

274

struct sil164_priv *sil = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_sil164.c

278

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_sil164.c

77

struct sil164_priv *sil = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_tfp410.c

135

struct tfp410_priv *tfp = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_tfp410.c

183

dvo->dev_priv = tfp;

drivers/gpu/drm/i915/display/dvo_tfp410.c

304

struct tfp410_priv *tfp = dvo->dev_priv;

drivers/gpu/drm/i915/display/dvo_tfp410.c

308

dvo->dev_priv = NULL;

drivers/gpu/drm/i915/display/dvo_tfp410.c

98

struct tfp410_priv *tfp = dvo->dev_priv;

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

100

#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

107

#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

12

#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

15

#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

49

#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

52

#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

55

#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

58

#define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

65

#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

72

#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

76

#define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

83

#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

86

#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

89

#define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

93

#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

44

#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

55

#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

71

#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

9

#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)

drivers/gpu/drm/i915/display/intel_color_regs.h

264

#define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)

drivers/gpu/drm/i915/display/intel_color_regs.h

265

#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)

drivers/gpu/drm/i915/display/intel_color_regs.h

266

#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)

drivers/gpu/drm/i915/display/intel_color_regs.h

267

#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)

drivers/gpu/drm/i915/display/intel_color_regs.h

268

#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)

drivers/gpu/drm/i915/display/intel_color_regs.h

269

#define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)

drivers/gpu/drm/i915/display/intel_color_regs.h

33

#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \

drivers/gpu/drm/i915/display/intel_color_regs.h

42

#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */

drivers/gpu/drm/i915/display/intel_cursor_regs.h

12

#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

44

#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

47

#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

56

#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

59

#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

66

#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

72

#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A)

drivers/gpu/drm/i915/display/intel_cursor_regs.h

75

#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE)

drivers/gpu/drm/i915/display/intel_display_regs.h

1001

#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1002

#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1003

#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1025

#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1029

#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1033

#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1037

#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1041

#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1045

#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1049

#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1053

#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)

drivers/gpu/drm/i915/display/intel_display_regs.h

123

#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

drivers/gpu/drm/i915/display/intel_display_regs.h

1946

#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

1950

#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1954

#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1958

#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1962

#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1966

#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1971

#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\

drivers/gpu/drm/i915/display/intel_display_regs.h

1976

#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1991

#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

1995

#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1999

#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

2003

#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

223

#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

drivers/gpu/drm/i915/display/intel_display_regs.h

2235

#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2292

#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2306

#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2333

#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2483

#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)

drivers/gpu/drm/i915/display/intel_display_regs.h

2490

#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)

drivers/gpu/drm/i915/display/intel_display_regs.h

2935

#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

348

#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

356

#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

364

#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

372

#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

380

#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

388

#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

396

#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)

drivers/gpu/drm/i915/display/intel_display_regs.h

404

#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

408

#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

412

#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

415

#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)

drivers/gpu/drm/i915/display/intel_display_regs.h

445

#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)

drivers/gpu/drm/i915/display/intel_display_regs.h

516

#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)

drivers/gpu/drm/i915/display/intel_display_regs.h

726

#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)

drivers/gpu/drm/i915/display/intel_display_regs.h

731

#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)

drivers/gpu/drm/i915/display/intel_display_regs.h

791

#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)

drivers/gpu/drm/i915/display/intel_display_regs.h

842

#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

953

#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)

drivers/gpu/drm/i915/display/intel_display_regs.h

958

#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)

drivers/gpu/drm/i915/display/intel_display_regs.h

966

#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)

drivers/gpu/drm/i915/display/intel_display_regs.h

969

#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)

drivers/gpu/drm/i915/display/intel_display_regs.h

973

#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

980

#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)

drivers/gpu/drm/i915/display/intel_dvo_dev.h

44

void *dev_priv;

drivers/gpu/drm/i915/display/intel_fb_pin.c

122

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/display/intel_fb_pin.c

165

else if (!ret && HAS_LMEM(dev_priv))

drivers/gpu/drm/i915/display/intel_fb_pin.c

34

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/display/intel_fb_pin.c

45

if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))

drivers/gpu/drm/i915/display/intel_fb_pin.c

58

if (HAS_LMEM(dev_priv)) {

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

22

struct drm_i915_private *dev_priv = to_i915(drm);

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

26

if (HAS_LMEM(dev_priv)) {

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

27

obj = i915_gem_object_create_lmem(dev_priv, size,

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

38

if (!IS_METEORLAKE(dev_priv) && size * 2 < dev_priv->dsm.usable_size)

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

39

obj = i915_gem_object_create_stolen(dev_priv, size);

drivers/gpu/drm/i915/display/intel_fbdev_fb.c

41

obj = i915_gem_object_create_shmem(dev_priv, size);

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

100

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

109

#define HDCP_ANLO(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

110

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

119

#define HDCP_ANHI(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

120

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

130

#define HDCP_BKSVLO(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

131

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

141

#define HDCP_BKSVHI(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

142

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

152

#define HDCP_RPRIME(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

153

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

163

#define HDCP_STATUS(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

164

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

204

#define HDCP2_AUTH(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

205

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

215

#define HDCP2_CTL(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

216

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

229

#define HDCP2_STATUS(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

230

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

251

#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

252

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

267

#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

268

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

86

#define HDCP_CONF(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

87

(TRANS_HDCP(dev_priv) ? \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

99

#define HDCP_ANINIT(dev_priv, trans, port) \

drivers/gpu/drm/i915/display/intel_overlay.c

1400

struct drm_i915_private *dev_priv = to_i915(display->drm);

drivers/gpu/drm/i915/display/intel_overlay.c

1408

engine = to_gt(dev_priv)->engine[RCS0];

drivers/gpu/drm/i915/display/intel_pfit_regs.h

10

#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)

drivers/gpu/drm/i915/display/intel_pfit_regs.h

31

#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)

drivers/gpu/drm/i915/display/intel_pfit_regs.h

39

#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

12

#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

63

#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

67

#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

71

#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

75

#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

79

#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

82

#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

85

#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

88

#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

91

#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)

drivers/gpu/drm/i915/display/intel_psr_regs.h

100

#define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */

drivers/gpu/drm/i915/display/intel_psr_regs.h

105

#define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

13

#define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

130

#define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

137

#define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

157

#define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

203

#define PSR_EVENT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

223

#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

229

#define _PSR2_SU_STATUS(dev_priv, tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)

drivers/gpu/drm/i915/display/intel_psr_regs.h

230

#define PSR2_SU_STATUS(dev_priv, tran, frame) (_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))

drivers/gpu/drm/i915/display/intel_psr_regs.h

237

#define PSR2_MAN_TRK_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

27

#define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

270

#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

280

#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

304

#define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

70

#define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

71

#define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

90

#define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)

drivers/gpu/drm/i915/gvt/cmd_parser.c

1294

struct drm_i915_private *dev_priv = s->engine->i915;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1295

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1312

if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))

drivers/gpu/drm/i915/gvt/cmd_parser.c

1332

drm_WARN_ON(&dev_priv->drm, 1);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1341

struct drm_i915_private *dev_priv = s->engine->i915;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1342

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1429

struct drm_i915_private *dev_priv = s->engine->i915;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1430

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1435

if (GRAPHICS_VER(dev_priv) >= 9) {

drivers/gpu/drm/i915/gvt/display.c

189

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

190

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

193

if (IS_BROXTON(dev_priv)) {

drivers/gpu/drm/i915/gvt/display.c

379

if (IS_SKYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

380

IS_KABYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

381

IS_COFFEELAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

382

IS_COMETLAKE(dev_priv)) {

drivers/gpu/drm/i915/gvt/display.c

433

if (IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/gvt/display.c

459

if (IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/gvt/display.c

485

if (IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/gvt/display.c

496

if ((IS_SKYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

497

IS_KABYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

498

IS_COFFEELAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

499

IS_COMETLAKE(dev_priv)) &&

drivers/gpu/drm/i915/gvt/display.c

505

if (IS_BROADWELL(dev_priv))

drivers/gpu/drm/i915/gvt/display.c

515

if (IS_BROADWELL(dev_priv))

drivers/gpu/drm/i915/gvt/display.c

640

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

641

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

75

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

76

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

779

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

781

if (IS_SKYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

782

IS_KABYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

783

IS_COFFEELAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

784

IS_COMETLAKE(dev_priv))

drivers/gpu/drm/i915/gvt/display.c

805

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

809

if (IS_SKYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

810

IS_KABYLAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

811

IS_COFFEELAKE(dev_priv) ||

drivers/gpu/drm/i915/gvt/display.c

812

IS_COMETLAKE(dev_priv))

drivers/gpu/drm/i915/gvt/display.c

88

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/display.c

89

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

91

if (drm_WARN_ON(&dev_priv->drm,

drivers/gpu/drm/i915/gvt/dmabuf.c

203

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/gvt/dmabuf.c

217

if (GRAPHICS_VER(dev_priv) >= 9) {

drivers/gpu/drm/i915/gvt/dmabuf.c

49

struct drm_i915_private *dev_priv = to_i915(obj->base.dev);

drivers/gpu/drm/i915/gvt/dmabuf.c

63

if (drm_WARN_ON(&dev_priv->drm, !fb_info))

drivers/gpu/drm/i915/gvt/dmabuf.c

67

if (drm_WARN_ON(&dev_priv->drm, !vgpu))

drivers/gpu/drm/i915/gvt/dmabuf.c

79

gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +

drivers/gpu/drm/i915/gvt/fb_decoder.c

158

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/fb_decoder.c

159

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/fb_decoder.c

164

if (GRAPHICS_VER(dev_priv) >= 9) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

215

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/fb_decoder.c

216

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/fb_decoder.c

229

if (GRAPHICS_VER(dev_priv) >= 9) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

270

(GRAPHICS_VER(dev_priv) >= 9) ?

drivers/gpu/drm/i915/gvt/fb_decoder.c

346

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/fb_decoder.c

347

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/gtt.c

1000

} else if (GRAPHICS_VER(dev_priv) >= 11) {

drivers/gpu/drm/i915/gvt/gtt.c

993

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/gtt.c

995

if (GRAPHICS_VER(dev_priv) == 9) {

drivers/gpu/drm/i915/gvt/handlers.c

1033

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

1034

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

1075

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

1076

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

1100

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

1115

drm_WARN_ON(&dev_priv->drm, true);

drivers/gpu/drm/i915/gvt/handlers.c

2210

struct drm_i915_private *dev_priv = gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

2211

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

3236

struct drm_i915_private *dev_priv = gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

3239

intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));

drivers/gpu/drm/i915/gvt/handlers.c

669

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/handlers.c

670

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

683

if (IS_BROADWELL(dev_priv))

drivers/gpu/drm/i915/gvt/handlers.c

685

else if (IS_BROXTON(dev_priv))

drivers/gpu/drm/i915/gvt/sched_policy.c

448

struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/sched_policy.c

470

wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/gvt/sched_policy.c

479

intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);

drivers/gpu/drm/i915/gvt/scheduler.c

95

struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;

drivers/gpu/drm/i915/gvt/scheduler.c

96

u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;

drivers/gpu/drm/i915/gvt/scheduler.c

97

u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;

drivers/gpu/drm/i915/gvt/vgpu.c

318

struct drm_i915_private *dev_priv = gvt->gt->i915;

drivers/gpu/drm/i915/gvt/vgpu.c

377

if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))

drivers/gpu/drm/i915/i915_cmd_parser.c

1589

int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_cmd_parser.c

1595

for_each_uabi_engine(engine, dev_priv) {

drivers/gpu/drm/i915/i915_cmd_parser.h

15

int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_debugfs.c

324

struct drm_i915_private *dev_priv = node_to_i915(m->private);

drivers/gpu/drm/i915/i915_debugfs.c

325

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_debugfs.c

329

swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));

drivers/gpu/drm/i915/i915_debugfs.c

331

swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));

drivers/gpu/drm/i915/i915_debugfs.c

333

if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)

drivers/gpu/drm/i915/i915_debugfs.c

337

if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_debugfs.c

340

wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_debugfs.c

342

if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {

drivers/gpu/drm/i915/i915_debugfs.c

351

} else if (GRAPHICS_VER(dev_priv) >= 6) {

drivers/gpu/drm/i915/i915_debugfs.c

360

if (GRAPHICS_VER(dev_priv) >= 8)

drivers/gpu/drm/i915/i915_debugfs.c

370

intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);

drivers/gpu/drm/i915/i915_debugfs.c

377

struct drm_i915_private *dev_priv = node_to_i915(m->private);

drivers/gpu/drm/i915/i915_debugfs.c

378

struct intel_rps *rps = &to_gt(dev_priv)->rps;

drivers/gpu/drm/i915/i915_debugfs.c

384

seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake));

drivers/gpu/drm/i915/i915_debugfs.c

408

struct drm_i915_private *dev_priv = node_to_i915(m->private);

drivers/gpu/drm/i915/i915_debugfs.c

409

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_debugfs.c

411

if (!HAS_RUNTIME_PM(dev_priv))

drivers/gpu/drm/i915/i915_debugfs.c

414

seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));

drivers/gpu/drm/i915/i915_debugfs.c

416

str_yes_no(!intel_irqs_enabled(dev_priv)));

drivers/gpu/drm/i915/i915_debugfs.c

419

atomic_read(&dev_priv->drm.dev->power.usage_count));

drivers/gpu/drm/i915/i915_debugfs.c

430

print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);

drivers/gpu/drm/i915/i915_debugfs.h

15

void i915_debugfs_register(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_debugfs.h

18

static inline void i915_debugfs_register(struct drm_i915_private *dev_priv) {}

drivers/gpu/drm/i915/i915_driver.c

1072

static bool suspend_to_idle(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

1105

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

1106

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1109

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

1122

intel_irq_suspend(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1132

i915_ggtt_suspend(to_gt(dev_priv)->ggtt);

drivers/gpu/drm/i915/i915_driver.c

1136

opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;

drivers/gpu/drm/i915/i915_driver.c

1139

dev_priv->suspend_count++;

drivers/gpu/drm/i915/i915_driver.c

1143

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

1145

i915_gem_drain_freed_objects(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1152

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

1153

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1154

struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

drivers/gpu/drm/i915/i915_driver.c

1157

bool s2idle = !hibernation && suspend_to_idle(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1161

intel_pxp_suspend(dev_priv->pxp);

drivers/gpu/drm/i915/i915_driver.c

1163

i915_gem_suspend_late(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1165

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1170

ret = vlv_suspend_complete(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1172

drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);

drivers/gpu/drm/i915/i915_driver.c

1178

if (!dev_priv->uncore.user_forcewake_count)

drivers/gpu/drm/i915/i915_driver.c

1186

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

1187

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_driver.c

1204

if (hibernation && GRAPHICS_VER(dev_priv) < 6)

drivers/gpu/drm/i915/i915_driver.c

1239

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

1240

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1244

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

1246

ret = i915_pcode_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1250

sanitize_gpu(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1252

ret = i915_ggtt_enable_hw(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1254

drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");

drivers/gpu/drm/i915/i915_driver.c

1256

i915_ggtt_resume(to_gt(dev_priv)->ggtt);

drivers/gpu/drm/i915/i915_driver.c

1258

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

127

static int i915_workqueues_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

1285

intel_irq_resume(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1290

i915_gem_resume(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1294

intel_clock_gating_init(&dev_priv->drm);

drivers/gpu/drm/i915/i915_driver.c

1315

intel_gvt_resume(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1317

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

1324

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

1325

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1339

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

1341

ret = vlv_resume_prepare(dev_priv, false);

drivers/gpu/drm/i915/i915_driver.c

1343

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

1346

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1351

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

143

dev_priv->wq = alloc_ordered_workqueue("i915", 0);

drivers/gpu/drm/i915/i915_driver.c

144

if (dev_priv->wq == NULL)

drivers/gpu/drm/i915/i915_driver.c

153

dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);

drivers/gpu/drm/i915/i915_driver.c

154

if (dev_priv->unordered_wq == NULL)

drivers/gpu/drm/i915/i915_driver.c

1547

struct drm_i915_private *dev_priv = kdev_to_i915(kdev);

drivers/gpu/drm/i915/i915_driver.c

1548

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1549

struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

drivers/gpu/drm/i915/i915_driver.c

1550

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_driver.c

1555

if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))

drivers/gpu/drm/i915/i915_driver.c

1558

drm_dbg(&dev_priv->drm, "Suspending device\n");

drivers/gpu/drm/i915/i915_driver.c

1566

i915_gem_runtime_suspend(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1568

intel_pxp_runtime_suspend(dev_priv->pxp);

drivers/gpu/drm/i915/i915_driver.c

1570

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1573

intel_irq_suspend(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1575

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1580

ret = vlv_suspend_complete(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1582

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

1584

intel_uncore_runtime_resume(&dev_priv->uncore);

drivers/gpu/drm/i915/i915_driver.c

1586

intel_irq_resume(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1588

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1599

if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))

drivers/gpu/drm/i915/i915_driver.c

160

destroy_workqueue(dev_priv->wq);

drivers/gpu/drm/i915/i915_driver.c

1600

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

1616

if (IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

162

drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");

drivers/gpu/drm/i915/i915_driver.c

1635

assert_forcewakes_inactive(&dev_priv->uncore);

drivers/gpu/drm/i915/i915_driver.c

1637

if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_driver.c

1640

drm_dbg(&dev_priv->drm, "Device suspended\n");

drivers/gpu/drm/i915/i915_driver.c

1646

struct drm_i915_private *dev_priv = kdev_to_i915(kdev);

drivers/gpu/drm/i915/i915_driver.c

1647

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1648

struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

drivers/gpu/drm/i915/i915_driver.c

1649

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_driver.c

1654

if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))

drivers/gpu/drm/i915/i915_driver.c

1657

drm_dbg(&dev_priv->drm, "Resuming device\n");

drivers/gpu/drm/i915/i915_driver.c

1659

drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));

drivers/gpu/drm/i915/i915_driver.c

1668

if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))

drivers/gpu/drm/i915/i915_driver.c

1669

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

167

static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

1674

ret = vlv_resume_prepare(dev_priv, true);

drivers/gpu/drm/i915/i915_driver.c

1676

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1679

intel_irq_resume(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

1685

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

1688

intel_pxp_runtime_resume(dev_priv->pxp);

drivers/gpu/drm/i915/i915_driver.c

169

destroy_workqueue(dev_priv->unordered_wq);

drivers/gpu/drm/i915/i915_driver.c

1695

if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

170

destroy_workqueue(dev_priv->wq);

drivers/gpu/drm/i915/i915_driver.c

1705

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

1708

drm_dbg(&dev_priv->drm, "Device resumed\n");

drivers/gpu/drm/i915/i915_driver.c

183

static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

187

pre |= IS_HASWELL_EARLY_SDV(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

188

pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;

drivers/gpu/drm/i915/i915_driver.c

189

pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;

drivers/gpu/drm/i915/i915_driver.c

190

pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;

drivers/gpu/drm/i915/i915_driver.c

191

pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;

drivers/gpu/drm/i915/i915_driver.c

192

pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;

drivers/gpu/drm/i915/i915_driver.c

193

pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;

drivers/gpu/drm/i915/i915_driver.c

194

pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;

drivers/gpu/drm/i915/i915_driver.c

195

pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;

drivers/gpu/drm/i915/i915_driver.c

196

pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;

drivers/gpu/drm/i915/i915_driver.c

197

pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;

drivers/gpu/drm/i915/i915_driver.c

200

drm_err(&dev_priv->drm, "This is a pre-production stepping. "

drivers/gpu/drm/i915/i915_driver.c

227

static int i915_driver_early_probe(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

229

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

232

intel_device_info_runtime_init_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

234

intel_step_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

236

intel_uncore_mmio_debug_init_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

238

spin_lock_init(&dev_priv->gpu_error.lock);

drivers/gpu/drm/i915/i915_driver.c

241

vlv_iosf_sb_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

242

mutex_init(&dev_priv->sb_lock);

drivers/gpu/drm/i915/i915_driver.c

244

i915_memcpy_init_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

245

intel_runtime_pm_init_early(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

247

ret = i915_workqueues_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

251

ret = vlv_suspend_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

255

ret = intel_region_ttm_device_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

259

ret = intel_root_gt_init_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

263

i915_gem_init_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

265

intel_irq_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

267

intel_clock_gating_hooks_init(&dev_priv->drm);

drivers/gpu/drm/i915/i915_driver.c

269

intel_detect_preproduction_hw(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

274

intel_region_ttm_device_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

276

vlv_suspend_cleanup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

278

i915_workqueues_cleanup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

288

static void i915_driver_late_release(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

290

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

292

intel_irq_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

294

i915_gem_cleanup_early(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

295

intel_gt_driver_late_release_all(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

296

intel_region_ttm_device_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

297

vlv_suspend_cleanup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

298

i915_workqueues_cleanup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

300

mutex_destroy(&dev_priv->sb_lock);

drivers/gpu/drm/i915/i915_driver.c

301

vlv_iosf_sb_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

304

i915_params_free(&dev_priv->params);

drivers/gpu/drm/i915/i915_driver.c

318

static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

320

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

324

ret = i915_gmch_bridge_setup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

328

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_driver.c

333

ret = drmm_add_action_or_reset(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

341

i915_gmch_bar_setup(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

342

intel_device_info_runtime_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

345

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_driver.c

352

sanitize_gpu(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

357

i915_gmch_bar_teardown(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

367

static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

369

i915_gmch_bar_teardown(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

463

static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

465

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

466

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_driver.c

469

if (HAS_PPGTT(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

470

if (intel_vgpu_active(dev_priv) &&

drivers/gpu/drm/i915/i915_driver.c

471

!intel_vgpu_has_full_ppgtt(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

472

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

478

if (HAS_EXECLISTS(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

484

if (intel_vgpu_active(dev_priv) &&

drivers/gpu/drm/i915/i915_driver.c

485

!intel_vgpu_has_hwsp_emulation(dev_priv)) {

drivers/gpu/drm/i915/i915_driver.c

486

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

493

i915_edram_detect(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

495

ret = i915_set_dma_info(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

499

ret = i915_perf_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

503

ret = i915_ggtt_probe_hw(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

507

ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name);

drivers/gpu/drm/i915/i915_driver.c

511

ret = i915_ggtt_init_hw(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

519

ret = intel_gt_tiles_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

523

ret = intel_memory_regions_hw_probe(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

527

ret = i915_ggtt_enable_hw(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

529

drm_err(&dev_priv->drm, "failed to enable GGTT\n");

drivers/gpu/drm/i915/i915_driver.c

554

if (GRAPHICS_VER(dev_priv) >= 5) {

drivers/gpu/drm/i915/i915_driver.c

556

drm_dbg(&dev_priv->drm, "can't enable MSI");

drivers/gpu/drm/i915/i915_driver.c

559

ret = intel_gvt_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

565

ret = i915_pcode_init(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

587

intel_memory_regions_driver_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

589

i915_ggtt_driver_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

590

i915_gem_drain_freed_objects(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

591

i915_ggtt_driver_late_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

593

i915_perf_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

602

static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

604

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

605

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_driver.c

607

i915_perf_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

622

static int i915_driver_register(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

624

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

629

i915_gem_driver_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

630

i915_pmu_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

632

intel_vgpu_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

635

ret = drm_dev_register(&dev_priv->drm, 0);

drivers/gpu/drm/i915/i915_driver.c

637

i915_probe_error(dev_priv,

drivers/gpu/drm/i915/i915_driver.c

639

drm_dev_unregister(&dev_priv->drm);

drivers/gpu/drm/i915/i915_driver.c

640

i915_pmu_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

641

i915_gem_driver_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

645

i915_debugfs_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

646

i915_setup_sysfs(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

649

i915_perf_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

651

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

654

intel_pxp_debugfs_register(dev_priv->pxp);

drivers/gpu/drm/i915/i915_driver.c

656

i915_hwmon_register(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

661

intel_runtime_pm_enable(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

663

if (i915_switcheroo_register(dev_priv))

drivers/gpu/drm/i915/i915_driver.c

664

drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");

drivers/gpu/drm/i915/i915_driver.c

673

static void i915_driver_unregister(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

675

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

679

i915_switcheroo_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

681

intel_runtime_pm_disable(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_driver.c

686

intel_pxp_fini(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

688

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

691

i915_hwmon_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

693

i915_perf_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

694

i915_pmu_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

696

i915_teardown_sysfs(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

697

drm_dev_unplug(&dev_priv->drm);

drivers/gpu/drm/i915/i915_driver.c

699

i915_gem_driver_unregister(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

709

static void i915_welcome_messages(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_driver.c

712

struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER,

drivers/gpu/drm/i915/i915_driver.c

718

INTEL_DEVID(dev_priv),

drivers/gpu/drm/i915/i915_driver.c

719

INTEL_REVID(dev_priv),

drivers/gpu/drm/i915/i915_driver.c

720

intel_platform_name(INTEL_INFO(dev_priv)->platform),

drivers/gpu/drm/i915/i915_driver.c

721

intel_subplatform(RUNTIME_INFO(dev_priv),

drivers/gpu/drm/i915/i915_driver.c

722

INTEL_INFO(dev_priv)->platform),

drivers/gpu/drm/i915/i915_driver.c

723

GRAPHICS_VER(dev_priv));

drivers/gpu/drm/i915/i915_driver.c

725

intel_device_info_print(INTEL_INFO(dev_priv),

drivers/gpu/drm/i915/i915_driver.c

726

RUNTIME_INFO(dev_priv), &p);

drivers/gpu/drm/i915/i915_driver.c

727

i915_print_iommu_status(dev_priv, &p);

drivers/gpu/drm/i915/i915_driver.c

728

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_driver.c

733

drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");

drivers/gpu/drm/i915/i915_driver.c

735

drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");

drivers/gpu/drm/i915/i915_driver.c

737

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/i915_driver.c

974

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_driver.c

975

struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

drivers/gpu/drm/i915/i915_driver.c

978

if (!dev_priv->do_release)

drivers/gpu/drm/i915/i915_driver.c

983

i915_gem_driver_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

985

intel_memory_regions_driver_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

986

i915_ggtt_driver_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

987

i915_gem_drain_freed_objects(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

988

i915_ggtt_driver_late_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

990

i915_driver_mmio_release(dev_priv);

drivers/gpu/drm/i915/i915_driver.c

996

i915_driver_late_release(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1142

int i915_gem_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem.c

1162

if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))

drivers/gpu/drm/i915/i915_gem.c

1163

RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;

drivers/gpu/drm/i915/i915_gem.c

1165

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_gem.c

1168

if (GRAPHICS_VER(dev_priv) >= 8)

drivers/gpu/drm/i915/i915_gem.c

1172

ret = i915_init_ggtt(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1187

intel_clock_gating_init(&dev_priv->drm);

drivers/gpu/drm/i915/i915_gem.c

1189

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_gem.c

1200

intel_engines_driver_register(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1211

i915_gem_drain_workqueue(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1214

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_gem.c

1227

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_gem.c

1229

i915_probe_error(dev_priv,

drivers/gpu/drm/i915/i915_gem.c

1236

ret = i915_ggtt_enable_hw(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1237

i915_ggtt_resume(to_gt(dev_priv)->ggtt);

drivers/gpu/drm/i915/i915_gem.c

1238

intel_clock_gating_init(&dev_priv->drm);

drivers/gpu/drm/i915/i915_gem.c

1241

i915_gem_drain_freed_objects(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1256

void i915_gem_driver_remove(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem.c

1261

i915_gem_suspend_late(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1262

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_gem.c

1264

dev_priv->uabi_engines = RB_ROOT;

drivers/gpu/drm/i915/i915_gem.c

1267

i915_gem_drain_workqueue(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1270

void i915_gem_driver_release(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem.c

1275

for_each_gt(gt, dev_priv, i) {

drivers/gpu/drm/i915/i915_gem.c

1281

i915_gem_drain_workqueue(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1283

drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));

drivers/gpu/drm/i915/i915_gem.c

1298

void i915_gem_init_early(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem.c

1300

i915_gem_init__mm(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1301

i915_gem_init__contexts(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1303

spin_lock_init(&dev_priv->frontbuffer_lock);

drivers/gpu/drm/i915/i915_gem.c

1306

void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem.c

1308

i915_gem_drain_workqueue(dev_priv);

drivers/gpu/drm/i915/i915_gem.c

1309

GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));

drivers/gpu/drm/i915/i915_gem.c

1310

GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));

drivers/gpu/drm/i915/i915_gem.c

1311

drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);

drivers/gpu/drm/i915/i915_gpu_error.c

2599

struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);

drivers/gpu/drm/i915/i915_gpu_error.c

2601

drm_dbg(&dev_priv->drm, "Resetting error state\n");

drivers/gpu/drm/i915/i915_gpu_error.c

2602

i915_reset_error_state(dev_priv);

drivers/gpu/drm/i915/i915_initial_plane.c

263

struct drm_i915_private *dev_priv = to_i915(_plane_state->plane->dev);

drivers/gpu/drm/i915/i915_initial_plane.c

274

dev_priv->preserve_bios_swizzle = true;

drivers/gpu/drm/i915/i915_irq.c

1004

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/i915_irq.c

1005

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

1008

if (!intel_irqs_enabled(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1012

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

1020

iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);

drivers/gpu/drm/i915/i915_irq.c

1034

i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);

drivers/gpu/drm/i915/i915_irq.c

1036

intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);

drivers/gpu/drm/i915/i915_irq.c

1039

intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],

drivers/gpu/drm/i915/i915_irq.c

1043

intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],

drivers/gpu/drm/i915/i915_irq.c

1047

i9xx_error_irq_handler(dev_priv, eir, eir_stuck);

drivers/gpu/drm/i915/i915_irq.c

1055

pmu_irq_stats(dev_priv, IRQ_HANDLED);

drivers/gpu/drm/i915/i915_irq.c

1057

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

1069

void intel_irq_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1073

INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);

drivers/gpu/drm/i915/i915_irq.c

1075

dev_priv->l3_parity.remap_info[i] = NULL;

drivers/gpu/drm/i915/i915_irq.c

1078

if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)

drivers/gpu/drm/i915/i915_irq.c

1079

to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16;

drivers/gpu/drm/i915/i915_irq.c

1096

static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1098

if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))

drivers/gpu/drm/i915/i915_irq.c

1100

else if (GRAPHICS_VER(dev_priv) >= 11)

drivers/gpu/drm/i915/i915_irq.c

1102

else if (IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1104

else if (GRAPHICS_VER(dev_priv) >= 8)

drivers/gpu/drm/i915/i915_irq.c

1106

else if (IS_VALLEYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1108

else if (GRAPHICS_VER(dev_priv) >= 5)

drivers/gpu/drm/i915/i915_irq.c

1110

else if (GRAPHICS_VER(dev_priv) == 4)

drivers/gpu/drm/i915/i915_irq.c

1116

static void intel_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1118

if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))

drivers/gpu/drm/i915/i915_irq.c

1119

dg1_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1120

else if (GRAPHICS_VER(dev_priv) >= 11)

drivers/gpu/drm/i915/i915_irq.c

1121

gen11_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1122

else if (IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1123

cherryview_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1124

else if (GRAPHICS_VER(dev_priv) >= 8)

drivers/gpu/drm/i915/i915_irq.c

1125

gen8_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1126

else if (IS_VALLEYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1127

valleyview_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1128

else if (GRAPHICS_VER(dev_priv) >= 5)

drivers/gpu/drm/i915/i915_irq.c

1129

ilk_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1130

else if (GRAPHICS_VER(dev_priv) == 4)

drivers/gpu/drm/i915/i915_irq.c

1131

i965_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1133

i915_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1136

static void intel_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1138

if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))

drivers/gpu/drm/i915/i915_irq.c

1139

dg1_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1140

else if (GRAPHICS_VER(dev_priv) >= 11)

drivers/gpu/drm/i915/i915_irq.c

1141

gen11_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1142

else if (IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1143

cherryview_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1144

else if (GRAPHICS_VER(dev_priv) >= 8)

drivers/gpu/drm/i915/i915_irq.c

1145

gen8_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1146

else if (IS_VALLEYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

1147

valleyview_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1148

else if (GRAPHICS_VER(dev_priv) >= 5)

drivers/gpu/drm/i915/i915_irq.c

1149

ilk_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1150

else if (GRAPHICS_VER(dev_priv) == 4)

drivers/gpu/drm/i915/i915_irq.c

1151

i965_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1153

i915_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1167

int intel_irq_install(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1169

int irq = to_pci_dev(dev_priv->drm.dev)->irq;

drivers/gpu/drm/i915/i915_irq.c

1177

dev_priv->irqs_enabled = true;

drivers/gpu/drm/i915/i915_irq.c

1179

intel_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1181

ret = request_irq(irq, intel_irq_handler(dev_priv),

drivers/gpu/drm/i915/i915_irq.c

1182

IRQF_SHARED, DRIVER_NAME, dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1184

dev_priv->irqs_enabled = false;

drivers/gpu/drm/i915/i915_irq.c

1188

intel_irq_postinstall(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1200

void intel_irq_uninstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1202

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

1203

int irq = to_pci_dev(dev_priv->drm.dev)->irq;

drivers/gpu/drm/i915/i915_irq.c

1205

if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled))

drivers/gpu/drm/i915/i915_irq.c

1208

intel_irq_reset(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1210

free_irq(irq, dev_priv);

drivers/gpu/drm/i915/i915_irq.c

1213

dev_priv->irqs_enabled = false;

drivers/gpu/drm/i915/i915_irq.c

1242

bool intel_irqs_enabled(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

1244

return dev_priv->irqs_enabled;

drivers/gpu/drm/i915/i915_irq.c

158

struct drm_i915_private *dev_priv =

drivers/gpu/drm/i915/i915_irq.c

159

container_of(work, typeof(*dev_priv), l3_parity.error_work);

drivers/gpu/drm/i915/i915_irq.c

160

struct intel_gt *gt = to_gt(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

168

if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))

drivers/gpu/drm/i915/i915_irq.c

171

misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,

drivers/gpu/drm/i915/i915_irq.c

173

intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);

drivers/gpu/drm/i915/i915_irq.c

175

while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {

drivers/gpu/drm/i915/i915_irq.c

179

if (drm_WARN_ON_ONCE(&dev_priv->drm,

drivers/gpu/drm/i915/i915_irq.c

180

slice >= NUM_L3_SLICES(dev_priv)))

drivers/gpu/drm/i915/i915_irq.c

183

dev_priv->l3_parity.which_slice &= ~(1<<slice);

drivers/gpu/drm/i915/i915_irq.c

187

error_status = intel_uncore_read(&dev_priv->uncore, reg);

drivers/gpu/drm/i915/i915_irq.c

192

intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);

drivers/gpu/drm/i915/i915_irq.c

193

intel_uncore_posting_read(&dev_priv->uncore, reg);

drivers/gpu/drm/i915/i915_irq.c

202

kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,

drivers/gpu/drm/i915/i915_irq.c

205

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/i915_irq.c

215

intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);

drivers/gpu/drm/i915/i915_irq.c

218

drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);

drivers/gpu/drm/i915/i915_irq.c

220

gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

227

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/i915_irq.c

228

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

231

if (!intel_irqs_enabled(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

235

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

244

gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);

drivers/gpu/drm/i915/i915_irq.c

245

pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);

drivers/gpu/drm/i915/i915_irq.c

246

iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);

drivers/gpu/drm/i915/i915_irq.c

266

intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);

drivers/gpu/drm/i915/i915_irq.c

267

ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);

drivers/gpu/drm/i915/i915_irq.c

270

intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);

drivers/gpu/drm/i915/i915_irq.c

272

intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);

drivers/gpu/drm/i915/i915_irq.c

293

intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);

drivers/gpu/drm/i915/i915_irq.c

295

intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);

drivers/gpu/drm/i915/i915_irq.c

296

intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);

drivers/gpu/drm/i915/i915_irq.c

299

gen6_gt_irq_handler(to_gt(dev_priv), gt_iir);

drivers/gpu/drm/i915/i915_irq.c

301

gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);

drivers/gpu/drm/i915/i915_irq.c

312

pmu_irq_stats(dev_priv, ret);

drivers/gpu/drm/i915/i915_irq.c

314

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

321

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/i915_irq.c

322

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

325

if (!intel_irqs_enabled(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

329

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

338

master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;

drivers/gpu/drm/i915/i915_irq.c

339

iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);

drivers/gpu/drm/i915/i915_irq.c

359

intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);

drivers/gpu/drm/i915/i915_irq.c

360

ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);

drivers/gpu/drm/i915/i915_irq.c

362

gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);

drivers/gpu/drm/i915/i915_irq.c

384

intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);

drivers/gpu/drm/i915/i915_irq.c

386

intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);

drivers/gpu/drm/i915/i915_irq.c

387

intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);

drivers/gpu/drm/i915/i915_irq.c

398

pmu_irq_stats(dev_priv, ret);

drivers/gpu/drm/i915/i915_irq.c

400

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

485

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/i915_irq.c

486

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

487

void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);

drivers/gpu/drm/i915/i915_irq.c

490

if (!intel_irqs_enabled(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

500

gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);

drivers/gpu/drm/i915/i915_irq.c

504

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

506

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

511

pmu_irq_stats(dev_priv, IRQ_HANDLED);

drivers/gpu/drm/i915/i915_irq.c

637

static void ilk_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

639

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

643

gen5_gt_irq_reset(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

646

static void valleyview_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

648

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

650

intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);

drivers/gpu/drm/i915/i915_irq.c

651

intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);

drivers/gpu/drm/i915/i915_irq.c

653

gen5_gt_irq_reset(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

658

static void gen8_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

660

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

661

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

665

gen8_gt_irq_reset(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

670

static void gen11_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

672

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

673

struct intel_gt *gt = to_gt(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

676

gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));

drivers/gpu/drm/i915/i915_irq.c

685

static void dg1_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

687

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

688

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

692

dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));

drivers/gpu/drm/i915/i915_irq.c

694

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_irq.c

705

static void cherryview_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

707

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

708

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

711

intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);

drivers/gpu/drm/i915/i915_irq.c

713

gen8_gt_irq_reset(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

720

static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

722

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

724

gen5_gt_irq_postinstall(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

729

static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

731

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

733

gen5_gt_irq_postinstall(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

737

intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);

drivers/gpu/drm/i915/i915_irq.c

738

intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);

drivers/gpu/drm/i915/i915_irq.c

741

static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

743

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

745

gen8_gt_irq_postinstall(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

748

gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));

drivers/gpu/drm/i915/i915_irq.c

751

static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

753

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

754

struct intel_gt *gt = to_gt(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

764

intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);

drivers/gpu/drm/i915/i915_irq.c

767

static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

769

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

770

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

775

for_each_gt(gt, dev_priv, i)

drivers/gpu/drm/i915/i915_irq.c

786

static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

788

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

790

gen8_gt_irq_postinstall(to_gt(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

794

intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);

drivers/gpu/drm/i915/i915_irq.c

795

intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);

drivers/gpu/drm/i915/i915_irq.c

821

static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/i915_irq.c

826

*eir = intel_uncore_read(&dev_priv->uncore, EIR);

drivers/gpu/drm/i915/i915_irq.c

827

intel_uncore_write(&dev_priv->uncore, EIR, *eir);

drivers/gpu/drm/i915/i915_irq.c

829

*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);

drivers/gpu/drm/i915/i915_irq.c

843

emr = intel_uncore_read(&dev_priv->uncore, EMR);

drivers/gpu/drm/i915/i915_irq.c

844

intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);

drivers/gpu/drm/i915/i915_irq.c

845

intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);

drivers/gpu/drm/i915/i915_irq.c

848

static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/i915_irq.c

851

drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir);

drivers/gpu/drm/i915/i915_irq.c

854

drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",

drivers/gpu/drm/i915/i915_irq.c

857

drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",

drivers/gpu/drm/i915/i915_irq.c

858

intel_uncore_read(&dev_priv->uncore, PGTBL_ER));

drivers/gpu/drm/i915/i915_irq.c

861

static void i915_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

863

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

864

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

870

dev_priv->gen2_imr_mask = ~0u;

drivers/gpu/drm/i915/i915_irq.c

873

static void i915_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

875

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

876

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

879

gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

884

dev_priv->gen2_imr_mask = ~enable_mask;

drivers/gpu/drm/i915/i915_irq.c

888

gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);

drivers/gpu/drm/i915/i915_irq.c

895

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/i915_irq.c

896

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

899

if (!intel_irqs_enabled(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

903

disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

911

iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);

drivers/gpu/drm/i915/i915_irq.c

925

i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);

drivers/gpu/drm/i915/i915_irq.c

927

intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);

drivers/gpu/drm/i915/i915_irq.c

930

intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);

drivers/gpu/drm/i915/i915_irq.c

933

i9xx_error_irq_handler(dev_priv, eir, eir_stuck);

drivers/gpu/drm/i915/i915_irq.c

941

pmu_irq_stats(dev_priv, ret);

drivers/gpu/drm/i915/i915_irq.c

943

enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/i915_irq.c

948

static void i965_irq_reset(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

950

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

951

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

957

dev_priv->gen2_imr_mask = ~0u;

drivers/gpu/drm/i915/i915_irq.c

979

static void i965_irq_postinstall(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

981

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

982

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_irq.c

985

gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv));

drivers/gpu/drm/i915/i915_irq.c

990

dev_priv->gen2_imr_mask = ~enable_mask;

drivers/gpu/drm/i915/i915_irq.c

994

if (IS_G4X(dev_priv))

drivers/gpu/drm/i915/i915_irq.c

997

gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);

drivers/gpu/drm/i915/i915_irq.h

23

void intel_irq_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

24

void intel_irq_fini(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

25

int intel_irq_install(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

26

void intel_irq_uninstall(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

28

void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

drivers/gpu/drm/i915/i915_irq.h

29

void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

drivers/gpu/drm/i915/i915_irq.h

30

void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

31

void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

32

void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

33

void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

34

void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_irq.h

39

bool intel_irqs_enabled(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_memcpy.c

163

void i915_memcpy_init_early(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_query.c

588

static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/i915_query.c

601

struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/i915_query.c

630

ret = i915_query_funcs[func_idx](dev_priv, &item);

drivers/gpu/drm/i915/i915_query.c

92

static int query_topology_info(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/i915_query.c

95

const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;

drivers/gpu/drm/i915/i915_reg.h

520

#define GT_PARITY_ERROR(dev_priv) \

drivers/gpu/drm/i915/i915_reg.h

522

(IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))

drivers/gpu/drm/i915/i915_sysfs.c

160

void i915_setup_sysfs(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_sysfs.c

162

struct device *kdev = dev_priv->drm.primary->kdev;

drivers/gpu/drm/i915/i915_sysfs.c

165

if (HAS_L3_DPF(dev_priv)) {

drivers/gpu/drm/i915/i915_sysfs.c

168

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_sysfs.c

171

if (NUM_L3_SLICES(dev_priv) > 1) {

drivers/gpu/drm/i915/i915_sysfs.c

175

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_sysfs.c

180

dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);

drivers/gpu/drm/i915/i915_sysfs.c

181

if (!dev_priv->sysfs_gt)

drivers/gpu/drm/i915/i915_sysfs.c

182

drm_warn(&dev_priv->drm,

drivers/gpu/drm/i915/i915_sysfs.c

185

i915_gpu_error_sysfs_setup(dev_priv);

drivers/gpu/drm/i915/i915_sysfs.c

187

intel_engines_add_sysfs(dev_priv);

drivers/gpu/drm/i915/i915_sysfs.c

190

void i915_teardown_sysfs(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_sysfs.c

192

struct device *kdev = dev_priv->drm.primary->kdev;

drivers/gpu/drm/i915/i915_sysfs.c

194

i915_gpu_error_sysfs_teardown(dev_priv);

drivers/gpu/drm/i915/i915_sysfs.c

199

kobject_put(dev_priv->sysfs_gt);

drivers/gpu/drm/i915/i915_vgpu.c

101

dev_priv->vgpu.active = true;

drivers/gpu/drm/i915/i915_vgpu.c

102

mutex_init(&dev_priv->vgpu.lock);

drivers/gpu/drm/i915/i915_vgpu.c

103

drm_info(&dev_priv->drm, "Virtual GPU for Intel GVT-g detected.\n");

drivers/gpu/drm/i915/i915_vgpu.c

119

bool intel_vgpu_active(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_vgpu.c

121

return dev_priv->vgpu.active;

drivers/gpu/drm/i915/i915_vgpu.c

124

bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_vgpu.c

126

return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;

drivers/gpu/drm/i915/i915_vgpu.c

129

bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_vgpu.c

131

return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;

drivers/gpu/drm/i915/i915_vgpu.c

134

bool intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_vgpu.c

136

return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;

drivers/gpu/drm/i915/i915_vgpu.c

153

struct drm_i915_private *dev_priv = ggtt->vm.i915;

drivers/gpu/drm/i915/i915_vgpu.c

157

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/i915_vgpu.c

176

struct drm_i915_private *dev_priv = ggtt->vm.i915;

drivers/gpu/drm/i915/i915_vgpu.c

182

drm_dbg(&dev_priv->drm, "VGT deballoon.\n");

drivers/gpu/drm/i915/i915_vgpu.c

192

struct drm_i915_private *dev_priv = ggtt->vm.i915;

drivers/gpu/drm/i915/i915_vgpu.c

199

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/i915_vgpu.c

257

struct drm_i915_private *dev_priv = ggtt->vm.i915;

drivers/gpu/drm/i915/i915_vgpu.c

258

struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/i915_vgpu.c

280

drm_info(&dev_priv->drm, "VGT ballooning configuration:\n");

drivers/gpu/drm/i915/i915_vgpu.c

281

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/i915_vgpu.c

284

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/i915_vgpu.c

291

drm_err(&dev_priv->drm, "Invalid ballooning configuration!\n");

drivers/gpu/drm/i915/i915_vgpu.c

328

drm_info(&dev_priv->drm, "VGT balloon successfully\n");

drivers/gpu/drm/i915/i915_vgpu.c

338

drm_err(&dev_priv->drm, "VGT balloon fail\n");

drivers/gpu/drm/i915/i915_vgpu.c

64

void intel_vgpu_detect(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_vgpu.c

66

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/i915_vgpu.c

79

if (GRAPHICS_VER(dev_priv) < 6)

drivers/gpu/drm/i915/i915_vgpu.c

84

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/i915_vgpu.c

95

drm_info(&dev_priv->drm, "VGT interface version mismatch!\n");

drivers/gpu/drm/i915/i915_vgpu.c

99

dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps));

drivers/gpu/drm/i915/intel_clock_gating.c

135

static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_clock_gating.c

137

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_clock_gating.c

141

intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),

drivers/gpu/drm/i915/intel_clock_gating.c

144

intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),

drivers/gpu/drm/i915/intel_clock_gating.c

146

intel_uncore_posting_read(&dev_priv->uncore,

drivers/gpu/drm/i915/intel_device_info.c

389

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_device_info.c

391

struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);

drivers/gpu/drm/i915/intel_device_info.c

395

if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {

drivers/gpu/drm/i915/intel_device_info.c

396

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/intel_device_info.h

258

void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_device_info.h

259

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

109

static int save_initial_hw_state(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

111

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/i915/intel_gvt.c

112

struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;

drivers/gpu/drm/i915/intel_gvt.c

134

iter.i915 = dev_priv;

drivers/gpu/drm/i915/intel_gvt.c

154

static void intel_gvt_init_device(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

156

if (!dev_priv->params.enable_gvt) {

drivers/gpu/drm/i915/intel_gvt.c

157

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/intel_gvt.c

162

if (intel_vgpu_active(dev_priv)) {

drivers/gpu/drm/i915/intel_gvt.c

163

drm_info(&dev_priv->drm, "GVT-g is disabled for guest\n");

drivers/gpu/drm/i915/intel_gvt.c

167

if (!is_supported_device(dev_priv)) {

drivers/gpu/drm/i915/intel_gvt.c

168

drm_info(&dev_priv->drm,

drivers/gpu/drm/i915/intel_gvt.c

173

if (intel_uc_wants_guc_submission(&to_gt(dev_priv)->uc)) {

drivers/gpu/drm/i915/intel_gvt.c

174

drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/intel_gvt.c

179

if (save_initial_hw_state(dev_priv)) {

drivers/gpu/drm/i915/intel_gvt.c

180

drm_dbg(&dev_priv->drm, "Failed to save initial HW state\n");

drivers/gpu/drm/i915/intel_gvt.c

184

if (intel_gvt_ops->init_device(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

185

drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");

drivers/gpu/drm/i915/intel_gvt.c

188

static void intel_gvt_clean_device(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

190

if (dev_priv->gvt)

drivers/gpu/drm/i915/intel_gvt.c

191

intel_gvt_ops->clean_device(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

192

free_initial_hw_state(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

197

struct drm_i915_private *dev_priv;

drivers/gpu/drm/i915/intel_gvt.c

206

list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry)

drivers/gpu/drm/i915/intel_gvt.c

207

intel_gvt_init_device(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

216

struct drm_i915_private *dev_priv;

drivers/gpu/drm/i915/intel_gvt.c

224

list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry)

drivers/gpu/drm/i915/intel_gvt.c

225

intel_gvt_clean_device(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

242

int intel_gvt_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

245

list_add_tail(&dev_priv->vgpu.entry, &intel_gvt_devices);

drivers/gpu/drm/i915/intel_gvt.c

247

intel_gvt_init_device(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

261

void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

264

intel_gvt_clean_device(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

265

list_del(&dev_priv->vgpu.entry);

drivers/gpu/drm/i915/intel_gvt.c

277

void intel_gvt_resume(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

280

if (dev_priv->gvt)

drivers/gpu/drm/i915/intel_gvt.c

281

intel_gvt_ops->pm_resume(dev_priv);

drivers/gpu/drm/i915/intel_gvt.c

57

static bool is_supported_device(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

59

if (IS_BROADWELL(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

61

if (IS_SKYLAKE(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

63

if (IS_KABYLAKE(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

65

if (IS_BROXTON(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

67

if (IS_COFFEELAKE(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

69

if (IS_COMETLAKE(dev_priv))

drivers/gpu/drm/i915/intel_gvt.c

75

static void free_initial_hw_state(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.c

77

struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;

drivers/gpu/drm/i915/intel_gvt.c

89

struct drm_i915_private *dev_priv = iter->i915;

drivers/gpu/drm/i915/intel_gvt.c

94

*mmio = intel_uncore_read_notrace(to_gt(dev_priv)->uncore,

drivers/gpu/drm/i915/intel_gvt.h

40

int intel_gvt_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.h

41

void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.h

43

void intel_gvt_resume(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.h

47

int (*init_device)(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.h

48

void (*clean_device)(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_gvt.h

56

static inline int intel_gvt_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.h

61

static inline void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt.h

65

static inline void intel_gvt_resume(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1105

if (IS_KABYLAKE(dev_priv) ||

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1106

IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1108

if (!IS_BROXTON(dev_priv))

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1116

struct drm_i915_private *dev_priv = iter->i915;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1117

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

66

struct drm_i915_private *dev_priv = iter->i915;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

67

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

745

struct drm_i915_private *dev_priv = iter->i915;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

822

if (!IS_BROXTON(dev_priv))

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

917

struct drm_i915_private *dev_priv = iter->i915;

drivers/gpu/drm/i915/intel_region_ttm.c

31

int intel_region_ttm_device_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_region_ttm.c

33

struct drm_device *drm = &dev_priv->drm;

drivers/gpu/drm/i915/intel_region_ttm.c

35

return ttm_device_init(&dev_priv->bdev, i915_ttm_driver(),

drivers/gpu/drm/i915/intel_region_ttm.c

44

void intel_region_ttm_device_fini(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_region_ttm.c

46

ttm_device_fini(&dev_priv->bdev);

drivers/gpu/drm/i915/intel_region_ttm.h

17

int intel_region_ttm_device_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_region_ttm.h

19

void intel_region_ttm_device_fini(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

1197

static int exercise_ppgtt(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

1207

if (!HAS_FULL_PPGTT(dev_priv))

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

1210

file = mock_file(dev_priv);

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

1214

ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

155

struct drm_i915_private *dev_priv = arg;

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

163

if (!HAS_PPGTT(dev_priv))

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

166

ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);

drivers/gpu/drm/i915/vlv_suspend.c

350

static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/vlv_suspend.c

366

if (vlv_wait_for_pw_status(dev_priv, mask, val))

drivers/gpu/drm/i915/vlv_suspend.c

367

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/vlv_suspend.c

383

int vlv_suspend_complete(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/vlv_suspend.c

388

if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/vlv_suspend.c

395

vlv_wait_for_gt_wells(dev_priv, false);

drivers/gpu/drm/i915/vlv_suspend.c

398

drm_WARN_ON(&dev_priv->drm,

drivers/gpu/drm/i915/vlv_suspend.c

399

(intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);

drivers/gpu/drm/i915/vlv_suspend.c

401

vlv_check_no_gt_access(dev_priv);

drivers/gpu/drm/i915/vlv_suspend.c

403

err = vlv_force_gfx_clock(dev_priv, true);

drivers/gpu/drm/i915/vlv_suspend.c

407

err = vlv_allow_gt_wake(dev_priv, false);

drivers/gpu/drm/i915/vlv_suspend.c

411

vlv_save_gunit_s0ix_state(dev_priv);

drivers/gpu/drm/i915/vlv_suspend.c

413

err = vlv_force_gfx_clock(dev_priv, false);

drivers/gpu/drm/i915/vlv_suspend.c

421

vlv_allow_gt_wake(dev_priv, true);

drivers/gpu/drm/i915/vlv_suspend.c

423

vlv_force_gfx_clock(dev_priv, false);

drivers/gpu/drm/i915/vlv_suspend.c

428

int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)

drivers/gpu/drm/i915/vlv_suspend.c

433

if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

drivers/gpu/drm/i915/vlv_suspend.c

441

ret = vlv_force_gfx_clock(dev_priv, true);

drivers/gpu/drm/i915/vlv_suspend.c

443

vlv_restore_gunit_s0ix_state(dev_priv);

drivers/gpu/drm/i915/vlv_suspend.c

445

err = vlv_allow_gt_wake(dev_priv, true);

drivers/gpu/drm/i915/vlv_suspend.c

449

err = vlv_force_gfx_clock(dev_priv, false);

drivers/gpu/drm/i915/vlv_suspend.c

453

vlv_check_no_gt_access(dev_priv);

drivers/gpu/drm/i915/vlv_suspend.c

456

intel_clock_gating_init(&dev_priv->drm);

drivers/gpu/drm/sti/sti_compositor.c

67

struct sti_private *dev_priv = drm_dev->dev_private;

drivers/gpu/drm/sti/sti_compositor.c

73

dev_priv->compo = compo;

drivers/gpu/drm/sti/sti_crtc.c

285

struct sti_private *dev_priv = dev->dev_private;

drivers/gpu/drm/sti/sti_crtc.c

286

struct sti_compositor *compo = dev_priv->compo;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1068

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1078

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1095

vmw_collect_view_ids(cbs, loc, vmw_max_num_uavs(cbs->dev_priv));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1098

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1110

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1125

vmw_collect_view_ids(cbs, loc, vmw_max_num_uavs(cbs->dev_priv));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1128

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1140

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1281

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1287

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1303

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1333

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1339

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1346

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1359

vmw_binding_state_alloc(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

1368

cbs->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

576

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

582

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

591

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

608

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

614

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

625

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

644

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

653

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

663

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

678

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

684

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

692

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

707

struct vmw_private *dev_priv = bi->ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

713

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

730

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

836

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

847

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

872

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

886

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

954

cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

962

vmw_cmd_commit(ctx->dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c

98

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_binding.h

233

vmw_binding_state_alloc(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

124

int vmw_bo_pin_in_vram_or_gmr(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

132

vmw_execbuf_release_pinned_bo(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

172

int vmw_bo_pin_in_vram(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

176

return vmw_bo_pin_in_placement(dev_priv, buf, &vmw_vram_placement,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

193

int vmw_bo_pin_in_start_of_vram(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

201

vmw_execbuf_release_pinned_bo(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

251

int vmw_bo_unpin(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

406

static int vmw_bo_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

416

struct ttm_device *bdev = &dev_priv->bdev;

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

417

struct drm_device *vdev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

56

mutex_lock(&res->dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

67

mutex_unlock(&res->dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

675

struct vmw_private *dev_priv = vmw_priv_from_ttm(bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

679

vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

87

static int vmw_bo_pin_in_placement(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

96

vmw_execbuf_release_pinned_bo(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_bo.h

108

int vmw_bo_create(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.h

115

int vmw_bo_pin_in_vram(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_bo.h

118

int vmw_bo_pin_in_vram_or_gmr(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

103

if (!dev_priv->fifo_mem)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

123

if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

124

min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

130

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MIN, min);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

131

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

133

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, min);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

134

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_STOP, min);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

135

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_BUSY, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

138

vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

140

max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

141

min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

142

fifo->capabilities = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

144

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

151

drm_warn(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

159

void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

161

u32 *fifo_mem = dev_priv->fifo_mem;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

163

vmw_write(dev_priv, SVGA_REG_SYNC, reason);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

167

void vmw_fifo_destroy(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

169

struct vmw_fifo_state *fifo = dev_priv->fifo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

184

dev_priv->fifo = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

187

static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

189

uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

190

uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

191

uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

192

uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

197

static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

208

prepare_to_wait(&dev_priv->fifo_queue, &__wait,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

211

if (!vmw_fifo_is_full(dev_priv, bytes))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

224

finish_wait(&dev_priv->fifo_queue, &__wait);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

225

wake_up_all(&dev_priv->fifo_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

230

static int vmw_fifo_wait(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

236

if (likely(!vmw_fifo_is_full(dev_priv, bytes)))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

239

vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

240

if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

241

return vmw_fifo_wait_noirq(dev_priv, bytes,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

244

vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

245

&dev_priv->fifo_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

249

(dev_priv->fifo_queue,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

250

!vmw_fifo_is_full(dev_priv, bytes), timeout);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

253

(dev_priv->fifo_queue,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

254

!vmw_fifo_is_full(dev_priv, bytes), timeout);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

261

vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

262

&dev_priv->fifo_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

277

static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

280

struct vmw_fifo_state *fifo_state = dev_priv->fifo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

281

u32 *fifo_mem = dev_priv->fifo_mem;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

289

max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

290

min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

291

next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

302

uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

311

else if (vmw_fifo_is_full(dev_priv, bytes)) {

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

312

ret = vmw_fifo_wait(dev_priv, bytes,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

324

ret = vmw_fifo_wait(dev_priv, bytes,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

336

vmw_fifo_mem_write(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

36

bool vmw_supports_3d(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

365

void *vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

370

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

371

ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

374

ret = vmw_local_fifo_reserve(dev_priv, bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

39

const struct vmw_fifo_state *fifo = dev_priv->fifo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

41

if (!(dev_priv->capabilities & SVGA_CAP_3D))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

427

static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

429

struct vmw_fifo_state *fifo_state = dev_priv->fifo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

430

uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

431

uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

432

uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

44

if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

442

vmw_fifo_res_copy(fifo_state, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

445

vmw_fifo_slow_copy(fifo_state, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

461

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, next_cmd);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

465

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_RESERVED, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

468

vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

47

if (!dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

472

void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

474

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

475

vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

477

vmw_local_fifo_commit(dev_priv, bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

487

void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

489

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

490

vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

492

vmw_local_fifo_commit(dev_priv, bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

50

result = vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_3D);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

502

int vmw_cmd_flush(struct vmw_private *dev_priv, bool interruptible)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

506

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

507

return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

512

int vmw_cmd_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

519

fm = VMW_CMD_RESERVE(dev_priv, bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

521

*seqno = atomic_read(&dev_priv->marker_seq);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

523

(void)vmw_fallback_wait(dev_priv, false, true, *seqno,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

529

*seqno = atomic_add_return(1, &dev_priv->marker_seq);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

532

if (!vmw_has_fences(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

539

vmw_cmd_commit(dev_priv, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

546

vmw_cmd_commit_flush(dev_priv, bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

547

vmw_fences_update(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

55

if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

562

static int vmw_cmd_emit_dummy_legacy_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

571

struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->tbo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

577

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

58

BUG_ON(vmw_is_svga_v3(dev_priv));

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

594

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

60

fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

608

static int vmw_cmd_emit_dummy_gb_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

617

struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->tbo;

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

623

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

635

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

64

hwversion = vmw_fifo_mem_read(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

659

int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

662

if (dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

663

return vmw_cmd_emit_dummy_gb_query(dev_priv, cid);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

665

return vmw_cmd_emit_dummy_legacy_query(dev_priv, cid);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

77

if (dev_priv->active_display_unit == vmw_du_legacy)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

83

bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

87

if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

90

caps = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

97

struct vmw_fifo_state *vmw_fifo_create(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

116

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1226

struct vmw_private *dev_priv = man->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1234

man->map = dma_alloc_coherent(dev_priv->drm.dev, size,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1252

if (!(dev_priv->capabilities & SVGA_CAP_DX) ||

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1253

!dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1256

ret = vmw_bo_create(dev_priv, &bo_params, &man->cmd_space);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1276

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1293

struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1300

if (!(dev_priv->capabilities & SVGA_CAP_COMMAND_BUFFERS))

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1307

man->num_contexts = (dev_priv->capabilities & SVGA_CAP_HP_CMD_QUEUE) ?

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1310

dev_priv->drm.dev,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1319

dev_priv->drm.dev,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1338

man->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1341

vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ERROR,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1342

&dev_priv->error_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1382

dma_free_coherent(man->dev_priv->drm.dev,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1401

vmw_generic_waiter_remove(man->dev_priv, SVGA_IRQFLAG_ERROR,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

1402

&man->dev_priv->error_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

311

vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

315

vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

450

vmw_generic_waiter_remove(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

452

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

455

vmw_generic_waiter_add(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

457

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

617

vmw_cmd_send_fence(man->dev_priv, &dummy);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

728

vmw_generic_waiter_add(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

730

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

741

vmw_generic_waiter_remove(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

743

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

826

vmw_generic_waiter_add(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

828

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

837

(man->dev_priv, SVGA_IRQFLAG_COMMAND_BUFFER,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

838

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

845

vmw_generic_waiter_remove(man->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c

847

&man->dev_priv->cmdbuf_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c

283

vmw_cmdbuf_res_man_create(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c

291

man->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c

66

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

121

static void vmw_context_cotables_unref(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

126

u32 cotable_max = has_sm5_context(dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

144

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

153

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

155

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

158

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

159

if (dev_priv->pinned_bo != NULL &&

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

160

!dev_priv->query_cid_valid)

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

161

__vmw_execbuf_release_pinned_bo(dev_priv, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

162

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

163

vmw_context_cotables_unref(dev_priv, uctx);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

167

vmw_execbuf_release_pinned_bo(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

168

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

176

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

177

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

180

static int vmw_gb_context_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

191

ret = vmw_resource_init(dev_priv, res, true,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

198

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

199

uctx->man = vmw_cmdbuf_res_man_create(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

207

uctx->cbs = vmw_binding_state_alloc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

216

u32 cotable_max = has_sm5_context(dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

219

uctx->cotables[i] = vmw_cotable_alloc(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

232

vmw_context_cotables_unref(dev_priv, uctx);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

241

static int vmw_context_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

253

if (dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

254

return vmw_gb_context_init(dev_priv, dx, res, res_free);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

256

ret = vmw_resource_init(dev_priv, res, false,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

270

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

280

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

281

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

300

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

321

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

330

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

331

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

344

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

353

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

363

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

372

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

392

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

397

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

399

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

416

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

417

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

423

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

436

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

445

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

452

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

453

if (dev_priv->query_cid == res->id)

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

454

dev_priv->query_cid_valid = false;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

456

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

467

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

488

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

497

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

498

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

511

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

520

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

530

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

555

u32 cotable_max = has_sm5_context(ctx->dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

581

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

601

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

613

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

615

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

632

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

633

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

639

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

652

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

661

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

668

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

669

if (dev_priv->query_cid == res->id)

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

670

dev_priv->query_cid_valid = false;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

672

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

728

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

736

if (!has_sm4_context(dev_priv) && dx) {

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

755

ret = vmw_context_init(dev_priv, res, vmw_user_context_free, dx);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

822

u32 cotable_max = has_sm5_context(ctx->dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

184

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

194

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

207

vmw_cmd_commit_flush(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

259

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

275

co_info[vcotbl->type].unbind_func(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

282

cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

302

vmw_cmd_commit_flush(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

326

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

336

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

339

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

340

(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

359

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

368

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

377

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

380

(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

402

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

435

ret = vmw_bo_create(dev_priv, &bo_params, &buf);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

599

struct vmw_resource *vmw_cotable_alloc(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

613

ret = vmw_resource_init(dev_priv, &vcotbl->res, true,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

225

struct vmw_private *dev_priv = vmw_priv(vcp->base.dev);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

233

if (!dev_priv->has_mob ||

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

234

(dev_priv->capabilities2 & SVGA_CAP2_CURSOR_MOB) == 0)

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

237

mob_max_size = vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

238

cursor_max_dim = vmw_read(dev_priv, SVGA_REG_CURSOR_MAX_DIMENSION);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

260

ret = vmw_bo_create_and_populate(dev_priv, size, VMW_BO_DOMAIN_MOB,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

271

ret = vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

289

static void vmw_cursor_update_position(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

296

spin_lock(&dev_priv->cursor_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

297

if (dev_priv->capabilities2 & SVGA_CAP2_EXTRA_REGS) {

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

298

vmw_write(dev_priv, SVGA_REG_CURSOR4_X, x);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

299

vmw_write(dev_priv, SVGA_REG_CURSOR4_Y, y);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

300

vmw_write(dev_priv, SVGA_REG_CURSOR4_SCREEN_ID, SVGA3D_INVALID_ID);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

301

vmw_write(dev_priv, SVGA_REG_CURSOR4_ON, svga_cursor_on);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

302

vmw_write(dev_priv, SVGA_REG_CURSOR4_SUBMIT, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

303

} else if (vmw_is_cursor_bypass3_enabled(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

304

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_ON, svga_cursor_on);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

305

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_X, x);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

306

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_Y, y);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

307

count = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CURSOR_COUNT);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

308

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_COUNT, ++count);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

310

vmw_write(dev_priv, SVGA_REG_CURSOR_X, x);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

311

vmw_write(dev_priv, SVGA_REG_CURSOR_Y, y);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

312

vmw_write(dev_priv, SVGA_REG_CURSOR_ON, svga_cursor_on);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

314

spin_unlock(&dev_priv->cursor_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

39

static void vmw_send_define_cursor_cmd(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

54

cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

70

vmw_cmd_commit_flush(dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

750

struct vmw_private *dev_priv = vmw_priv(plane->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

759

vmw_cursor_update_position(dev_priv, false, 0, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

765

vmw_cursor_plane_update_legacy(dev_priv, vps);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

768

vmw_cursor_update_mob(dev_priv, vps);

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

773

vmw_send_define_cursor_cmd(dev_priv, bo->map.virtual,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

793

vmw_cursor_update_position(dev_priv, true, cursor_x + hotspot_x,

drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c

56

static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce,

drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c

80

(i, dev_priv->devcaps[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1000

if (unlikely(dev_priv->tdev == NULL)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1001

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1007

if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1008

ret = vmw_irq_install(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1010

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1016

dev_priv->fman = vmw_fence_manager_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1017

if (unlikely(dev_priv->fman == NULL)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1022

ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1023

dev_priv->drm.dev,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1024

dev_priv->drm.anon_inode->i_mapping,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1025

dev_priv->drm.vma_offset_manager,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1026

(dev_priv->map_mode == vmw_dma_alloc_coherent) ?

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1029

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1039

ret = vmw_vram_manager_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1041

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1046

ret = vmw_devcaps_create(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1048

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1058

dev_priv->has_gmr = true;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1060

if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1062

vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1063

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1066

dev_priv->has_gmr = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1069

if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1070

dev_priv->has_mob = true;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1072

if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1073

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1076

dev_priv->has_mob = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1078

if (vmw_sys_man_init(dev_priv) != 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1079

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1082

dev_priv->has_mob = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1086

if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1087

if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1088

dev_priv->sm_type = VMW_SM_4;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1092

if (has_sm4_context(dev_priv) &&

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1093

(dev_priv->capabilities2 & SVGA_CAP2_DX2)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1094

if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1095

dev_priv->sm_type = VMW_SM_4_1;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1096

if (has_sm4_1_context(dev_priv) &&

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1097

(dev_priv->capabilities2 & SVGA_CAP2_DX3)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1098

if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1099

dev_priv->sm_type = VMW_SM_5;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1100

if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1101

dev_priv->sm_type = VMW_SM_5_1X;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1106

ret = vmw_kms_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1109

vmw_overlay_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1111

ret = vmw_request_device(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1115

vmw_print_sm_type(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1119

vmw_write_driver_id(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1121

dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1122

register_pm_notifier(&dev_priv->pm_nb);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1127

vmw_overlay_close(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1128

vmw_kms_close(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1130

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1131

vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1132

vmw_sys_man_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1134

if (dev_priv->has_gmr)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1135

vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1136

vmw_devcaps_destroy(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1137

vmw_vram_manager_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1139

ttm_device_fini(&dev_priv->bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1141

vmw_fence_manager_takedown(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1143

if (dev_priv->capabilities & SVGA_CAP_IRQMASK)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1144

vmw_irq_uninstall(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1146

ttm_object_device_release(&dev_priv->tdev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1149

idr_destroy(&dev_priv->res_idr[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1151

if (dev_priv->ctx.staged_bindings)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1152

vmw_binding_state_free(dev_priv->ctx.staged_bindings);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1159

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1162

unregister_pm_notifier(&dev_priv->pm_nb);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1164

vmw_sw_context_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1165

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1167

vmw_svga_disable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1169

vmw_vkms_cleanup(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1170

vmw_kms_close(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1171

vmw_overlay_close(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1173

if (dev_priv->has_gmr)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1174

vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1176

vmw_release_device_early(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1177

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1178

vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1179

vmw_sys_man_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1181

vmw_devcaps_destroy(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1182

vmw_vram_manager_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1183

ttm_device_fini(&dev_priv->bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1184

vmw_release_device_late(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1185

vmw_fence_manager_takedown(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1186

if (dev_priv->capabilities & SVGA_CAP_IRQMASK)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1187

vmw_irq_uninstall(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1189

ttm_object_device_release(&dev_priv->tdev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1192

idr_destroy(&dev_priv->res_idr[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1194

vmw_mksstat_remove_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1208

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1216

vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1325

static void __vmw_svga_enable(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1327

struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1330

vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1340

void vmw_svga_enable(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1342

__vmw_svga_enable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1352

static void __vmw_svga_disable(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1354

struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1358

vmw_write(dev_priv, SVGA_REG_ENABLE,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1371

void vmw_svga_disable(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1373

struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1386

vmw_kms_lost_device(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1388

if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1391

vmw_write(dev_priv, SVGA_REG_ENABLE,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1428

struct vmw_private *dev_priv =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1441

dev_priv->suspend_locked = true;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1445

if (READ_ONCE(dev_priv->suspend_locked)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1446

dev_priv->suspend_locked = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1458

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1460

if (dev_priv->refuse_hibernation)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1497

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1507

ret = vmw_kms_suspend(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1513

vmw_execbuf_release_pinned_bo(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1514

vmw_resource_evict_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1515

vmw_release_device_early(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1516

while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1517

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1518

if (atomic_read(&dev_priv->num_fifo_resources) != 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1520

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1521

WARN_ON(vmw_request_device_late(dev_priv));

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1522

dev_priv->suspend_locked = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1523

if (dev_priv->suspend_state)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1528

vmw_fence_fifo_down(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1529

__vmw_svga_disable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1531

vmw_release_device_late(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1539

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1542

vmw_detect_version(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1544

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1546

ret = vmw_request_device(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1550

__vmw_svga_enable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1552

vmw_fence_fifo_up(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1553

dev_priv->suspend_locked = false;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1554

if (dev_priv->suspend_state)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

1555

vmw_kms_resume(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

346

static void vmw_print_sm_type(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

357

drm_info(&dev_priv->drm, "Available shader model: %s.\n",

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

358

names[dev_priv->sm_type]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

374

static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

395

ret = vmw_bo_create(dev_priv, &bo_params, &vbo);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

414

dev_priv->dummy_query_bo = vbo;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

419

static int vmw_device_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

423

dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

424

dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

425

dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

427

vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

430

uses_fb_traces = !vmw_cmd_supported(dev_priv) &&

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

431

(dev_priv->capabilities & SVGA_CAP_TRACES) != 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

433

vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

434

dev_priv->fifo = vmw_fifo_create(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

435

if (IS_ERR(dev_priv->fifo)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

436

int err = PTR_ERR(dev_priv->fifo);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

437

dev_priv->fifo = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

439

} else if (!dev_priv->fifo) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

440

vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

443

u32 seqno = vmw_fence_read(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

445

atomic_set(&dev_priv->last_read_seqno, seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

446

atomic_set(&dev_priv->marker_seq, seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

481

static int vmw_request_device_late(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

485

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

486

ret = vmw_otables_setup(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

494

if (dev_priv->cman) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

495

ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

497

struct vmw_cmdbuf_man *man = dev_priv->cman;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

499

dev_priv->cman = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

507

static int vmw_request_device(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

511

ret = vmw_device_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

516

vmw_fence_fifo_up(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

517

dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

518

if (IS_ERR(dev_priv->cman)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

519

dev_priv->cman = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

520

dev_priv->sm_type = VMW_SM_LEGACY;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

523

ret = vmw_request_device_late(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

527

ret = vmw_dummy_query_bo_create(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

534

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

535

vmw_cmdbuf_remove_pool(dev_priv->cman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

536

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

539

man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

540

ttm_resource_manager_evict_all(&dev_priv->bdev, man);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

541

vmw_otables_takedown(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

543

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

544

vmw_cmdbuf_man_destroy(dev_priv->cman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

546

vmw_fence_fifo_down(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

547

vmw_device_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

559

static void vmw_release_device_early(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

566

BUG_ON(dev_priv->pinned_bo != NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

568

vmw_bo_unreference(&dev_priv->dummy_query_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

569

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

570

vmw_cmdbuf_remove_pool(dev_priv->cman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

572

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

575

man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

576

ttm_resource_manager_evict_all(&dev_priv->bdev, man);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

577

vmw_otables_takedown(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

589

static void vmw_release_device_late(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

591

vmw_fence_fifo_down(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

592

if (dev_priv->cman)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

593

vmw_cmdbuf_man_destroy(dev_priv->cman);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

595

vmw_device_fini(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

607

static void vmw_get_initial_size(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

612

width = vmw_read(dev_priv, SVGA_REG_WIDTH);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

613

height = vmw_read(dev_priv, SVGA_REG_HEIGHT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

618

if (width > dev_priv->fb_max_width ||

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

619

height > dev_priv->fb_max_height) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

629

dev_priv->initial_width = width;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

630

dev_priv->initial_height = height;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

645

static int vmw_dma_select_mode(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

658

dev_priv->map_mode = vmw_dma_alloc_coherent;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

660

dev_priv->map_mode = vmw_dma_map_bind;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

662

dev_priv->map_mode = vmw_dma_map_populate;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

664

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

665

"DMA map mode: %s\n", names[dev_priv->map_mode]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

677

static int vmw_dma_masks(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

679

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

684

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

692

static int vmw_vram_manager_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

695

ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

696

dev_priv->vram_size >> PAGE_SHIFT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

697

ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

701

static void vmw_vram_manager_fini(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

703

ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

817

static void vmw_sw_context_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

819

struct vmw_sw_context *sw_context = &dev_priv->ctx;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

824

static void vmw_sw_context_fini(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

826

struct vmw_sw_context *sw_context = &dev_priv->ctx;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

833

static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

839

vmw_sw_context_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

841

mutex_init(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

842

mutex_init(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

843

spin_lock_init(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

844

spin_lock_init(&dev_priv->hw_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

845

spin_lock_init(&dev_priv->waiter_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

846

spin_lock_init(&dev_priv->cursor_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

848

ret = vmw_setup_pci_resources(dev_priv, pci_id);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

851

ret = vmw_detect_version(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

857

idr_init_base(&dev_priv->res_idr[i], 1);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

858

INIT_LIST_HEAD(&dev_priv->res_lru[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

861

init_waitqueue_head(&dev_priv->fence_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

862

init_waitqueue_head(&dev_priv->fifo_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

863

dev_priv->fence_queue_waiters = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

864

dev_priv->fifo_queue_waiters = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

866

dev_priv->used_memory_size = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

868

dev_priv->assume_16bpp = !!vmw_assume_16bpp;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

870

dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

871

vmw_print_bitmap(&dev_priv->drm, "Capabilities",

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

872

dev_priv->capabilities,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

874

if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

875

dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

876

vmw_print_bitmap(&dev_priv->drm, "Capabilities2",

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

877

dev_priv->capabilities2,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

881

if (!vmwgfx_supported(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

883

drm_err_once(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

885

drm_err_once(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

887

drm_err_once(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

891

vmw_vkms_init(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

893

ret = vmw_dma_select_mode(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

895

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

898

if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

899

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

903

dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

904

dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

905

dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

906

dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

908

vmw_get_initial_size(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

910

if (dev_priv->capabilities & SVGA_CAP_GMR2) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

911

dev_priv->max_gmr_ids =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

912

vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

913

dev_priv->max_gmr_pages =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

914

vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

915

dev_priv->memory_size =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

916

vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

917

dev_priv->memory_size -= dev_priv->vram_size;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

923

dev_priv->memory_size = 512*1024*1024;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

925

dev_priv->max_mob_pages = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

926

dev_priv->max_mob_size = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

927

if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

930

if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

931

mem_size = vmw_read(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

935

vmw_read(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

938

dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

939

dev_priv->max_primary_mem =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

940

vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

941

dev_priv->max_mob_size =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

942

vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

943

dev_priv->stdu_max_width =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

944

vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

945

dev_priv->stdu_max_height =

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

946

vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

948

vmw_write(dev_priv, SVGA_REG_DEV_CAP,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

950

dev_priv->texture_max_width = vmw_read(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

952

vmw_write(dev_priv, SVGA_REG_DEV_CAP,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

954

dev_priv->texture_max_height = vmw_read(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

957

dev_priv->texture_max_width = 8192;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

958

dev_priv->texture_max_height = 8192;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

959

dev_priv->max_primary_mem = dev_priv->vram_size;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

961

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

963

(u64)dev_priv->vram_size / 1024,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

964

(u64)dev_priv->fifo_mem_size / 1024,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

965

dev_priv->memory_size / 1024);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

967

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

969

dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

971

ret = vmw_dma_masks(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

975

dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

977

if (dev_priv->capabilities & SVGA_CAP_GMR2) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

978

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

980

(unsigned)dev_priv->max_gmr_ids);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

981

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

983

(unsigned)dev_priv->max_gmr_pages);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

985

drm_info(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

987

(uint64_t)dev_priv->max_primary_mem / 1024);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

990

if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

991

!(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

992

!vmw_fifo_have_pitchlock(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

998

dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1000

struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1003

extern int vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1017

extern int vmw_irq_install(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1019

extern bool vmw_seqno_passed(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1021

extern int vmw_fallback_wait(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1027

bool vmw_seqno_waiter_add(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1028

bool vmw_seqno_waiter_remove(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1029

bool vmw_goal_waiter_add(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1030

bool vmw_goal_waiter_remove(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1031

bool vmw_generic_waiter_add(struct vmw_private *dev_priv, u32 flag,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1033

bool vmw_generic_waiter_remove(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1040

int vmw_kms_init(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1041

int vmw_kms_close(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1051

int vmw_kms_present(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1072

int vmw_overlay_init(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1073

int vmw_overlay_close(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1076

int vmw_overlay_resume_all(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1077

int vmw_overlay_pause_all(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1078

int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1079

int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1080

int vmw_overlay_num_overlays(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1081

int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1087

int vmw_gmrid_man_init(struct vmw_private *dev_priv, int type);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1088

void vmw_gmrid_man_fini(struct vmw_private *dev_priv, int type);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1093

int vmw_sys_man_init(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1094

void vmw_sys_man_fini(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1116

extern int vmw_mob_bind(struct vmw_private *dev_priv, struct vmw_mob *mob,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1119

extern void vmw_mob_unbind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1123

extern int vmw_otables_setup(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1124

extern void vmw_otables_takedown(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1177

int vmw_gb_surface_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1200

extern int vmw_compat_shader_add(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1214

extern void vmw_dx_shader_cotable_list_scrub(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1236

void vmw_dx_streamoutput_cotable_list_scrub(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1245

vmw_cmdbuf_res_man_create(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1268

extern struct vmw_resource *vmw_cotable_alloc(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1283

vmw_cmdbuf_man_create(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1360

int vmw_mksstat_get_kern_slot(pid_t pid, struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1368

int vmw_mksstat_remove_all(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

137

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1426

static inline void vmw_fifo_resource_inc(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1428

atomic_inc(&dev_priv->num_fifo_resources);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1431

static inline void vmw_fifo_resource_dec(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1433

atomic_dec(&dev_priv->num_fifo_resources);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1468

static inline u32 vmw_fence_read(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1471

if (vmw_is_svga_v3(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1472

fence = vmw_read(dev_priv, SVGA_REG_FENCE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1474

fence = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1478

static inline void vmw_fence_write(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1481

BUG_ON(vmw_is_svga_v3(dev_priv));

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

1482

vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, fence);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

337

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

659

static inline void vmw_write(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

662

if (vmw_is_svga_v3(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

663

iowrite32(value, dev_priv->rmmio + offset);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

665

spin_lock(&dev_priv->hw_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

666

outl(offset, dev_priv->io_start + SVGA_INDEX_PORT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

667

outl(value, dev_priv->io_start + SVGA_VALUE_PORT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

668

spin_unlock(&dev_priv->hw_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

672

static inline uint32_t vmw_read(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

677

if (vmw_is_svga_v3(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

678

val = ioread32(dev_priv->rmmio + offset);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

680

spin_lock(&dev_priv->hw_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

681

outl(offset, dev_priv->io_start + SVGA_INDEX_PORT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

682

val = inl(dev_priv->io_start + SVGA_VALUE_PORT);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

683

spin_unlock(&dev_priv->hw_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

695

static inline bool has_sm4_context(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

697

return (dev_priv->sm_type >= VMW_SM_4);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

706

static inline bool has_sm4_1_context(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

708

return (dev_priv->sm_type >= VMW_SM_4_1);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

717

static inline bool has_sm5_context(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

719

return (dev_priv->sm_type >= VMW_SM_5);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

728

static inline bool has_gl43_context(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

730

return (dev_priv->sm_type >= VMW_SM_5_1X);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

734

static inline u32 vmw_max_num_uavs(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

736

return (has_gl43_context(dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

740

extern void vmw_svga_enable(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

741

extern void vmw_svga_disable(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

749

extern int vmw_gmr_bind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

753

extern void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

763

int vmw_user_object_lookup(struct vmw_private *dev_priv, struct drm_file *filp,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

790

struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

800

extern int vmw_user_stream_lookup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

814

void vmw_resource_evict_all(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

840

extern int vmw_gem_object_create_with_handle(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

866

extern struct vmw_fifo_state *vmw_fifo_create(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

867

extern void vmw_fifo_destroy(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

870

vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

871

extern void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

872

extern void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

873

extern int vmw_cmd_send_fence(struct vmw_private *dev_priv, uint32_t *seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

874

extern bool vmw_supports_3d(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

875

extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

876

extern bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

877

extern int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

879

extern int vmw_cmd_flush(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

902

static inline uint32_t vmw_fifo_caps(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

904

if (!dev_priv->fifo_mem || !dev_priv->fifo)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

906

return dev_priv->fifo->capabilities;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

918

vmw_is_cursor_bypass3_enabled(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

920

return (vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_CURSOR_BYPASS_3) != 0;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

933

int vmw_bo_create_and_populate(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

985

struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

995

extern void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

997

extern void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1006

static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1034

vmw_bo_placement_set_default_accelerated(dev_priv->dummy_query_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1036

dev_priv->dummy_query_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1061

static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1077

ret = vmw_cmd_emit_dummy_query(dev_priv, ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1083

if (dev_priv->pinned_bo != sw_context->cur_query_bo) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1084

if (dev_priv->pinned_bo) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1085

vmw_bo_pin_reserved(dev_priv->pinned_bo, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1086

vmw_bo_unreference(&dev_priv->pinned_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1097

if (!dev_priv->dummy_query_bo_pinned) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1098

vmw_bo_pin_reserved(dev_priv->dummy_query_bo,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1100

dev_priv->dummy_query_bo_pinned = true;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1104

dev_priv->query_cid = sw_context->last_query_ctx->id;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1105

dev_priv->query_cid_valid = true;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1106

dev_priv->pinned_bo =

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1132

static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1145

drm_dbg(&dev_priv->drm, "Could not find or use MOB buffer.\n");

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1188

static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1201

drm_dbg(&dev_priv->drm, "Could not find or use GMR region.\n");

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1233

static int vmw_cmd_dx_define_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1270

static int vmw_cmd_dx_bind_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1284

ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

129

static int vmw_resource_context_res_add(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1302

static int vmw_cmd_begin_gb_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1309

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

132

static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1321

static int vmw_cmd_begin_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1328

if (unlikely(dev_priv->has_mob)) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1339

return vmw_cmd_begin_gb_query(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1342

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1354

static int vmw_cmd_end_gb_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1363

ret = vmw_cmd_cid_check(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1367

ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1372

ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1384

static int vmw_cmd_end_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1393

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1406

return vmw_cmd_end_gb_query(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1409

ret = vmw_cmd_cid_check(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1413

ret = vmw_translate_guest_ptr(dev_priv, sw_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1418

ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1430

static int vmw_cmd_wait_gb_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1439

ret = vmw_cmd_cid_check(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1443

ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1458

static int vmw_cmd_wait_query(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1467

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1480

return vmw_cmd_wait_gb_query(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1483

ret = vmw_cmd_cid_check(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1487

ret = vmw_translate_guest_ptr(dev_priv, sw_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1495

static int vmw_cmd_dma(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1518

ret = vmw_translate_guest_ptr(dev_priv, sw_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1536

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dirty,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1558

static int vmw_cmd_draw(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1570

ret = vmw_cmd_cid_check(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1583

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1600

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1610

static int vmw_cmd_tex_state(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1625

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1641

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1648

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1668

static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1679

return vmw_translate_guest_ptr(dev_priv, sw_context, &cmd->body.ptr,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1698

static int vmw_cmd_res_switch_backup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1711

ret = vmw_translate_mob_ptr(dev_priv, sw_context, buf_id, &vbo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1736

static int vmw_cmd_switch_backup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1746

ret = vmw_cmd_res_check(dev_priv, sw_context, res_type,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1751

return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, buf_id,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1762

static int vmw_cmd_bind_gb_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1769

return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1781

static int vmw_cmd_update_gb_image(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1788

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1800

static int vmw_cmd_update_gb_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1807

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1819

static int vmw_cmd_readback_gb_image(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1826

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1839

static int vmw_cmd_readback_gb_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1846

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1859

static int vmw_cmd_invalidate_gb_image(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1866

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1879

static int vmw_cmd_invalidate_gb_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1886

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1898

static int vmw_cmd_shader_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1909

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1915

if (unlikely(!dev_priv->has_mob))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1919

ret = vmw_compat_shader_add(dev_priv, vmw_context_res_man(ctx),

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1938

static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1948

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1954

if (unlikely(!dev_priv->has_mob))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

196

static int vmw_cmd_ctx_first_setup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1975

static int vmw_cmd_set_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1993

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

1999

if (!dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2028

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_shader,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

203

ret = vmw_resource_context_res_add(dev_priv, sw_context, res);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2056

static int vmw_cmd_set_shader_const(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2065

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2071

if (dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

208

sw_context->staged_bindings = vmw_binding_state_alloc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2084

static int vmw_cmd_bind_gb_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2091

return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_shader,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2105

vmw_cmd_dx_set_single_constant_buffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2120

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2126

if (!vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type) ||

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2157

vmw_cmd_dx_set_constant_buffer_offset(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2166

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

217

node->staged = vmw_binding_state_alloc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2194

static int vmw_cmd_dx_set_shader_res(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2206

!vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type)) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2225

static int vmw_cmd_dx_set_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2240

if (!vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type)) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2278

static int vmw_cmd_dx_set_vertex_buffers(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2305

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2333

static int vmw_cmd_dx_set_index_buffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2347

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2372

static int vmw_cmd_dx_set_rendertargets(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2405

static int vmw_cmd_dx_clear_rendertarget_view(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2427

static int vmw_cmd_dx_clear_depthstencil_view(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2441

static int vmw_cmd_dx_view_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2472

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2498

static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

250

static unsigned int vmw_execbuf_res_size(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2524

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

254

(res_type == vmw_res_context && dev_priv->has_mob)) ?

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2544

static int vmw_cmd_dx_so_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2582

static int vmw_cmd_dx_check_subresource(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2604

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2609

static int vmw_cmd_dx_cid_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2632

static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2672

static int vmw_cmd_dx_define_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2704

static int vmw_cmd_dx_destroy_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2729

static int vmw_cmd_dx_bind_shader(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2740

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2769

return vmw_cmd_res_switch_backup(dev_priv, sw_context, res,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2781

static int vmw_cmd_dx_genmips(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2815

static int vmw_cmd_dx_transfer_from_buffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2823

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2829

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2841

static int vmw_cmd_intra_surface_copy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2848

if (!(dev_priv->capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2851

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2856

static int vmw_cmd_sm5(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2860

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2866

static int vmw_cmd_sm5_view_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2870

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2873

return vmw_cmd_dx_view_define(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2876

static int vmw_cmd_sm5_view_remove(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2880

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2883

return vmw_cmd_dx_view_remove(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2886

static int vmw_cmd_clear_uav_uint(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2896

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2905

static int vmw_cmd_clear_uav_float(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2915

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2924

static int vmw_cmd_set_uav(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2936

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2939

if (num_uav > vmw_max_num_uavs(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2956

static int vmw_cmd_set_cs_uav(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2968

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

297

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2971

if (num_uav > vmw_max_num_uavs(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

2988

static int vmw_cmd_dx_define_streamoutput(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3000

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3020

static int vmw_cmd_dx_destroy_streamoutput(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3040

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3056

static int vmw_cmd_dx_bind_streamoutput(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3068

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3092

return vmw_cmd_res_switch_backup(dev_priv, sw_context, res,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3097

static int vmw_cmd_dx_set_streamoutput(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3122

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3153

static int vmw_cmd_indexed_instanced_indirect(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3162

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3165

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3170

static int vmw_cmd_instanced_indirect(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3179

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3182

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3187

static int vmw_cmd_dispatch_indirect(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3196

if (!has_sm5_context(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3199

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

320

priv_size = vmw_execbuf_res_size(dev_priv, res_type);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3204

static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3242

return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

328

ret = vmw_cmd_ctx_first_setup(dev_priv, sw_context, res,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3653

static int vmw_cmd_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3662

bool gb = dev_priv->capabilities & SVGA_CAP_GBOBJECTS;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3667

return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3698

ret = entry->func(dev_priv, sw_context, header);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3724

static int vmw_cmd_check_all(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3735

ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3820

struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3831

ret = vmw_cmd_send_fence(dev_priv, &sequence);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3838

ret = vmw_user_fence_create(file_priv, dev_priv->fman,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3841

ret = vmw_fence_create(dev_priv->fman, sequence, p_fence);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3844

(void) vmw_fallback_wait(dev_priv, false, false, sequence,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3873

vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3893

fence_rep.passed_seqno = vmw_fences_update(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3929

static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3936

cmd = VMW_CMD_CTX_RESERVE(dev_priv, command_size,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3939

cmd = VMW_CMD_RESERVE(dev_priv, command_size);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3948

vmw_cmd_commit(dev_priv, command_size);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3965

static int vmw_execbuf_submit_cmdbuf(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3972

void *cmd = vmw_cmdbuf_reserve(dev_priv->cman, command_size, id, false,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

3978

vmw_cmdbuf_commit(dev_priv->cman, command_size, header, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4007

static void *vmw_execbuf_cmdbuf(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4021

if (!dev_priv->cman || kernel_commands)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4027

kernel_commands = vmw_cmdbuf_alloc(dev_priv->cman, cmdbuf_size, true,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4043

static int vmw_execbuf_tie_context(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4054

size = vmw_execbuf_res_size(dev_priv, vmw_res_dx_context);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4060

(dev_priv, sw_context->fp->tfile, handle,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4083

struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4090

struct vmw_sw_context *sw_context = &dev_priv->ctx;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4111

kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4119

ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4147

sw_context->cur_query_bo = dev_priv->pinned_bo;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

416

static int vmw_resource_context_res_add(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4162

ret = vmw_execbuf_tie_context(dev_priv, sw_context, dx_context_handle);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4166

ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4189

ret = mutex_lock_interruptible(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4195

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4202

ret = vmw_execbuf_submit_fifo(dev_priv, kernel_commands,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4205

ret = vmw_execbuf_submit_cmdbuf(dev_priv, header, command_size,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4209

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4213

vmw_query_bo_switch_commit(dev_priv, sw_context);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4214

ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4230

if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4231

__vmw_execbuf_release_pinned_bo(dev_priv, fence);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

425

u32 cotable_max = has_sm5_context(ctx->dev_priv) ?

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4251

ret = vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4274

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4285

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

429

if (has_sm4_context(dev_priv) &&

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4293

if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid))

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4294

__vmw_execbuf_release_pinned_bo(dev_priv, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4299

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4325

static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4329

(void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4330

vmw_bo_pin_reserved(dev_priv->pinned_bo, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4331

if (dev_priv->dummy_query_bo_pinned) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4332

vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4333

dev_priv->dummy_query_bo_pinned = false;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4361

void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4368

if (dev_priv->pinned_bo == NULL)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4371

vmw_bo_placement_set(dev_priv->pinned_bo,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4374

ret = vmw_validation_add_bo(&val_ctx, dev_priv->pinned_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4378

vmw_bo_placement_set(dev_priv->dummy_query_bo,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4381

ret = vmw_validation_add_bo(&val_ctx, dev_priv->dummy_query_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4389

if (dev_priv->query_cid_valid) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4391

ret = vmw_cmd_emit_dummy_query(dev_priv, dev_priv->query_cid);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4394

dev_priv->query_cid_valid = false;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4397

vmw_bo_pin_reserved(dev_priv->pinned_bo, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4398

if (dev_priv->dummy_query_bo_pinned) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4399

vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4400

dev_priv->dummy_query_bo_pinned = false;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4403

(void) vmw_execbuf_fence_commands(NULL, dev_priv, &lfence,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4412

vmw_bo_unreference(&dev_priv->pinned_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4420

vmw_execbuf_unpin_panic(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4421

vmw_bo_unreference(&dev_priv->pinned_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4440

void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4442

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4443

if (dev_priv->query_cid_valid)

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4444

__vmw_execbuf_release_pinned_bo(dev_priv, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4445

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

445

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4451

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

4498

ret = vmw_execbuf_process(file_priv, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

459

if (has_sm4_context(dev_priv) &&

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

473

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

553

static int vmw_cmd_invalid(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

560

static int vmw_cmd_ok(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

614

vmw_cmd_res_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

644

unsigned int size = vmw_execbuf_res_size(dev_priv, res_type);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

651

(dev_priv, sw_context->fp->tfile, *id_loc, converter, &res);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

692

struct vmw_private *dev_priv = ctx_res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

701

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), ctx_res->id);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

709

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

806

static int vmw_cmd_cid_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

813

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

846

static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

863

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

869

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

875

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

893

static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

902

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

908

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

913

static int vmw_cmd_buffer_copy_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

921

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

927

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

932

static int vmw_cmd_pred_copy_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

940

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

946

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

951

static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

959

ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

965

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

970

static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

977

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

982

static int vmw_cmd_present_check(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

989

return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

104

struct vmw_private *dev_priv = fman->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

106

seqno = vmw_fence_read(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

109

vmw_seqno_waiter_remove(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

115

if (vmw_seqno_waiter_add(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

130

struct vmw_fence_manager *vmw_fence_manager_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

137

fman->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

14

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

190

const u32 seqno = vmw_fence_read(fman->dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

196

vmw_seqno_waiter_remove(fman->dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

204

atomic_set_release(&fman->dev_priv->last_read_seqno, seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

486

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

497

arg->passed_seqno = atomic_read_acquire(&dev_priv->last_read_seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

588

eaction->dev = &fman->dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

612

struct drm_device *dev = &fman->dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

660

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

705

ret = vmw_execbuf_fence_commands(file_priv, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

727

vmw_execbuf_copy_fence_user(dev_priv, vmw_fp, 0, user_fence_rep, fence,

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c

74

vmw_seqno_waiter_remove(fman->dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_fence.h

50

vmw_fence_manager_init(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

157

int vmw_gem_object_create_with_handle(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

165

.domain = (dev_priv->has_mob) ? VMW_BO_DOMAIN_SYS : VMW_BO_DOMAIN_VRAM,

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

172

ret = vmw_bo_create(dev_priv, &params, p_vbo);

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

186

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

190

.domain = (dev_priv->has_mob) ? VMW_BO_DOMAIN_SYS : VMW_BO_DOMAIN_VRAM,

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

203

ret = vmw_bo_create(dev_priv, &params, &vbo);

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

218

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

227

ret = vmw_gem_object_create_with_handle(dev_priv, filp,

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

100

vmw_cmd_commit(dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

105

static void vmw_gmr2_unbind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

112

cmd = VMW_CMD_RESERVE(dev_priv, define_size);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

122

vmw_cmd_commit(dev_priv, define_size);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

126

int vmw_gmr_bind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

138

if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR2)))

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

141

return vmw_gmr2_bind(dev_priv, &data_iter, num_pages, gmr_id);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

145

void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id)

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

147

if (likely(dev_priv->capabilities & SVGA_CAP_GMR2))

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

148

vmw_gmr2_unbind(dev_priv, gmr_id);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

37

static int vmw_gmr2_bind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c

53

cmd_orig = cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

154

int vmw_gmrid_man_init(struct vmw_private *dev_priv, int type)

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

166

ttm_resource_manager_init(man, &dev_priv->bdev, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

174

gman->max_gmr_ids = dev_priv->max_gmr_ids;

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

175

gman->max_gmr_pages = dev_priv->max_gmr_pages;

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

179

gman->max_gmr_pages = dev_priv->max_mob_pages;

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

184

ttm_set_driver_manager(&dev_priv->bdev, type, &gman->manager);

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

189

void vmw_gmrid_man_fini(struct vmw_private *dev_priv, int type)

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

191

struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, type);

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

196

ttm_resource_manager_evict_all(&dev_priv->bdev, man);

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

200

ttm_set_driver_manager(&dev_priv->bdev, type, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

101

param->value = has_sm4_context(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

104

param->value = has_sm4_1_context(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

107

param->value = has_sm5_context(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

110

param->value = has_gl43_context(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

113

param->value = to_pci_dev(dev_priv->drm.dev)->device;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

128

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

140

size = vmw_devcaps_size(dev_priv, vmw_fp->gb_aware);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

155

ret = vmw_devcaps_copy(dev_priv, vmw_fp->gb_aware, bounce, size);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

175

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

223

ret = vmw_user_resource_lookup_handle(dev_priv, tfile, arg->sid,

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

230

ret = vmw_kms_present(dev_priv, file_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

251

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

306

ret = vmw_kms_readback(dev_priv, file_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

39

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

46

param->value = vmw_overlay_num_overlays(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

49

param->value = vmw_overlay_num_free_overlays(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

52

param->value = vmw_supports_3d(dev_priv) ? 1 : 0;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

55

param->value = dev_priv->capabilities;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

58

param->value = dev_priv->capabilities2;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

61

param->value = vmw_fifo_caps(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

64

param->value = dev_priv->max_primary_mem;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

68

if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS))

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

72

dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

73

((vmw_fifo_caps(dev_priv) &

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

80

if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) &&

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

82

param->value = dev_priv->max_mob_pages * PAGE_SIZE / 2;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

84

param->value = dev_priv->memory_size;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

87

param->value = vmw_devcaps_size(dev_priv, vmw_fp->gb_aware);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

91

param->value = dev_priv->max_mob_pages * PAGE_SIZE;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

94

param->value = dev_priv->max_mob_size;

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

98

(dev_priv->active_display_unit == vmw_du_screen_target);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

104

wake_up_all(&dev_priv->fifo_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

107

vmw_irqflag_fence_goal(dev_priv))) &&

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

108

!test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

114

dev_priv->irqthread_pending))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

120

static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

123

return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

126

bool vmw_seqno_passed(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

130

u32 last_read_seqno = atomic_read_acquire(&dev_priv->last_read_seqno);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

135

last_read_seqno = vmw_fences_update(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

139

if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

147

ret = ((atomic_read(&dev_priv->marker_seq) - seqno)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

153

int vmw_fallback_wait(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

160

struct vmw_fifo_state *fifo_state = dev_priv->fifo;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

178

if (dev_priv->cman) {

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

179

ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

189

signal_seq = atomic_read(&dev_priv->marker_seq);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

193

prepare_to_wait(&dev_priv->fence_queue, &__wait,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

196

if (wait_condition(dev_priv, seqno))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

221

finish_wait(&dev_priv->fence_queue, &__wait);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

223

vmw_fence_write(dev_priv, signal_seq);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

225

wake_up_all(&dev_priv->fence_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

233

bool vmw_generic_waiter_add(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

238

spin_lock(&dev_priv->waiter_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

240

vmw_irq_status_write(dev_priv, flag);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

241

dev_priv->irq_mask |= flag;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

242

vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

245

spin_unlock(&dev_priv->waiter_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

249

bool vmw_generic_waiter_remove(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

254

spin_lock(&dev_priv->waiter_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

256

dev_priv->irq_mask &= ~flag;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

257

vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

260

spin_unlock(&dev_priv->waiter_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

264

bool vmw_seqno_waiter_add(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

266

return vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

267

&dev_priv->fence_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

270

bool vmw_seqno_waiter_remove(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

272

return vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

273

&dev_priv->fence_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

276

bool vmw_goal_waiter_add(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

278

return vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv),

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

279

&dev_priv->goal_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

282

bool vmw_goal_waiter_remove(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

284

return vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv),

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

285

&dev_priv->goal_queue_waiters);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

290

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

293

status = vmw_irq_status_read(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

294

vmw_irq_status_write(dev_priv, status);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

299

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

304

if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

307

vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

309

status = vmw_irq_status_read(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

310

vmw_irq_status_write(dev_priv, status);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

312

for (i = 0; i < dev_priv->num_irq_vectors; ++i)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

313

free_irq(dev_priv->irqs[i], dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

316

dev_priv->num_irq_vectors = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

325

int vmw_irq_install(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

327

struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

328

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

340

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

351

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

355

dev_priv->irqs[i] = ret;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

357

ret = request_threaded_irq(dev_priv->irqs[i], vmw_irq_handler, vmw_thread_fn,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

360

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

362

dev_priv->irqs[i], ret);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

368

dev_priv->num_irq_vectors = i;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

57

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

61

dev_priv->irqthread_pending)) {

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

62

vmw_fences_update(dev_priv->fman);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

63

wake_up_all(&dev_priv->fence_queue);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

68

dev_priv->irqthread_pending)) {

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

69

vmw_cmdbuf_irqthread(dev_priv->cman);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

90

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

94

status = vmw_irq_status_read(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

95

masked_status = status & READ_ONCE(dev_priv->irq_mask);

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

98

vmw_irq_status_write(dev_priv, status);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1072

static int vmw_kms_generic_present(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1081

return vmw_kms_sou_do_surface_dirty(dev_priv, vfb, NULL, clips,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1087

int vmw_kms_present(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1098

switch (dev_priv->active_display_unit) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1100

ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL, clips,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1105

ret = vmw_kms_generic_present(dev_priv, file_priv, vfb, surface,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1118

vmw_cmd_flush(dev_priv, false);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1124

vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1126

if (dev_priv->hotplug_mode_update_property)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1129

dev_priv->hotplug_mode_update_property =

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1130

drm_property_create_range(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1158

int vmw_kms_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1160

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1174

dev->mode_config.max_width = dev_priv->texture_max_width;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1175

dev->mode_config.max_height = dev_priv->texture_max_height;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1176

dev->mode_config.preferred_depth = dev_priv->assume_16bpp ? 16 : 32;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1180

vmw_kms_create_hotplug_mode_update_property(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1182

ret = vmw_kms_stdu_init_display(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1184

ret = vmw_kms_sou_init_display(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1186

ret = vmw_kms_ldu_init_display(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1189

drm_info(&dev_priv->drm, "%s display unit initialized\n",

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1190

display_unit_names[dev_priv->active_display_unit]);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1195

int vmw_kms_close(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1204

drm_mode_config_cleanup(&dev_priv->drm);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1205

if (dev_priv->active_display_unit == vmw_du_legacy)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1206

ret = vmw_kms_ldu_close_display(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1234

bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1238

return (pitch * height) < (u64)dev_priv->vram_size;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1248

static int vmw_du_update_layout(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1251

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1327

struct vmw_private *dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1333

vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1334

vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1335

vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1351

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1354

num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1404

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1418

vmw_du_update_layout(dev_priv, 1, &def_rect);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1481

vmw_du_update_layout(dev_priv, arg->num_outputs, drm_rects);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1505

int vmw_kms_helper_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1519

dirty->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1525

list_for_each_entry(crtc, &dev_priv->drm.mode_config.crtc_list,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1545

dirty->cmd = VMW_CMD_RESERVE(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1621

void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1634

ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1638

vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv),

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1656

vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1658

if (dev_priv->implicit_placement_property)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1661

dev_priv->implicit_placement_property =

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1662

drm_property_create_range(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1675

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1677

dev_priv->suspend_state = drm_atomic_helper_suspend(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1678

if (IS_ERR(dev_priv->suspend_state)) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1679

int ret = PTR_ERR(dev_priv->suspend_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1682

dev_priv->suspend_state = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1702

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1705

if (WARN_ON(!dev_priv->suspend_state))

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1708

ret = drm_atomic_helper_resume(dev, dev_priv->suspend_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1709

dev_priv->suspend_state = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1769

if (update->dev_priv->active_display_unit == vmw_du_screen_target) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1774

WARN_ON(update->dev_priv->has_mob);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1796

cmd_start = VMW_CMD_RESERVE(update->dev_priv, reserved_size);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1845

vmw_cmd_commit(update->dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1847

vmw_kms_helper_validation_finish(update->dev_priv, NULL, &val_ctx,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1872

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1875

if (dev_priv->assume_16bpp)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1878

ret = drm_mode_validate_size(mode, dev_priv->texture_max_width,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1879

dev_priv->texture_max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1883

if (!vmw_kms_validate_mode_vram(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1902

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1927

max_width = dev_priv->texture_max_width;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1928

max_height = dev_priv->texture_max_height;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1930

if (dev_priv->active_display_unit == vmw_du_screen_target) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1931

max_width = min(dev_priv->stdu_max_width, max_width);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1932

max_height = min(dev_priv->stdu_max_height, max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

31

struct vmw_private *dev_priv = vmw_priv(du->primary.dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

35

if (vmw_cmd_supported(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

458

int vmw_kms_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

465

switch (dev_priv->active_display_unit) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

467

return vmw_kms_sou_readback(dev_priv, file_priv, vfb,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

471

return vmw_kms_stdu_readback(dev_priv, file_priv, vfb,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

500

static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

508

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

514

if (dev_priv->active_display_unit == vmw_du_legacy)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

523

if (!drm_any_plane_has_format(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

526

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

606

static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

614

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

626

if (!drm_any_plane_has_format(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

629

drm_dbg(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

672

vmw_kms_srf_ok(struct vmw_private *dev_priv, uint32_t width, uint32_t height)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

674

if (width > dev_priv->texture_max_width ||

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

675

height > dev_priv->texture_max_height)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

691

vmw_kms_new_framebuffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

701

ret = vmw_kms_new_framebuffer_surface(dev_priv, uo, &vfb,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

704

ret = vmw_kms_new_framebuffer_bo(dev_priv, uo->buffer, &vfb,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

725

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

733

ret = vmw_user_object_lookup(dev_priv, file_priv, mode_cmd->handles[0],

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

743

!vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

745

dev_priv->texture_max_width,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

746

dev_priv->texture_max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

752

vfb = vmw_kms_new_framebuffer(dev_priv, &uo, info, mode_cmd);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

798

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

808

if (dev_priv->active_display_unit == vmw_du_screen_target &&

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

809

(drm_rect_width(&rects[i]) > dev_priv->stdu_max_width ||

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

810

drm_rect_height(&rects[i]) > dev_priv->stdu_max_height)) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

834

if (pixel_mem > dev_priv->max_primary_mem) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

840

if (dev_priv->active_display_unit != vmw_du_screen_target ||

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

841

!(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

844

if (bb_mem > dev_priv->max_primary_mem) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

106

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

170

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

375

int vmw_kms_helper_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

387

void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

393

int vmw_kms_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

400

vmw_kms_new_framebuffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

405

void vmw_kms_update_implicit_fb(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

406

void vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

440

int vmw_kms_ldu_init_display(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

441

int vmw_kms_ldu_close_display(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

450

int vmw_kms_sou_init_display(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

451

int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

461

int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

469

int vmw_kms_sou_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

480

int vmw_kms_stdu_init_display(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

481

int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h

491

int vmw_kms_stdu_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

103

return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0],

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

112

vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitches[0],

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

117

vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

124

vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

125

vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

126

vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

127

vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

128

vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

129

vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

147

struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

157

WARN_ON(dev_priv->active_display_unit != vmw_du_legacy);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

159

if (dev_priv->active_display_unit == vmw_du_legacy) {

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

160

vmw_overlay_pause_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

161

ret = vmw_bo_pin_in_start_of_vram(dev_priv, buf, false);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

162

vmw_overlay_resume_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

171

struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

182

return vmw_bo_unpin(dev_priv, buf, false);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

301

static int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

319

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

326

dev_priv = vmw_priv(plane->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

332

vmw_ldu_add_active(dev_priv, ldu, vfb);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

334

vmw_ldu_del_active(dev_priv, ldu);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

336

vmw_ldu_commit_list(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

338

if (vfb && vmw_cmd_supported(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

354

ret = vmw_kms_ldu_do_bo_dirty(dev_priv, vfb, 0, 0, damage_rects, rect_count);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

359

vmw_cmd_flush(dev_priv, false);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

408

static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

411

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

433

ldu->base.pref_width = dev_priv->initial_width;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

434

ldu->base.pref_height = dev_priv->initial_height;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

458

if (vmw_cmd_supported(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

501

vmw_cmd_supported(dev_priv) ? &cursor->base : NULL,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

513

dev_priv->hotplug_mode_update_property, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

518

if (dev_priv->implicit_placement_property)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

521

dev_priv->implicit_placement_property,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

539

int vmw_kms_ldu_init_display(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

541

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

543

int num_display_units = (dev_priv->capabilities & SVGA_CAP_MULTIMON) ?

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

546

if (unlikely(dev_priv->ldu_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

550

dev_priv->ldu_priv = kmalloc_obj(*dev_priv->ldu_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

551

if (!dev_priv->ldu_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

554

INIT_LIST_HEAD(&dev_priv->ldu_priv->active);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

555

dev_priv->ldu_priv->num_active = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

556

dev_priv->ldu_priv->last_num_active = 0;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

557

dev_priv->ldu_priv->fb = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

559

vmw_kms_create_implicit_placement_property(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

562

ret = vmw_ldu_init(dev_priv, i);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

567

dev_priv->active_display_unit = vmw_du_legacy;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

574

kfree(dev_priv->ldu_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

575

dev_priv->ldu_priv = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

579

int vmw_kms_ldu_close_display(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

581

if (!dev_priv->ldu_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

584

BUG_ON(!list_empty(&dev_priv->ldu_priv->active));

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

586

kfree(dev_priv->ldu_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

592

static int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

607

cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

620

vmw_cmd_commit(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

80

static int vmw_ldu_commit_list(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

82

struct vmw_legacy_display *lds = dev_priv->ldu_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c

91

if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)) {

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

102

.slot = vmw_mksstat_get_kern_slot(current->pid, dev_priv) \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

108

_##kern_cntr.old_top = dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot]; \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

109

dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot] = kern_cntr; \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

116

const pid_t pid = atomic_cmpxchg(&dev_priv->mksstat_kern_pids[_##kern_cntr.slot], current->pid, MKSSTAT_PID_RESERVED); \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

117

dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot] = _##kern_cntr.old_top; \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

123

BUG_ON(!dev_priv->mksstat_kern_pages[_##kern_cntr.slot]); \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

125

pstat = vmw_mksstat_get_kern_pstat(page_address(dev_priv->mksstat_kern_pages[_##kern_cntr.slot])); \

drivers/gpu/drm/vmwgfx/vmwgfx_mksstat.h

134

atomic_set(&dev_priv->mksstat_kern_pids[_##kern_cntr.slot], current->pid); \

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

114

static int vmw_setup_otable_base(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

145

ret = vmw_mob_pt_populate(dev_priv, mob);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

153

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

175

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

194

static void vmw_takedown_otable_base(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

208

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

220

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

237

static int vmw_otable_batch_setup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

255

ret = vmw_bo_create_and_populate(dev_priv, bo_size,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

266

ret = vmw_setup_otable_base(dev_priv, i,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

280

vmw_takedown_otable_base(dev_priv, i,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

300

int vmw_otables_setup(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

302

struct vmw_otable **otables = &dev_priv->otable_batch.otables;

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

305

if (has_sm4_context(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

310

dev_priv->otable_batch.num_otables = ARRAY_SIZE(dx_tables);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

317

dev_priv->otable_batch.num_otables = ARRAY_SIZE(pre_dx_tables);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

320

ret = vmw_otable_batch_setup(dev_priv, &dev_priv->otable_batch);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

331

static void vmw_otable_batch_takedown(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

340

vmw_takedown_otable_base(dev_priv, i,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

360

void vmw_otables_takedown(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

362

vmw_otable_batch_takedown(dev_priv, &dev_priv->otable_batch);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

363

kfree(dev_priv->otable_batch.otables);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

413

static int vmw_mob_pt_populate(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

418

return vmw_bo_create_and_populate(dev_priv, mob->num_pages * PAGE_SIZE,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

550

void vmw_mob_unbind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

568

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

573

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

580

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

598

int vmw_mob_bind(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

621

ret = vmw_mob_pt_populate(dev_priv, mob);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

630

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

632

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

643

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

648

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c

86

static int vmw_mob_pt_populate(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1047

dev_priv->mksstat_user_pages[slot] = page;

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1048

atomic_set(&dev_priv->mksstat_user_pids[slot], task_pgrp_vnr(current));

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1070

atomic_set(&dev_priv->mksstat_user_pids[slot], 0);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1097

struct vmw_private *const dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1102

if (slot >= ARRAY_SIZE(dev_priv->mksstat_user_pids))

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1108

pid = atomic_cmpxchg(&dev_priv->mksstat_user_pids[slot], pgid, MKSSTAT_PID_RESERVED);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1114

struct page *const page = dev_priv->mksstat_user_pages[slot];

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1118

dev_priv->mksstat_user_pages[slot] = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

1119

atomic_set(&dev_priv->mksstat_user_pids[slot], 0);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

758

int vmw_mksstat_get_kern_slot(pid_t pid, struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

763

for (i = 0; i < ARRAY_SIZE(dev_priv->mksstat_kern_pids); ++i) {

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

764

const size_t slot = (i + base) % ARRAY_SIZE(dev_priv->mksstat_kern_pids);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

767

if (pid == (pid_t)atomic_read(&dev_priv->mksstat_kern_pids[slot]))

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

771

if (!atomic_cmpxchg(&dev_priv->mksstat_kern_pids[slot], 0, MKSSTAT_PID_RESERVED)) {

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

772

const int ret = mksstat_init_kern_id(&dev_priv->mksstat_kern_pages[slot]);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

776

dev_priv->mksstat_kern_top_timer[slot] = MKSSTAT_KERN_COUNT;

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

778

atomic_set(&dev_priv->mksstat_kern_pids[slot], pid);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

782

atomic_set(&dev_priv->mksstat_kern_pids[slot], 0);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

830

int vmw_mksstat_remove_all(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

839

for (i = 0; i < ARRAY_SIZE(dev_priv->mksstat_user_pids); ++i) {

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

840

const pid_t pid0 = (pid_t)atomic_read(&dev_priv->mksstat_user_pids[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

846

const pid_t pid1 = atomic_cmpxchg(&dev_priv->mksstat_user_pids[i], pid0, MKSSTAT_PID_RESERVED);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

852

struct page *const page = dev_priv->mksstat_user_pages[i];

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

856

dev_priv->mksstat_user_pages[i] = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

857

atomic_set(&dev_priv->mksstat_user_pids[i], 0);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

869

for (i = 0; i < ARRAY_SIZE(dev_priv->mksstat_kern_pids); ++i) {

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

870

const pid_t pid0 = (pid_t)atomic_read(&dev_priv->mksstat_kern_pids[i]);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

876

const pid_t pid1 = atomic_cmpxchg(&dev_priv->mksstat_kern_pids[i], pid0, MKSSTAT_PID_RESERVED);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

882

struct page *const page = dev_priv->mksstat_kern_pages[i];

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

886

dev_priv->mksstat_kern_pages[i] = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

887

atomic_set(&dev_priv->mksstat_kern_pids[i], 0);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

917

struct vmw_private *const dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

918

return vmw_mksstat_remove_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

940

struct vmw_private *const dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

974

for (slot = 0; slot < ARRAY_SIZE(dev_priv->mksstat_user_pids); ++slot)

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

975

if (!atomic_cmpxchg(&dev_priv->mksstat_user_pids[slot], 0, MKSSTAT_PID_RESERVED))

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

978

if (slot == ARRAY_SIZE(dev_priv->mksstat_user_pids))

drivers/gpu/drm/vmwgfx/vmwgfx_msg.c

981

BUG_ON(dev_priv->mksstat_user_pages[slot]);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

119

cmds = VMW_CMD_RESERVE(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

166

vmw_cmd_commit(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

177

static int vmw_overlay_send_stop(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

189

cmds = VMW_CMD_RESERVE(dev_priv, sizeof(*cmds));

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

193

ret = vmw_fallback_wait(dev_priv, false, true, 0,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

208

vmw_cmd_commit(dev_priv, sizeof(*cmds));

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

219

static int vmw_overlay_move_buffer(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

224

return vmw_bo_unpin(dev_priv, buf, inter);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

226

if (dev_priv->active_display_unit == vmw_du_legacy)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

227

return vmw_bo_pin_in_vram(dev_priv, buf, inter);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

229

return vmw_bo_pin_in_vram_or_gmr(dev_priv, buf, inter);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

244

static int vmw_overlay_stop(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

248

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

258

ret = vmw_overlay_send_stop(dev_priv, stream_id,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

264

ret = vmw_overlay_move_buffer(dev_priv, stream->buf, false,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

291

static int vmw_overlay_update_stream(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

296

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

307

ret = vmw_overlay_stop(dev_priv, arg->stream_id,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

315

ret = vmw_overlay_send_put(dev_priv, buf, arg, interruptible);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

327

ret = vmw_overlay_move_buffer(dev_priv, buf, true, interruptible);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

331

ret = vmw_overlay_send_put(dev_priv, buf, arg, interruptible);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

336

BUG_ON(vmw_overlay_move_buffer(dev_priv, buf, false, false)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

357

int vmw_overlay_resume_all(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

359

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

372

ret = vmw_overlay_update_stream(dev_priv, stream->buf,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

391

int vmw_overlay_pause_all(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

393

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

405

ret = vmw_overlay_stop(dev_priv, i, true, false);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

415

static bool vmw_overlay_available(const struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

417

return (dev_priv->overlay_priv != NULL &&

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

418

((vmw_fifo_caps(dev_priv) & VMW_OVERLAY_CAP_MASK) ==

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

426

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

427

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

434

if (!vmw_overlay_available(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

437

ret = vmw_user_stream_lookup(dev_priv, tfile, &arg->stream_id, &res);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

444

ret = vmw_overlay_stop(dev_priv, arg->stream_id, false, true);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

452

ret = vmw_overlay_update_stream(dev_priv, buf, arg, true);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

463

int vmw_overlay_num_overlays(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

465

if (!vmw_overlay_available(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

471

int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

473

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

476

if (!vmw_overlay_available(dev_priv))

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

490

int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

492

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

515

int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

517

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

527

vmw_overlay_stop(dev_priv, stream_id, false, false);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

534

int vmw_overlay_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

539

if (dev_priv->overlay_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

553

dev_priv->overlay_priv = overlay;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

558

int vmw_overlay_close(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

560

struct vmw_overlay *overlay = dev_priv->overlay_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

570

vmw_overlay_stop(dev_priv, i, false, false);

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

576

dev_priv->overlay_priv = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

88

static int vmw_overlay_send_put(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

95

bool have_so = (dev_priv->active_display_unit != vmw_du_legacy);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

1014

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

1029

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

1032

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

104

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

1048

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

105

struct idr *idr = &dev_priv->res_idr[res->func->res_type];

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

107

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

111

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

118

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

121

struct idr *idr = &dev_priv->res_idr[res->func->res_type];

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

123

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

125

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

150

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

152

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

162

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

165

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

187

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

189

struct idr *idr = &dev_priv->res_idr[res->func->res_type];

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

194

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

200

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

215

int vmw_resource_init(struct vmw_private *dev_priv, struct vmw_resource *res,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

223

res->dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

257

int vmw_user_resource_lookup_handle(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

292

int vmw_user_object_lookup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

303

ret = vmw_user_resource_lookup_handle(dev_priv, tfile, handle,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

314

uo->surface = vmw_lookup_surface_for_buffer(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

350

ret = vmw_bo_create(res->dev_priv, &bo_params, &gbo);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

459

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

498

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

500

&res->dev_priv->res_lru[res->func->res_type]);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

501

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

582

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

585

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

587

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

686

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

687

struct list_head *lru_list = &dev_priv->res_lru[res->func->res_type];

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

703

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

708

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

717

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

722

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

724

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

796

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

808

dev_priv = dx_query_ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

810

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), dx_query_ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

818

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

844

struct vmw_private *dev_priv = vmw_priv_from_ttm(bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

846

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

856

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

861

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

864

(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

872

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

894

static void vmw_resource_evict_type(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

897

struct list_head *lru_list = &dev_priv->res_lru[type];

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

904

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

913

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

918

spin_lock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

920

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

931

spin_unlock(&dev_priv->resource_lock);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

944

void vmw_resource_evict_all(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

948

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

951

vmw_resource_evict_type(dev_priv, type);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

953

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

969

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

972

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_resource_priv.h

141

int vmw_resource_init(struct vmw_private *dev_priv, struct vmw_resource *res,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1002

vmw_cmd_commit(dirty->dev_priv, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1034

vmw_cmd_commit(dirty->dev_priv, region_size + sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1093

int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1118

ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1124

sdirty.base.dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1135

ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1138

vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1158

vmw_cmd_commit(dirty->dev_priv, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1162

vmw_cmd_commit(dirty->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

119

static int vmw_sou_fifo_create(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1209

int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1235

ret = do_bo_define_gmrfb(dev_priv, framebuffer);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1244

ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1246

vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1270

vmw_cmd_commit(dirty->dev_priv, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1274

vmw_cmd_commit(dirty->dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1319

int vmw_kms_sou_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1343

ret = do_bo_define_gmrfb(dev_priv, vfb);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1352

ret = vmw_kms_helper_dirty(dev_priv, vfb, NULL, vclips,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

1354

vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

136

cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

157

vmw_cmd_commit(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

167

static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

185

cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

193

vmw_cmd_commit(dev_priv, fifo_size);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

196

ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

215

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

224

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

232

ret = vmw_sou_fifo_destroy(dev_priv, sou);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

252

ret = vmw_sou_fifo_create(dev_priv, sou, x, y, &crtc->mode);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

282

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

293

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

295

if (dev_priv->vkms_enabled)

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

299

ret = vmw_sou_fifo_destroy(dev_priv, sou);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

408

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

426

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

435

return vmw_bo_pin_in_vram(dev_priv, bo, true);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

442

vmw_svga_enable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

447

vmw_overlay_pause_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

448

ret = vmw_bo_create(dev_priv, &bo_params, &vps->uo.buffer);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

449

vmw_overlay_resume_all(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

459

return vmw_bo_pin_in_vram(dev_priv, vps->uo.buffer, true);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

531

static int vmw_sou_plane_update_bo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

542

bo_update.base.dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

693

static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

704

srf_update.base.dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

708

srf_update.base.mutex = &dev_priv->cmdbuf_mutex;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

732

struct vmw_private *dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

737

ret = vmw_sou_plane_update_bo(dev_priv, plane,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

740

ret = vmw_sou_plane_update_surface(dev_priv, plane,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

803

static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

806

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

826

sou->base.pref_width = dev_priv->initial_width;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

827

sou->base.pref_height = dev_priv->initial_height;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

902

dev_priv->hotplug_mode_update_property, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

923

int vmw_kms_sou_init_display(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

925

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

929

if (!dev_priv->has_gmr)

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

932

if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

937

vmw_sou_init(dev_priv, i);

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

939

dev_priv->active_display_unit = vmw_du_screen_object;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

946

static int do_bo_define_gmrfb(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

965

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

976

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

157

static int vmw_gb_shader_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

170

ret = vmw_resource_init(dev_priv, res, true, res_free,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

201

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

223

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

234

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

235

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

248

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

257

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

267

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

276

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

285

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

294

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

300

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

313

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

322

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

325

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

327

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

334

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

335

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

337

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

358

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

361

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

366

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

368

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

372

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

386

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

395

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), shader->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

405

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

422

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

429

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

431

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

448

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

452

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

454

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

472

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

482

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

492

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

510

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

516

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

518

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

523

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

544

void vmw_dx_shader_cotable_list_scrub(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

550

lockdep_assert_held_once(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

592

struct vmw_private *dev_priv = ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

610

ret = vmw_resource_init(dev_priv, res, true,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

685

static int vmw_user_shader_alloc(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

713

ret = vmw_gb_shader_init(dev_priv, res, shader_size,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

739

static struct vmw_resource *vmw_shader_alloc(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

760

ret = vmw_gb_shader_init(dev_priv, res, shader_size,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

775

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

808

ret = vmw_user_shader_alloc(dev_priv, buffer, size, offset,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

881

int vmw_compat_shader_add(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

906

ret = vmw_bo_create(dev_priv, &bo_params, &buf);

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

925

res = vmw_shader_alloc(dev_priv, buf, size, 0, shader_type);

drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c

142

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c

167

ret = vmw_simple_resource_init(dev_priv, &usimple->simple,

drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c

60

static int vmw_simple_resource_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c

68

ret = vmw_resource_init(dev_priv, res, false, res_free,

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

132

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

134

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

149

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

164

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

170

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

172

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

176

cmd = VMW_CMD_CTX_RESERVE(res->dev_priv, view->cmd_size, view->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

178

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

187

vmw_cmd_commit(res->dev_priv, view->cmd_size);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

191

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

206

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

213

lockdep_assert_held_once(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

219

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), view->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

226

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

243

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

245

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

248

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

326

struct vmw_private *dev_priv = ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

362

ret = vmw_resource_init(dev_priv, res, true,

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

421

void vmw_view_cotable_list_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

427

lockdep_assert_held_once(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

442

void vmw_view_surface_list_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_so.c

447

lockdep_assert_held_once(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_so.h

162

extern void vmw_view_surface_list_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_so.h

164

extern void vmw_view_cotable_list_destroy(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1058

ret = vmw_gb_surface_define(dev_priv, &metadata,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1243

static int vmw_stdu_plane_update_bo(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1254

bo_update.base.dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1353

static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1369

srf_update.dev_priv = dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1373

srf_update.mutex = &dev_priv->cmdbuf_mutex;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1410

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1418

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1424

ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1429

ret = vmw_stdu_plane_update_bo(dev_priv, plane,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1432

ret = vmw_stdu_plane_update_surface(dev_priv, plane,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1440

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1446

ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1450

ret = vmw_stdu_update_st(dev_priv, stdu);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1533

static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1536

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1556

stdu->base.pref_width = dev_priv->initial_width;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1557

stdu->base.pref_height = dev_priv->initial_height;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1628

dev_priv->hotplug_mode_update_property, 1);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1685

int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1687

struct drm_device *dev = &dev_priv->drm;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

169

static int vmw_stdu_define_st(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1692

if (!dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1695

if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1698

dev_priv->active_display_unit = vmw_du_screen_target;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1701

ret = vmw_stdu_init(dev_priv, i);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

1704

drm_err(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

179

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

197

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

219

static int vmw_stdu_bind_st(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

240

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

250

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

294

static int vmw_stdu_update_st(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

304

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

312

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

328

static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

343

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

352

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

355

ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

377

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

384

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

389

ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

393

(void) vmw_stdu_update_st(dev_priv, stdu);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

395

ret = vmw_stdu_destroy_st(dev_priv, stdu);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

408

vmw_svga_enable(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

409

ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, x, y);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

419

struct vmw_private *dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

430

dev_priv = vmw_priv(crtc->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

433

if (dev_priv->vkms_enabled)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

437

ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

441

(void) vmw_stdu_update_st(dev_priv, stdu);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

451

ret = vmw_stdu_destroy_st(dev_priv, stdu);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

555

int vmw_kms_stdu_readback(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

601

ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

604

vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

672

vmw_cmd_commit(dirty->dev_priv, 0);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

694

vmw_cmd_commit(dirty->dev_priv, commit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

722

int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

747

ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

761

ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

765

vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

846

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

847

u64 assumed_cpp = dev_priv->assume_16bpp ? 2 : 4;

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

854

ret = drm_mode_validate_size(mode, dev_priv->stdu_max_width,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

855

dev_priv->stdu_max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

859

ret = drm_mode_validate_size(mode, dev_priv->texture_max_width,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

860

dev_priv->texture_max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

864

if (required_mem > dev_priv->max_primary_mem)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

867

if (required_mem > dev_priv->max_mob_pages * PAGE_SIZE)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

870

if (required_mem > dev_priv->max_mob_size)

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

973

struct vmw_private *dev_priv = vmw_priv(plane->dev);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

102

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

112

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

121

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

128

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

130

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

141

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

148

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

150

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

163

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

175

cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

185

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

196

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

203

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

205

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

210

(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

222

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

226

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

230

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

232

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

236

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

284

struct vmw_private *dev_priv = ctx->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

299

ret = vmw_resource_init(dev_priv, res, true,

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

355

void vmw_dx_streamoutput_cotable_list_scrub(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

361

lockdep_assert_held_once(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c

93

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1006

base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1070

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1082

ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1121

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1146

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1158

if (has_sm5_context(dev_priv) && metadata->array_size > 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1162

} else if (has_sm4_1_context(dev_priv) && metadata->array_size > 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1177

cmd = VMW_CMD_RESERVE(dev_priv, submit_len);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1186

if (has_sm5_context(dev_priv) && metadata->array_size > 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1202

} else if (has_sm4_1_context(dev_priv) && metadata->array_size > 0) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1244

vmw_cmd_commit(dev_priv, submit_len);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1251

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1259

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1275

cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1289

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1305

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1328

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1351

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1357

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1370

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1380

mutex_lock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1381

vmw_view_surface_list_destroy(dev_priv, &srf->view_list);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1384

cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1386

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1393

vmw_cmd_commit(dev_priv, sizeof(*cmd));

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1394

mutex_unlock(&dev_priv->binding_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1396

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1511

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1524

if (req->base.array_size > 0 && !has_sm4_context(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1529

if (!has_sm4_1_context(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1548

if (req->buffer_byte_stride > 0 && !has_sm5_context(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1578

ret = vmw_gb_surface_define(dev_priv, &metadata, &srf);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1611

ret = vmw_gem_object_create_with_handle(dev_priv, file_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1694

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1702

ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1715

mutex_lock(&dev_priv->cmdbuf_mutex); /* Protect res->backup */

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1718

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1927

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1954

alloc_size = num_dirty * ((has_sm4_context(dev_priv)) ? sizeof(*cmd1) : sizeof(*cmd2));

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1955

cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1972

if (has_sm4_context(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1991

vmw_cmd_commit(dev_priv, alloc_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2067

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2075

cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2082

vmw_cmd_commit(dev_priv, alloc_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2099

int vmw_gb_surface_define(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2118

if (req->base_size.width > dev_priv->texture_max_width ||

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2119

req->base_size.height > dev_priv->texture_max_height) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2123

dev_priv->texture_max_width,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2124

dev_priv->texture_max_height);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2187

if (dev_priv->active_display_unit == vmw_du_screen_target &&

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2189

metadata->base_size.width <= dev_priv->stdu_max_width &&

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2190

metadata->base_size.height <= dev_priv->stdu_max_height)

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2197

ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2239

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2251

SVGA3dSurfaceFormat format = vmw_format_bpp_to_svga(dev_priv, args->bpp);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2269

if (!dev_priv->has_mob || !vmw_supports_3d(dev_priv)) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2274

ret = vmw_gem_object_create_with_handle(dev_priv, file_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

2312

ret = vmw_user_resource_lookup_handle(dev_priv, tfile, arg.rep.handle,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

340

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

350

cmd = VMW_CMD_RESERVE(dev_priv, vmw_surface_destroy_size());

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

355

vmw_cmd_commit(dev_priv, vmw_surface_destroy_size());

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

363

mutex_lock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

364

dev_priv->used_memory_size -= res->guest_memory_size;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

365

mutex_unlock(&dev_priv->cmdbuf_mutex);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

384

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

394

if (unlikely(dev_priv->used_memory_size + res->guest_memory_size >=

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

395

dev_priv->memory_size))

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

418

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

425

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

426

vmw_fifo_resource_inc(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

432

dev_priv->used_memory_size += res->guest_memory_size;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

466

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

470

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

477

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

483

(void) vmw_execbuf_fence_commands(NULL, dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

546

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

557

cmd = VMW_CMD_RESERVE(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

562

vmw_cmd_commit(dev_priv, submit_size);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

568

dev_priv->used_memory_size -= res->guest_memory_size;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

575

vmw_fifo_resource_dec(dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

589

static int vmw_surface_init(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

597

ret = vmw_resource_init(dev_priv, res, true, res_free,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

598

(dev_priv->has_mob) ? &vmw_gb_surface_func :

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

707

struct vmw_private *dev_priv = vmw_priv(dev);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

816

ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

824

if (dev_priv->has_mob) {

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

833

ret = vmw_bo_create(dev_priv, &params, &res->guest_memory_bo);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

932

static int vmw_buffer_prime_to_surface_base(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

943

ret = drm_gem_prime_fd_to_handle(&dev_priv->drm, file_priv, fd, handle);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

945

drm_warn(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

952

drm_warn(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

957

user_srf = vmw_lookup_user_surface_for_buffer(dev_priv, bo, *handle);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

959

drm_warn(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

968

drm_warn(&dev_priv->drm,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

981

vmw_surface_handle_reference(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

996

return vmw_buffer_prime_to_surface_base(dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

60

int vmw_sys_man_init(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

62

struct ttm_device *bdev = &dev_priv->bdev;

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

77

void vmw_sys_man_fini(struct vmw_private *dev_priv)

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

79

struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev,

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

82

ttm_resource_manager_evict_all(&dev_priv->bdev, man);

drivers/gpu/drm/vmwgfx/vmwgfx_system_manager.c

87

ttm_set_driver_manager(&dev_priv->bdev, VMW_PL_SYSTEM, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

137

struct device *dev = vmw_tt->dev_priv->drm.dev;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

158

struct device *dev = vmw_tt->dev_priv->drm.dev;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

175

struct vmw_private *dev_priv = vmw_tt->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

182

vsgt->mode = dev_priv->map_mode;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

188

switch (dev_priv->map_mode) {

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

198

dma_get_max_seg_size(dev_priv->drm.dev),

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

217

drm_warn(&dev_priv->drm, "VSG table map failed!");

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

235

struct vmw_private *dev_priv = vmw_tt->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

240

switch (dev_priv->map_mode) {

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

295

ret = vmw_gmr_bind(vmw_be->dev_priv, &vmw_be->vsgt,

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

306

ret = vmw_mob_bind(vmw_be->dev_priv, vmw_be->mob,

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

331

vmw_gmr_unbind(vmw_be->dev_priv, vmw_be->gmr_id);

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

334

vmw_mob_unbind(vmw_be->dev_priv, vmw_be->mob);

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

342

if (vmw_be->dev_priv->map_mode == vmw_dma_map_bind)

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

411

vmw_be->dev_priv = vmw_priv_from_ttm(bo->bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

417

if (vmw_be->dev_priv->map_mode == vmw_dma_alloc_coherent || external)

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

440

struct vmw_private *dev_priv = vmw_priv_from_ttm(bdev);

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

450

dev_priv->vram_start;

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

560

int vmw_bo_create_and_populate(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c

579

ret = vmw_bo_create(dev_priv, &bo_params, &vbo);

drivers/gpu/drm/vmwgfx/vmwgfx_va.c

154

int vmw_user_stream_lookup(struct vmw_private *dev_priv,

drivers/gpu/drm/vmwgfx/vmwgfx_va.c

59

struct vmw_private *dev_priv = res->dev_priv;

drivers/gpu/drm/vmwgfx/vmwgfx_va.c

63

ret = vmw_overlay_unref(dev_priv, stream->stream_id);

drivers/gpu/drm/vmwgfx/vmwgfx_va.c

71

return vmw_overlay_claim(res->dev_priv, &stream->stream_id);

drivers/gpu/drm/vmwgfx/vmwgfx_validation.c

317

if (!res->dev_priv->has_mob) {

drivers/infiniband/hw/hfi1/ipoib.h

138

struct hfi1_ipoib_dev_priv dev_priv;

drivers/infiniband/hw/hfi1/ipoib.h

144

return &((struct hfi1_ipoib_rdma_netdev *)netdev_priv(dev))->dev_priv;

drivers/media/v4l2-core/v4l2-subdev.c

2561

sd->dev_priv = NULL;

drivers/mtd/hyperbus/hbmc-am654.c

162

struct am654_hbmc_device_priv *dev_priv;

drivers/mtd/hyperbus/hbmc-am654.c

206

dev_priv = devm_kzalloc(dev, sizeof(*dev_priv), GFP_KERNEL);

drivers/mtd/hyperbus/hbmc-am654.c

207

if (!dev_priv) {

drivers/mtd/hyperbus/hbmc-am654.c

212

priv->hbdev.priv = dev_priv;

drivers/mtd/hyperbus/hbmc-am654.c

213

dev_priv->device_base = res.start;

drivers/mtd/hyperbus/hbmc-am654.c

214

dev_priv->ctlr = &priv->ctlr;

drivers/mtd/hyperbus/hbmc-am654.c

216

ret = am654_hbmc_request_mmap_dma(dev_priv);

drivers/mtd/hyperbus/hbmc-am654.c

228

if (dev_priv->rx_chan)

drivers/mtd/hyperbus/hbmc-am654.c

229

dma_release_channel(dev_priv->rx_chan);

drivers/mtd/hyperbus/hbmc-am654.c

241

struct am654_hbmc_device_priv *dev_priv = priv->hbdev.priv;

drivers/mtd/hyperbus/hbmc-am654.c

248

if (dev_priv->rx_chan)

drivers/mtd/hyperbus/hbmc-am654.c

249

dma_release_channel(dev_priv->rx_chan);

drivers/net/ethernet/micrel/ksz884x.c

4260

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4455

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4530

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4611

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4778

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4862

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4934

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

4974

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5061

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5090

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5111

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5215

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5271

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5297

static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,

drivers/net/ethernet/micrel/ksz884x.c

5332

static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,

drivers/net/ethernet/micrel/ksz884x.c

5359

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5407

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5447

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5508

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5528

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5566

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5593

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5663

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5683

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5700

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5753

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5791

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5811

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5839

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5853

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5886

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5914

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5948

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

5981

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6030

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6093

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6113

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6136

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6204

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6251

static void update_link(struct net_device *dev, struct dev_priv *priv,

drivers/net/ethernet/micrel/ksz884x.c

6335

struct dev_priv *priv = timer_container_of(priv, t,

drivers/net/ethernet/micrel/ksz884x.c

6403

struct dev_priv *priv = netdev_priv(dev);

drivers/net/ethernet/micrel/ksz884x.c

6542

struct dev_priv *priv;

drivers/net/ethernet/micrel/ksz884x.c

6686

dev = alloc_etherdev(sizeof(struct dev_priv));

drivers/net/ethernet/netronome/nfp/bpf/cmsg.c

297

struct nfp_bpf_map *nfp_map = offmap->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/jit.c

4424

nfp_map = map_to_offmap(map)->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

197

prog->aux->offload->dev_priv = nfp_prog;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

220

struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

247

struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

292

nfp_map_bpf_byte_swap(offmap->dev_priv, value);

drivers/net/ethernet/netronome/nfp/bpf/offload.c

300

nfp_map_bpf_byte_swap(offmap->dev_priv, value);

drivers/net/ethernet/netronome/nfp/bpf/offload.c

301

nfp_map_bpf_byte_swap_record(offmap->dev_priv, value);

drivers/net/ethernet/netronome/nfp/bpf/offload.c

387

offmap->dev_priv = nfp_map;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

410

struct nfp_bpf_map *nfp_map = offmap->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/offload.c

498

struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

100

nfp_map = offmap->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

434

nfp_map = offmap->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

634

struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

771

nfp_prog = env->prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

810

struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv;

drivers/net/ethernet/netronome/nfp/bpf/verifier.c

843

struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv;

drivers/net/ethernet/seeq/ether3.c

173

struct dev_priv *private = timer_container_of(private, t, timer);

drivers/net/ethernet/seeq/ether3.c

760

dev = alloc_etherdev(sizeof(struct dev_priv));

drivers/net/ethernet/seeq/ether3.h

22

#define priv(dev) ((struct dev_priv *)netdev_priv(dev))

drivers/net/netdevsim/bpf.c

251

prog->aux->offload->dev_priv = state;

drivers/net/netdevsim/bpf.c

269

struct nsim_bpf_bound_prog *state = prog->aux->offload->dev_priv;

drivers/net/netdevsim/bpf.c

280

state = prog->aux->offload->dev_priv;

drivers/net/netdevsim/bpf.c

326

state = bpf->prog->aux->offload->dev_priv;

drivers/net/netdevsim/bpf.c

342

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

355

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

376

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

406

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

424

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

463

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

508

offmap->dev_priv = nmap;

drivers/net/netdevsim/bpf.c

542

struct nsim_bpf_bound_map *nmap = offmap->dev_priv;

drivers/net/netdevsim/bpf.c

68

state = env->prog->aux->offload->dev_priv;

drivers/net/netdevsim/bpf.c

99

state = prog->aux->offload->dev_priv;

drivers/usb/cdns3/cdns3-trace.h

272

TP_PROTO(struct cdns3_device *dev_priv, struct usb_request *request),

drivers/usb/cdns3/cdns3-trace.h

273

TP_ARGS(dev_priv, request),

drivers/usb/cdns3/cdns3-trace.h

279

__entry->dir = dev_priv->ep0_data_dir;

include/linux/bpf.h

1144

void *dev_priv;

include/linux/bpf.h

639

void *dev_priv;

include/media/v4l2-subdev.h

1064

void *dev_priv;

include/media/v4l2-subdev.h

1155

sd->dev_priv = p;

include/media/v4l2-subdev.h

1167

return sd->dev_priv;

include/rdma/opa_vnic.h

37

char *dev_priv[];

include/rdma/opa_vnic.h

51

return oparn->dev_priv;