arch/arm/include/asm/hardware/ssp.h

12

unsigned int cr1;

arch/arm/mach-sa1100/ssp.c

161

ssp->cr1 = Ser4SSCR1;

arch/arm/mach-sa1100/ssp.c

177

Ser4SSCR1 = ssp->cr1;

arch/powerpc/platforms/52xx/mpc52xx_pci.c

68

u32 cr1; /* PCI + 0x0C */

arch/s390/lib/uaccess.c

23

struct ctlreg cr1, cr7;

arch/s390/lib/uaccess.c

25

local_ctl_store(1, &cr1);

arch/s390/lib/uaccess.c

27

if (cr1.val == lc->user_asce.val && cr7.val == lc->user_asce.val)

arch/s390/lib/uaccess.c

32

exit ? "exit" : "entry", cr1.val, cr7.val,

drivers/clk/clk-si521xx.c

42

#define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1))

drivers/clk/renesas/rcar-gen4-cpg.c

226

static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = {

drivers/clk/renesas/rcar-gen4-cpg.c

248

pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 1].cr1;

drivers/counter/stm32-timer-cnt.c

115

u32 cr1, sms;

drivers/counter/stm32-timer-cnt.c

141

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/counter/stm32-timer-cnt.c

151

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);

drivers/counter/stm32-timer-cnt.c

161

u32 cr1;

drivers/counter/stm32-timer-cnt.c

163

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/counter/stm32-timer-cnt.c

164

*direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :

drivers/counter/stm32-timer-cnt.c

202

u32 cr1;

drivers/counter/stm32-timer-cnt.c

204

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/counter/stm32-timer-cnt.c

206

*enable = cr1 & TIM_CR1_CEN;

drivers/counter/stm32-timer-cnt.c

215

u32 cr1;

drivers/counter/stm32-timer-cnt.c

219

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/counter/stm32-timer-cnt.c

220

if (!(cr1 & TIM_CR1_CEN)) {

drivers/counter/stm32-timer-cnt.c

231

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/counter/stm32-timer-cnt.c

233

if (cr1 & TIM_CR1_CEN)

drivers/counter/stm32-timer-cnt.c

32

u32 cr1;

drivers/counter/stm32-timer-cnt.c

807

regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);

drivers/counter/stm32-timer-cnt.c

839

regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);

drivers/gpu/drm/mcde/mcde_display.c

637

u32 cr0, cr1;

drivers/gpu/drm/mcde/mcde_display.c

643

cr1 = MCDE_CRA1;

drivers/gpu/drm/mcde/mcde_display.c

648

cr1 = MCDE_CRB1;

drivers/gpu/drm/mcde/mcde_display.c

704

val = readl(mcde->regs + cr1);

drivers/gpu/drm/mcde/mcde_display.c

745

writel(val, mcde->regs + cr1);

drivers/i2c/busses/i2c-stm32f4.c

485

u32 cr1;

drivers/i2c/busses/i2c-stm32f4.c

502

cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

503

cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS);

drivers/i2c/busses/i2c-stm32f4.c

504

writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

509

cr1 |= STM32F4_I2C_CR1_STOP;

drivers/i2c/busses/i2c-stm32f4.c

511

cr1 |= STM32F4_I2C_CR1_START;

drivers/i2c/busses/i2c-stm32f4.c

512

writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

522

cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

523

cr1 &= ~STM32F4_I2C_CR1_ACK;

drivers/i2c/busses/i2c-stm32f4.c

524

cr1 |= STM32F4_I2C_CR1_POS;

drivers/i2c/busses/i2c-stm32f4.c

525

writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

537

cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f4.c

538

cr1 |= STM32F4_I2C_CR1_ACK;

drivers/i2c/busses/i2c-stm32f4.c

539

cr1 &= ~STM32F4_I2C_CR1_POS;

drivers/i2c/busses/i2c-stm32f4.c

540

writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

1080

cr1 |= STM32F7_I2C_CR1_PECEN;

drivers/i2c/busses/i2c-stm32f7.c

1086

cr1 &= ~STM32F7_I2C_CR1_PECEN;

drivers/i2c/busses/i2c-stm32f7.c

1095

cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |

drivers/i2c/busses/i2c-stm32f7.c

1099

cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |

drivers/i2c/busses/i2c-stm32f7.c

1118

cr1 |= STM32F7_I2C_CR1_RXIE;

drivers/i2c/busses/i2c-stm32f7.c

1120

cr1 |= STM32F7_I2C_CR1_TXIE;

drivers/i2c/busses/i2c-stm32f7.c

1123

cr1 |= STM32F7_I2C_CR1_RXDMAEN;

drivers/i2c/busses/i2c-stm32f7.c

1125

cr1 |= STM32F7_I2C_CR1_TXDMAEN;

drivers/i2c/busses/i2c-stm32f7.c

1134

writel_relaxed(cr1, base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

1144

u32 cr1, cr2;

drivers/i2c/busses/i2c-stm32f7.c

1148

cr1 = readl_relaxed(base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

1172

if (cr1 & STM32F7_I2C_CR1_PECEN) {

drivers/i2c/busses/i2c-stm32f7.c

1184

cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);

drivers/i2c/busses/i2c-stm32f7.c

1185

cr1 |= STM32F7_I2C_CR1_RXIE;

drivers/i2c/busses/i2c-stm32f7.c

1192

cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |

drivers/i2c/busses/i2c-stm32f7.c

1212

cr1 |= STM32F7_I2C_CR1_RXIE;

drivers/i2c/busses/i2c-stm32f7.c

1214

cr1 |= STM32F7_I2C_CR1_RXDMAEN;

drivers/i2c/busses/i2c-stm32f7.c

1220

writel_relaxed(cr1, base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

195

u32 cr1;

drivers/i2c/busses/i2c-stm32f7.c

2415

backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

2429

u32 cr1;

drivers/i2c/busses/i2c-stm32f7.c

2437

cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

2438

if (cr1 & STM32F7_I2C_CR1_PE)

drivers/i2c/busses/i2c-stm32f7.c

2443

writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,

drivers/i2c/busses/i2c-stm32f7.c

2445

if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)

drivers/i2c/busses/i2c-stm32f7.c

880

u32 cr1, cr2;

drivers/i2c/busses/i2c-stm32f7.c

889

cr1 = readl_relaxed(base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

918

cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |

drivers/i2c/busses/i2c-stm32f7.c

922

cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |

drivers/i2c/busses/i2c-stm32f7.c

948

cr1 |= STM32F7_I2C_CR1_RXIE;

drivers/i2c/busses/i2c-stm32f7.c

950

cr1 |= STM32F7_I2C_CR1_TXIE;

drivers/i2c/busses/i2c-stm32f7.c

953

cr1 |= STM32F7_I2C_CR1_RXDMAEN;

drivers/i2c/busses/i2c-stm32f7.c

955

cr1 |= STM32F7_I2C_CR1_TXDMAEN;

drivers/i2c/busses/i2c-stm32f7.c

959

cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */

drivers/i2c/busses/i2c-stm32f7.c

967

writel_relaxed(cr1, base + STM32F7_I2C_CR1);

drivers/i2c/busses/i2c-stm32f7.c

978

u32 cr1, cr2;

drivers/i2c/busses/i2c-stm32f7.c

985

cr1 = readl_relaxed(base + STM32F7_I2C_CR1);

drivers/iio/adc/stm32-dfsdm-adc.c

509

u32 cr1;

drivers/iio/adc/stm32-dfsdm-adc.c

565

cr1 = DFSDM_CR1_RCH(chan->channel);

drivers/iio/adc/stm32-dfsdm-adc.c

569

cr1 |= DFSDM_CR1_RCONT(1);

drivers/iio/adc/stm32-dfsdm-adc.c

571

cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);

drivers/iio/adc/stm32-dfsdm-adc.c

584

cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);

drivers/iio/adc/stm32-dfsdm-adc.c

594

cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);

drivers/iio/adc/stm32-dfsdm-adc.c

598

cr1);

drivers/iio/trigger/stm32-timer-trigger.c

246

u32 psc, arr, cr1;

drivers/iio/trigger/stm32-timer-trigger.c

249

regmap_read(priv->regmap, TIM_CR1, &cr1);

drivers/iio/trigger/stm32-timer-trigger.c

253

if (cr1 & TIM_CR1_CEN) {

drivers/iio/trigger/stm32-timer-trigger.c

83

u32 cr1;

drivers/iio/trigger/stm32-timer-trigger.c

848

regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);

drivers/iio/trigger/stm32-timer-trigger.c

883

regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);

drivers/input/touchscreen/mc13783_ts.c

69

int cr0, cr1;

drivers/input/touchscreen/mc13783_ts.c

82

cr1 = (priv->sample[3] >> 12) & 0xfff;

drivers/input/touchscreen/mc13783_ts.c

86

x0, x1, x2, y0, y1, y2, cr0, cr1);

drivers/input/touchscreen/mc13783_ts.c

91

cr0 = (cr0 + cr1) / 2;

drivers/irqchip/irq-gic-v5-irs.c

551

u32 cr0, cr1;

drivers/irqchip/irq-gic-v5-irs.c

563

cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_NO_WRITE_ALLOC) |

drivers/irqchip/irq-gic-v5-irs.c

575

cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_WRITE_ALLOC) |

drivers/irqchip/irq-gic-v5-irs.c

588

irs_writel_relaxed(irs_data, cr1, GICV5_IRS_CR1);

drivers/irqchip/irq-gic-v5-its.c

1106

u32 cr0, cr1;

drivers/irqchip/irq-gic-v5-its.c

1137

cr1 = FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_NO_READ_ALLOC) |

drivers/irqchip/irq-gic-v5-its.c

1143

cr1 = FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_READ_ALLOC) |

drivers/irqchip/irq-gic-v5-its.c

1150

its_writel_relaxed(its_node, cr1, GICV5_ITS_CR1);

drivers/media/platform/nxp/imx7-media-csi.c

322

u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

324

cr1 |= BIT_RFF_OR_INT;

drivers/media/platform/nxp/imx7-media-csi.c

325

cr1 |= BIT_FB1_DMA_DONE_INTEN;

drivers/media/platform/nxp/imx7-media-csi.c

326

cr1 |= BIT_FB2_DMA_DONE_INTEN;

drivers/media/platform/nxp/imx7-media-csi.c

328

imx7_csi_reg_write(csi, cr1, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

333

u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

335

cr1 &= ~BIT_RFF_OR_INT;

drivers/media/platform/nxp/imx7-media-csi.c

336

cr1 &= ~BIT_FB1_DMA_DONE_INTEN;

drivers/media/platform/nxp/imx7-media-csi.c

337

cr1 &= ~BIT_FB2_DMA_DONE_INTEN;

drivers/media/platform/nxp/imx7-media-csi.c

339

imx7_csi_reg_write(csi, cr1, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

371

u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1) & ~BIT_FCC;

drivers/media/platform/nxp/imx7-media-csi.c

373

imx7_csi_reg_write(csi, cr1, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

374

imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

375

imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);

drivers/media/platform/nxp/imx7-media-csi.c

533

u32 cr1, cr18;

drivers/media/platform/nxp/imx7-media-csi.c

548

cr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL

drivers/media/platform/nxp/imx7-media-csi.c

563

cr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC

drivers/media/platform/nxp/imx7-media-csi.c

637

imx7_csi_reg_write(csi, cr1, CSI_CSICR1);

drivers/mtd/devices/st_spi_fsm.c

1393

uint8_t sr1, cr1, dyb;

drivers/mtd/devices/st_spi_fsm.c

1443

stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1);

drivers/mtd/devices/st_spi_fsm.c

1446

if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {

drivers/mtd/devices/st_spi_fsm.c

1448

cr1 |= STFSM_S25FL_CONFIG_QE;

drivers/mtd/devices/st_spi_fsm.c

1453

if (cr1 & STFSM_S25FL_CONFIG_QE) {

drivers/mtd/devices/st_spi_fsm.c

1455

cr1 &= ~STFSM_S25FL_CONFIG_QE;

drivers/mtd/devices/st_spi_fsm.c

1462

sta_wr = ((uint16_t)cr1 << 8) | sr1;

drivers/net/phy/realtek/realtek_main.c

1117

u16 cr1, cr2;

drivers/net/phy/realtek/realtek_main.c

1127

cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index;

drivers/net/phy/realtek/realtek_main.c

1128

if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) {

drivers/net/phy/realtek/realtek_main.c

1164

u16 cr1 = 0, cr2 = 0;

drivers/net/phy/realtek/realtek_main.c

1172

cr1 |= RTL8211E_LEDCR1_ACT_TXRX;

drivers/net/phy/realtek/realtek_main.c

1175

cr1 <<= RTL8211E_LEDCR1_SHIFT * index;

drivers/net/phy/realtek/realtek_main.c

1177

RTL8211E_LEDCR1, cr1mask, cr1);

drivers/parport/parport_pc.c

1008

(cr1 & 4) ? "yes" : "no");

drivers/parport/parport_pc.c

1010

(cr1 & 0x08) ? "Standard mode only (SPP)"

drivers/parport/parport_pc.c

969

int cr1, cr4, cra, cr23, cr26, cr27;

drivers/parport/parport_pc.c

981

cr1 = inb(io + 1);

drivers/parport/parport_pc.c

996

cr1, cr4, cra, cr23, cr26, cr27);

drivers/spi/spi-pl022.c

1713

chip->cr1 = 0;

drivers/spi/spi-pl022.c

1741

SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,

drivers/spi/spi-pl022.c

1751

SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,

drivers/spi/spi-pl022.c

1764

SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);

drivers/spi/spi-pl022.c

1765

SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);

drivers/spi/spi-pl022.c

1766

SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,

drivers/spi/spi-pl022.c

1768

SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,

drivers/spi/spi-pl022.c

1797

SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);

drivers/spi/spi-pl022.c

1799

SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);

drivers/spi/spi-pl022.c

1800

SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);

drivers/spi/spi-pl022.c

1801

SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,

drivers/spi/spi-pl022.c

410

u16 cr1;

drivers/spi/spi-pl022.c

479

writew(chip->cr1, SSP_CR1(pl022->virtbase));

drivers/spi/spi-pxa2xx.c

1007

cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;

drivers/spi/spi-pxa2xx.c

1050

pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);

drivers/spi/spi-pxa2xx.c

1084

pxa2xx_spi_write(drv_data, SSCR1, cr1);

drivers/spi/spi-pxa2xx.c

1191

chip->cr1 = 0;

drivers/spi/spi-pxa2xx.c

1193

chip->cr1 |= SSCR1_SCFR;

drivers/spi/spi-pxa2xx.c

1194

chip->cr1 |= SSCR1_SCLKDIR;

drivers/spi/spi-pxa2xx.c

1195

chip->cr1 |= SSCR1_SFRMDIR;

drivers/spi/spi-pxa2xx.c

1196

chip->cr1 |= SSCR1_SPH;

drivers/spi/spi-pxa2xx.c

1227

chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);

drivers/spi/spi-pxa2xx.c

1228

chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |

drivers/spi/spi-pxa2xx.c

1232

chip->cr1 |= SSCR1_LBM;

drivers/spi/spi-pxa2xx.c

62

u32 cr1;

drivers/spi/spi-pxa2xx.c

945

u32 cr1;

drivers/spi/spi-pxa2xx.c

998

cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;

drivers/spi/spi-rockchip.c

537

u32 cr1;

drivers/spi/spi-rockchip.c

561

cr1 = xfer->len - 1;

drivers/spi/spi-rockchip.c

565

cr1 = xfer->len - 1;

drivers/spi/spi-rockchip.c

569

cr1 = xfer->len / 2 - 1;

drivers/spi/spi-rockchip.c

589

writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);

drivers/spi/spi-sh.c

185

ss->cr1 &= ~SPI_SH_TBE;

drivers/spi/spi-sh.c

188

ss->cr1 & SPI_SH_TBE,

drivers/spi/spi-sh.c

190

if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {

drivers/spi/spi-sh.c

201

ss->cr1 &= ~SPI_SH_TBE;

drivers/spi/spi-sh.c

204

ss->cr1 & SPI_SH_TBE,

drivers/spi/spi-sh.c

206

if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {

drivers/spi/spi-sh.c

237

ss->cr1 &= ~SPI_SH_RBF;

drivers/spi/spi-sh.c

240

ss->cr1 & SPI_SH_RBF,

drivers/spi/spi-sh.c

360

unsigned long cr1;

drivers/spi/spi-sh.c

362

cr1 = spi_sh_read(ss, SPI_SH_CR1);

drivers/spi/spi-sh.c

363

if (cr1 & SPI_SH_TBE)

drivers/spi/spi-sh.c

364

ss->cr1 |= SPI_SH_TBE;

drivers/spi/spi-sh.c

365

if (cr1 & SPI_SH_TBF)

drivers/spi/spi-sh.c

366

ss->cr1 |= SPI_SH_TBF;

drivers/spi/spi-sh.c

367

if (cr1 & SPI_SH_RBE)

drivers/spi/spi-sh.c

368

ss->cr1 |= SPI_SH_RBE;

drivers/spi/spi-sh.c

369

if (cr1 & SPI_SH_RBF)

drivers/spi/spi-sh.c

370

ss->cr1 |= SPI_SH_RBF;

drivers/spi/spi-sh.c

372

if (ss->cr1) {

drivers/spi/spi-sh.c

373

spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);

drivers/spi/spi-sh.c

76

unsigned long cr1;

drivers/spi/spi-stm32.c

2199

u32 cr1 = 0, cfg2 = 0;

drivers/spi/spi-stm32.c

2216

cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI;

drivers/spi/spi-stm32.c

2227

stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);

drivers/spi/spi-stm32.c

888

u32 cr1;

drivers/spi/spi-stm32.c

894

cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);

drivers/spi/spi-stm32.c

896

if (!(cr1 & STM32H7_SPI_CR1_SPE)) {

drivers/tty/serial/fsl_linflexuart.c

317

unsigned long cr, ier, cr1;

drivers/tty/serial/fsl_linflexuart.c

331

cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME

drivers/tty/serial/fsl_linflexuart.c

333

writel(cr1, sport->membase + LINCR1);

drivers/tty/serial/fsl_linflexuart.c

357

cr1 &= ~(LINFLEXD_LINCR1_INIT);

drivers/tty/serial/fsl_linflexuart.c

359

writel(cr1, sport->membase + LINCR1);

drivers/tty/serial/fsl_linflexuart.c

407

unsigned long cr, old_cr, cr1;

drivers/tty/serial/fsl_linflexuart.c

414

cr1 = readl(port->membase + LINCR1);

drivers/tty/serial/fsl_linflexuart.c

415

cr1 |= LINFLEXD_LINCR1_INIT;

drivers/tty/serial/fsl_linflexuart.c

416

writel(cr1, port->membase + LINCR1);

drivers/tty/serial/fsl_linflexuart.c

507

cr1 &= ~(LINFLEXD_LINCR1_INIT);

drivers/tty/serial/fsl_linflexuart.c

509

writel(cr1, port->membase + LINCR1);

drivers/tty/serial/fsl_lpuart.c

1532

u8 cr1;

drivers/tty/serial/fsl_lpuart.c

1534

cr1 = readb(port->membase + UARTCR1);

drivers/tty/serial/fsl_lpuart.c

1535

if (cr1 & UARTCR1_LOOPS)

drivers/tty/serial/fsl_lpuart.c

1555

u8 cr1;

drivers/tty/serial/fsl_lpuart.c

1557

cr1 = readb(port->membase + UARTCR1);

drivers/tty/serial/fsl_lpuart.c

1560

cr1 &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);

drivers/tty/serial/fsl_lpuart.c

1562

cr1 |= UARTCR1_LOOPS;

drivers/tty/serial/fsl_lpuart.c

1564

writeb(cr1, port->membase + UARTCR1);

drivers/tty/serial/fsl_lpuart.c

2002

u8 cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;

drivers/tty/serial/fsl_lpuart.c

2007

cr1 = old_cr1 = readb(port->membase + UARTCR1);

drivers/tty/serial/fsl_lpuart.c

2030

cr1 = old_cr1 & ~UARTCR1_M;

drivers/tty/serial/fsl_lpuart.c

2037

cr1 |= UARTCR1_M;

drivers/tty/serial/fsl_lpuart.c

2060

cr1 &= ~UARTCR1_PE;

drivers/tty/serial/fsl_lpuart.c

2066

cr1 |= UARTCR1_PE;

drivers/tty/serial/fsl_lpuart.c

2068

cr1 |= UARTCR1_M;

drivers/tty/serial/fsl_lpuart.c

2070

cr1 |= UARTCR1_PT;

drivers/tty/serial/fsl_lpuart.c

2072

cr1 &= ~UARTCR1_PT;

drivers/tty/serial/fsl_lpuart.c

2075

cr1 &= ~UARTCR1_PE;

drivers/tty/serial/fsl_lpuart.c

2133

writeb(cr1, port->membase + UARTCR1);

drivers/tty/serial/stm32-usart.c

1000

stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);

drivers/tty/serial/stm32-usart.c

1016

stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);

drivers/tty/serial/stm32-usart.c

1041

stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);

drivers/tty/serial/stm32-usart.c

1097

stm32_usart_set_bits(port, ofs->cr1, val);

drivers/tty/serial/stm32-usart.c

1144

stm32_usart_clr_bits(port, ofs->cr1, val);

drivers/tty/serial/stm32-usart.c

1162

u32 cr1, cr2, cr3, isr, brr, presc;

drivers/tty/serial/stm32-usart.c

1185

writel_relaxed(0, port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

1192

cr1 = USART_CR1_TE | USART_CR1_RE;

drivers/tty/serial/stm32-usart.c

1194

cr1 |= USART_CR1_FIFOEN;

drivers/tty/serial/stm32-usart.c

1215

cr1 |= USART_CR1_PCE;

drivers/tty/serial/stm32-usart.c

1226

cr1 |= USART_CR1_M0;

drivers/tty/serial/stm32-usart.c

1228

cr1 |= USART_CR1_M1;

drivers/tty/serial/stm32-usart.c

1238

cr1 |= USART_CR1_M0;

drivers/tty/serial/stm32-usart.c

1261

cr1 |= stm32_port->cr1_irq;

drivers/tty/serial/stm32-usart.c

1265

cr1 |= USART_CR1_PS;

drivers/tty/serial/stm32-usart.c

1285

cr1 |= USART_CR1_OVER8;

drivers/tty/serial/stm32-usart.c

1286

stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);

drivers/tty/serial/stm32-usart.c

1289

cr1 &= ~USART_CR1_OVER8;

drivers/tty/serial/stm32-usart.c

1290

stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);

drivers/tty/serial/stm32-usart.c

1347

cr1 |= USART_CR1_PEIE;

drivers/tty/serial/stm32-usart.c

1357

stm32_usart_config_reg_rs485(&cr1, &cr3,

drivers/tty/serial/stm32-usart.c

1371

cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);

drivers/tty/serial/stm32-usart.c

1382

writel_relaxed(cr1, port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

1384

stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));

drivers/tty/serial/stm32-usart.c

1436

stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));

drivers/tty/serial/stm32-usart.c

185

static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,

drivers/tty/serial/stm32-usart.c

1881

stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);

drivers/tty/serial/stm32-usart.c

193

over8 = *cr1 & USART_CR1_OVER8;

drivers/tty/serial/stm32-usart.c

1943

old_cr1 = readl_relaxed(port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

1946

writel_relaxed(new_cr1, port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

195

*cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);

drivers/tty/serial/stm32-usart.c

1951

writel_relaxed(old_cr1, port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

207

*cr1 |= rs485_deat_dedt;

drivers/tty/serial/stm32-usart.c

2079

stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);

drivers/tty/serial/stm32-usart.c

2108

stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);

drivers/tty/serial/stm32-usart.c

219

*cr1 |= rs485_deat_dedt;

drivers/tty/serial/stm32-usart.c

228

u32 usartdiv, baud, cr1, cr3;

drivers/tty/serial/stm32-usart.c

231

stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));

drivers/tty/serial/stm32-usart.c

234

cr1 = readl_relaxed(port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

238

over8 = cr1 & USART_CR1_OVER8;

drivers/tty/serial/stm32-usart.c

245

stm32_usart_config_reg_rs485(&cr1, &cr3,

drivers/tty/serial/stm32-usart.c

256

writel_relaxed(cr1, port->membase + ofs->cr1);

drivers/tty/serial/stm32-usart.c

264

stm32_usart_clr_bits(port, ofs->cr1,

drivers/tty/serial/stm32-usart.c

268

stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));

drivers/tty/serial/stm32-usart.c

47

.cr1 = 0x0c,

drivers/tty/serial/stm32-usart.c

65

.cr1 = 0x00,

drivers/tty/serial/stm32-usart.c

665

stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);

drivers/tty/serial/stm32-usart.c

673

stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);

drivers/tty/serial/stm32-usart.c

684

stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);

drivers/tty/serial/stm32-usart.c

692

stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);

drivers/tty/serial/stm32-usart.c

88

.cr1 = 0x00,

drivers/tty/serial/stm32-usart.h

12

u16 cr1;

fs/btrfs/send.c

1288

const struct clone_root *cr1 = e1;

fs/btrfs/send.c

1291

if (btrfs_root_id(cr1->root) < btrfs_root_id(cr2->root))

fs/btrfs/send.c

1293

if (btrfs_root_id(cr1->root) > btrfs_root_id(cr2->root))

fs/nfsd/nfs4state.c

2782

same_creds(struct svc_cred *cr1, struct svc_cred *cr2)

fs/nfsd/nfs4state.c

2784

if ((is_gss_cred(cr1) != is_gss_cred(cr2))

fs/nfsd/nfs4state.c

2785

|| (!uid_eq(cr1->cr_uid, cr2->cr_uid))

fs/nfsd/nfs4state.c

2786

|| (!gid_eq(cr1->cr_gid, cr2->cr_gid))

fs/nfsd/nfs4state.c

2787

|| !groups_equal(cr1->cr_group_info, cr2->cr_group_info))

fs/nfsd/nfs4state.c

2790

if (cr1->cr_principal == cr2->cr_principal)

fs/nfsd/nfs4state.c

2792

if (!cr1->cr_principal || !cr2->cr_principal)

fs/nfsd/nfs4state.c

2794

return 0 == strcmp(cr1->cr_principal, cr2->cr_principal);

fs/smb/client/smb1pdu.h

2316

char cr1; /* \n */

sound/soc/codecs/peb2466.c

763

u8 cr1;

sound/soc/codecs/peb2466.c

767

cr1 = PEB2466_CR1_LAW_MULAW;

sound/soc/codecs/peb2466.c

770

cr1 = PEB2466_CR1_LAW_ALAW;

sound/soc/codecs/peb2466.c

780

PEB2466_CR1_LAW_MASK, cr1);

sound/soc/pxa/pxa-ssp.c

127

priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);

sound/soc/pxa/pxa-ssp.c

146

__raw_writel(priv->cr1, ssp->mmio_base + SSCR1);

sound/soc/pxa/pxa-ssp.c

47

uint32_t cr1;

sound/soc/stm/stm32_sai_sub.c

1121

int div = 0, cr1 = 0;

sound/soc/stm/stm32_sai_sub.c

1169

cr1 = SAI_XCR1_OSR;

sound/soc/stm/stm32_sai_sub.c

1179

SAI_XCR1_OSR, cr1);

sound/soc/stm/stm32_sai_sub.c

1317

int cr1 = 0, cr1_mask, ret;

sound/soc/stm/stm32_sai_sub.c

1344

cr1 |= SAI_XCR1_RX_TX;

sound/soc/stm/stm32_sai_sub.c

1356

cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);

sound/soc/stm/stm32_sai_sub.c

1358

return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);

sound/soc/stm/stm32_sai_sub.c

345

int ret, cr1, mask;

sound/soc/stm/stm32_sai_sub.c

353

cr1 = SAI_XCR1_MCKDIV_SET(div);

sound/soc/stm/stm32_sai_sub.c

354

ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);

sound/soc/stm/stm32_sai_sub.c

777

int cr1, frcr = 0;

sound/soc/stm/stm32_sai_sub.c

784

cr1 = SAI_XCR1_NODIV;

sound/soc/stm/stm32_sai_sub.c

789

cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);

sound/soc/stm/stm32_sai_sub.c

793

cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);

sound/soc/stm/stm32_sai_sub.c

798

cr1 |= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

803

cr1 |= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

811

cr1 |= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

815

cr1 |= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

833

cr1 ^= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

840

cr1 ^= SAI_XCR1_CKSTR;

sound/soc/stm/stm32_sai_sub.c

857

cr1 |= SAI_XCR1_SLAVE;

sound/soc/stm/stm32_sai_sub.c

872

cr1 |= SAI_XCR1_SLAVE;

sound/soc/stm/stm32_sai_sub.c

879

ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);

sound/soc/stm/stm32_sai_sub.c

940

int cr1, cr1_mask, ret;

sound/soc/stm/stm32_sai_sub.c

962

cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);

sound/soc/stm/stm32_sai_sub.c

965

cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);

sound/soc/stm/stm32_sai_sub.c

968

cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);

sound/soc/stm/stm32_sai_sub.c

977

cr1 |= SAI_XCR1_MONO;

sound/soc/stm/stm32_sai_sub.c

979

ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);