arch/arm/kernel/hw_breakpoint.c

298

u32 ctrl_reg;

arch/arm/kernel/hw_breakpoint.c

307

ctrl_reg = encode_ctrl_reg(ctrl);

arch/arm/kernel/hw_breakpoint.c

310

write_wb_reg(ARM_BASE_WCR, ctrl_reg);

arch/arm/kernel/hw_breakpoint.c

311

if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)

arch/arm/kernel/hw_breakpoint.c

732

u32 val, ctrl_reg;

arch/arm/kernel/hw_breakpoint.c

769

ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);

arch/arm/kernel/hw_breakpoint.c

770

decode_ctrl_reg(ctrl_reg, &ctrl);

arch/arm/kernel/hw_breakpoint.c

857

u32 ctrl_reg, val, addr;

arch/arm/kernel/hw_breakpoint.c

884

ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);

arch/arm/kernel/hw_breakpoint.c

885

decode_ctrl_reg(ctrl_reg, &ctrl);

arch/arm64/kernel/hw_breakpoint.c

230

int i, max_slots, ctrl_reg, val_reg, reg_enable;

arch/arm64/kernel/hw_breakpoint.c

236

ctrl_reg = AARCH64_DBG_REG_BCR;

arch/arm64/kernel/hw_breakpoint.c

243

ctrl_reg = AARCH64_DBG_REG_WCR;

arch/arm64/kernel/hw_breakpoint.c

269

write_wb_reg(ctrl_reg, i,

arch/arm64/kernel/hw_breakpoint.c

274

write_wb_reg(ctrl_reg, i, 0);

arch/arm64/kernel/hw_breakpoint.c

625

u32 ctrl_reg;

arch/arm64/kernel/hw_breakpoint.c

649

ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);

arch/arm64/kernel/hw_breakpoint.c

650

decode_ctrl_reg(ctrl_reg, &ctrl);

arch/arm64/kernel/hw_breakpoint.c

757

u32 ctrl_reg;

arch/arm64/kernel/hw_breakpoint.c

787

ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);

arch/arm64/kernel/hw_breakpoint.c

788

decode_ctrl_reg(ctrl_reg, &ctrl);

arch/powerpc/platforms/52xx/mpc52xx_pic.c

179

u32 ctrl_reg, type;

arch/powerpc/platforms/52xx/mpc52xx_pic.c

195

ctrl_reg = in_be32(&intr->ctrl);

arch/powerpc/platforms/52xx/mpc52xx_pic.c

196

ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));

arch/powerpc/platforms/52xx/mpc52xx_pic.c

197

ctrl_reg |= (type << (22 - (l2irq * 2)));

arch/powerpc/platforms/52xx/mpc52xx_pic.c

198

out_be32(&intr->ctrl, ctrl_reg);

arch/x86/kvm/pmu.h

17

#define fixed_ctrl_field(ctrl_reg, idx) \

arch/x86/kvm/pmu.h

18

(((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK)

drivers/atm/iphase.c

2437

static u32 ctrl_reg;

drivers/atm/iphase.c

2440

ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2443

ctrl_reg &= (~CTRL_LED);

drivers/atm/iphase.c

2444

writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2449

ctrl_reg |= CTRL_LED;

drivers/atm/iphase.c

2450

writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2506

u32 ctrl_reg;

drivers/atm/iphase.c

2533

ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2534

ctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST))

drivers/atm/iphase.c

2549

writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2564

ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/atm/iphase.c

2565

writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);

drivers/bluetooth/bluecard_cs.c

265

info->ctrl_reg |= REG_CONTROL_RTS;

drivers/bluetooth/bluecard_cs.c

266

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

307

info->ctrl_reg &= ~0x03;

drivers/bluetooth/bluecard_cs.c

308

info->ctrl_reg |= baud_reg;

drivers/bluetooth/bluecard_cs.c

309

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

312

info->ctrl_reg &= ~REG_CONTROL_RTS;

drivers/bluetooth/bluecard_cs.c

313

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

512

info->ctrl_reg &= ~REG_CONTROL_INTERRUPT;

drivers/bluetooth/bluecard_cs.c

513

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

546

info->ctrl_reg |= REG_CONTROL_INTERRUPT;

drivers/bluetooth/bluecard_cs.c

547

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

726

info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;

drivers/bluetooth/bluecard_cs.c

727

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

739

info->ctrl_reg = REG_CONTROL_BT_ON | REG_CONTROL_BT_RES_PU;

drivers/bluetooth/bluecard_cs.c

740

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

744

info->ctrl_reg |= REG_CONTROL_INTERRUPT;

drivers/bluetooth/bluecard_cs.c

745

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

749

info->ctrl_reg |= REG_CONTROL_RTS;

drivers/bluetooth/bluecard_cs.c

750

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

753

info->ctrl_reg |= 0x03;

drivers/bluetooth/bluecard_cs.c

754

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

757

info->ctrl_reg &= ~REG_CONTROL_RTS;

drivers/bluetooth/bluecard_cs.c

758

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/bluetooth/bluecard_cs.c

79

unsigned char ctrl_reg;

drivers/bluetooth/bluecard_cs.c

806

info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;

drivers/bluetooth/bluecard_cs.c

807

outb(info->ctrl_reg, iobase + REG_CONTROL);

drivers/clk/clk-rp1.c

1253

desc->div.reg = clockman->regs + divider_data->ctrl_reg;

drivers/clk/clk-rp1.c

1363

.ctrl_reg = PLL_SYS_PRIM,

drivers/clk/clk-rp1.c

1378

.ctrl_reg = PLL_AUDIO_PRIM,

drivers/clk/clk-rp1.c

1393

.ctrl_reg = PLL_VIDEO_PRIM,

drivers/clk/clk-rp1.c

1408

.ctrl_reg = PLL_SYS_SEC,

drivers/clk/clk-rp1.c

1423

.ctrl_reg = PLL_VIDEO_SEC,

drivers/clk/clk-rp1.c

1449

.ctrl_reg = CLK_ETH_TSU_CTRL,

drivers/clk/clk-rp1.c

1474

.ctrl_reg = CLK_ETH_CTRL,

drivers/clk/clk-rp1.c

1499

.ctrl_reg = CLK_SYS_CTRL,

drivers/clk/clk-rp1.c

1570

.ctrl_reg = PLL_AUDIO_SEC,

drivers/clk/clk-rp1.c

1585

.ctrl_reg = PLL_AUDIO_TERN,

drivers/clk/clk-rp1.c

1600

.ctrl_reg = CLK_SLOW_SYS_CTRL,

drivers/clk/clk-rp1.c

1626

.ctrl_reg = CLK_DMA_CTRL,

drivers/clk/clk-rp1.c

1651

.ctrl_reg = CLK_UART_CTRL,

drivers/clk/clk-rp1.c

1676

.ctrl_reg = CLK_PWM0_CTRL,

drivers/clk/clk-rp1.c

1702

.ctrl_reg = CLK_PWM1_CTRL,

drivers/clk/clk-rp1.c

1730

.ctrl_reg = CLK_AUDIO_IN_CTRL,

drivers/clk/clk-rp1.c

1756

.ctrl_reg = CLK_AUDIO_OUT_CTRL,

drivers/clk/clk-rp1.c

1781

.ctrl_reg = CLK_I2S_CTRL,

drivers/clk/clk-rp1.c

1800

.ctrl_reg = CLK_MIPI0_CFG_CTRL,

drivers/clk/clk-rp1.c

1819

.ctrl_reg = CLK_MIPI1_CFG_CTRL,

drivers/clk/clk-rp1.c

1839

.ctrl_reg = CLK_ADC_CTRL,

drivers/clk/clk-rp1.c

1858

.ctrl_reg = CLK_SDIO_TIMER_CTRL,

drivers/clk/clk-rp1.c

1879

.ctrl_reg = CLK_SDIO_ALT_SRC_CTRL,

drivers/clk/clk-rp1.c

1909

.ctrl_reg = VIDEO_CLK_DPI_CTRL,

drivers/clk/clk-rp1.c

1948

.ctrl_reg = CLK_GP0_CTRL,

drivers/clk/clk-rp1.c

1988

.ctrl_reg = CLK_GP1_CTRL,

drivers/clk/clk-rp1.c

2045

.ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL,

drivers/clk/clk-rp1.c

2076

.ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL,

drivers/clk/clk-rp1.c

2116

.ctrl_reg = CLK_GP2_CTRL,

drivers/clk/clk-rp1.c

2156

.ctrl_reg = CLK_GP3_CTRL,

drivers/clk/clk-rp1.c

2196

.ctrl_reg = CLK_GP4_CTRL,

drivers/clk/clk-rp1.c

2227

.ctrl_reg = VIDEO_CLK_VEC_CTRL,

drivers/clk/clk-rp1.c

2266

.ctrl_reg = CLK_GP5_CTRL,

drivers/clk/clk-rp1.c

331

u32 ctrl_reg;

drivers/clk/clk-rp1.c

352

u32 ctrl_reg;

drivers/clk/clk-rp1.c

590

prim = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

595

clockman_write(clockman, data->ctrl_reg, prim);

drivers/clk/clk-rp1.c

609

prim = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

702

return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST);

drivers/clk/clk-rp1.c

713

WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL));

drivers/clk/clk-rp1.c

714

clockman_write(clockman, data->ctrl_reg,

drivers/clk/clk-rp1.c

715

clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST);

drivers/clk/clk-rp1.c

728

clockman_write(clockman, data->ctrl_reg,

drivers/clk/clk-rp1.c

729

clockman_read(clockman, data->ctrl_reg) | PLL_SEC_RST);

drivers/clk/clk-rp1.c

746

sec = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

752

clockman_write(clockman, data->ctrl_reg, sec);

drivers/clk/clk-rp1.c

758

clockman_write(clockman, data->ctrl_reg, sec);

drivers/clk/clk-rp1.c

784

return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE);

drivers/clk/clk-rp1.c

820

clockman_write(clockman, data->ctrl_reg,

drivers/clk/clk-rp1.c

821

clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE);

drivers/clk/clk-rp1.c

838

clockman_write(clockman, data->ctrl_reg,

drivers/clk/clk-rp1.c

839

clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE);

drivers/clk/clk-rp1.c

893

ctrl = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

905

ctrl = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

921

ctrl = clockman_read(clockman, data->ctrl_reg);

drivers/clk/clk-rp1.c

941

clockman_write(clockman, data->ctrl_reg, ctrl);

drivers/clk/hisilicon/clk-hix5hd2.c

136

u32 ctrl_reg;

drivers/clk/hisilicon/clk-hix5hd2.c

148

void __iomem *ctrl_reg;

drivers/clk/hisilicon/clk-hix5hd2.c

174

val = readl_relaxed(clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

176

writel_relaxed(val, clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

178

writel_relaxed(val, clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

203

val = readl_relaxed(clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

205

writel_relaxed(val, clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

218

val = readl_relaxed(clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

221

writel_relaxed(val, clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

236

val = readl_relaxed(clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

239

writel_relaxed(val, clk->ctrl_reg);

drivers/clk/hisilicon/clk-hix5hd2.c

279

p_clk->ctrl_reg = base + clks[i].ctrl_reg;

drivers/clk/microchip/clk-core.c

100

return readl(pb->ctrl_reg) & PB_DIV_ENABLE;

drivers/clk/microchip/clk-core.c

107

writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));

drivers/clk/microchip/clk-core.c

115

writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));

drivers/clk/microchip/clk-core.c

146

return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;

drivers/clk/microchip/clk-core.c

175

err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,

drivers/clk/microchip/clk-core.c

186

v = readl(pb->ctrl_reg);

drivers/clk/microchip/clk-core.c

192

writel(v, pb->ctrl_reg);

drivers/clk/microchip/clk-core.c

197

err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,

drivers/clk/microchip/clk-core.c

227

pbclk->ctrl_reg = desc->ctrl_reg + core->iobase;

drivers/clk/microchip/clk-core.c

241

void __iomem *ctrl_reg;

drivers/clk/microchip/clk-core.c

252

return readl(refo->ctrl_reg) & REFO_ON;

drivers/clk/microchip/clk-core.c

259

writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

267

writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

283

v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;

drivers/clk/microchip/clk-core.c

365

v = readl(refo->ctrl_reg);

drivers/clk/microchip/clk-core.c

369

v = readl(refo->ctrl_reg + REFO_TRIM_REG);

drivers/clk/microchip/clk-core.c

447

err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),

drivers/clk/microchip/clk-core.c

459

v = readl(refo->ctrl_reg);

drivers/clk/microchip/clk-core.c

463

writel(v, refo->ctrl_reg);

drivers/clk/microchip/clk-core.c

487

err = readl_poll_timeout(refo->ctrl_reg, v,

drivers/clk/microchip/clk-core.c

496

v = readl(refo->ctrl_reg);

drivers/clk/microchip/clk-core.c

510

writel(v, refo->ctrl_reg);

drivers/clk/microchip/clk-core.c

513

v = readl(refo->ctrl_reg + REFO_TRIM_REG);

drivers/clk/microchip/clk-core.c

516

writel(v, refo->ctrl_reg + REFO_TRIM_REG);

drivers/clk/microchip/clk-core.c

519

writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

522

err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),

drivers/clk/microchip/clk-core.c

525

writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

565

refo->ctrl_reg = data->ctrl_reg + core->iobase;

drivers/clk/microchip/clk-core.c

577

void __iomem *ctrl_reg;

drivers/clk/microchip/clk-core.c

647

v = readl(pll->ctrl_reg);

drivers/clk/microchip/clk-core.c

700

v = readl(pll->ctrl_reg);

drivers/clk/microchip/clk-core.c

708

writel(v, pll->ctrl_reg);

drivers/clk/microchip/clk-core.c

742

spll->ctrl_reg = data->ctrl_reg + core->iobase;

drivers/clk/microchip/clk-core.c

747

spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK;

drivers/clk/microchip/clk-core.c

90

void __iomem *ctrl_reg;

drivers/clk/microchip/clk-core.h

21

const u32 ctrl_reg;

drivers/clk/microchip/clk-core.h

38

const u32 ctrl_reg;

drivers/clk/microchip/clk-core.h

45

const u32 ctrl_reg;

drivers/clk/microchip/clk-pic32mzda.c

29

.ctrl_reg = (__reg), \

drivers/clk/microchip/clk-pic32mzda.c

43

.ctrl_reg = (__reg), \

drivers/clk/microchip/clk-pic32mzda.c

97

.ctrl_reg = 0x020,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1097

ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1101

flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

999

void __iomem *ctrl_reg;

drivers/clocksource/timer-cadence-ttc.c

113

u32 ctrl_reg;

drivers/clocksource/timer-cadence-ttc.c

116

ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

117

ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;

drivers/clocksource/timer-cadence-ttc.c

118

writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

126

ctrl_reg |= CNT_CNTRL_RESET;

drivers/clocksource/timer-cadence-ttc.c

127

ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;

drivers/clocksource/timer-cadence-ttc.c

128

writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

201

u32 ctrl_reg;

drivers/clocksource/timer-cadence-ttc.c

203

ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

204

ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;

drivers/clocksource/timer-cadence-ttc.c

205

writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

229

u32 ctrl_reg;

drivers/clocksource/timer-cadence-ttc.c

231

ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-cadence-ttc.c

232

ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;

drivers/clocksource/timer-cadence-ttc.c

233

writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

drivers/clocksource/timer-rockchip.c

133

u32 ctrl_reg = TIMER_CONTROL_REG3288;

drivers/clocksource/timer-rockchip.c

142

ctrl_reg = TIMER_CONTROL_REG3399;

drivers/clocksource/timer-rockchip.c

144

timer->ctrl = timer->base + ctrl_reg;

drivers/comedi/drivers/das16.c

1156

devpriv->ctrl_reg = DAS16_CTRL_IRQ(dev->irq);

drivers/comedi/drivers/das16.c

1157

outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);

drivers/comedi/drivers/das16.c

434

unsigned int ctrl_reg;

drivers/comedi/drivers/das16.c

479

if (!(devpriv->ctrl_reg & DAS16_CTRL_DMAE)) {

drivers/comedi/drivers/das16.c

746

devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_PACING_MASK);

drivers/comedi/drivers/das16.c

747

devpriv->ctrl_reg |= DAS16_CTRL_DMAE;

drivers/comedi/drivers/das16.c

749

devpriv->ctrl_reg |= DAS16_CTRL_EXT_PACER;

drivers/comedi/drivers/das16.c

751

devpriv->ctrl_reg |= DAS16_CTRL_INT_PACER;

drivers/comedi/drivers/das16.c

752

outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);

drivers/comedi/drivers/das16.c

770

devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_DMAE |

drivers/comedi/drivers/das16.c

772

outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);

drivers/dma/xilinx/xilinx_dma.c

1482

u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);

drivers/dma/xilinx/xilinx_dma.c

1501

ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;

drivers/dma/xilinx/xilinx_dma.c

1502

ctrl_reg |= chan->desc_pendingcount <<

drivers/dma/xilinx/xilinx_dma.c

1504

dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);

drivers/fpga/socfpga.c

338

u32 ctrl_reg;

drivers/fpga/socfpga.c

347

ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);

drivers/fpga/socfpga.c

348

ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;

drivers/fpga/socfpga.c

349

ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;

drivers/fpga/socfpga.c

350

ctrl_reg |= cfgmgr_modes[mode].ctrl;

drivers/fpga/socfpga.c

353

ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;

drivers/fpga/socfpga.c

354

socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);

drivers/fpga/socfpga.c

362

u32 ctrl_reg, status;

drivers/fpga/socfpga.c

379

ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);

drivers/fpga/socfpga.c

380

ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL;

drivers/fpga/socfpga.c

381

socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);

drivers/fpga/socfpga.c

387

ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL;

drivers/fpga/socfpga.c

388

socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);

drivers/gpio/gpio-pcie-idio-24.c

236

unsigned int ctrl_reg;

drivers/gpio/gpio-pcie-idio-24.c

254

err = regmap_read(map, IDIO_24_CONTROL_REG, &ctrl_reg);

drivers/gpio/gpio-pcie-idio-24.c

259

if (ctrl_reg & CONTROL_REG_OUT_MODE) {

drivers/gpu/drm/bridge/imx/imx-ldb-helper.c

103

regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);

drivers/gpu/drm/bridge/imx/imx-ldb-helper.c

88

regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);

drivers/gpu/drm/bridge/imx/imx-ldb-helper.h

61

unsigned int ctrl_reg;

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

479

ldb->ctrl_reg = 0xe0;

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

560

regmap_write(ldb->regmap, ldb->ctrl_reg, 0);

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

198

regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

630

ldb->ctrl_reg = 0xe0;

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

703

regmap_write(ldb->regmap, ldb->ctrl_reg, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

142

i915_reg_t data_reg, ctrl_reg;

drivers/gpu/drm/i915/display/vlv_dsi.c

154

ctrl_reg = MIPI_LP_GEN_CTRL(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

159

ctrl_reg = MIPI_HS_GEN_CTRL(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

185

intel_de_write(display, ctrl_reg,

drivers/gpu/drm/i915/gt/intel_engine_types.h

232

u32 __iomem *ctrl_reg;

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3557

execlists->ctrl_reg = intel_uncore_regs(uncore) +

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

725

if (execlists->ctrl_reg) {

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

937

if (execlists->ctrl_reg)

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

938

writel(EL_CTRL_LOAD, execlists->ctrl_reg);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1277

i915_reg_t ctrl_reg;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1324

info->ctrl_reg = DSPCNTR(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1328

info->ctrl_reg = SPRCTL(info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1391

info->ctrl_reg = DSPCNTR(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1408

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1413

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1438

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1443

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

drivers/gpu/drm/mediatek/mtk_hdmi.c

123

u32 ctrl_reg = GRL_CTRL;

drivers/gpu/drm/mediatek/mtk_hdmi.c

145

ctrl_reg = GRL_CTRL;

drivers/gpu/drm/mediatek/mtk_hdmi.c

149

ctrl_reg = GRL_CTRL;

drivers/gpu/drm/mediatek/mtk_hdmi.c

153

ctrl_reg = GRL_CTRL;

drivers/gpu/drm/mediatek/mtk_hdmi.c

157

ctrl_reg = GRL_ACP_ISRC_CTRL;

drivers/gpu/drm/mediatek/mtk_hdmi.c

163

regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);

drivers/gpu/drm/mediatek/mtk_hdmi.c

172

regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

537

u32 ctrl_reg, sts_reg, sts;

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

540

ctrl_reg = (channel == THC_RXDMA1) ? THC_M_PRT_READ_DMA_CNTRL_1_OFFSET :

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

544

regmap_write_bits(dev->thc_regmap, ctrl_reg, THC_M_PRT_READ_DMA_CNTRL_START, 0);

drivers/hwmon/aspeed-pwm-tacho.c

210

u32 ctrl_reg;

drivers/hwmon/aspeed-pwm-tacho.c

221

.ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

230

.ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

239

.ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

248

u32 ctrl_reg;

drivers/hwmon/aspeed-pwm-tacho.c

261

.ctrl_reg = ASPEED_PTCR_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

272

.ctrl_reg = ASPEED_PTCR_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

283

.ctrl_reg = ASPEED_PTCR_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

294

.ctrl_reg = ASPEED_PTCR_CTRL,

drivers/hwmon/aspeed-pwm-tacho.c

305

.ctrl_reg = ASPEED_PTCR_CTRL_EXT,

drivers/hwmon/aspeed-pwm-tacho.c

316

.ctrl_reg = ASPEED_PTCR_CTRL_EXT,

drivers/hwmon/aspeed-pwm-tacho.c

327

.ctrl_reg = ASPEED_PTCR_CTRL_EXT,

drivers/hwmon/aspeed-pwm-tacho.c

338

.ctrl_reg = ASPEED_PTCR_CTRL_EXT,

drivers/hwmon/aspeed-pwm-tacho.c

405

regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,

drivers/hwmon/aspeed-pwm-tacho.c

417

regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,

drivers/hwmon/aspeed-pwm-tacho.c

438

regmap_update_bits(regmap, type_params[type].ctrl_reg,

drivers/hwmon/aspeed-pwm-tacho.c

450

regmap_update_bits(regmap, type_params[type].ctrl_reg,

drivers/i2c/busses/i2c-cadence.c

1320

unsigned int ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

1328

ctrl_reg = id->ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

1329

ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);

drivers/i2c/busses/i2c-cadence.c

1330

ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |

drivers/i2c/busses/i2c-cadence.c

1332

id->ctrl_reg = ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

1333

cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

1335

id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |

drivers/i2c/busses/i2c-cadence.c

1578

id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;

drivers/i2c/busses/i2c-cadence.c

215

u32 ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

245

cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

718

unsigned int ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

730

ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

731

ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;

drivers/i2c/busses/i2c-cadence.c

748

ctrl_reg |= CDNS_I2C_CR_HOLD;

drivers/i2c/busses/i2c-cadence.c

750

cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

772

if (ctrl_reg & CDNS_I2C_CR_HOLD) {

drivers/i2c/busses/i2c-cadence.c

783

ctrl_reg &= ~CDNS_I2C_CR_HOLD;

drivers/i2c/busses/i2c-cadence.c

784

ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;

drivers/i2c/busses/i2c-cadence.c

796

cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

844

unsigned int ctrl_reg;

drivers/i2c/busses/i2c-cadence.c

852

ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

853

ctrl_reg &= ~CDNS_I2C_CR_RW;

drivers/i2c/busses/i2c-cadence.c

854

ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;

drivers/i2c/busses/i2c-cadence.c

861

ctrl_reg |= CDNS_I2C_CR_HOLD;

drivers/i2c/busses/i2c-cadence.c

862

cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-mv64xxx.c

639

unsigned long ctrl_reg;

drivers/i2c/busses/i2c-mv64xxx.c

645

ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |

drivers/i2c/busses/i2c-mv64xxx.c

649

ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;

drivers/i2c/busses/i2c-mv64xxx.c

655

ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |

drivers/i2c/busses/i2c-mv64xxx.c

663

ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |

drivers/i2c/busses/i2c-mv64xxx.c

674

ctrl_reg |=

drivers/i2c/busses/i2c-mv64xxx.c

685

writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);

drivers/iio/accel/sca3000.c

394

u8 ctrl_reg)

drivers/iio/accel/sca3000.c

407

ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);

drivers/iio/adc/pac1934.c

1221

u8 regs[PAC1934_CTRL_STATUS_INFO_LEN], idx, ctrl_reg;

drivers/iio/adc/pac1934.c

1290

ctrl_reg = FIELD_PREP(PAC1934_CRTL_SAMPLE_RATE_MASK, PAC1934_SAMP_1024SPS);

drivers/iio/adc/pac1934.c

1292

ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_REG_ADDR, ctrl_reg);

drivers/iio/adc/pac1934.c

917

u8 ctrl_reg;

drivers/iio/adc/pac1934.c

927

ctrl_reg = FIELD_PREP(PAC1934_CRTL_SAMPLE_RATE_MASK, ret);

drivers/iio/adc/pac1934.c

928

ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_REG_ADDR, ctrl_reg);

drivers/input/keyboard/pmic8xxx-keypad.c

105

u8 ctrl_reg;

drivers/input/keyboard/pmic8xxx-keypad.c

454

kp->ctrl_reg |= KEYP_CTRL_KEYP_EN;

drivers/input/keyboard/pmic8xxx-keypad.c

456

rc = regmap_write(kp->regmap, KEYP_CTRL, kp->ctrl_reg);

drivers/input/keyboard/pmic8xxx-keypad.c

467

kp->ctrl_reg &= ~KEYP_CTRL_KEYP_EN;

drivers/input/keyboard/pmic8xxx-keypad.c

469

rc = regmap_write(kp->regmap, KEYP_CTRL, kp->ctrl_reg);

drivers/input/keyboard/pmic8xxx-keypad.c

611

kp->ctrl_reg = ctrl_val;

drivers/input/rmi4/rmi_f30.c

275

u8 *ctrl_reg = f30->ctrl_regs;

drivers/input/rmi4/rmi_f30.c

300

f30->register_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

303

sizeof(u8), &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

307

f30->register_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

310

f30->register_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

315

f30->register_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

319

&ctrl_reg);

drivers/input/rmi4/rmi_f30.c

325

f30->gpioled_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

331

f30->gpioled_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

336

f30->register_count, &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

339

sizeof(u8), &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

344

sizeof(u8), &ctrl_reg);

drivers/input/rmi4/rmi_f30.c

346

f30->ctrl_regs_size = ctrl_reg -

drivers/iommu/mtk_iommu.c

1500

reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu.c

1539

writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu.c

191

u32 ctrl_reg;

drivers/iommu/mtk_iommu_v1.c

102

u32 ctrl_reg;

drivers/iommu/mtk_iommu_v1.c

743

reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu_v1.c

758

writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);

drivers/media/platform/ti/davinci/vpif.h

391

u32 ctrl_reg;

drivers/media/platform/ti/davinci/vpif.h

393

ctrl_reg = VPIF_CH0_CTRL;

drivers/media/platform/ti/davinci/vpif.h

395

ctrl_reg = VPIF_CH1_CTRL;

drivers/media/platform/ti/davinci/vpif.h

398

vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);

drivers/media/platform/ti/davinci/vpif.h

400

vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);

drivers/media/platform/ti/davinci/vpif.h

405

u32 ctrl_reg;

drivers/media/platform/ti/davinci/vpif.h

407

ctrl_reg = VPIF_CH0_CTRL;

drivers/media/platform/ti/davinci/vpif.h

409

ctrl_reg = VPIF_CH1_CTRL;

drivers/media/platform/ti/davinci/vpif.h

412

vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);

drivers/media/platform/ti/davinci/vpif.h

414

vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);

drivers/misc/ibmasm/lowlevel.h

53

void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;

drivers/misc/ibmasm/lowlevel.h

54

writel( readl(ctrl_reg) & ~mask, ctrl_reg);

drivers/misc/ibmasm/lowlevel.h

59

void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;

drivers/misc/ibmasm/lowlevel.h

60

writel( readl(ctrl_reg) | mask, ctrl_reg);

drivers/mmc/host/mvsdio.c

602

u32 ctrl_reg = 0;

drivers/mmc/host/mvsdio.c

624

ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;

drivers/mmc/host/mvsdio.c

625

ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;

drivers/mmc/host/mvsdio.c

628

ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;

drivers/mmc/host/mvsdio.c

629

ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;

drivers/mmc/host/mvsdio.c

632

ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;

drivers/mmc/host/mvsdio.c

635

ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;

drivers/mmc/host/mvsdio.c

647

ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;

drivers/mmc/host/mvsdio.c

650

host->ctrl = ctrl_reg;

drivers/mmc/host/mvsdio.c

651

mvsd_write(MVSD_HOST_CTRL, ctrl_reg);

drivers/mmc/host/mvsdio.c

652

dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,

drivers/mmc/host/mvsdio.c

653

(ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?

drivers/mmc/host/mvsdio.c

655

(ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?

drivers/mmc/host/mvsdio.c

657

(ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c

1259

unsigned int ctrl_reg = CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c

1260

void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1142

u32 ctrl_reg;

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1147

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1148

ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1154

ew32(CTRL, ctrl_reg);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1209

u32 ctrl_reg = 0;

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1224

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1230

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1231

ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1232

ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1239

ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1246

ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

1249

ew32(CTRL, ctrl_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1311

u32 ctrl_reg = 0;

drivers/net/ethernet/intel/e1000e/ethtool.c

1322

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000e/ethtool.c

1323

ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */

drivers/net/ethernet/intel/e1000e/ethtool.c

1324

ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */

drivers/net/ethernet/intel/e1000e/ethtool.c

1329

ew32(CTRL, ctrl_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1401

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000e/ethtool.c

1402

ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */

drivers/net/ethernet/intel/e1000e/ethtool.c

1403

ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */

drivers/net/ethernet/intel/e1000e/ethtool.c

1409

ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */

drivers/net/ethernet/intel/e1000e/ethtool.c

1413

ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */

drivers/net/ethernet/intel/e1000e/ethtool.c

1419

ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);

drivers/net/ethernet/intel/e1000e/ethtool.c

1422

ew32(CTRL, ctrl_reg);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2446

u32 ctrl_reg = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

2468

ctrl_reg = er32(CTRL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2470

reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2477

ew32(CTRL, ctrl_reg);

drivers/net/ethernet/intel/igb/e1000_82575.c

1654

u32 ctrl_ext, ctrl_reg, reg, anadv_reg;

drivers/net/ethernet/intel/igb/e1000_82575.c

1677

ctrl_reg = rd32(E1000_CTRL);

drivers/net/ethernet/intel/igb/e1000_82575.c

1678

ctrl_reg |= E1000_CTRL_SLU;

drivers/net/ethernet/intel/igb/e1000_82575.c

1682

ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;

drivers/net/ethernet/intel/igb/e1000_82575.c

1723

ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |

drivers/net/ethernet/intel/igb/e1000_82575.c

1731

wr32(E1000_CTRL, ctrl_reg);

drivers/net/ethernet/intel/igb/igb_ethtool.c

1624

u32 ctrl_reg = 0;

drivers/net/ethernet/intel/igb/igb_ethtool.c

1653

ctrl_reg = rd32(E1000_CTRL);

drivers/net/ethernet/intel/igb/igb_ethtool.c

1654

ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */

drivers/net/ethernet/intel/igb/igb_ethtool.c

1655

ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */

drivers/net/ethernet/intel/igb/igb_ethtool.c

1662

ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */

drivers/net/ethernet/intel/igb/igb_ethtool.c

1664

wr32(E1000_CTRL, ctrl_reg);

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

121

u32 reg = dwmac->ctrl_reg;

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

156

reg = dwmac->ctrl_reg;

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

195

1, &dwmac->ctrl_reg);

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

89

u32 ctrl_reg; /* GMAC glue-logic control register */

drivers/net/ethernet/sun/niu.c

2372

unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;

drivers/net/ethernet/sun/niu.c

2377

ctrl_reg = ENET_SERDES_0_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

2382

ctrl_reg = ENET_SERDES_1_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

2417

nw64(ctrl_reg, ctrl_val);

drivers/net/ethernet/sun/niu.c

776

unsigned long ctrl_reg, test_cfg_reg, i;

drivers/net/ethernet/sun/niu.c

782

ctrl_reg = ENET_SERDES_0_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

786

ctrl_reg = ENET_SERDES_1_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

818

nw64(ctrl_reg, ctrl_val);

drivers/net/ethernet/sun/niu.c

929

unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;

drivers/net/ethernet/sun/niu.c

940

ctrl_reg = ENET_SERDES_0_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

946

ctrl_reg = ENET_SERDES_1_CTRL_CFG;

drivers/net/ethernet/sun/niu.c

984

nw64(ctrl_reg, ctrl_val);

drivers/net/ethernet/xilinx/xilinx_emaclite.c

724

u32 ctrl_reg;

drivers/net/ethernet/xilinx/xilinx_emaclite.c

734

ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);

drivers/net/ethernet/xilinx/xilinx_emaclite.c

738

xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,

drivers/net/ethernet/xilinx/xilinx_emaclite.c

769

u32 ctrl_reg;

drivers/net/ethernet/xilinx/xilinx_emaclite.c

783

ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);

drivers/net/ethernet/xilinx/xilinx_emaclite.c

788

xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,

drivers/net/wireless/realtek/rtw88/sec.c

127

u16 ctrl_reg;

drivers/net/wireless/realtek/rtw88/sec.c

133

ctrl_reg = rtw_read16(rtwdev, REG_CR);

drivers/net/wireless/realtek/rtw88/sec.c

134

ctrl_reg |= RTW_SEC_ENGINE_EN;

drivers/net/wireless/realtek/rtw88/sec.c

135

rtw_write16(rtwdev, REG_CR, ctrl_reg);

drivers/net/wireless/realtek/rtw89/mac.c

120

u32 ctrl_reg, data_reg, ctrl_data;

drivers/net/wireless/realtek/rtw89/mac.c

126

ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;

drivers/net/wireless/realtek/rtw89/mac.c

133

ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;

drivers/net/wireless/realtek/rtw89/mac.c

144

rtw89_write32(rtwdev, ctrl_reg, ctrl_data);

drivers/net/wireless/realtek/rtw89/mac.c

147

1, 1000, false, rtwdev, ctrl_reg);

drivers/net/wireless/realtek/rtw89/mac.c

150

ctrl_reg, ctrl_data);

drivers/net/wireless/silabs/wfx/bh.c

137

int ctrl_reg, piggyback;

drivers/net/wireless/silabs/wfx/bh.c

142

ctrl_reg = piggyback;

drivers/net/wireless/silabs/wfx/bh.c

144

ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0);

drivers/net/wireless/silabs/wfx/bh.c

146

ctrl_reg = 0;

drivers/net/wireless/silabs/wfx/bh.c

147

if (!(ctrl_reg & CTRL_NEXT_LEN_MASK))

drivers/net/wireless/silabs/wfx/bh.c

150

len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2;

drivers/net/wireless/silabs/wfx/bh.c

159

ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback);

drivers/net/wireless/silabs/wfx/bh.c

161

if (ctrl_reg)

drivers/net/wireless/silabs/wfx/bh.c

163

ctrl_reg, piggyback);

drivers/net/wireless/silabs/wfx/bh.c

268

prev = atomic_xchg(&wdev->hif.ctrl_reg, cur);

drivers/net/wireless/silabs/wfx/bh.h

22

atomic_t ctrl_reg;

drivers/net/wireless/st/cw1200/bh.c

174

u16 *ctrl_reg)

drivers/net/wireless/st/cw1200/bh.c

179

ST90TDS_CONTROL_REG_ID, ctrl_reg);

drivers/net/wireless/st/cw1200/bh.c

182

ST90TDS_CONTROL_REG_ID, ctrl_reg);

drivers/net/wireless/st/cw1200/bh.c

192

u16 ctrl_reg;

drivers/net/wireless/st/cw1200/bh.c

209

ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg);

drivers/net/wireless/st/cw1200/bh.c

216

if (ctrl_reg & ST90TDS_CONT_RDY_BIT) {

drivers/net/wireless/st/cw1200/bh.c

234

uint16_t *ctrl_reg,

drivers/net/wireless/st/cw1200/bh.c

248

read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2;

drivers/net/wireless/st/cw1200/bh.c

255

read_len, *ctrl_reg);

drivers/net/wireless/st/cw1200/bh.c

289

*ctrl_reg = __le16_to_cpu(

drivers/net/wireless/st/cw1200/bh.c

416

u16 ctrl_reg = 0;

drivers/net/wireless/st/cw1200/bh.c

540

if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))

drivers/net/wireless/st/cw1200/bh.c

544

if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {

drivers/net/wireless/st/cw1200/bh.c

545

ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);

drivers/net/wireless/st/cw1200/bh.c

549

if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {

drivers/net/wireless/st/cw1200/bh.c

550

ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);

drivers/net/wireless/st/cw1200/bh.c

578

if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))

drivers/net/wireless/st/cw1200/bh.c

585

if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK)

drivers/net/wwan/t7xx/t7xx_pci.c

197

void __iomem *ctrl_reg = IREG_BASE(t7xx_dev) + T7XX_PCIE_MISC_CTRL;

drivers/net/wwan/t7xx/t7xx_pci.c

200

value = ioread32(ctrl_reg);

drivers/net/wwan/t7xx/t7xx_pci.c

207

iowrite32(value, ctrl_reg);

drivers/ntb/hw/epf/ntb_hw_epf.c

108

writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT);

drivers/ntb/hw/epf/ntb_hw_epf.c

109

writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND);

drivers/ntb/hw/epf/ntb_hw_epf.c

114

status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS);

drivers/ntb/hw/epf/ntb_hw_epf.c

132

writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS);

drivers/ntb/hw/epf/ntb_hw_epf.c

200

status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS);

drivers/ntb/hw/epf/ntb_hw_epf.c

216

offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);

drivers/ntb/hw/epf/ntb_hw_epf.c

219

return readl(ndev->ctrl_reg + offset);

drivers/ntb/hw/epf/ntb_hw_epf.c

234

offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);

drivers/ntb/hw/epf/ntb_hw_epf.c

236

writel(val, ndev->ctrl_reg + offset);

drivers/ntb/hw/epf/ntb_hw_epf.c

428

writel(lower_32_bits(addr), ndev->ctrl_reg + NTB_EPF_LOWER_ADDR);

drivers/ntb/hw/epf/ntb_hw_epf.c

429

writel(upper_32_bits(addr), ndev->ctrl_reg + NTB_EPF_UPPER_ADDR);

drivers/ntb/hw/epf/ntb_hw_epf.c

430

writel(lower_32_bits(size), ndev->ctrl_reg + NTB_EPF_LOWER_SIZE);

drivers/ntb/hw/epf/ntb_hw_epf.c

431

writel(upper_32_bits(size), ndev->ctrl_reg + NTB_EPF_UPPER_SIZE);

drivers/ntb/hw/epf/ntb_hw_epf.c

458

offset = readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET);

drivers/ntb/hw/epf/ntb_hw_epf.c

488

db_entry_size = readl(ndev->ctrl_reg + NTB_EPF_DB_ENTRY_SIZE);

drivers/ntb/hw/epf/ntb_hw_epf.c

490

db_data = readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num));

drivers/ntb/hw/epf/ntb_hw_epf.c

491

db_offset = readl(ndev->ctrl_reg + NTB_EPF_DB_OFFSET(interrupt_num));

drivers/ntb/hw/epf/ntb_hw_epf.c

564

ndev->mw_count = readl(ndev->ctrl_reg + NTB_EPF_MW_COUNT);

drivers/ntb/hw/epf/ntb_hw_epf.c

565

ndev->spad_count = readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT);

drivers/ntb/hw/epf/ntb_hw_epf.c

608

ndev->ctrl_reg = pci_iomap(pdev, ndev->barno_map[BAR_CONFIG], 0);

drivers/ntb/hw/epf/ntb_hw_epf.c

609

if (!ndev->ctrl_reg) {

drivers/ntb/hw/epf/ntb_hw_epf.c

622

spad_sz = 4 * readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT);

drivers/ntb/hw/epf/ntb_hw_epf.c

623

spad_off = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);

drivers/ntb/hw/epf/ntb_hw_epf.c

624

ndev->peer_spad_reg = ndev->ctrl_reg + spad_off + spad_sz;

drivers/ntb/hw/epf/ntb_hw_epf.c

648

pci_iounmap(pdev, ndev->ctrl_reg);

drivers/ntb/hw/epf/ntb_hw_epf.c

86

void __iomem *ctrl_reg;

drivers/pci/hotplug/cpqphp.h

140

SLOT_RST = offsetof(struct ctrl_reg, slot_RST),

drivers/pci/hotplug/cpqphp.h

141

SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),

drivers/pci/hotplug/cpqphp.h

142

MISC = offsetof(struct ctrl_reg, misc),

drivers/pci/hotplug/cpqphp.h

143

LED_CONTROL = offsetof(struct ctrl_reg, led_control),

drivers/pci/hotplug/cpqphp.h

144

INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),

drivers/pci/hotplug/cpqphp.h

145

INT_MASK = offsetof(struct ctrl_reg, int_mask),

drivers/pci/hotplug/cpqphp.h

146

CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),

drivers/pci/hotplug/cpqphp.h

147

CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),

drivers/pci/hotplug/cpqphp.h

148

CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),

drivers/pci/hotplug/cpqphp.h

149

GEN_OUTPUT_AB = offsetof(struct ctrl_reg, gen_output_AB),

drivers/pci/hotplug/cpqphp.h

150

NON_INT_INPUT = offsetof(struct ctrl_reg, non_int_input),

drivers/pci/hotplug/cpqphp.h

151

CTRL_RESERVED3 = offsetof(struct ctrl_reg, reserved3),

drivers/pci/hotplug/cpqphp.h

152

CTRL_RESERVED4 = offsetof(struct ctrl_reg, reserved4),

drivers/pci/hotplug/cpqphp.h

153

CTRL_RESERVED5 = offsetof(struct ctrl_reg, reserved5),

drivers/pci/hotplug/cpqphp.h

154

CTRL_RESERVED6 = offsetof(struct ctrl_reg, reserved6),

drivers/pci/hotplug/cpqphp.h

155

CTRL_RESERVED7 = offsetof(struct ctrl_reg, reserved7),

drivers/pci/hotplug/cpqphp.h

156

CTRL_RESERVED8 = offsetof(struct ctrl_reg, reserved8),

drivers/pci/hotplug/cpqphp.h

157

SLOT_MASK = offsetof(struct ctrl_reg, slot_mask),

drivers/pci/hotplug/cpqphp.h

158

CTRL_RESERVED9 = offsetof(struct ctrl_reg, reserved9),

drivers/pci/hotplug/cpqphp.h

159

CTRL_RESERVED10 = offsetof(struct ctrl_reg, reserved10),

drivers/pci/hotplug/cpqphp.h

160

CTRL_RESERVED11 = offsetof(struct ctrl_reg, reserved11),

drivers/pci/hotplug/cpqphp.h

161

SLOT_SERR = offsetof(struct ctrl_reg, slot_SERR),

drivers/pci/hotplug/cpqphp.h

162

SLOT_POWER = offsetof(struct ctrl_reg, slot_power),

drivers/pci/hotplug/cpqphp.h

163

NEXT_CURR_FREQ = offsetof(struct ctrl_reg, next_curr_freq),

drivers/pci/hotplug/cpqphp.h

164

RESET_FREQ_MODE = offsetof(struct ctrl_reg, reset_freq_mode),

drivers/pci/hotplug/shpchp.h

177

BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),

drivers/pci/hotplug/shpchp.h

178

SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),

drivers/pci/hotplug/shpchp.h

179

SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),

drivers/pci/hotplug/shpchp.h

180

SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),

drivers/pci/hotplug/shpchp.h

181

SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),

drivers/pci/hotplug/shpchp.h

182

MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),

drivers/pci/hotplug/shpchp.h

183

PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),

drivers/pci/hotplug/shpchp.h

184

CMD = offsetof(struct ctrl_reg, cmd),

drivers/pci/hotplug/shpchp.h

185

CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),

drivers/pci/hotplug/shpchp.h

186

INTR_LOC = offsetof(struct ctrl_reg, intr_loc),

drivers/pci/hotplug/shpchp.h

187

SERR_LOC = offsetof(struct ctrl_reg, serr_loc),

drivers/pci/hotplug/shpchp.h

188

SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),

drivers/pci/hotplug/shpchp.h

189

SLOT1 = offsetof(struct ctrl_reg, slot1),

drivers/perf/marvell_cn10k_ddr_pmu.c

507

u64 ctrl_reg = p_data->cnt_start_op_ctrl;

drivers/perf/marvell_cn10k_ddr_pmu.c

510

DDRC_PERF_REG(ctrl_reg, counter));

drivers/perf/marvell_cn10k_ddr_pmu.c

517

u64 ctrl_reg = p_data->cnt_end_op_ctrl;

drivers/perf/marvell_cn10k_ddr_pmu.c

520

DDRC_PERF_REG(ctrl_reg, counter));

drivers/perf/marvell_cn10k_ddr_pmu.c

527

u64 ctrl_reg = pmu->p_data->cnt_op_mode_ctrl;

drivers/perf/marvell_cn10k_ddr_pmu.c

555

reg = DDRC_PERF_REG(ctrl_reg, counter);

drivers/phy/marvell/phy-berlin-sata.c

105

phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,

drivers/phy/marvell/phy-berlin-sata.c

110

phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,

drivers/phy/marvell/phy-berlin-sata.c

114

phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,

drivers/phy/marvell/phy-berlin-sata.c

118

phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,

drivers/phy/marvell/phy-berlin-sata.c

122

regval = readl(ctrl_reg + PORT_SCR_CTL);

drivers/phy/marvell/phy-berlin-sata.c

125

writel(regval, ctrl_reg + PORT_SCR_CTL);

drivers/phy/marvell/phy-berlin-sata.c

66

static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,

drivers/phy/marvell/phy-berlin-sata.c

72

writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);

drivers/phy/marvell/phy-berlin-sata.c

75

regval = readl(ctrl_reg + PORT_VSR_DATA);

drivers/phy/marvell/phy-berlin-sata.c

78

writel(regval, ctrl_reg + PORT_VSR_DATA);

drivers/phy/marvell/phy-berlin-sata.c

85

void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);

drivers/pinctrl/cirrus/pinctrl-lochnagar.c

1006

ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);

drivers/pinctrl/cirrus/pinctrl-lochnagar.c

376

.ctrl_reg = LOCHNAGAR1_##CTRL, \

drivers/pinctrl/cirrus/pinctrl-lochnagar.c

388

.ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \

drivers/pinctrl/cirrus/pinctrl-lochnagar.c

402

u16 ctrl_reg;

drivers/pinctrl/cirrus/pinctrl-lochnagar.c

881

ret = regmap_update_bits(regmap, aif->ctrl_reg,

drivers/pmdomain/mediatek/mtk-scpsys.c

154

struct scp_ctrl_reg ctrl_reg;

drivers/pmdomain/mediatek/mtk-scpsys.c

176

u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &

drivers/pmdomain/mediatek/mtk-scpsys.c

178

u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &

drivers/pmdomain/mediatek/mtk-scpsys.c

436

scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;

drivers/pmdomain/mediatek/mtk-scpsys.c

437

scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;

drivers/power/supply/ltc2941-battery-gauge.c

211

u8 ctrl_reg;

drivers/power/supply/ltc2941-battery-gauge.c

223

LTC294X_REG_CONTROL, &ctrl_reg, 1);

drivers/power/supply/ltc2941-battery-gauge.c

227

ctrl_reg |= LTC294X_REG_CONTROL_SHUTDOWN_MASK;

drivers/power/supply/ltc2941-battery-gauge.c

229

LTC294X_REG_CONTROL, &ctrl_reg, 1);

drivers/power/supply/ltc2941-battery-gauge.c

241

ctrl_reg &= ~LTC294X_REG_CONTROL_SHUTDOWN_MASK;

drivers/power/supply/ltc2941-battery-gauge.c

243

LTC294X_REG_CONTROL, &ctrl_reg, 1);

drivers/regulator/qcom_spmi-regulator.c

1842

u8 ctrl_reg[8], reg, mask;

drivers/regulator/qcom_spmi-regulator.c

1846

ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);

drivers/regulator/qcom_spmi-regulator.c

1856

ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=

drivers/regulator/qcom_spmi-regulator.c

1858

ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=

drivers/regulator/qcom_spmi-regulator.c

1871

ctrl_reg[SPMI_COMMON_IDX_MODE] &=

drivers/regulator/qcom_spmi-regulator.c

1873

ctrl_reg[SPMI_COMMON_IDX_MODE] |=

drivers/regulator/qcom_spmi-regulator.c

1880

ctrl_reg[SPMI_COMMON_IDX_MODE] &=

drivers/regulator/qcom_spmi-regulator.c

1882

ctrl_reg[SPMI_COMMON_IDX_MODE] |=

drivers/regulator/qcom_spmi-regulator.c

1891

ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);

drivers/regulator/vctrl-regulator.c

323

struct regulator *ctrl_reg)

drivers/regulator/vctrl-regulator.c

332

n_voltages = regulator_count_voltages(ctrl_reg);

drivers/regulator/vctrl-regulator.c

338

ctrl_uV = regulator_list_voltage(ctrl_reg, i);

drivers/regulator/vctrl-regulator.c

358

ctrl_uV = regulator_list_voltage(ctrl_reg, i);

drivers/regulator/vctrl-regulator.c

450

struct regulator *ctrl_reg;

drivers/regulator/vctrl-regulator.c

465

ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl");

drivers/regulator/vctrl-regulator.c

466

if (IS_ERR(ctrl_reg))

drivers/regulator/vctrl-regulator.c

467

return PTR_ERR(ctrl_reg);

drivers/regulator/vctrl-regulator.c

477

if ((regulator_get_linear_step(ctrl_reg) == 1) ||

drivers/regulator/vctrl-regulator.c

478

(regulator_count_voltages(ctrl_reg) == -EINVAL)) {

drivers/regulator/vctrl-regulator.c

495

ret = vctrl_init_vtable(pdev, ctrl_reg);

drivers/regulator/vctrl-regulator.c

500

ctrl_uV = regulator_get_voltage(ctrl_reg);

drivers/regulator/vctrl-regulator.c

524

devm_regulator_put(ctrl_reg);

drivers/regulator/wm831x-ldo.c

109

int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;

drivers/regulator/wm831x-ldo.c

123

ret = wm831x_set_bits(wm831x, ctrl_reg,

drivers/regulator/wm831x-ldo.c

136

ret = wm831x_set_bits(wm831x, ctrl_reg,

drivers/regulator/wm831x-ldo.c

83

int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;

drivers/regulator/wm831x-ldo.c

94

ret = wm831x_reg_read(wm831x, ctrl_reg);

drivers/rtc/rtc-ds1307.c

1234

unsigned int ctrl_reg;

drivers/rtc/rtc-ds1307.c

1236

regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);

drivers/rtc/rtc-ds1307.c

1238

return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n");

drivers/rtc/rtc-ds1307.c

851

unsigned int ctrl_reg;

drivers/rtc/rtc-ds1307.c

854

regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);

drivers/rtc/rtc-ds1307.c

856

val = ctrl_reg & M41TXX_M_CALIBRATION;

drivers/rtc/rtc-ds1307.c

859

if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)

drivers/rtc/rtc-ds1307.c

870

unsigned int ctrl_reg;

drivers/rtc/rtc-ds1307.c

876

ctrl_reg = DIV_ROUND_CLOSEST(offset,

drivers/rtc/rtc-ds1307.c

878

ctrl_reg |= M41TXX_BIT_CALIB_SIGN;

drivers/rtc/rtc-ds1307.c

880

ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),

drivers/rtc/rtc-ds1307.c

886

ctrl_reg);

drivers/rtc/rtc-pm8xxx.c

423

unsigned int ctrl_reg;

drivers/rtc/rtc-pm8xxx.c

436

rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);

drivers/rtc/rtc-pm8xxx.c

440

alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);

drivers/rtc/rtc-rk808.c

103

ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,

drivers/rtc/rtc-rk808.c

117

ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,

drivers/rtc/rtc-rk808.c

163

ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,

drivers/rtc/rtc-rk808.c

178

ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,

drivers/rtc/rtc-rk808.c

363

.ctrl_reg = RK808_RTC_CTRL_REG,

drivers/rtc/rtc-rk808.c

371

.ctrl_reg = RK817_RTC_CTRL_REG,

drivers/rtc/rtc-rk808.c

403

ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,

drivers/rtc/rtc-rk808.c

45

unsigned int ctrl_reg;

drivers/scsi/advansys.c

6928

uchar ctrl_reg;

drivers/scsi/advansys.c

6952

ctrl_reg = AscGetChipControl(iop_base);

drivers/scsi/advansys.c

6953

saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |

drivers/scsi/advansys.c

6982

if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {

drivers/scsi/zorro_esp.c

445

writeb(*ctrl_data, &dregs->ctrl_reg);

drivers/scsi/zorro_esp.c

538

writeb(*ctrl_data, &dregs->ctrl_reg);

drivers/spi/spi-armada-3700.c

343

unsigned int ctrl_reg;

drivers/spi/spi-armada-3700.c

354

ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);

drivers/spi/spi-armada-3700.c

355

if (a3700_spi->wait_mask & ctrl_reg)

drivers/spi/spi-armada-3700.c

380

ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);

drivers/spi/spi-armada-3700.c

381

if (a3700_spi->wait_mask & ctrl_reg)

drivers/spi/spi-axiado.c

110

u32 ctrl_reg;

drivers/spi/spi-axiado.c

112

ctrl_reg = ax_spi_read(xspi, AX_SPI_CR2);

drivers/spi/spi-axiado.c

114

ctrl_reg &= ~AX_SPI_DEFAULT_TS_MASK;

drivers/spi/spi-axiado.c

115

ctrl_reg |= spi_get_chipselect(spi, 0);

drivers/spi/spi-axiado.c

117

ax_spi_write(xspi, AX_SPI_CR2, ctrl_reg);

drivers/spi/spi-axiado.c

129

u32 ctrl_reg, new_ctrl_reg;

drivers/spi/spi-axiado.c

132

ctrl_reg = new_ctrl_reg;

drivers/spi/spi-axiado.c

141

if (new_ctrl_reg != ctrl_reg)

drivers/spi/spi-cadence.c

167

u32 ctrl_reg = 0;

drivers/spi/spi-cadence.c

170

ctrl_reg |= CDNS_SPI_CR_DEFAULT;

drivers/spi/spi-cadence.c

173

ctrl_reg |= CDNS_SPI_CR_PERI_SEL;

drivers/spi/spi-cadence.c

183

cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);

drivers/spi/spi-cadence.c

195

u32 ctrl_reg;

drivers/spi/spi-cadence.c

197

ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);

drivers/spi/spi-cadence.c

201

ctrl_reg |= CDNS_SPI_CR_SSCTRL;

drivers/spi/spi-cadence.c

204

ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;

drivers/spi/spi-cadence.c

206

ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<

drivers/spi/spi-cadence.c

210

ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &

drivers/spi/spi-cadence.c

214

cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);

drivers/spi/spi-cadence.c

226

u32 ctrl_reg, new_ctrl_reg;

drivers/spi/spi-cadence.c

229

ctrl_reg = new_ctrl_reg;

drivers/spi/spi-cadence.c

238

if (new_ctrl_reg != ctrl_reg) {

drivers/spi/spi-cadence.c

269

u32 ctrl_reg, baud_rate_val;

drivers/spi/spi-cadence.c

274

ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);

drivers/spi/spi-cadence.c

284

ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;

drivers/spi/spi-cadence.c

285

ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;

drivers/spi/spi-cadence.c

289

cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);

drivers/spi/spi-cadence.c

570

u32 ctrl_reg;

drivers/spi/spi-cadence.c

579

ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);

drivers/spi/spi-cadence.c

580

ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;

drivers/spi/spi-cadence.c

581

if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))

drivers/spi/spi-jcore.c

102

void __iomem *ctrl_reg = hw->base + CTRL_REG;

drivers/spi/spi-jcore.c

120

if (jcore_spi_wait(ctrl_reg))

drivers/spi/spi-jcore.c

124

writel(xmit, ctrl_reg);

drivers/spi/spi-jcore.c

126

if (jcore_spi_wait(ctrl_reg))

drivers/spi/spi-jcore.c

44

static int jcore_spi_wait(void __iomem *ctrl_reg)

drivers/spi/spi-jcore.c

49

if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))

drivers/spi/spi-jcore.c

59

void __iomem *ctrl_reg = hw->base + CTRL_REG;

drivers/spi/spi-jcore.c

61

if (jcore_spi_wait(ctrl_reg))

drivers/spi/spi-jcore.c

65

writel(hw->cs_reg | hw->speed_reg, ctrl_reg);

drivers/spi/spi-orion.c

330

void __iomem *ctrl_reg;

drivers/spi/spi-orion.c

334

ctrl_reg = spi_reg(orion_spi, ORION_SPI_IF_CTRL_REG);

drivers/spi/spi-orion.c

336

val = readl(ctrl_reg);

drivers/spi/spi-orion.c

364

writel(val, ctrl_reg);

drivers/spi/spi-ti-qspi.c

48

unsigned int ctrl_reg;

drivers/spi/spi-ti-qspi.c

531

regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,

drivers/spi/spi-ti-qspi.c

545

regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,

drivers/spi/spi-ti-qspi.c

832

1, &qspi->ctrl_reg);

drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c

657

int ctrl_reg, int shift, bool on)

drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c

668

ret = gmin_i2c_write(dev, gs->pwm_i2c_addr, ctrl_reg, val, 1 << shift);

drivers/thermal/loongson2_thermal.c

101

writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG);

drivers/thermal/loongson2_thermal.c

139

data->ctrl_reg = devm_platform_ioremap_resource(pdev, 0);

drivers/thermal/loongson2_thermal.c

140

if (IS_ERR(data->ctrl_reg))

drivers/thermal/loongson2_thermal.c

141

return PTR_ERR(data->ctrl_reg);

drivers/thermal/loongson2_thermal.c

158

writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG);

drivers/thermal/loongson2_thermal.c

45

void __iomem *ctrl_reg;

drivers/thermal/loongson2_thermal.c

55

int ctrl_reg = low ? LOONGSON2_THSENS_CTRL_LOW_REG : LOONGSON2_THSENS_CTRL_HI_REG;

drivers/thermal/loongson2_thermal.c

59

writew(reg_ctrl, data->ctrl_reg + ctrl_reg + reg_off);

drivers/thermal/loongson2_thermal.c

79

val = readl(data->ctrl_reg + LOONGSON2_THSENS_OUT_REG);

drivers/tty/serial/xilinx_uartps.c

1282

unsigned int ctrl_reg;

drivers/tty/serial/xilinx_uartps.c

1287

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

1288

if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))

drivers/tty/serial/xilinx_uartps.c

1300

ctrl_reg = readl(port->membase + CDNS_UART_SR);

drivers/tty/serial/xilinx_uartps.c

1302

if (!(ctrl_reg & CDNS_UART_SR_TXFULL))

drivers/tty/serial/xilinx_uartps.c

1503

u32 ctrl_reg;

drivers/tty/serial/xilinx_uartps.c

1523

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

1524

ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;

drivers/tty/serial/xilinx_uartps.c

1525

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

1533

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

1534

ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);

drivers/tty/serial/xilinx_uartps.c

1535

ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;

drivers/tty/serial/xilinx_uartps.c

1536

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

605

u32 ctrl_reg;

drivers/tty/serial/xilinx_uartps.c

635

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

636

ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;

drivers/tty/serial/xilinx_uartps.c

637

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

662

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

663

ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;

drivers/tty/serial/xilinx_uartps.c

664

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

676

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

677

ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);

drivers/tty/serial/xilinx_uartps.c

678

ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;

drivers/tty/serial/xilinx_uartps.c

679

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

819

unsigned int ctrl_reg, mode_reg;

drivers/tty/serial/xilinx_uartps.c

824

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

825

ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;

drivers/tty/serial/xilinx_uartps.c

826

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

845

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

846

ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;

drivers/tty/serial/xilinx_uartps.c

847

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

857

ctrl_reg = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

858

ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);

drivers/tty/serial/xilinx_uartps.c

859

ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;

drivers/tty/serial/xilinx_uartps.c

860

writel(ctrl_reg, port->membase + CDNS_UART_CR);

drivers/usb/c67x00/c67x00-sched.c

1032

!(td->ctrl_reg & SEQ_SEL));

drivers/usb/c67x00/c67x00-sched.c

125

!(td->ctrl_reg & SEQ_SEL)))

drivers/usb/c67x00/c67x00-sched.c

148

dev_dbg(dev, "ctrl_reg: 0x%02x\n", td->ctrl_reg);

drivers/usb/c67x00/c67x00-sched.c

48

u8 ctrl_reg; /* Byte 6 */

drivers/usb/c67x00/c67x00-sched.c

620

td->ctrl_reg = cmd;

drivers/video/fbdev/sm501fb.c

723

void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;

drivers/video/fbdev/sm501fb.c

726

control = smc501_readl(ctrl_reg);

drivers/video/fbdev/sm501fb.c

732

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

737

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

749

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

760

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

772

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

783

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

789

smc501_writel(control, ctrl_reg);

drivers/video/fbdev/sm501fb.c

794

smc501_writel(control, ctrl_reg);

drivers/watchdog/machzwd.c

188

unsigned int ctrl_reg = 0;

drivers/watchdog/machzwd.c

196

ctrl_reg = zf_get_control();

drivers/watchdog/machzwd.c

197

ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */

drivers/watchdog/machzwd.c

198

ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2);

drivers/watchdog/machzwd.c

199

zf_set_control(ctrl_reg);

drivers/watchdog/machzwd.c

211

unsigned int ctrl_reg = 0;

drivers/watchdog/machzwd.c

227

ctrl_reg = zf_get_control();

drivers/watchdog/machzwd.c

228

ctrl_reg |= (ENABLE_WD1|zf_action);

drivers/watchdog/machzwd.c

229

zf_set_control(ctrl_reg);

drivers/watchdog/machzwd.c

238

unsigned int ctrl_reg = 0;

drivers/watchdog/machzwd.c

251

ctrl_reg = zf_get_control();

drivers/watchdog/machzwd.c

252

ctrl_reg |= RESET_WD1;

drivers/watchdog/machzwd.c

253

zf_set_control(ctrl_reg);

drivers/watchdog/machzwd.c

256

ctrl_reg &= ~(RESET_WD1);

drivers/watchdog/machzwd.c

257

zf_set_control(ctrl_reg);

drivers/watchdog/meson_gxbb_wdt.c

166

u32 ctrl_reg;

drivers/watchdog/meson_gxbb_wdt.c

194

ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &

drivers/watchdog/meson_gxbb_wdt.c

197

if (ctrl_reg) {

drivers/watchdog/meson_gxbb_wdt.c

207

ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &

drivers/watchdog/meson_gxbb_wdt.c

213

writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);