drivers/bluetooth/btusb.c
3121
btdata->qca_dump.controller_id);
drivers/bluetooth/btusb.c
3699
btdata->qca_dump.controller_id = le32_to_cpu(ver.rom_version);
drivers/bluetooth/btusb.c
935
u32 controller_id;
drivers/bluetooth/hci_qca.c
1019
qca->controller_id);
drivers/bluetooth/hci_qca.c
170
u16 controller_id;
drivers/bluetooth/hci_qca.c
2086
qca->controller_id = le16_to_cpu(ver.rom_ver);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
100
adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
930
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
943
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
951
return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
1759
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
1772
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
1780
return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1030
uint8_t controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1037
bp_params->controller_id, &controller_id)) {
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1038
clk.sPCLKInput.ucCRTC = controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1100
uint8_t controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1107
bp_params->controller_id, &controller_id)) {
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1127
clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1192
uint8_t controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1198
&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1218
clk.ucCRTC = controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1633
if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1737
if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
1762
if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2094
bp_params->controller_id, &atom_controller_id))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2167
bp_params->controller_id, &atom_controller_id))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2249
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2268
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2275
if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2301
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2318
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2325
if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2580
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
2601
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.c
997
if (CONTROLLER_ID_D1 != bp_params->controller_id)
drivers/gpu/drm/amd/display/dc/bios/command_table.h
82
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.h
86
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table.h
96
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
491
uint8_t controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
498
controller_id, &controller_id)) {
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
518
clk.crtc_id = controller_id;
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
538
bp_params->target_pixel_clock_100hz, (int)controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
620
bp_params->controller_id, &atom_controller_id))
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
712
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
729
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
736
if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
808
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
813
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
853
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
885
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
76
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
80
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
90
enum controller_id crtc_id,
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
76
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
41
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
101
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
41
enum controller_id id,
drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h
35
bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
542
ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
549
if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
112
enum controller_id id,
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
135
enum controller_id controller_id,
drivers/gpu/drm/amd/display/dc/dc_types.h
713
enum controller_id controllerId;
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
104
dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
114
if (controller_id == 0)
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
235
unsigned int controller_id,
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
246
controller_id,
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
58
static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
76
MASTER_COMM_CMD_REG_BYTE1, controller_id);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
91
uint32_t controller_id,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1020
bp_pc_params.controller_id = pix_clk_params->controller_id;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1079
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1125
pix_clk_params->controller_id - 1);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1137
bp_pc_params.controller_id = pix_clk_params->controller_id;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1199
bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1360
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1406
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
860
bp_pc_params.controller_id = pix_clk_params->controller_id;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
935
bp_pc_params.controller_id = pix_clk_params->controller_id;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
970
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
173
unsigned int controller_id,
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
176
(void)controller_id;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
147
result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1808
switch (tg110->controller_id) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2355
tg110->controller_id = CONTROLLER_ID_D0 + instance;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
239
result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
308
bp_params.controller_id = tg110->controller_id;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
101
enum controller_id controller_id;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
703
tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
1268
tg110->controller_id = CONTROLLER_ID_D0 + instance;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
151
result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
394
switch (tg110->controller_id) {
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
251
tg110->controller_id = CONTROLLER_ID_D0 + instance;
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
239
tg110->controller_id = CONTROLLER_ID_D0 + instance;
drivers/gpu/drm/amd/display/dc/dm_services.h
242
bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
74
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
89
if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
92
dcb, controller_id + 1, cntl);
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
98
HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
45
bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1344
enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
211
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
227
if (controller_id == underlay_idx)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
228
controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
230
if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
233
dcb, controller_id + 1, cntl);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
242
if (controller_id < CONTROLLER_ID_MAX - 1)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
244
HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3397
uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3412
controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
117
enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id);
drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
115
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
130
if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
133
dcb, controller_id + 1, cntl);
drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
139
HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
153
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
158
(void)controller_id;
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
174
if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
177
dcb, controller_id + 1, cntl);
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
183
HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
188
dce120_init_pte(ctx, controller_id);
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
79
#define CNTL_ID(controller_id)\
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
80
controller_id
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
84
static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3643
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3648
(void)controller_id;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
149
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
101
uint8_t controller_id,
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
92
enum controller_id controller_id;
drivers/gpu/drm/amd/display/dc/inc/core_types.h
705
enum controller_id controllerId;
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
42
bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
50
unsigned int controller_id,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
902
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1037
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1274
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1879
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1673
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1638
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/include/bios_parser_types.h
139
enum controller_id controller_id;
drivers/gpu/drm/amd/display/include/bios_parser_types.h
173
enum controller_id controller_id;
drivers/gpu/drm/amd/display/include/bios_parser_types.h
221
enum controller_id controller_id; /* (Which CRTC uses this PLL) */
drivers/gpu/drm/amd/display/include/grph_object_id.h
255
static inline enum controller_id dal_graphics_object_id_get_controller_id(
drivers/gpu/drm/amd/display/include/grph_object_id.h
259
return (enum controller_id) id.id;
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
61
unsigned int controller_id;
drivers/gpu/drm/amd/include/dm_pp_interface.h
50
uint32_t controller_id;
drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
88
display_cfg->controller_id = amdgpu_crtc->crtc_id;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
309
if (display_config->displays[index].controller_id != 0)
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
354
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
362
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
371
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
380
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
191
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
199
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
208
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
396
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
404
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
413
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
422
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
403
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
411
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
420
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
429
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
437
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
445
.controller_id = MSM_DP_CONTROLLER_3,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
453
.controller_id = MSM_DP_CONTROLLER_2,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
461
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
469
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
267
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
275
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
284
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
293
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
394
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
402
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
411
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
420
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
127
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
135
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
114
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
127
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
135
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
241
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
249
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
218
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
226
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
234
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
189
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
197
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
205
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
137
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
145
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
237
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
245
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
253
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
261
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
293
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
301
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
310
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
319
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
299
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
307
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
316
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
327
.controller_id = 999,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
335
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
343
.controller_id = MSM_DP_CONTROLLER_2,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
207
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
215
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
224
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
233
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
171
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
179
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
188
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
150
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
158
.controller_id = 0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
278
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
286
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
295
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
304
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
131
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
139
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
89
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
160
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
168
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
89
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
98
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
303
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
311
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
320
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
329
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
185
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
193
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
202
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
296
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
304
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
313
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
322
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
330
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
338
.controller_id = MSM_DP_CONTROLLER_3,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
346
.controller_id = MSM_DP_CONTROLLER_2,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
354
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
362
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_8 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
316
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
324
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
333
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
342
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
323
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
331
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
340
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
349
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
357
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
365
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
373
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
381
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
311
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
319
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
328
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
337
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
311
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
319
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
328
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
337
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
311
.controller_id = MSM_DP_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
319
.controller_id = MSM_DSI_CONTROLLER_0,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
328
.controller_id = MSM_DSI_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
337
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
345
.controller_id = MSM_DP_CONTROLLER_1,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
353
.controller_id = MSM_DP_CONTROLLER_3,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
361
.controller_id = MSM_DP_CONTROLLER_2,
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
369
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
377
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
1441
enum dpu_intf_type type, u32 controller_id)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
1450
&& catalog->intf[i].controller_id == controller_id) {
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
2663
u32 controller_id = disp_info->h_tile_instance[i];
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
2675
i, controller_id, phys_params.split_role);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
2679
controller_id);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
2681
if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
2682
phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
517
u32 controller_id;
drivers/net/ethernet/emulex/benet/be_cmds.h
1361
struct controller_id cont_id;
drivers/pci/controller/dwc/pci-imx6.c
164
u32 controller_id;
drivers/pci/controller/dwc/pci-imx6.c
1860
imx_pcie->controller_id = domain;
drivers/pci/controller/dwc/pci-imx6.c
251
return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
drivers/pci/controller/dwc/pci-imx6.c
305
id = imx_pcie->controller_id;
drivers/pci/hotplug/ibmphp.h
243
u8 controller_id;
drivers/pci/hotplug/ibmphp_ebda.c
119
debug("%s - controller_id = %x\n", __func__, ptr->controller_id);
drivers/pci/hotplug/ibmphp_ebda.c
754
bus_info_ptr1->controller_id = hpc_ptr->ctlr_id;
drivers/scsi/aic94xx/aic94xx_sds.h
85
struct controller_id contrl_id; /*PCI id to identify the controller */
drivers/soundwire/amd_manager.c
1100
amd_manager->bus.controller_id = 0;
drivers/soundwire/bus.c
26
if (bus->controller_id == -1)
drivers/soundwire/bus.c
27
bus->controller_id = rc;
drivers/soundwire/debugfs.c
25
snprintf(name, sizeof(name), "master-%d-%d", bus->controller_id, bus->link_id);
drivers/soundwire/intel_auxdevice.c
333
bus->controller_id = 0;
drivers/soundwire/master.c
148
dev_set_name(&md->dev, "sdw-master-%d-%d", bus->controller_id, bus->link_id);
drivers/soundwire/qcom.c
1649
ctrl->bus.controller_id = -1;
drivers/soundwire/qcom.c
1653
ctrl->bus.controller_id = val;
drivers/soundwire/slave.c
47
bus->controller_id, bus->link_id, id->mfg_id, id->part_id,
drivers/soundwire/slave.c
52
bus->controller_id, bus->link_id, id->mfg_id, id->part_id,
include/acpi/actbl2.h
2920
u16 controller_id;
include/linux/soundwire/sdw.h
1035
int controller_id;
sound/soc/sdca/sdca_hid.c
107
bus->controller_id, bus->link_id, sdw->id.mfg_id,
