/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
 */

#ifndef _DPU_6_3_SM6115_H
#define _DPU_6_3_SM6115_H

static const struct dpu_caps sm6115_dpu_caps = {
        .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
        .max_mixer_blendstages = 0x4,
        .has_dim_layer = true,
        .has_idle_pc = true,
        .max_linewidth = 2160,
        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};

static const struct dpu_mdp_cfg sm6115_mdp = {
        .name = "top_0",
        .base = 0x0, .len = 0x494,
        .clk_ctrls = {
                [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
                [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
        },
};

static const struct dpu_ctl_cfg sm6115_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x1dc,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        },
};

static const struct dpu_sspp_cfg sm6115_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
                .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
                .clk_ctrl = DPU_CLK_CTRL_VIG0,
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
                .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
                .clk_ctrl = DPU_CLK_CTRL_DMA0,
        },
};

static const struct dpu_lm_cfg sm6115_lm[] = {
        {
                .name = "lm_0", .id = LM_0,
                .base = 0x44000, .len = 0x320,
                .sblk = &qcm2290_lm_sblk,
                .pingpong = PINGPONG_0,
                .dspp = DSPP_0,
        },
};

static const struct dpu_dspp_cfg sm6115_dspp[] = {
        {
                .name = "dspp_0", .id = DSPP_0,
                .base = 0x54000, .len = 0x1800,
                .sblk = &sdm845_dspp_sblk,
        },
};

static const struct dpu_pingpong_cfg sm6115_pp[] = {
        {
                .name = "pingpong_0", .id = PINGPONG_0,
                .base = 0x70000, .len = 0xd4,
                .sblk = &sdm845_pp_sblk,
                .merge_3d = 0,
                .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
        },
};

static const struct dpu_intf_cfg sm6115_intf[] = {
        {
                .name = "intf_1", .id = INTF_1,
                .base = 0x6a800, .len = 0x2c0,
                .type = INTF_DSI,
                .controller_id = MSM_DSI_CONTROLLER_0,
                .prog_fetch_lines_worst_case = 24,
                .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
        },
};

static const struct dpu_perf_cfg sm6115_perf_data = {
        .max_bw_low = 3100000,
        .max_bw_high = 4000000,
        .min_core_ib = 2400000,
        .min_llcc_ib = 800000,
        .min_dram_ib = 800000,
        .min_prefill_lines = 24,
        .danger_lut_tbl = {0xff, 0xffff, 0x0},
        .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
        .qos_lut_tbl = {
                {.nentry = ARRAY_SIZE(sc7180_qos_linear),
                .entries = sc7180_qos_linear
                },
                {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
                .entries = sc7180_qos_macrotile
                },
                {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
                .entries = sc7180_qos_nrt
                },
                /* TODO: macrotile-qseed is different from macrotile */
        },
        .cdp_cfg = {
                {.rd_enable = 1, .wr_enable = 1},
                {.rd_enable = 1, .wr_enable = 0}
        },
        .clk_inefficiency_factor = 105,
        .bw_inefficiency_factor = 120,
};

static const struct dpu_mdss_version sm6115_mdss_ver = {
        .core_major_ver = 6,
        .core_minor_ver = 3,
};

const struct dpu_mdss_cfg dpu_sm6115_cfg = {
        .mdss_ver = &sm6115_mdss_ver,
        .caps = &sm6115_dpu_caps,
        .mdp = &sm6115_mdp,
        .ctl_count = ARRAY_SIZE(sm6115_ctl),
        .ctl = sm6115_ctl,
        .sspp_count = ARRAY_SIZE(sm6115_sspp),
        .sspp = sm6115_sspp,
        .mixer_count = ARRAY_SIZE(sm6115_lm),
        .mixer = sm6115_lm,
        .dspp_count = ARRAY_SIZE(sm6115_dspp),
        .dspp = sm6115_dspp,
        .pingpong_count = ARRAY_SIZE(sm6115_pp),
        .pingpong = sm6115_pp,
        .intf_count = ARRAY_SIZE(sm6115_intf),
        .intf = sm6115_intf,
        .vbif = &sdm845_vbif,
        .perf = &sm6115_perf_data,
};

#endif