clk_sel
uint64_t clk_sel:2;
uint64_t clk_sel:2;
uint64_t clk_sel:2;
uint64_t clk_sel:2;
uint64_t clk_sel:2;
uint64_t clk_sel:2;
enum clk_sel sel;
u32 clk_sel;
data->clk_sel = readl(data->reg + CLK_SEL);
writel(data->clk_sel, data->reg + CLK_SEL);
u32 clkcfg, clk_sel, curclk, ffiv, ffrac;
clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg);
switch (clk_sel) {
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
s8 clk_sel;
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
clk_sel = 0;
clk_sel = 1;
mux = &mmux->mux[clk_sel];
return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];
s8 clk_sel = mmux->parent2sel[index];
if (index == 0 || clk_sel == -1) {
if (clk_sel)
cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel);
cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);
mux = &mmux->mux[clk_sel];
.clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
struct cv1800_clk_regbit clk_sel;
iowrite8(clk_cfg->clk_sel[i] | tmp,
unsigned int *clk_sel;
.clk_sel = npcm750_CLK_SEL,
.clk_sel = npcm845_CLK_SEL,
uint32_t clk_sel = 0;
REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
intel_de_rmw(display, reg, clk_sel_mask, clk_sel);
ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
if (IS_ERR(imx_ldb->clk_sel[i])) {
ret = PTR_ERR(imx_ldb->clk_sel[i]);
imx_ldb->clk_sel[i] = NULL;
imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
struct clk *clk_sel[4]; /* parent of display clock */
unsigned int clk_sel)
st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel);
u32 clk_sel;
clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl);
return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT;
unsigned int power_mode, clk_sel;
clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT_OUT;
clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4;
clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT;
clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_CLK_SEL, clk_sel);
unsigned int clk_sel)
st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
u32 clk_sel;
clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
ret = priv->cfg->clk_sel(pdev, priv);
.clk_sel = stm32f4_adc_clk_sel,
.clk_sel = stm32h7_adc_clk_sel,
.clk_sel = stm32h7_adc_clk_sel,
.clk_sel = stm32h7_adc_clk_sel,
enum clk_sel clk_sel;
adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
switch (adc_feature->clk_sel) {
switch (adc_feature->clk_sel) {
unsigned int clk_sel;
unsigned int clk_sel, clk_len, best_clk = 0;
for (clk_sel = 1; clk_sel < clk_len; clk_sel++) {
u64 numerator = period * clk_rate_arr[clk_sel];
clk_rate_arr[clk_sel]);
best_clk = clk_sel;
chan->clk_sel = best_clk;
clk_rate = lpg_clk_rates_hi_res[chan->clk_sel];
clk_rate = lpg_clk_rates[chan->clk_sel];
val = chan->clk_sel;
u32 m_div, clk_sel;
clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
m_div = ((clk_sel * mclk) / intp->quartz) - 1;
u32 reg, div, clk_sel;
clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
div = ((clk_sel * mclk) / config->xtal) - 1;
u32 val, clk_sel;
clk_sel = hw->link_speed != SPEED_UNKNOWN ?
clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
u32 val, clk_sel;
clk_sel = hw->link_speed != SPEED_UNKNOWN ?
clk_sel << ALX_MDIO_CLK_SEL_SHIFT;
clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel)
FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
u16 clk_sel = MDIO_CTRL_CLK_25_4;
clk_sel = MDIO_CTRL_CLK_25_128;
FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
atl1c_start_phy_polling(hw, clk_sel);
u16 clk_sel = MDIO_CTRL_CLK_25_4;
clk_sel = MDIO_CTRL_CLK_25_128;
FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
atl1c_start_phy_polling(hw, clk_sel);
void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed);
spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) |
val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
unsigned long clk_sel, val;
clk_sel = ETHER_CLK_SEL_FREQ_SEL_125M;
clk_sel = ETHER_CLK_SEL_FREQ_SEL_25M;
clk_sel = ETHER_CLK_SEL_FREQ_SEL_2P5M;
val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
clk_sel = ETHER_CLK_SEL_DIV_SEL_2;
clk_sel = ETHER_CLK_SEL_DIV_SEL_20;
u32 clk_sel, m_clk_cfg, idx, div;
clk_sel = idx & CLK_SEL_MSK;
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
u32 clk_rate, clk_sel, div;
clk_sel = (div / 2) - 1;
pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel);
static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel)
if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
ucon |= clk_sel << info->clksel_shift;
if (ourport->cfg->clk_sel &&
!(ourport->cfg->clk_sel & (1 << cnt)))
u8 clk_sel = 0;
quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
s3c24xx_serial_setsource(port, clk_sel);
u8 clk_sel, clk_num;
clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
if (!(clk_sel & (1 << clk_num)))
u8 clk_sel;
clk_sel = s3c24xx_serial_getsource(port);
sprintf(clk_name, "clk_uart_baud%d", clk_sel);
par->clk_sel = i;
__raw_writel((par->clk_sel << 6) | (func << 4) | 1,
int clk_sel;
unsigned int clk_sel;
u64 clk_sel:3;
struct regmap_field *clk_sel;
player->clk_sel = regmap_field_alloc(regmap, regfield[0]);
if (player->clk_sel) {
ret = regmap_field_write(player->clk_sel, 1);
if (player->clk_sel) {
ret = regmap_field_write(player->clk_sel, 1);