clk_gate
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
return clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, true);
(void)clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, false);
struct clk_gate *gate = NULL;
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate;
static inline u32 clk_gate_readl(struct clk_gate *gate)
static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
struct clk_gate *gate = NULL;
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags,
struct clk_gate *gate;
struct clk_gate *gate = NULL;
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = NULL;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = NULL;
struct clk_gate *gate = NULL;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
struct clk_gate *gate = NULL;
struct clk_gate *gate = NULL;
struct clk_gate sysclk_gate;
struct clk_gate sspa0_gate;
struct clk_gate sspa1_gate;
struct clk_gate gate_##_name = { \
struct clk_gate *gate;
struct clk_gate *gate =
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate gate;
struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
struct regmap *sysc = clk_gate->priv->sysc;
clk_gate->bit_idx, clk_gate->bit_idx);
struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
struct regmap *sysc = clk_gate->priv->sysc;
regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
struct regmap *sysc = clk_gate->priv->sysc;
return val & clk_gate->bit_idx;
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate = NULL;
struct clk_gate gate;
struct clk_gate *gate = NULL;
struct clk_gate *gate = NULL;
struct clk_gate *gate = NULL;
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
u32 clk_gate[2];
rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
clk_gate[0] = 0;
if (clk_gate[0]) {
socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];
socfpga_clk->hw.bit_idx = clk_gate[1];
u32 clk_gate[2];
rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
clk_gate[0] = 0;
if (clk_gate[0]) {
socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
socfpga_clk->hw.bit_idx = clk_gate[1];
struct clk_gate hw;
struct clk_gate hw;
struct clk_gate hw;
struct clk_gate *config = to_clk_gate(sync_hw);
struct clk_gate pgate;
struct clk_gate fgate;
struct clk_gate sync;
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
struct clk_gate *gate;
struct clk_gate gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate *gate;
gate = kzalloc_obj(struct clk_gate);
struct clk_gate *gate;
struct clk_gate *gate;
gate = kzalloc_obj(struct clk_gate);
struct clk_gate *gate;
struct clk_gate *gate;
gate = kzalloc_obj(struct clk_gate);
struct clk_gate *gate = NULL;
gate = kzalloc_obj(struct clk_gate);
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate;
struct clk_gate *gate = NULL;
struct clk_gate gate;
struct clk_gate gate;
struct clk_gate clk_gate;
priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
priv->clk_gate.hw.init = &init;
priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
struct hantro_reg clk_gate;
.clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
struct clk_gate mod_clk_en;
struct clk_gate tx_clk_en;
struct clk_gate rx_clk_en;
struct clk_gate sd_clk_en;
ret = clk_prepare_enable(gphy_fw->clk_gate);
gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
if (IS_ERR(gphy_fw->clk_gate)) {
return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
clk_disable_unprepare(gphy_fw->clk_gate);
struct clk *clk_gate;
struct clk_gate rgmii_tx_en;
struct clk_gate gate;
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)