#include <sys/errno.h>
#include <sys/types.h>
#include <sys/param.h>
#include <sys/cpu.h>
#include <sys/cpuvar.h>
#include <sys/clock.h>
#include <sys/promif.h>
#include <sys/promimpl.h>
#include <sys/systm.h>
#include <sys/machsystm.h>
#include <sys/debug.h>
#include <sys/sunddi.h>
#include <sys/modctl.h>
#include <sys/spitregs.h>
#include <sys/cheetahregs.h>
#include <sys/cpu_module.h>
#include <sys/kobj.h>
#include <sys/cmp.h>
#include <sys/async.h>
#include <vm/page.h>
typedef enum { XDRBOOL, XDRINT, XDRSTRING } xdrs;
struct getprop_info {
char *name;
xdrs type;
uint_t *var;
};
struct convert_info {
char *name;
uint_t var;
char *realname;
};
struct node_info {
char *name;
int size;
struct getprop_info *prop;
struct getprop_info *prop_end;
unsigned int *value;
};
#define NEXT prom_nextnode
#define CHILD prom_childnode
#define GETPROP prom_getprop
#define GETPROPLEN prom_getproplen
int debug_fillsysinfo = 0;
#define VPRINTF if (debug_fillsysinfo) prom_printf
int ncpunode;
struct cpu_node cpunodes[NCPU];
static void check_cpus_ver(void);
static void check_cpus_set(void);
static void fill_address(pnode_t, char *);
void fill_cpu(pnode_t);
void fill_cpu_ddi(dev_info_t *);
void empty_cpu(int);
void plat_fill_mc(pnode_t);
#pragma weak plat_fill_mc
uint64_t system_clock_freq;
caddr_t v_auxio_addr = NULL;
caddr_t v_eeprom_addr = NULL;
caddr_t v_timecheck_addr = NULL;
caddr_t v_rtc_addr_reg = NULL;
volatile unsigned char *v_rtc_data_reg = NULL;
volatile uint8_t *v_pmc_addr_reg = NULL;
volatile uint8_t *v_pmc_data_reg = NULL;
int niobus = 0;
uint_t niommu_tsbs = 0;
#define CHOSEN_EEPROM "eeprom"
#define WATCHDOG_ENABLE "watchdog-enable"
static pnode_t chosen_eeprom;
char *tod_module_name;
int cpr_supported_override;
int cpr_platform_enable = 0;
static void have_sbus(pnode_t);
static void have_pci(pnode_t);
static void have_eeprom(pnode_t);
static void have_auxio(pnode_t);
static void have_rtc(pnode_t);
static void have_tod(pnode_t);
static void have_pmc(pnode_t);
static struct wkdevice {
char *wk_namep;
void (*wk_func)(pnode_t);
caddr_t *wk_vaddrp;
ushort_t wk_flags;
#define V_OPTIONAL 0x0000
#define V_MUSTHAVE 0x0001
#define V_MAPPED 0x0002
#define V_MULTI 0x0003
} wkdevice[] = {
{ "sbus", have_sbus, NULL, V_MULTI },
{ "pci", have_pci, NULL, V_MULTI },
{ "eeprom", have_eeprom, NULL, V_MULTI },
{ "auxio", have_auxio, NULL, V_OPTIONAL },
{ "rtc", have_rtc, NULL, V_OPTIONAL },
{ "pmc", have_pmc, NULL, V_OPTIONAL },
{ 0, },
};
static void map_wellknown(pnode_t);
void
map_wellknown_devices()
{
struct wkdevice *wkp;
phandle_t ieeprom;
pnode_t root;
uint_t stick_freq;
if (GETPROPLEN(prom_chosennode(), CHOSEN_EEPROM) ==
sizeof (phandle_t) &&
GETPROP(prom_chosennode(), CHOSEN_EEPROM, (caddr_t)&ieeprom) != -1)
chosen_eeprom = (pnode_t)prom_decode_int(ieeprom);
root = prom_nextnode((pnode_t)0);
if (GETPROP(root, "stick-frequency", (caddr_t)&stick_freq) != -1)
system_clock_freq = stick_freq;
map_wellknown(NEXT((pnode_t)0));
for (wkp = wkdevice; wkp->wk_namep; ++wkp) {
if (wkp->wk_flags == V_MUSTHAVE) {
cmn_err(CE_PANIC, "map_wellknown_devices: required "
"device %s not mapped", wkp->wk_namep);
}
}
if (niobus == 0)
cmn_err(CE_PANIC, "map_wellknown_devices: no i/o bus node");
check_cpus_ver();
check_cpus_set();
}
static void
map_wellknown(pnode_t curnode)
{
extern int status_okay(int, char *, int);
char tmp_name[MAXSYSNAME];
int sok;
#ifdef VPRINTF
VPRINTF("map_wellknown(%x)\n", curnode);
#endif
for (curnode = CHILD(curnode); curnode; curnode = NEXT(curnode)) {
sok = status_okay((int)curnode, (char *)NULL, 0);
if (!sok) {
char devtype_buf[OBP_MAXPROPNAME];
int size;
#ifdef VPRINTF
VPRINTF("map_wellknown: !okay status property\n");
#endif
if ((size = GETPROPLEN(curnode,
OBP_DEVICETYPE)) == -1)
continue;
if (size > OBP_MAXPROPNAME) {
cmn_err(CE_CONT, "node %x '%s' prop too "
"big\n", curnode, OBP_DEVICETYPE);
continue;
}
if (GETPROP(curnode, OBP_DEVICETYPE,
devtype_buf) == -1) {
cmn_err(CE_CONT, "node %x '%s' get failed\n",
curnode, OBP_DEVICETYPE);
continue;
}
if (strcmp(devtype_buf, "memory-controller") != 0)
continue;
}
bzero(tmp_name, MAXSYSNAME);
if (GETPROP(curnode, OBP_NAME, (caddr_t)tmp_name) != -1)
fill_address(curnode, tmp_name);
if (GETPROP(curnode, OBP_DEVICETYPE, tmp_name) != -1 &&
strcmp(tmp_name, "cpu") == 0) {
fill_cpu(curnode);
}
if (strcmp(tmp_name, "tod") == 0)
have_tod(curnode);
if (sok && (strcmp(tmp_name, "memory-controller") == 0) &&
(&plat_fill_mc != NULL))
plat_fill_mc(curnode);
map_wellknown(curnode);
}
}
static void
fill_address(pnode_t curnode, char *namep)
{
struct wkdevice *wkp;
int size;
uint32_t vaddr;
for (wkp = wkdevice; wkp->wk_namep; ++wkp) {
if (strcmp(wkp->wk_namep, namep) != 0)
continue;
if (wkp->wk_flags == V_MAPPED)
return;
if (wkp->wk_vaddrp != NULL) {
if ((size = GETPROPLEN(curnode, OBP_ADDRESS)) == -1) {
cmn_err(CE_CONT, "device %s size %d\n",
namep, size);
continue;
}
if (size != sizeof (vaddr)) {
cmn_err(CE_CONT, "device %s address prop too "
"big\n", namep);
continue;
}
if (GETPROP(curnode, OBP_ADDRESS,
(caddr_t)&vaddr) == -1) {
cmn_err(CE_CONT, "device %s not mapped\n",
namep);
continue;
}
*wkp->wk_vaddrp = (caddr_t)(uintptr_t)vaddr;
#ifdef VPRINTF
VPRINTF("fill_address: %s mapped to %p\n", namep,
(void *)*wkp->wk_vaddrp);
#endif
}
if (wkp->wk_func != NULL)
(*wkp->wk_func)(curnode);
if (wkp->wk_flags != V_MULTI)
wkp->wk_flags = V_MAPPED;
}
}
int
get_portid(pnode_t node, pnode_t *cmpp)
{
int portid;
int i;
char dev_type[OBP_MAXPROPNAME];
pnode_t cpu_parent;
if (cmpp != NULL)
*cmpp = OBP_NONODE;
if (GETPROP(node, "portid", (caddr_t)&portid) != -1)
return (portid);
if (GETPROP(node, "upa-portid", (caddr_t)&portid) != -1)
return (portid);
if (GETPROP(node, "device_type", (caddr_t)&dev_type) == -1)
return (-1);
if (strcmp(dev_type, "cpu") == 0) {
cpu_parent = node = prom_parentnode(node);
for (i = 0; i < 2; i++) {
if (node == OBP_NONODE || node == OBP_BADNODE)
break;
if (GETPROP(node, "portid", (caddr_t)&portid) != -1) {
if (cmpp != NULL)
*cmpp = cpu_parent;
return (portid);
}
node = prom_parentnode(node);
}
}
return (-1);
}
static void
adj_ecache_setsize(int ecsetsize)
{
if (ecsetsize > ecache_setsize)
ecache_setsize = ecsetsize;
switch (cpu_setsize) {
case -1:
break;
case 0:
cpu_setsize = ecsetsize;
break;
default:
if (cpu_setsize != ecsetsize) {
if (do_pg_coloring)
cpu_page_colors = -1;
cpu_setsize = -1;
}
break;
}
}
void
fill_cpu(pnode_t node)
{
extern int cpu_get_cpu_unum(int, char *, int, int *);
struct cpu_node *cpunode;
processorid_t cpuid;
int portid;
int tlbsize;
int size;
uint_t clk_freq;
pnode_t cmpnode;
char namebuf[OBP_MAXPROPNAME], unum[UNUM_NAMLEN];
char *namebufp;
int proplen;
if ((portid = get_portid(node, &cmpnode)) == -1) {
cmn_err(CE_PANIC, "portid not found");
}
if (GETPROP(node, "cpuid", (caddr_t)&cpuid) == -1) {
cpuid = portid;
}
if (cpuid < 0 || cpuid >= NCPU) {
cmn_err(CE_PANIC, "cpu node %x: cpuid %d out of range", node,
cpuid);
return;
}
cpunode = &cpunodes[cpuid];
cpunode->portid = portid;
cpunode->nodeid = node;
if (cpu_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, &size) != 0) {
cpunode->fru_fmri[0] = '\0';
} else {
(void) snprintf(cpunode->fru_fmri, sizeof (cpunode->fru_fmri),
"%s%s", CPU_FRU_FMRI, unum);
}
if (cmpnode) {
if ((GETPROP(cmpnode, "device_type", namebuf) > 0) &&
(strcmp(namebuf, "core") == 0)) {
node = cmpnode;
}
}
(void) GETPROP(node, (cmpnode ? "compatible" : "name"), namebuf);
proplen = GETPROPLEN(node, (cmpnode ? "compatible" : "name"));
ASSERT(proplen > 0 && proplen <= OBP_MAXPROPNAME);
if (proplen >= OBP_MAXPROPNAME)
proplen = OBP_MAXPROPNAME - 1;
namebuf[proplen] = '\0';
namebufp = namebuf;
if (strncmp(namebufp, "SUNW,", 5) == 0)
namebufp += 5;
else if (strncmp(namebufp, "FJSV,", 5) == 0)
namebufp += 5;
(void) strcpy(cpunode->name, namebufp);
(void) GETPROP(node, "implementation#",
(caddr_t)&cpunode->implementation);
(void) GETPROP(node, "mask#", (caddr_t)&cpunode->version);
if (IS_CHEETAH(cpunode->implementation)) {
cpunode->version = REMAP_CHEETAH_MASK(cpunode->version);
}
if (GETPROP(node, "clock-frequency", (caddr_t)&clk_freq) == -1) {
pnode_t root = prom_nextnode((pnode_t)0);
if (GETPROP(root, "clock-frequency", (caddr_t)&clk_freq) == -1)
clk_freq = 0;
}
cpunode->clock_freq = clk_freq;
ASSERT(cpunode->clock_freq != 0);
cpunode->tick_nsec_scale = (uint_t)(((uint64_t)NANOSEC <<
(32 - TICK_NSEC_SHIFT)) / cpunode->clock_freq);
(void) GETPROP(node, "#itlb-entries", (caddr_t)&tlbsize);
ASSERT(tlbsize < USHRT_MAX);
cpunode->itlb_size = (ushort_t)tlbsize;
(void) GETPROP(node, "#dtlb-entries", (caddr_t)&tlbsize);
ASSERT(tlbsize < USHRT_MAX);
cpunode->dtlb_size = (ushort_t)tlbsize;
if (cmpnode != OBP_NONODE) {
size = 0;
(void) GETPROP(node, "l3-cache-size", (caddr_t)&size);
if (size <= 0)
(void) GETPROP(node, "l2-cache-size", (caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_size = size;
size = 0;
(void) GETPROP(node, "l3-cache-line-size", (caddr_t)&size);
if (size <= 0)
(void) GETPROP(node, "l2-cache-line-size",
(caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_linesize = size;
size = 0;
(void) GETPROP(node, "l2-cache-associativity", (caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_associativity = size;
cmp_add_cpu(portid, cpuid);
} else {
size = 0;
(void) GETPROP(node, "ecache-size", (caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_size = size;
size = 0;
(void) GETPROP(node, "ecache-line-size", (caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_linesize = size;
size = 0;
(void) GETPROP(node, "ecache-associativity", (caddr_t)&size);
ASSERT(size != 0);
cpunode->ecache_associativity = size;
}
cpunode->msram = ECACHE_CPU_NON_MIRROR;
if (GETPROPLEN(node, "msram") != -1) {
cpunode->msram = ECACHE_CPU_MIRROR;
}
if (GETPROPLEN(node, "msram-observed") != -1) {
cpunode->msram = ECACHE_CPU_MIRROR;
}
if (ncpunode == 0) {
cpu_fiximp(node);
}
cpunode->ecache_setsize =
cpunode->ecache_size / cpunode->ecache_associativity;
adj_ecache_setsize(cpunode->ecache_setsize);
ncpunode++;
}
int
get_portid_ddi(dev_info_t *dip, dev_info_t **cmpp)
{
int portid;
int i;
char dev_type[OBP_MAXPROPNAME];
int len = OBP_MAXPROPNAME;
dev_info_t *cpu_parent;
if (cmpp != NULL)
*cmpp = NULL;
if ((portid = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "portid", -1)) != -1)
return (portid);
if ((portid = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "upa-portid", -1)) != -1)
return (portid);
if (ddi_prop_op(DDI_DEV_T_ANY, dip, PROP_LEN_AND_VAL_BUF,
DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
&len) != 0)
return (-1);
if (strcmp(dev_type, "cpu") == 0) {
cpu_parent = dip = ddi_get_parent(dip);
for (i = 0; dip != NULL && i < 2; i++) {
if ((portid = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "portid", -1)) != -1) {
if (cmpp != NULL)
*cmpp = cpu_parent;
return (portid);
}
dip = ddi_get_parent(dip);
}
}
return (-1);
}
void
fill_cpu_ddi(dev_info_t *dip)
{
extern int cpu_get_cpu_unum(int, char *, int, int *);
struct cpu_node *cpunode;
processorid_t cpuid;
int portid;
int len = OBP_MAXPROPNAME;
int tlbsize;
dev_info_t *cmpnode;
char namebuf[OBP_MAXPROPNAME], unum[UNUM_NAMLEN];
char *namebufp;
char dev_type[OBP_MAXPROPNAME];
if ((portid = get_portid_ddi(dip, &cmpnode)) == -1) {
cmn_err(CE_PANIC, "portid not found");
}
if ((cpuid = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "cpuid", -1)) == -1) {
cpuid = portid;
}
if (cpuid < 0 || cpuid >= NCPU) {
cmn_err(CE_PANIC, "cpu dip %p: cpuid %d out of range",
(void *)dip, cpuid);
return;
}
cpunode = &cpunodes[cpuid];
cpunode->portid = portid;
cpunode->nodeid = ddi_get_nodeid(dip);
if (cmpnode != NULL) {
if ((ddi_prop_op(DDI_DEV_T_ANY, cmpnode, PROP_LEN_AND_VAL_BUF,
DDI_PROP_DONTPASS, "device_type",
(caddr_t)dev_type, &len) == DDI_PROP_SUCCESS) &&
(strcmp(dev_type, "core") == 0))
dip = cmpnode;
}
if (cpu_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, &len) != 0) {
cpunode->fru_fmri[0] = '\0';
} else {
(void) snprintf(cpunode->fru_fmri, sizeof (cpunode->fru_fmri),
"%s%s", CPU_FRU_FMRI, unum);
}
len = sizeof (namebuf);
(void) ddi_prop_op(DDI_DEV_T_ANY, dip, PROP_LEN_AND_VAL_BUF,
DDI_PROP_DONTPASS, (cmpnode ? "compatible" : "name"),
(caddr_t)namebuf, &len);
namebufp = namebuf;
if (strncmp(namebufp, "SUNW,", 5) == 0)
namebufp += 5;
else if (strncmp(namebufp, "FJSV,", 5) == 0)
namebufp += 5;
(void) strcpy(cpunode->name, namebufp);
cpunode->implementation = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "implementation#", 0);
cpunode->version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "mask#", 0);
if (IS_CHEETAH(cpunode->implementation)) {
cpunode->version = REMAP_CHEETAH_MASK(cpunode->version);
}
cpunode->clock_freq = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "clock-frequency", 0);
ASSERT(cpunode->clock_freq != 0);
cpunode->tick_nsec_scale = (uint_t)(((uint64_t)NANOSEC <<
(32 - TICK_NSEC_SHIFT)) / cpunode->clock_freq);
tlbsize = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "#itlb-entries", 0);
ASSERT(tlbsize < USHRT_MAX);
cpunode->itlb_size = (ushort_t)tlbsize;
tlbsize = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "#dtlb-entries", 0);
ASSERT(tlbsize < USHRT_MAX);
cpunode->dtlb_size = (ushort_t)tlbsize;
if (cmpnode != NULL) {
cpunode->ecache_size = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "l3-cache-size", 0);
if (cpunode->ecache_size == 0)
cpunode->ecache_size = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "l2-cache-size", 0);
ASSERT(cpunode->ecache_size != 0);
cpunode->ecache_linesize = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "l3-cache-line-size", 0);
if (cpunode->ecache_linesize == 0)
cpunode->ecache_linesize =
ddi_prop_get_int(DDI_DEV_T_ANY, dip,
DDI_PROP_DONTPASS, "l2-cache-line-size", 0);
ASSERT(cpunode->ecache_linesize != 0);
cpunode->ecache_associativity = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "l2-cache-associativity", 0);
ASSERT(cpunode->ecache_associativity != 0);
cmp_add_cpu(portid, cpuid);
} else {
cpunode->ecache_size = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "ecache-size", 0);
ASSERT(cpunode->ecache_size != 0);
cpunode->ecache_linesize = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "ecache-line-size", 0);
ASSERT(cpunode->ecache_linesize != 0);
cpunode->ecache_associativity = ddi_prop_get_int(DDI_DEV_T_ANY,
dip, DDI_PROP_DONTPASS, "ecache-associativity", 0);
ASSERT(cpunode->ecache_associativity != 0);
}
cpunode->msram = ECACHE_CPU_NON_MIRROR;
if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "msram")) {
cpunode->msram = ECACHE_CPU_MIRROR;
} else if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
"msram-observed")) {
cpunode->msram = ECACHE_CPU_MIRROR;
}
ASSERT(ncpunode > 0);
cpunode->ecache_setsize =
cpunode->ecache_size / cpunode->ecache_associativity;
adj_ecache_setsize(cpunode->ecache_setsize);
ncpunode++;
}
void
empty_cpu(int cpuid)
{
bzero(&cpunodes[cpuid], sizeof (struct cpu_node));
ncpunode--;
}
#ifdef SF_ERRATA_30
int spitfire_call_bug = 0;
#endif
#ifdef SF_V9_TABLE_28
int spitfire_bb_fsr_bug = 0;
#endif
#ifdef JALAPENO_ERRATA_85
int jp_errata_85_allow_slow_scrub = 1;
int jp_errata_85_enable = 0;
#endif
static void
check_cpus_ver(void)
{
int i;
int impl, cpuid = getprocessorid();
int min_supported_rev;
ASSERT(cpunodes[cpuid].nodeid != 0);
impl = cpunodes[cpuid].implementation;
switch (impl) {
default:
min_supported_rev = 0;
break;
case SPITFIRE_IMPL:
min_supported_rev = SPITFIRE_MINREV_SUPPORTED;
break;
case CHEETAH_IMPL:
min_supported_rev = CHEETAH_MINREV_SUPPORTED;
break;
}
for (i = 0; i < NCPU; i++) {
if (cpunodes[i].nodeid == 0)
continue;
if (IS_SPITFIRE(impl)) {
if (cpunodes[i].version < min_supported_rev) {
cmn_err(CE_PANIC, "UltraSPARC versions older "
"than %d.%d are no longer supported "
"(cpu #%d)",
SPITFIRE_MAJOR_VERSION(min_supported_rev),
SPITFIRE_MINOR_VERSION(min_supported_rev),
i);
}
if (cpunodes[i].version < 0x22) {
cmn_err(CE_WARN,
"UltraSPARC versions older than "
"2.2 are not supported (cpu #%d)", i);
#ifdef SF_ERRATA_30
spitfire_call_bug = 1;
#endif
}
}
#ifdef SF_V9_TABLE_28
if (IS_SPITFIRE(impl) || IS_BLACKBIRD(impl))
spitfire_bb_fsr_bug = 1;
#endif
if (IS_CHEETAH(impl)) {
if (cpunodes[i].version < min_supported_rev) {
cmn_err(CE_PANIC, "UltraSPARC-III versions "
"older than %d.%d are no longer supported "
"(cpu #%d)",
CHEETAH_MAJOR_VERSION(min_supported_rev),
CHEETAH_MINOR_VERSION(min_supported_rev),
i);
}
}
#ifdef JALAPENO_ERRATA_85
if (IS_JALAPENO(impl) && (cpunodes[i].version < 0x24)) {
jp_errata_85_allow_slow_scrub = 0;
jp_errata_85_enable = 1;
}
#endif
}
}
static void
check_cpus_set(void)
{
int i;
int impl;
int npanther = 0;
int njupiter = 0;
impl = cpunodes[getprocessorid()].implementation;
switch (impl) {
case CHEETAH_PLUS_IMPL:
case JAGUAR_IMPL:
case PANTHER_IMPL:
for (i = 0; i < NCPU; i++) {
if (cpunodes[i].nodeid == 0)
continue;
if (IS_PANTHER(cpunodes[i].implementation)) {
npanther += 1;
}
if (!(IS_CHEETAH_PLUS(cpunodes[i].implementation) ||
IS_JAGUAR(cpunodes[i].implementation) ||
IS_PANTHER(cpunodes[i].implementation))) {
use_mp = 0;
break;
}
}
break;
case OLYMPUS_C_IMPL:
case JUPITER_IMPL:
for (i = 0; i < NCPU; i++) {
if (cpunodes[i].nodeid == 0)
continue;
if (IS_JUPITER(cpunodes[i].implementation)) {
njupiter += 1;
}
if (!(IS_OLYMPUS_C(cpunodes[i].implementation) ||
IS_JUPITER(cpunodes[i].implementation))) {
use_mp = 0;
break;
}
}
break;
default:
for (i = 0; i < NCPU; i++) {
if (cpunodes[i].nodeid == 0)
continue;
if (cpunodes[i].implementation != impl) {
use_mp = 0;
break;
}
}
break;
}
if (&mmu_init_mmu_page_sizes) {
(void) mmu_init_mmu_page_sizes(npanther);
}
if ((npanther == ncpunode) && (&cpu_fix_allpanther)) {
cpu_fix_allpanther();
}
if ((njupiter == ncpunode) && (&cpu_fix_alljupiter)) {
cpu_fix_alljupiter();
}
if (use_mp) {
int (*set_max_ncpus)(void);
set_max_ncpus = (int (*)(void))
kobj_getsymvalue("set_platform_max_ncpus", 0);
if (set_max_ncpus) {
max_ncpus = set_max_ncpus();
if (max_ncpus < ncpunode)
max_ncpus = ncpunode;
boot_ncpus = boot_max_ncpus = ncpunode;
} else {
max_ncpus = ncpunode;
boot_ncpus = ncpunode;
}
} else {
cmn_err(CE_NOTE, "MP not supported on mismatched modules,"
" booting UP only");
for (i = 0; i < NCPU; i++) {
if (cpunodes[i].nodeid == 0)
continue;
cmn_err(CE_NOTE, "cpu%d: %s version 0x%x", i,
cpunodes[i].name, cpunodes[i].version);
}
max_ncpus = 1;
boot_ncpus = 1;
}
}
static void
have_sbus(pnode_t node)
{
int size;
uint_t portid;
size = GETPROPLEN(node, "upa-portid");
if (size == -1 || size > sizeof (portid))
cmn_err(CE_PANIC, "upa-portid size");
if (GETPROP(node, "upa-portid", (caddr_t)&portid) == -1)
cmn_err(CE_PANIC, "upa-portid");
niobus++;
niommu_tsbs++;
}
#define IOMMU_PER_SCHIZO 2
static void
have_pci(pnode_t node)
{
int size;
uint_t portid;
char compatible[OBP_MAXDRVNAME];
size = GETPROPLEN(node, "portid");
if (size == -1) size = GETPROPLEN(node, "upa-portid");
if (size == -1)
return;
if (size > sizeof (portid))
cmn_err(CE_PANIC, "portid size wrong");
if (GETPROP(node, "portid", (caddr_t)&portid) == -1)
if (GETPROP(node, "upa-portid", (caddr_t)&portid) == -1)
cmn_err(CE_PANIC, "portid not found");
niobus++;
compatible[0] = '\0';
(void) prom_getprop(node, OBP_COMPATIBLE, compatible);
if (strcmp(compatible, "pci108e,8001") == 0)
niommu_tsbs += IOMMU_PER_SCHIZO;
else
niommu_tsbs++;
}
static void
have_eeprom(pnode_t node)
{
int size;
uint32_t eaddr;
if (tod_module_name == NULL) {
char buf[MAXSYSNAME];
if ((GETPROP(node, "model", buf) != -1) &&
(strcmp(buf, "mk48t59") == 0))
tod_module_name = "todmostek";
}
if (v_eeprom_addr && v_timecheck_addr != v_eeprom_addr)
return;
if ((size = GETPROPLEN(node, OBP_ADDRESS)) == -1)
return;
if (size != sizeof (eaddr))
cmn_err(CE_PANIC, "eeprom addr size");
if (GETPROP(node, OBP_ADDRESS, (caddr_t)&eaddr) == -1)
cmn_err(CE_PANIC, "eeprom addr");
if (chosen_eeprom != 0 && chosen_eeprom != node) {
v_timecheck_addr = (caddr_t)(uintptr_t)eaddr;
return;
}
v_eeprom_addr = (caddr_t)(uintptr_t)eaddr;
if (v_timecheck_addr == NULL)
v_timecheck_addr = v_eeprom_addr;
if (GETPROPLEN(node, WATCHDOG_ENABLE) != -1)
watchdog_available = 1;
}
static void
have_rtc(pnode_t node)
{
int size;
uint32_t eaddr;
if (tod_module_name == NULL) {
char buf[MAXSYSNAME];
if (GETPROP(node, "model", buf) != -1) {
if ((strcmp(buf, "m5819p") == 0) ||
(strcmp(buf, "m5823") == 0))
tod_module_name = "todm5823";
else if (strcmp(buf, "ds1287") == 0)
tod_module_name = "todds1287";
}
}
if ((size = GETPROPLEN(node, OBP_ADDRESS)) == -1)
return;
if (size != sizeof (eaddr))
cmn_err(CE_PANIC, "rtc addr size");
if (GETPROP(node, OBP_ADDRESS, (caddr_t)&eaddr) == -1)
cmn_err(CE_PANIC, "rtc addr");
v_rtc_addr_reg = (caddr_t)(uintptr_t)eaddr;
v_rtc_data_reg = (volatile unsigned char *)(uintptr_t)eaddr + 1;
if (GETPROPLEN(node, WATCHDOG_ENABLE) != -1)
watchdog_available = 1;
}
static void
have_pmc(pnode_t node)
{
uint32_t vaddr;
pnode_t root;
root = prom_nextnode((pnode_t)0);
if (GETPROPLEN(root, WATCHDOG_ENABLE) != -1) {
if (GETPROP(node, OBP_ADDRESS, (caddr_t)&vaddr) == -1) {
watchdog_available = 0;
return;
}
v_pmc_addr_reg = (volatile uint8_t *)(uintptr_t)vaddr;
v_pmc_data_reg = (volatile uint8_t *)(uintptr_t)vaddr + 1;
watchdog_available = 1;
}
}
static void
have_auxio(pnode_t node)
{
size_t size, n;
uint32_t addr[5];
if ((size = GETPROPLEN(node, OBP_ADDRESS)) == -1)
cmn_err(CE_PANIC, "no auxio address property");
switch (n = (size / sizeof (addr[0]))) {
case 1:
break;
case 5:
break;
default:
cmn_err(CE_PANIC, "auxio addr has %lu entries?", n);
}
if (GETPROP(node, OBP_ADDRESS, (caddr_t)addr) == -1)
cmn_err(CE_PANIC, "auxio addr");
v_auxio_addr = (caddr_t)(uintptr_t)(addr[0]);
}
static void
have_tod(pnode_t node)
{
static char tod_name[MAXSYSNAME];
if (GETPROP(node, OBP_NAME, (caddr_t)tod_name) == -1)
cmn_err(CE_PANIC, "tod name");
tod_module_name = tod_name;
}