#ifndef __shmem_h__
#define __shmem_h__

#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
        #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
#endif

#define FUNC_0              0
#define FUNC_1              1
#define FUNC_2              2
#define FUNC_3              3
#define FUNC_4              4
#define FUNC_5              5
#define FUNC_6              6
#define FUNC_7              7
#define E1_FUNC_MAX         2
#define E1H_FUNC_MAX            8
#define E2_FUNC_MAX         4   /* per path */

#define VN_0                0
#define VN_1                1
#define VN_2                2
#define VN_3                3
#define E1VN_MAX            1
#define E1HVN_MAX           4

#define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
/* This value (in milliseconds) determines the frequency of the driver
 * issuing the PULSE message code.  The firmware monitors this periodic
 * pulse to determine when to switch to an OS-absent mode. */
#define DRV_PULSE_PERIOD_MS     250

/* This value (in milliseconds) determines how long the driver should
 * wait for an acknowledgement from the firmware before timing out.  Once
 * the firmware has timed out, the driver will assume there is no firmware
 * running and there won't be any firmware-driver synchronization during a
 * driver reset. */
#define FW_ACK_TIME_OUT_MS      5000

#define FW_ACK_POLL_TIME_MS     1

#define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)

#define MFW_TRACE_SIGNATURE     0x54524342

/****************************************************************************
 * Driver <-> FW Mailbox                                                    *
 ****************************************************************************/
struct drv_port_mb {

        u32 link_status;
        /* Driver should update this field on any link change event */

        #define LINK_STATUS_NONE                                (0<<0)
        #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
        #define LINK_STATUS_LINK_UP                             0x00000001
        #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
        #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
        #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)

        #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
        #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020

        #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
        #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
        #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080

        #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
        #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
        #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
        #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
        #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
        #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
        #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000

        #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
        #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000

        #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
        #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000

        #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
        #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
        #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
        #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
        #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)

        #define LINK_STATUS_SERDES_LINK                         0x00100000

        #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
        #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
        #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
        #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000

        #define LINK_STATUS_PFC_ENABLED                         0x20000000

        #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
        #define LINK_STATUS_SFP_TX_FAULT                        0x80000000

        u32 port_stx;

        u32 stat_nig_timer;

        /* MCP firmware does not use this field */
        u32 ext_phy_fw_version;

};


struct drv_func_mb {

        u32 drv_mb_header;
        #define DRV_MSG_CODE_MASK                       0xffff0000
        #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
        #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
        #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
        #define DRV_MSG_CODE_DCC_OK                     0x30000000
        #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
        #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
        #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
        #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
        #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
        #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
        #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
        #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
        #define DRV_MSG_CODE_OEM_OK                     0x00010000
        #define DRV_MSG_CODE_OEM_FAILURE                0x00020000
        #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK         0x00030000
        #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE    0x00040000
        /*
         * The optic module verification command requires bootcode
         * v5.0.6 or later, te specific optic module verification command
         * requires bootcode v5.2.12 or later
         */
        #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
        #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
        #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
        #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
        #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
        #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
        #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
        #define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
        #define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
        #define REQ_BC_VER_4_FCOE_FEATURES              0x00070209

        #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
        #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
        #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401

        #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000

        #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
        #define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
        #define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
        #define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
        #define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000

        #define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
        #define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000

        #define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000

        #define DRV_MSG_CODE_RMMOD                      0xdb000000
        #define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f

        #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
        #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
        #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000

        #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000

        #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
        #define REQ_BC_VER_4_INITIATE_FLR               0x00070213

        #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
        #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
        #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
        #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000

        #define DRV_MSG_CODE_IMG_OFFSET_REQ             0xe2000000
        #define DRV_MSG_CODE_IMG_SIZE_REQ               0xe3000000

        #define DRV_MSG_CODE_UFP_CONFIG_ACK             0xe4000000

        #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff

        u32 drv_mb_param;
        #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
        #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000

        #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER        0x00000001
        #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002

        #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
        #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000

        #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ          0x00000001
        #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ       0x00000002
        #define DRV_MSG_CODE_VPD_IMAGE_REQ              0x00000003

        u32 fw_mb_header;
        #define FW_MSG_CODE_MASK                        0xffff0000
        #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
        #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
        #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
        /* Load common chip is supported from bc 6.0.0  */
        #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
        #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000

        #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
        #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
        #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
        #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
        #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
        #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
        #define FW_MSG_CODE_DCC_DONE                    0x30100000
        #define FW_MSG_CODE_LLDP_DONE                   0x40100000
        #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
        #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
        #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
        #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
        #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
        #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
        #define FW_MSG_CODE_NO_KEY                      0x80f00000
        #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
        #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
        #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
        #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
        #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
        #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
        #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
        #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
        #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
        #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
        #define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000

        #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
        #define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
        #define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
        #define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
        #define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000

        #define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
        #define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000

        #define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000

        #define FW_MSG_CODE_RMMOD_ACK                   0xdb100000

        #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
        #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000

        #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000

        #define FW_MSG_CODE_FLR_ACK                     0x02000000
        #define FW_MSG_CODE_FLR_NACK                    0x02100000

        #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
        #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
        #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
        #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000

        #define FW_MSG_CODE_IMG_OFFSET_RESPONSE         0xe2100000
        #define FW_MSG_CODE_IMG_SIZE_RESPONSE           0xe3100000

        #define FW_MSG_CODE_OEM_ACK                     0x00010000
        #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK        0x00020000

        #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff

        u32 fw_mb_param;

        #define FW_PARAM_INVALID_IMG                    0xffffffff

        u32 drv_pulse_mb;
        #define DRV_PULSE_SEQ_MASK                      0x00007fff
        #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
        /*
         * The system time is in the format of
         * (year-2001)*12*32 + month*32 + day.
         */
        #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
        /*
         * Indicate to the firmware not to go into the
         * OS-absent when it is not getting driver pulse.
         * This is used for debugging as well for PXE(MBA).
         */

        u32 mcp_pulse_mb;
        #define MCP_PULSE_SEQ_MASK                      0x00007fff
        #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
        /* Indicates to the driver not to assert due to lack
         * of MCP response */
        #define MCP_EVENT_MASK                          0xffff0000
        #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000

        u32 iscsi_boot_signature;
        u32 iscsi_boot_block_offset;

        u32 drv_status;
        #define DRV_STATUS_PMF                          0x00000001
        #define DRV_STATUS_VF_DISABLED                  0x00000002
        #define DRV_STATUS_SET_MF_BW                    0x00000004
        #define DRV_STATUS_LINK_EVENT                   0x00000008

        #define DRV_STATUS_OEM_EVENT_MASK               0x00000070
        #define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x00000010
        #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x00000020

        #define DRV_STATUS_OEM_UPDATE_SVID              0x00000080

        #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
        #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
        #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
        #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
        #define DRV_STATUS_DCC_RESERVED1                0x00000800
        #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
        #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000

        #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
        #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
        #define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
        #define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
        #define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
        #define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
        #define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000

        #define DRV_STATUS_DRV_INFO_REQ                 0x04000000

        #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000

        u32 virt_mac_upper;
        #define VIRT_MAC_SIGN_MASK                      0xffff0000
        #define VIRT_MAC_SIGNATURE                      0x564d0000
        u32 virt_mac_lower;

};


/****************************************************************************
 * Management firmware state                                                *
 ****************************************************************************/
/* Allocate 440 bytes for management firmware */
#define MGMTFW_STATE_WORD_SIZE                          110

struct mgmtfw_state {
        u32 opaque[MGMTFW_STATE_WORD_SIZE];
};


/****************************************************************************
 * Multi-Function configuration                                             *
 ****************************************************************************/
struct shared_mf_cfg {

        u32 clp_mb;
        #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
        /* set by CLP */
        #define SHARED_MF_CLP_EXIT                      0x00000001
        /* set by MCP */
        #define SHARED_MF_CLP_EXIT_DONE                 0x00010000

};

struct port_mf_cfg {

        u32 dynamic_cfg;    /* device control channel */
        #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
        #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
        #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK

        u32 reserved[1];

};

struct func_mf_cfg {

        u32 config;
        /* E/R/I/D */
        /* function 0 of each port cannot be hidden */
        #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001

        #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
        #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
        #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
        #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
        #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
        #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
                                FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA

        #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
        #define FUNC_MF_CFG_FUNC_DELETED                0x00000010

        #define FUNC_MF_CFG_FUNC_BOOT_MASK              0x00000060
        #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL         0x00000000
        #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED      0x00000020
        #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED       0x00000040

        /* PRI */
        /* 0 - low priority, 3 - high priority */
        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000

        /* MINBW, MAXBW */
        /* value range - 0..100, increments in 100Mbps */
        #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
        #define FUNC_MF_CFG_MIN_BW_SHIFT                16
        #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
        #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
        #define FUNC_MF_CFG_MAX_BW_SHIFT                24
        #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000

        u32 mac_upper;      /* MAC */
        #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
        #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
        #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
        u32 mac_lower;
        #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff

        u32 e1hov_tag;  /* VNI */
        #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
        #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
        #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK

        /* afex default VLAN ID - 12 bits */
        #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
        #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16

        u32 afex_config;
        #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
        #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
        #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
        #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16

        u32 pf_allocation;
        /* number of vfs in function, if 0 - sriov disabled */
        #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK                      0x000000FF
        #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT                     0
};

enum mf_cfg_afex_vlan_mode {
        FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
        FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
        FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
};

/* This structure is not applicable and should not be accessed on 57711 */
struct func_ext_cfg {
        u32 func_cfg;
        #define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
        #define MACP_FUNC_CFG_FLAGS_SHIFT               0
        #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
        #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
        #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
        #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
    #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080

        u32 iscsi_mac_addr_upper;
        u32 iscsi_mac_addr_lower;

        u32 fcoe_mac_addr_upper;
        u32 fcoe_mac_addr_lower;

        u32 fcoe_wwn_port_name_upper;
        u32 fcoe_wwn_port_name_lower;

        u32 fcoe_wwn_node_name_upper;
        u32 fcoe_wwn_node_name_lower;

        u32 preserve_data;
        #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
        #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
        #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
        #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
        #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
        #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
};

struct mf_cfg {

        struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
        struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
    /* 0x10*2=0x20 */
        /* for all chips, there are 8 mf functions */
        struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
        /*
         * Extended configuration per function  - this array does not exist and
         * should not be accessed on 57711
         */
        struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
}; /* 0x224 */

/****************************************************************************
 * Shared Memory Region                                                     *
 ****************************************************************************/
struct shmem_region {                  /*   SharedMem Offset (size) */

        u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
        #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
        #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
        /* validity bits */
        #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
        #define SHR_MEM_VALIDITY_MB                         0x00200000
        #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
        #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
        /* One licensing bit should be set */
        #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
        #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
        #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
        #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
        /* Active MFW */
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
        #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0

        struct shm_dev_info dev_info;        /* 0x8     (0x438) */

        license_key_t       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */

        /* FW information (for internal FW use) */
        u32         fw_info_fio_offset;         /* 0x4a8       (0x4) */
        struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */

        struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */


#ifdef BMAPI
        /* This is a variable length array */
        /* the number of function depends on the chip type */
        struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
#else
        /* the number of function depends on the chip type */
        struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
#endif /* BMAPI */

}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */

/****************************************************************************
 * Shared Memory 2 Region                                                   *
 ****************************************************************************/
/* The fw_flr_ack is actually built in the following way:                   */
/* 8 bit:  PF ack                                                           */
/* 64 bit: VF ack                                                           */
/* 8 bit:  ios_dis_ack                                                      */
/* In order to maintain endianity in the mailbox hsi, we want to keep using */
/* u32. The fw must have the VF right after the PF since this is how it     */
/* access arrays(it expects always the VF to reside after the PF, and that  */
/* makes the calculation much easier for it. )                              */
/* In order to answer both limitations, and keep the struct small, the code */
/* will abuse the structure defined here to achieve the actual partition    */
/* above                                                                    */
/****************************************************************************/
struct fw_flr_ack {
        u32         pf_ack;
        u32         vf_ack;
        u32         iov_dis_ack;
};

struct fw_flr_mb {
        u32         aggint;
        u32         opgen_addr;
        struct fw_flr_ack ack;
};

struct eee_remote_vals {
        u32         tx_tw;
        u32         rx_tw;
};

/**** SUPPORT FOR SHMEM ARRRAYS ***
 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
 * define arrays with storage types smaller then unsigned dwords.
 * The macros below add generic support for SHMEM arrays with numeric elements
 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
 * array with individual bit-filed elements accessed using shifts and masks.
 *
 */

/* eb is the bitwidth of a single element */
#define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
#define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))

/* the bit-position macro allows the used to flip the order of the arrays
 * elements on a per byte or word boundary.
 *
 * example: an array with 8 entries each 4 bit wide. This array will fit into
 * a single dword. The diagrmas below show the array order of the nibbles.
 *
 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
 *
 *                |                |                |               |
 *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
 *                |                |                |               |
 *
 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
 *
 *                |                |                |               |
 *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
 *                |                |                |               |
 *
 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
 *
 *                |                |                |               |
 *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
 *                |                |                |               |
 */
#define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
        ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
        (((i)%((fb)/(eb))) * (eb)))

#define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
        ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
        SHMEM_ARRAY_MASK(eb))

#define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
do {                                                                       \
        a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
        SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
        a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
        SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
} while (0)



/****START OF DCBX STRUCTURES DECLARATIONS****/
#define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
#define DCBX_PRI_PG_BITWIDTH            4
#define DCBX_PRI_PG_FBITS               8
#define DCBX_PRI_PG_GET(a, i)           \
        SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
#define DCBX_PRI_PG_SET(a, i, val)      \
        SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
#define DCBX_MAX_NUM_PG_BW_ENTRIES      8
#define DCBX_BW_PG_BITWIDTH             8
#define DCBX_PG_BW_GET(a, i)            \
        SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
#define DCBX_PG_BW_SET(a, i, val)       \
        SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
#define DCBX_STRICT_PRI_PG              15
#define DCBX_MAX_APP_PROTOCOL           16
#define DCBX_MAX_APP_LOCAL          32
#define FCOE_APP_IDX                    0
#define ISCSI_APP_IDX                   1
#define PREDEFINED_APP_IDX_MAX          2


/* Big/Little endian have the same representation. */
struct dcbx_ets_feature {
        /*
         * For Admin MIB - is this feature supported by the
         * driver | For Local MIB - should this feature be enabled.
         */
        u32 enabled;
        u32  pg_bw_tbl[2];
        u32  pri_pg_tbl[1];
};

/* Driver structure in LE */
struct dcbx_pfc_feature {
#ifdef __BIG_ENDIAN
        u8 pri_en_bitmap;
        #define DCBX_PFC_PRI_0 0x01
        #define DCBX_PFC_PRI_1 0x02
        #define DCBX_PFC_PRI_2 0x04
        #define DCBX_PFC_PRI_3 0x08
        #define DCBX_PFC_PRI_4 0x10
        #define DCBX_PFC_PRI_5 0x20
        #define DCBX_PFC_PRI_6 0x40
        #define DCBX_PFC_PRI_7 0x80
        u8 pfc_caps;
        u8 reserved;
        u8 enabled;
#elif defined(__LITTLE_ENDIAN)
        u8 enabled;
        u8 reserved;
        u8 pfc_caps;
        u8 pri_en_bitmap;
        #define DCBX_PFC_PRI_0 0x01
        #define DCBX_PFC_PRI_1 0x02
        #define DCBX_PFC_PRI_2 0x04
        #define DCBX_PFC_PRI_3 0x08
        #define DCBX_PFC_PRI_4 0x10
        #define DCBX_PFC_PRI_5 0x20
        #define DCBX_PFC_PRI_6 0x40
        #define DCBX_PFC_PRI_7 0x80
#endif
};

struct dcbx_app_priority_entry {
#ifdef __BIG_ENDIAN
        u16  app_id;
        u8  pri_bitmap;
        u8  appBitfield;
        #define DCBX_APP_ENTRY_VALID         0x01
        #define DCBX_APP_ENTRY_SF_MASK       0x30
        #define DCBX_APP_ENTRY_SF_SHIFT      4
        #define DCBX_APP_SF_ETH_TYPE         0x10
        #define DCBX_APP_SF_PORT             0x20
        #define DCBX_APP_PRI_0               0x01
        #define DCBX_APP_PRI_1               0x02
        #define DCBX_APP_PRI_2               0x04
        #define DCBX_APP_PRI_3               0x08
        #define DCBX_APP_PRI_4               0x10
        #define DCBX_APP_PRI_5               0x20
        #define DCBX_APP_PRI_6               0x40
        #define DCBX_APP_PRI_7               0x80
#elif defined(__LITTLE_ENDIAN)
        u8 appBitfield;
        #define DCBX_APP_ENTRY_VALID         0x01
        #define DCBX_APP_ENTRY_SF_MASK       0x30
        #define DCBX_APP_ENTRY_SF_SHIFT      4
        #define DCBX_APP_SF_ETH_TYPE         0x10
        #define DCBX_APP_SF_PORT             0x20
        u8  pri_bitmap;
        u16  app_id;
#endif
};


/* FW structure in BE */
struct dcbx_app_priority_feature {
#ifdef __BIG_ENDIAN
        u8 reserved;
        u8 default_pri;
        u8 tc_supported;
        u8 enabled;
#elif defined(__LITTLE_ENDIAN)
        u8 enabled;
        u8 tc_supported;
        u8 default_pri;
        u8 reserved;
#endif
        struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
};

/* FW structure in BE */
struct dcbx_features {
        /* PG feature */
        struct dcbx_ets_feature ets;
        /* PFC feature */
        struct dcbx_pfc_feature pfc;
        /* APP feature */
        struct dcbx_app_priority_feature app;
};

/* LLDP protocol parameters */
/* FW structure in BE */
struct lldp_params {
#ifdef __BIG_ENDIAN
        u8  msg_fast_tx_interval;
        u8  msg_tx_hold;
        u8  msg_tx_interval;
        u8  admin_status;
        #define LLDP_TX_ONLY  0x01
        #define LLDP_RX_ONLY  0x02
        #define LLDP_TX_RX    0x03
        #define LLDP_DISABLED 0x04
        u8  reserved1;
        u8  tx_fast;
        u8  tx_crd_max;
        u8  tx_crd;
#elif defined(__LITTLE_ENDIAN)
        u8  admin_status;
        #define LLDP_TX_ONLY  0x01
        #define LLDP_RX_ONLY  0x02
        #define LLDP_TX_RX    0x03
        #define LLDP_DISABLED 0x04
        u8  msg_tx_interval;
        u8  msg_tx_hold;
        u8  msg_fast_tx_interval;
        u8  tx_crd;
        u8  tx_crd_max;
        u8  tx_fast;
        u8  reserved1;
#endif
        #define REM_CHASSIS_ID_STAT_LEN 4
        #define REM_PORT_ID_STAT_LEN 4
        /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
        u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
        /* Holds remote Port ID TLV header, subtype and 9B of payload. */
        u32 peer_port_id[REM_PORT_ID_STAT_LEN];
};

struct lldp_dcbx_stat {
        #define LOCAL_CHASSIS_ID_STAT_LEN 2
        #define LOCAL_PORT_ID_STAT_LEN 2
        /* Holds local Chassis ID 8B payload of constant subtype 4. */
        u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
        /* Holds local Port ID 8B payload of constant subtype 3. */
        u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
        /* Number of DCBX frames transmitted. */
        u32 num_tx_dcbx_pkts;
        /* Number of DCBX frames received. */
        u32 num_rx_dcbx_pkts;
};

/* ADMIN MIB - DCBX local machine default configuration. */
struct lldp_admin_mib {
        u32     ver_cfg_flags;
        #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
        #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
        #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
        #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
        #define DCBX_ETS_RECO_VALID              0x00000010
        #define DCBX_ETS_WILLING                 0x00000020
        #define DCBX_PFC_WILLING                 0x00000040
        #define DCBX_APP_WILLING                 0x00000080
        #define DCBX_VERSION_CEE                 0x00000100
        #define DCBX_VERSION_IEEE                0x00000200
        #define DCBX_DCBX_ENABLED                0x00000400
        #define DCBX_CEE_VERSION_MASK            0x0000f000
        #define DCBX_CEE_VERSION_SHIFT           12
        #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
        #define DCBX_CEE_MAX_VERSION_SHIFT       16
        struct dcbx_features     features;
};

/* REMOTE MIB - remote machine DCBX configuration. */
struct lldp_remote_mib {
        u32 prefix_seq_num;
        u32 flags;
        #define DCBX_ETS_TLV_RX                  0x00000001
        #define DCBX_PFC_TLV_RX                  0x00000002
        #define DCBX_APP_TLV_RX                  0x00000004
        #define DCBX_ETS_RX_ERROR                0x00000010
        #define DCBX_PFC_RX_ERROR                0x00000020
        #define DCBX_APP_RX_ERROR                0x00000040
        #define DCBX_ETS_REM_WILLING             0x00000100
        #define DCBX_PFC_REM_WILLING             0x00000200
        #define DCBX_APP_REM_WILLING             0x00000400
        #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
        #define DCBX_REMOTE_MIB_VALID            0x00002000
        struct dcbx_features features;
        u32 suffix_seq_num;
};

/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
struct lldp_local_mib {
        u32 prefix_seq_num;
        /* Indicates if there is mismatch with negotiation results. */
        u32 error;
        #define DCBX_LOCAL_ETS_ERROR             0x00000001
        #define DCBX_LOCAL_PFC_ERROR             0x00000002
        #define DCBX_LOCAL_APP_ERROR             0x00000004
        #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
        #define DCBX_LOCAL_APP_MISMATCH          0x00000020
        #define DCBX_REMOTE_MIB_ERROR            0x00000040
        #define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
        #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
        #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
        struct dcbx_features   features;
        u32 suffix_seq_num;
};

struct lldp_local_mib_ext {
        u32 prefix_seq_num;
        /* APP TLV extension - 16 more entries for negotiation results*/
        struct dcbx_app_priority_entry  app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
        u32 suffix_seq_num;
};
/***END OF DCBX STRUCTURES DECLARATIONS***/

/***********************************************************/
/*                         Elink section                   */
/***********************************************************/
#define SHMEM_LINK_CONFIG_SIZE 2
struct shmem_lfa {
        u32 req_duplex;
        #define REQ_DUPLEX_PHY0_MASK        0x0000ffff
        #define REQ_DUPLEX_PHY0_SHIFT       0
        #define REQ_DUPLEX_PHY1_MASK        0xffff0000
        #define REQ_DUPLEX_PHY1_SHIFT       16
        u32 req_flow_ctrl;
        #define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
        #define REQ_FLOW_CTRL_PHY0_SHIFT    0
        #define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
        #define REQ_FLOW_CTRL_PHY1_SHIFT    16
        u32 req_line_speed; /* Also determine AutoNeg */
        #define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
        #define REQ_LINE_SPD_PHY0_SHIFT     0
        #define REQ_LINE_SPD_PHY1_MASK      0xffff0000
        #define REQ_LINE_SPD_PHY1_SHIFT     16
        u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
        u32 additional_config;
        #define REQ_FC_AUTO_ADV_MASK        0x0000ffff
        #define REQ_FC_AUTO_ADV0_SHIFT      0
        #define NO_LFA_DUE_TO_DCC_MASK      0x00010000
        u32 lfa_sts;
        #define LFA_LINK_FLAP_REASON_OFFSET             0
        #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
                #define LFA_LINK_DOWN                       0x1
                #define LFA_LOOPBACK_ENABLED            0x2
                #define LFA_DUPLEX_MISMATCH                 0x3
                #define LFA_MFW_IS_TOO_OLD                  0x4
                #define LFA_LINK_SPEED_MISMATCH         0x5
                #define LFA_FLOW_CTRL_MISMATCH          0x6
                #define LFA_SPEED_CAP_MISMATCH          0x7
                #define LFA_DCC_LFA_DISABLED            0x8
                #define LFA_EEE_MISMATCH                0x9

        #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
        #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00

        #define LINK_FLAP_COUNT_OFFSET                  16
        #define LINK_FLAP_COUNT_MASK                    0x00ff0000

        #define LFA_FLAGS_MASK                          0xff000000
        #define SHMEM_LFA_DONT_CLEAR_STAT               (1<<24)

};

/*
Used to suppoert NSCI get OS driver version
On driver load the version value will be set
On driver unload driver value of 0x0 will be set
*/
struct os_drv_ver{
        #define DRV_VER_NOT_LOADED                      0
        /*personalites orrder is importent */
        #define DRV_PERS_ETHERNET                       0
        #define DRV_PERS_ISCSI                          1
        #define DRV_PERS_FCOE                           2
        /*shmem2 struct is constatnt can't add more personalites here*/
        #define MAX_DRV_PERS                            3
        u32  versions[MAX_DRV_PERS];
};

struct shmem2_region {

        u32 size;                                       /* 0x0000 */

        u32 dcc_support;                                /* 0x0004 */
        #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
        #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
        #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
        #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
        #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
        #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080

        u32 ext_phy_fw_version2[PORT_MAX];              /* 0x0008 */
        /*
         * For backwards compatibility, if the mf_cfg_addr does not exist
         * (the size filed is smaller than 0xc) the mf_cfg resides at the
         * end of struct shmem_region
         */
        u32 mf_cfg_addr;                                /* 0x0010 */
        #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000

        struct fw_flr_mb flr_mb;                        /* 0x0014 */
        u32 dcbx_lldp_params_offset;                    /* 0x0028 */
        #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
        u32 dcbx_neg_res_offset;                        /* 0x002c */
        #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
        u32 dcbx_remote_mib_offset;                     /* 0x0030 */
        #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
        /*
         * The other shmemX_base_addr holds the other path's shmem address
         * required for example in case of common phy init, or for path1 to know
         * the address of mcp debug trace which is located in offset from shmem
         * of path0
         */
        u32 other_shmem_base_addr;                      /* 0x0034 */
        u32 other_shmem2_base_addr;                     /* 0x0038 */
        /*
         * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
         * which were disabled/flred
         */
        u32 mcp_vf_disabled[E2_VF_MAX / 32];            /* 0x003c */

        /*
         * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
         * VFs
         */
        u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */

        u32 dcbx_lldp_dcbx_stat_offset;                 /* 0x0064 */
        #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000

        /*
         * edebug_driver_if field is used to transfer messages between edebug
         * app to the driver through shmem2.
         *
         * message format:
         * bits 0-2 -  function number / instance of driver to perform request
         * bits 3-5 -  op code / is_ack?
         * bits 6-63 - data
         */
        u32 edebug_driver_if[2];                        /* 0x0068 */
        #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
        #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
        #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3

        u32 nvm_retain_bitmap_addr;                     /* 0x0070 */

        /* afex support of that driver */
        u32 afex_driver_support;                        /* 0x0074 */
        #define SHMEM_AFEX_VERSION_MASK                  0x100f
        #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
        #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000

        /* driver receives addr in scratchpad to which it should respond */
        u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];

        /*
         * generic params from MCP to driver (value depends on the msg sent
         * to driver
         */
        u32 afex_param1_to_driver[E2_FUNC_MAX];         /* 0x0088 */
        u32 afex_param2_to_driver[E2_FUNC_MAX];         /* 0x0098 */

        u32 swim_base_addr;                             /* 0x0108 */
        u32 swim_funcs;
        u32 swim_main_cb;

        /*
         * bitmap notifying which VIF profiles stored in nvram are enabled by
         * switch
         */
        u32 afex_profiles_enabled[2];

        /* generic flags controlled by the driver */
        u32 drv_flags;
        #define DRV_FLAGS_DCB_CONFIGURED                0x0
        #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED     0x1
        #define DRV_FLAGS_DCB_MFW_CONFIGURED    0x2

    #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
                        (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
                        (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
        /* Port offset*/
        #define DRV_FLAGS_P0_OFFSET             0
        #define DRV_FLAGS_P1_OFFSET             16
        #define DRV_FLAGS_GET_PORT_OFFSET(_port)        ((0 == _port) ? \
                                                DRV_FLAGS_P0_OFFSET : \
                                                DRV_FLAGS_P1_OFFSET)

        #define DRV_FLAGS_GET_PORT_MASK(_port)  (DRV_FLAGS_PORT_MASK << \
        DRV_FLAGS_GET_PORT_OFFSET(_port))

        #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port)      (1 << ( \
        (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))

        /* pointer to extended dev_info shared data copied from nvm image */
        u32 extended_dev_info_shared_addr;
        u32 ncsi_oem_data_addr;

        u32 sensor_data_addr;
        u32 buffer_block_addr;
        u32 sensor_data_req_update_interval;
        u32 temperature_in_half_celsius;
        u32 glob_struct_in_host;

        u32 dcbx_neg_res_ext_offset;
        #define SHMEM_DCBX_NEG_RES_EXT_NONE                     0x00000000

        u32 drv_capabilities_flag[E2_FUNC_MAX];
        #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
        #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
        #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
        #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
        #define DRV_FLAGS_MTU_MASK                      0xffff0000
        #define DRV_FLAGS_MTU_SHIFT                             16

        u32 extended_dev_info_shared_cfg_size;

        u32 dcbx_en[PORT_MAX];

        /* The offset points to the multi threaded meta structure */
        u32 multi_thread_data_offset;

        /* address of DMAable host address holding values from the drivers */
        u32 drv_info_host_addr_lo;
        u32 drv_info_host_addr_hi;

        /* general values written by the MFW (such as current version) */
        u32 drv_info_control;
        #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
        #define DRV_INFO_CONTROL_VER_SHIFT         0
        #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
        #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
        u32 ibft_host_addr; /* initialized by option ROM */

        struct eee_remote_vals eee_remote_vals[PORT_MAX];
        u32 pf_allocation[E2_FUNC_MAX];
        #define PF_ALLOACTION_MSIX_VECTORS_MASK    0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
        #define PF_ALLOACTION_MSIX_VECTORS_SHIFT   0

        /* the status of EEE auto-negotiation
         * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
         * bits 19:16 the supported modes for EEE.
         * bits 23:20 the speeds advertised for EEE.
         * bits 27:24 the speeds the Link partner advertised for EEE.
         * The supported/adv. modes in bits 27:19 originate from the
         * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
         * bit 28 when 1'b1 EEE was requested.
         * bit 29 when 1'b1 tx lpi was requested.
         * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
         * 30:29 are 2'b11.
         * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
         * value. When 1'b1 those bits contains a value times 16 microseconds.
         */
        u32 eee_status[PORT_MAX];
        #define SHMEM_EEE_TIMER_MASK               0x0000ffff
        #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
        #define SHMEM_EEE_SUPPORTED_SHIFT          16
        #define SHMEM_EEE_ADV_STATUS_MASK          0x00f00000
                #define SHMEM_EEE_100M_ADV         (1U<<0)
                #define SHMEM_EEE_1G_ADV           (1U<<1)
                #define SHMEM_EEE_10G_ADV          (1U<<2)
        #define SHMEM_EEE_ADV_STATUS_SHIFT         20
        #define SHMEM_EEE_LP_ADV_STATUS_MASK       0x0f000000
        #define SHMEM_EEE_LP_ADV_STATUS_SHIFT      24
        #define SHMEM_EEE_REQUESTED_BIT            0x10000000
        #define SHMEM_EEE_LPI_REQUESTED_BIT        0x20000000
        #define SHMEM_EEE_ACTIVE_BIT               0x40000000
        #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000

        u32 sizeof_port_stats;

        /* Link Flap Avoidance */
        u32 lfa_host_addr[PORT_MAX];

    /* External PHY temperature in deg C. */
        u32 extphy_temps_in_celsius;
        #define EXTPHY1_TEMP_MASK                  0x0000ffff
        #define EXTPHY1_TEMP_SHIFT                 0

        u32 ocdata_info_addr;                   /* Offset 0x148 */
        u32 drv_func_info_addr;                 /* Offset 0x14C */
        u32 drv_func_info_size;                 /* Offset 0x150 */
        u32 link_attr_sync[PORT_MAX];           /* Offset 0x154 */
        #define LINK_ATTR_SYNC_KR2_ENABLE       0x00000001
        #define LINK_SFP_EEPROM_COMP_CODE_MASK  0x0000ff00
        #define LINK_SFP_EEPROM_COMP_CODE_SHIFT          8
        #define LINK_SFP_EEPROM_COMP_CODE_SR    0x00001000
        #define LINK_SFP_EEPROM_COMP_CODE_LR    0x00002000
        #define LINK_SFP_EEPROM_COMP_CODE_LRM   0x00004000

        u32 ibft_host_addr_hi;  /* Initialize by uEFI ROM Offset 0x158 */
        u32 fcode_ver;                          /* Offset 0x15c */
        u32 link_change_count[PORT_MAX];        /* Offset 0x160-0x164 */
        #define LINK_CHANGE_COUNT_MASK 0xff     /* Offset 0x168 */
        /* driver version for each personality*/
        struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */

        /* Flag to the driver that PF's drv_info_host_addr buffer was read  */
        u32 mfw_drv_indication;

        /* We use inidcation for each PF (0..3) */
        #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_)  (1 << _pf_)
};

#endif