Symbol: outb
usr/src/boot/common/isapnp.c
132
outb(_PNP_ADDRESS, STATUS);
usr/src/boot/common/isapnp.c
142
outb(_PNP_ADDRESS, RESOURCE_DATA);
usr/src/boot/common/isapnp.c
246
outb(_PNP_ADDRESS, SERIAL_ISOLATION);
usr/src/boot/common/isapnp.c
62
outb(_PNP_ADDRESS, d);
usr/src/boot/common/isapnp.c
63
outb(_PNP_WRITE_DATA, r);
usr/src/boot/common/isapnp.c
76
outb(_PNP_ADDRESS, 0);
usr/src/boot/common/isapnp.c
77
outb(_PNP_ADDRESS, 0); /* yes, we do need it twice! */
usr/src/boot/common/isapnp.c
80
outb(_PNP_ADDRESS, cur);
usr/src/boot/common/isapnp.c
84
outb(_PNP_ADDRESS, cur);
usr/src/boot/common/isapnp.c
97
outb(_PNP_ADDRESS, SERIAL_ISOLATION);
usr/src/boot/common/misc.c
236
outb(port, c);
usr/src/boot/efi/libefi/efiisaio.c
403
outb(Offset, *buf++);
usr/src/boot/i386/libi386/comconsole.c
106
outb(ioaddr + com_scr, COMC_TEST);
usr/src/boot/i386/libi386/comconsole.c
285
outb(sp->ioaddr + com_data, (uchar_t)c);
usr/src/boot/i386/libi386/comconsole.c
531
outb(sp->ioaddr + com_cfcr, CFCR_DLAB | sp->lcr);
usr/src/boot/i386/libi386/comconsole.c
532
outb(sp->ioaddr + com_dlbl, COMC_BPS(sp->speed) & 0xff);
usr/src/boot/i386/libi386/comconsole.c
533
outb(sp->ioaddr + com_dlbh, COMC_BPS(sp->speed) >> 8);
usr/src/boot/i386/libi386/comconsole.c
534
outb(sp->ioaddr + com_cfcr, sp->lcr);
usr/src/boot/i386/libi386/comconsole.c
535
outb(sp->ioaddr + com_mcr,
usr/src/boot/i386/libi386/comconsole.c
559
outb(ioaddr + com_cfcr, CFCR_DLAB | cfcr);
usr/src/boot/i386/libi386/comconsole.c
564
outb(ioaddr + com_cfcr, cfcr);
usr/src/boot/i386/libi386/vidconsole.c
1082
outb(IO_KBD + KBD_DATA_PORT, KBDC_ECHO);
usr/src/boot/i386/loader/main.c
362
outb(port, value);
usr/src/boot/sys/amd64/include/cpufunc.h
843
void outb(u_int port, u_char data);
usr/src/boot/sys/i386/include/cpufunc.h
689
outb(0x22, reg);
usr/src/boot/sys/i386/include/cpufunc.h
696
outb(0x22, reg);
usr/src/boot/sys/i386/include/cpufunc.h
697
outb(0x23, data);
usr/src/boot/sys/i386/include/cpufunc.h
756
void outb(u_int port, u_char data);
usr/src/common/vga/vgasubr.c
60
#define PUTB(reg, off, v) outb(reg + (off), v)
usr/src/grub/grub-0.97/netboot/3c595.c
108
outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i);
usr/src/grub/grub-0.97/netboot/3c595.c
198
outb(0x0, BASE + VX_W1_TX_STATUS);
usr/src/grub/grub-0.97/netboot/3c595.c
214
outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1);
usr/src/grub/grub-0.97/netboot/3c595.c
217
outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */
usr/src/grub/grub-0.97/netboot/3c90x.c
437
outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
usr/src/grub/grub-0.97/netboot/3c90x.c
543
outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
usr/src/grub/grub-0.97/netboot/3c90x.c
560
outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
usr/src/grub/grub-0.97/netboot/3c90x.c
923
outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
usr/src/grub/grub-0.97/netboot/eepro100.c
461
outb(RX_ABORT, ioaddr + SCBCmd);
usr/src/grub/grub-0.97/netboot/eepro100.c
467
outb(RX_START, ioaddr + SCBCmd);
usr/src/grub/grub-0.97/netboot/i386_timer.c
29
outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
usr/src/grub/grub-0.97/netboot/i386_timer.c
31
outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT);
usr/src/grub/grub-0.97/netboot/i386_timer.c
33
outb(ticks & 0xFF, TIMER2_PORT);
usr/src/grub/grub-0.97/netboot/i386_timer.c
35
outb(ticks >> 8, TIMER2_PORT);
usr/src/grub/grub-0.97/netboot/ns8390.c
120
outb(src & 0xff, eth_asic_base + WD_GP2);
usr/src/grub/grub-0.97/netboot/ns8390.c
121
outb(src >> 8, eth_asic_base + WD_GP2);
usr/src/grub/grub-0.97/netboot/ns8390.c
123
outb(D8390_COMMAND_RD2 |
usr/src/grub/grub-0.97/netboot/ns8390.c
125
outb(cnt, eth_nic_base + D8390_P0_RBCR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
126
outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
127
outb(src, eth_nic_base + D8390_P0_RSAR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
128
outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
129
outb(D8390_COMMAND_RD0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
133
outb(src & 0xff, eth_asic_base + _3COM_DALSB);
usr/src/grub/grub-0.97/netboot/ns8390.c
134
outb(src >> 8, eth_asic_base + _3COM_DAMSB);
usr/src/grub/grub-0.97/netboot/ns8390.c
135
outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
157
outb(t503_output, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
170
outb(dst & 0xff, eth_asic_base + WD_GP2);
usr/src/grub/grub-0.97/netboot/ns8390.c
171
outb(dst >> 8, eth_asic_base + WD_GP2);
usr/src/grub/grub-0.97/netboot/ns8390.c
173
outb(D8390_COMMAND_RD2 |
usr/src/grub/grub-0.97/netboot/ns8390.c
175
outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
usr/src/grub/grub-0.97/netboot/ns8390.c
176
outb(cnt, eth_nic_base + D8390_P0_RBCR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
177
outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
178
outb(dst, eth_nic_base + D8390_P0_RSAR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
179
outb(dst>>8, eth_nic_base + D8390_P0_RSAR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
180
outb(D8390_COMMAND_RD1 |
usr/src/grub/grub-0.97/netboot/ns8390.c
184
outb(dst & 0xff, eth_asic_base + _3COM_DALSB);
usr/src/grub/grub-0.97/netboot/ns8390.c
185
outb(dst >> 8, eth_asic_base + _3COM_DAMSB);
usr/src/grub/grub-0.97/netboot/ns8390.c
187
outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
206
outb(*(src++), eth_asic_base + ASIC_PIO);
usr/src/grub/grub-0.97/netboot/ns8390.c
210
outb(t503_output, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
243
outb(4, eth_nic_base+D8390_P0_RCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
244
outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
247
outb(mcfilter[i], eth_nic_base + 8 + i);
usr/src/grub/grub-0.97/netboot/ns8390.c
251
outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
252
outb(4 | 0x08, eth_nic_base+D8390_P0_RCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
265
outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
268
outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
usr/src/grub/grub-0.97/netboot/ns8390.c
271
outb(0x49, eth_nic_base+D8390_P0_DCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
273
outb(0x48, eth_nic_base+D8390_P0_DCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
274
outb(0, eth_nic_base+D8390_P0_RBCR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
275
outb(0, eth_nic_base+D8390_P0_RBCR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
276
outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */
usr/src/grub/grub-0.97/netboot/ns8390.c
277
outb(2, eth_nic_base+D8390_P0_TCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
278
outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
279
outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
usr/src/grub/grub-0.97/netboot/ns8390.c
283
outb(0x10, eth_asic_base + 0x06); /* disable interrupts, enable PIO */
usr/src/grub/grub-0.97/netboot/ns8390.c
284
outb(0x01, eth_nic_base + 0x09); /* enable ring read auto-wrap */
usr/src/grub/grub-0.97/netboot/ns8390.c
286
outb(0, eth_nic_base + 0x09);
usr/src/grub/grub-0.97/netboot/ns8390.c
290
outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
usr/src/grub/grub-0.97/netboot/ns8390.c
291
outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
usr/src/grub/grub-0.97/netboot/ns8390.c
292
outb(0xFF, eth_nic_base+D8390_P0_ISR);
usr/src/grub/grub-0.97/netboot/ns8390.c
293
outb(0, eth_nic_base+D8390_P0_IMR);
usr/src/grub/grub-0.97/netboot/ns8390.c
296
outb(D8390_COMMAND_PS1 |
usr/src/grub/grub-0.97/netboot/ns8390.c
300
outb(D8390_COMMAND_PS1 |
usr/src/grub/grub-0.97/netboot/ns8390.c
303
outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
usr/src/grub/grub-0.97/netboot/ns8390.c
305
outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
usr/src/grub/grub-0.97/netboot/ns8390.c
306
outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
usr/src/grub/grub-0.97/netboot/ns8390.c
309
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
313
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
315
outb(0xFF, eth_nic_base+D8390_P0_ISR);
usr/src/grub/grub-0.97/netboot/ns8390.c
316
outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */
usr/src/grub/grub-0.97/netboot/ns8390.c
317
outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */
usr/src/grub/grub-0.97/netboot/ns8390.c
329
outb(t503_output, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
345
outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
348
outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
usr/src/grub/grub-0.97/netboot/ns8390.c
356
outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */
usr/src/grub/grub-0.97/netboot/ns8390.c
357
outb(0, eth_nic_base+D8390_P0_RBCR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
365
outb(2, eth_nic_base+D8390_P0_TCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
368
outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
371
outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
usr/src/grub/grub-0.97/netboot/ns8390.c
379
outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR);
usr/src/grub/grub-0.97/netboot/ns8390.c
382
outb(0, eth_nic_base+D8390_P0_TCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
413
outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
usr/src/grub/grub-0.97/netboot/ns8390.c
419
outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
431
outb(0, eth_asic_base + WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
461
outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
usr/src/grub/grub-0.97/netboot/ns8390.c
465
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
469
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
471
outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
472
outb(s, eth_nic_base+D8390_P0_TBCR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
473
outb(s>>8, eth_nic_base+D8390_P0_TBCR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
476
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
480
outb(D8390_COMMAND_PS0 |
usr/src/grub/grub-0.97/netboot/ns8390.c
508
outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
510
outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
usr/src/grub/grub-0.97/netboot/ns8390.c
518
outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
usr/src/grub/grub-0.97/netboot/ns8390.c
523
outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
566
outb(0, eth_asic_base + WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
571
outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
usr/src/grub/grub-0.97/netboot/ns8390.c
579
outb(next-1, eth_nic_base+D8390_P0_BOUND);
usr/src/grub/grub-0.97/netboot/ns8390.c
684
outb(0x80, eth_asic_base + WD_MSR); /* Reset */
usr/src/grub/grub-0.97/netboot/ns8390.c
694
outb(0, eth_asic_base+WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
697
outb(WD_MSR_MENB, eth_asic_base+WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
698
outb((inb(eth_asic_base+0x04) |
usr/src/grub/grub-0.97/netboot/ns8390.c
700
outb(((unsigned)(eth_bmem >> 13) & 0x0F) |
usr/src/grub/grub-0.97/netboot/ns8390.c
703
outb((inb(eth_asic_base+0x04) &
usr/src/grub/grub-0.97/netboot/ns8390.c
708
outb(((unsigned)(eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR);
usr/src/grub/grub-0.97/netboot/ns8390.c
713
outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
usr/src/grub/grub-0.97/netboot/ns8390.c
715
outb((eth_laar =
usr/src/grub/grub-0.97/netboot/ns8390.c
812
outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR );
usr/src/grub/grub-0.97/netboot/ns8390.c
813
outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR );
usr/src/grub/grub-0.97/netboot/ns8390.c
817
outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
829
outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR);
usr/src/grub/grub-0.97/netboot/ns8390.c
834
outb(_3COM_GACFR_RSEL |
usr/src/grub/grub-0.97/netboot/ns8390.c
837
outb(0xff, eth_asic_base + _3COM_VPTR2);
usr/src/grub/grub-0.97/netboot/ns8390.c
838
outb(0xff, eth_asic_base + _3COM_VPTR1);
usr/src/grub/grub-0.97/netboot/ns8390.c
839
outb(0x00, eth_asic_base + _3COM_VPTR0);
usr/src/grub/grub-0.97/netboot/ns8390.c
855
outb(eth_tx_start, eth_asic_base + _3COM_PSTR);
usr/src/grub/grub-0.97/netboot/ns8390.c
856
outb(eth_memsize, eth_asic_base + _3COM_PSPR);
usr/src/grub/grub-0.97/netboot/ns8390.c
885
outb(c, eth_asic_base + NE_RESET);
usr/src/grub/grub-0.97/netboot/ns8390.c
887
outb(D8390_COMMAND_STP |
usr/src/grub/grub-0.97/netboot/ns8390.c
889
outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
890
outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
usr/src/grub/grub-0.97/netboot/ns8390.c
891
outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
usr/src/grub/grub-0.97/netboot/ns8390.c
892
outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
usr/src/grub/grub-0.97/netboot/ns8390.c
905
outb(D8390_DCR_WTS |
usr/src/grub/grub-0.97/netboot/ns8390.c
907
outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
usr/src/grub/grub-0.97/netboot/ns8390.c
908
outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);
usr/src/grub/grub-0.97/netboot/pci_io.c
56
outb(value, 0xCFC + (where&3));
usr/src/grub/grub-0.97/netboot/pic8259.c
83
outb ( ICR_EOI_SPECIFIC | ICR_VALUE(irq), ICR_REG(irq) );
usr/src/grub/grub-0.97/netboot/pic8259.c
85
outb ( ICR_EOI_SPECIFIC | ICR_VALUE(CHAINED_IRQ),
usr/src/grub/grub-0.97/netboot/pic8259.h
50
#define enable_irq(x) outb ( inb( IMR_REG(x) ) & ~IMR_BIT(x), IMR_REG(x) )
usr/src/grub/grub-0.97/netboot/pic8259.h
51
#define disable_irq(x) outb ( inb( IMR_REG(x) ) | IMR_BIT(x), IMR_REG(x) )
usr/src/grub/grub-0.97/netboot/pnic.c
61
outb( ((char*)input)[i], nic->ioaddr + PNIC_REG_DATA );
usr/src/grub/grub-0.97/netboot/rtl8139.c
206
outb(0x00, nic->ioaddr + Config1);
usr/src/grub/grub-0.97/netboot/rtl8139.c
263
outb(EE_ENB & ~EE_CS, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
264
outb(EE_ENB, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
270
outb(EE_ENB | dataval, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
272
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
275
outb(EE_ENB, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
279
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
282
outb(EE_ENB, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
287
outb(~EE_CS, ee_addr);
usr/src/grub/grub-0.97/netboot/rtl8139.c
314
outb(CmdReset, nic->ioaddr + ChipCmd);
usr/src/grub/grub-0.97/netboot/rtl8139.c
326
outb(nic->node_addr[i], nic->ioaddr + MAC0 + i);
usr/src/grub/grub-0.97/netboot/rtl8139.c
329
outb(CmdRxEnb | CmdTxEnb, nic->ioaddr + ChipCmd);
usr/src/grub/grub-0.97/netboot/rtl8139.c
353
outb(CmdRxEnb | CmdTxEnb, nic->ioaddr + ChipCmd);
usr/src/grub/grub-0.97/netboot/rtl8139.c
507
outb(EROK, nic->ioaddr + RxEarlyStatus);
usr/src/grub/grub-0.97/netboot/rtl8139.c
519
outb(CmdReset, nic->ioaddr + ChipCmd);
usr/src/grub/grub-0.97/netboot/sis900.c
258
outb(0x09 + i, 0x70);
usr/src/grub/grub-0.97/netboot/sis900.c
465
outb(EECS, ee_addr);
usr/src/grub/grub-0.97/netboot/sis900.c
558
outb(dataval, mdio_addr);
usr/src/grub/grub-0.97/netboot/sis900.c
560
outb(dataval | MDC, mdio_addr);
usr/src/grub/grub-0.97/netboot/sis900.c
577
outb(0, mdio_addr);
usr/src/grub/grub-0.97/netboot/sis900.c
579
outb(MDC, mdio_addr);
usr/src/grub/grub-0.97/netboot/sundance.c
418
outb(100, BASE + RxDMAPollPeriod);
usr/src/grub/grub-0.97/netboot/sundance.c
778
#define mdio_out(value, mdio_addr) outb(value, mdio_addr)
usr/src/grub/grub-0.97/netboot/sundance.c
880
outb(rx_mode, BASE + RxMode);
usr/src/grub/grub-0.97/netboot/tlan.c
505
outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
usr/src/grub/grub-0.97/netboot/tlan.h
429
outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
usr/src/grub/grub-0.97/netboot/via-rhine.c
1046
outb (MIICRbak & 0x7F, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1048
outb (0x41, byMIIAD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1052
outb (MIICRbak | 0x80, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1154
outb (CR1_SFRST, byCR1);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1170
outb (0x06, byBCR0);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1171
outb (0x00, byBCR1);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1172
outb (0x2c, byRCR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1173
outb (0x60, byTCR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1178
outb (CFGD_CFDX, byCFGD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1214
outb(0x08, nic->ioaddr + IntrStatus2);
usr/src/grub/grub-0.97/netboot/via-rhine.c
1290
outb (CR1bak, byCR1);
usr/src/grub/grub-0.97/netboot/via-rhine.c
748
outb (byMIICRbak & 0x7f, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
751
outb (byMIIIndex, byMIIAD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
754
outb (inb (byMIICR) | 0x40, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
768
outb (byMIIAdrbak, byMIIAD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
769
outb (byMIICRbak, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
789
outb (byMIICRbak & 0x7f, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
791
outb (byMIISetByte, byMIIAD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
794
outb (inb (byMIICR) | 0x40, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
824
outb (inb (byMIICR) | 0x20, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
835
outb (byMIIAdrbak & 0x7f, byMIIAD);
usr/src/grub/grub-0.97/netboot/via-rhine.c
836
outb (byMIICRbak, byMIICR);
usr/src/grub/grub-0.97/netboot/via-rhine.c
943
outb(0x60 /* thresh */ | rx_mode, byRCR );
usr/src/grub/grub-0.97/netboot/via-rhine.c
969
outb(byOrgValue, bySTICKHW);
usr/src/grub/grub-0.97/netboot/via-rhine.c
973
outb(0x80, byWOLcgClr);
usr/src/grub/grub-0.97/netboot/via-rhine.c
975
outb(0xFF, byWOLcrClr);
usr/src/grub/grub-0.97/netboot/via-rhine.c
977
outb(0xFF, byPwrcsrClr);
usr/src/grub/grub-0.97/netboot/w89c840.c
162
#define writeb outb
usr/src/grub/grub-0.97/stage2/graphics.c
119
outb(0x3c4, 2);
usr/src/grub/grub-0.97/stage2/graphics.c
120
outb(0x3c5, value);
usr/src/grub/grub-0.97/stage2/graphics.c
125
outb(0x3ce, 8);
usr/src/grub/grub-0.97/stage2/graphics.c
126
outb(0x3cf, value);
usr/src/grub/grub-0.97/stage2/hercules.c
177
outb (HERCULES_INDEX_REG, 0x0a);
usr/src/grub/grub-0.97/stage2/hercules.c
178
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/hercules.c
179
outb (HERCULES_DATA_REG, on ? 0 : (1 << 5));
usr/src/grub/grub-0.97/stage2/hercules.c
180
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/hercules.c
50
outb (HERCULES_INDEX_REG, 0x0f);
usr/src/grub/grub-0.97/stage2/hercules.c
51
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/hercules.c
52
outb (HERCULES_DATA_REG, offset & 0xFF);
usr/src/grub/grub-0.97/stage2/hercules.c
53
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/hercules.c
55
outb (HERCULES_INDEX_REG, 0x0e);
usr/src/grub/grub-0.97/stage2/hercules.c
56
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/hercules.c
57
outb (HERCULES_DATA_REG, offset >> 8);
usr/src/grub/grub-0.97/stage2/hercules.c
58
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/serial.c
111
outb (serial_hw_port + UART_TX, c);
usr/src/grub/grub-0.97/stage2/serial.c
117
outb (0x80, 0);
usr/src/grub/grub-0.97/stage2/serial.c
149
outb (port + UART_SR, UART_SR_TEST);
usr/src/grub/grub-0.97/stage2/serial.c
150
outb (port + UART_FCR, 0);
usr/src/grub/grub-0.97/stage2/serial.c
156
outb (port + UART_IER, 0);
usr/src/grub/grub-0.97/stage2/serial.c
159
outb (port + UART_LCR, UART_DLAB);
usr/src/grub/grub-0.97/stage2/serial.c
172
outb (port + UART_DLL, div & 0xFF);
usr/src/grub/grub-0.97/stage2/serial.c
173
outb (port + UART_DLH, div >> 8);
usr/src/grub/grub-0.97/stage2/serial.c
177
outb (port + UART_LCR, status);
usr/src/grub/grub-0.97/stage2/serial.c
180
outb (port + UART_FCR, UART_ENABLE_FIFO);
usr/src/grub/grub-0.97/stage2/serial.c
183
outb (port + UART_MCR, UART_ENABLE_MODEM);
usr/src/grub/grub-0.97/stage2/smp-imps.c
91
outb (0x70, loc);
usr/src/grub/grub-0.97/stage2/smp-imps.c
92
outb (0x71, val);
usr/src/grub/grub-0.97/stage2/smp-imps.c
98
outb (0x70, loc);
usr/src/test/bhyve-tests/tests/common/payload_utils.h
22
void outb(uint16_t, uint8_t);
usr/src/test/bhyve-tests/tests/inst_emul/payload_cpuid.c
134
outb(IOP_TEST_RESULT, TEST_RESULT_FAIL);
usr/src/test/bhyve-tests/tests/inst_emul/payload_cpuid.c
145
outb(IOP_TEST_RESULT, TEST_RESULT_FAIL);
usr/src/test/bhyve-tests/tests/inst_emul/payload_cpuid.c
149
outb(IOP_TEST_RESULT, TEST_RESULT_FAIL);
usr/src/test/bhyve-tests/tests/inst_emul/payload_cpuid.c
168
outb(IOP_TEST_RESULT, TEST_RESULT_PASS);
usr/src/test/bhyve-tests/tests/kdev/payload_vatpit_freq.c
28
outb(IOP_ATPIT_CMD, 0x30);
usr/src/test/bhyve-tests/tests/kdev/payload_vatpit_freq.c
31
outb(IOP_ATPIT_C0, 0xff);
usr/src/test/bhyve-tests/tests/kdev/payload_vatpit_freq.c
32
outb(IOP_ATPIT_C0, 0xff);
usr/src/test/bhyve-tests/tests/kdev/payload_vatpit_freq.c
41
outb(IOP_ATPIT_CMD, 0x00);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
51
outb(IOP_TEST_RESULT, TEST_RESULT_FAIL);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
84
outb(IOP_TEST_RESULT, TEST_RESULT_PASS);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
108
outb(IOP_TEST_RESULT, TEST_RESULT_FAIL);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
131
outb(IOP_TEST_RESULT, TEST_RESULT_PASS);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
100
outb(IOP_ATPIC_SDATA, 0x00);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
102
outb(IOP_ATPIC_SDATA, 0x03);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
104
outb(IOP_ATPIC_SDATA, 0x00);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
116
outb(IOP_ATPIC_SCMD, 0x0c);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
61
outb(IOP_RTC_ADDR, off);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
72
outb(IOP_RTC_ADDR, off);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
76
return (outb(IOP_RTC_DATA, data));
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
96
outb(IOP_ATPIC_SCMD, 0x11);
usr/src/test/bhyve-tests/tests/kdev/payload_vrtc_ops.c
98
outb(IOP_ATPIC_SDATA, 0x20);
usr/src/uts/common/fs/udfs/udf_vnops.c
1122
caddr_t outb, end_outb;
usr/src/uts/common/fs/udfs/udf_vnops.c
1153
outb = outbuf = (char *)kmem_alloc((uint32_t)bufsize, KM_SLEEP);
usr/src/uts/common/fs/udfs/udf_vnops.c
1154
end_outb = outb + bufsize;
usr/src/uts/common/io/fd.c
291
outb(CMOS_ADDR, CMOS_FDRV);
usr/src/uts/common/io/fd.c
368
outb(CMOS_ADDR, CMOS_FDRV);
usr/src/uts/common/os/sunpm.c
9321
outb(CPR_DATAREG, c);
usr/src/uts/common/sys/epm.h
719
#define PT(code) {outb(0x80, (char)code); drv_usecwait(pt_sleep); }
usr/src/uts/common/sys/sunddi.h
1855
extern void outb(int port, uint8_t value);
usr/src/uts/i86pc/boot/boot_console.c
139
outb(port + ISR, 0x20);
usr/src/uts/i86pc/boot/boot_console.c
144
outb(port + DAT+7, 0x04); /* clear status */
usr/src/uts/i86pc/boot/boot_console.c
145
outb(port + ISR, 0x40); /* set to bank 2 */
usr/src/uts/i86pc/boot/boot_console.c
146
outb(port + MCR, 0x08); /* IMD */
usr/src/uts/i86pc/boot/boot_console.c
147
outb(port + DAT, 0x21); /* FMD */
usr/src/uts/i86pc/boot/boot_console.c
148
outb(port + ISR, 0x00); /* set to bank 0 */
usr/src/uts/i86pc/boot/boot_console.c
156
outb(port + FIFOR, 0x00); /* clear */
usr/src/uts/i86pc/boot/boot_console.c
157
outb(port + FIFOR, FIFO_ON); /* enable */
usr/src/uts/i86pc/boot/boot_console.c
158
outb(port + FIFOR, FIFO_ON|FIFORXFLSH); /* reset */
usr/src/uts/i86pc/boot/boot_console.c
159
outb(port + FIFOR,
usr/src/uts/i86pc/boot/boot_console.c
166
outb(port + FIFOR, 0x00);
usr/src/uts/i86pc/boot/boot_console.c
171
outb(port + ICR, 0);
usr/src/uts/i86pc/boot/boot_console.c
456
outb(port + LCR, DLAB);
usr/src/uts/i86pc/boot/boot_console.c
457
outb(port + DAT + DLL, baud & 0xff);
usr/src/uts/i86pc/boot/boot_console.c
458
outb(port + DAT + DLH, (baud >> 8) & 0xff);
usr/src/uts/i86pc/boot/boot_console.c
513
outb(port + LCR, lcr);
usr/src/uts/i86pc/boot/boot_console.c
523
outb(port + MCR, mcr | OUT2);
usr/src/uts/i86pc/boot/boot_console.c
887
outb(port + DAT, (char)c);
usr/src/uts/i86pc/boot/boot_keyboard.c
476
outb(I8042_DATA, cmd);
usr/src/uts/i86pc/boot/boot_vga.c
322
outb(VGA_REG_ADDR + VGA_ATR_AD, index);
usr/src/uts/i86pc/boot/boot_vga.c
323
outb(VGA_REG_ADDR + VGA_ATR_AD, val);
usr/src/uts/i86pc/boot/boot_vga.c
326
outb(VGA_REG_ADDR + VGA_ATR_AD, VGA_ATR_ENB_PLT);
usr/src/uts/i86pc/boot/boot_vga.c
335
outb(VGA_REG_ADDR + VGA_ATR_AD, index);
usr/src/uts/i86pc/boot/boot_vga.c
339
outb(VGA_REG_ADDR + VGA_ATR_AD, VGA_ATR_ENB_PLT);
usr/src/uts/i86pc/boot/boot_vga.c
347
outb(VGA_REG_ADDR + VGA_CRTC_ADR, index);
usr/src/uts/i86pc/boot/boot_vga.c
348
outb(VGA_REG_ADDR + VGA_CRTC_DATA, val);
usr/src/uts/i86pc/boot/boot_vga.c
354
outb(VGA_REG_ADDR + VGA_CRTC_ADR, index);
usr/src/uts/i86pc/cpu/amd_opteron/ao_mca.c
959
outb(asd_port, asd->asd_code);
usr/src/uts/i86pc/dboot/dboot_asm.h
35
extern void outb(int port, uint8_t value);
usr/src/uts/i86pc/dboot/dboot_printf.c
67
outb(0x64, 0xfe); /* this resets the system, see pc_reset() */
usr/src/uts/i86pc/io/apix/apix.c
594
outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
usr/src/uts/i86pc/io/apix/apix.c
595
outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
usr/src/uts/i86pc/io/isa.c
1179
outb(port + COM_SCR, (char)0x5a);
usr/src/uts/i86pc/io/isa.c
1180
outb(port + COM_ISR, (char)0x00);
usr/src/uts/i86pc/io/pci/pci_tools.c
704
outb(port, (uint8_t)local_data);
usr/src/uts/i86pc/io/pcplusmp/apic.c
518
outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
usr/src/uts/i86pc/io/pcplusmp/apic.c
519
outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1140
outb(PITCTL_PORT, PIT_C0 | PIT_LOADMODE | PIT_ENDSIGMODE);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1146
outb(PITCTR0_PORT, 0xFF);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1147
outb(PITCTR0_PORT, 0xFF);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1412
outb(CMOS_ADDR, SSB);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1413
outb(CMOS_DATA, 0);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1420
outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1421
outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1454
outb(CMOS_ADDR, RTC_REGA);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1456
outb(CMOS_DATA, (byte | EXT_BANK));
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1458
outb(CMOS_ADDR, PFR_REG);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1468
outb(CMOS_DATA, byte);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1478
outb(CMOS_DATA, byte);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1498
outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1501
outb(MISMIC_FLAG_REGISTER, byte);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1516
outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1517
outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1520
outb(MISMIC_FLAG_REGISTER, byte);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1542
outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1557
outb(sitka_bmc[i].port, sitka_bmc[i].data);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
455
outb(CMOS_ADDR, SSB);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
456
outb(CMOS_DATA, BIOS_SHUTDOWN);
usr/src/uts/i86pc/io/psm/psm_common.c
1005
outb(elcr_port, inb(elcr_port) | elcr_bit);
usr/src/uts/i86pc/io/psm/psm_common.c
1008
outb(elcr_port, inb(elcr_port) & ~elcr_bit);
usr/src/uts/i86pc/io/psm/uppc.c
1035
outb(SIMR_PORT, smask);
usr/src/uts/i86pc/io/psm/uppc.c
1041
outb(MIMR_PORT, mmask);
usr/src/uts/i86pc/io/psm/uppc.c
1063
outb(PITCTL_PORT, 0); /* latch counter 0 */
usr/src/uts/i86pc/io/psm/uppc.c
273
outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE));
usr/src/uts/i86pc/io/psm/uppc.c
274
outb(PITCTR0_PORT, (uchar_t)clkticks);
usr/src/uts/i86pc/io/psm/uppc.c
275
outb(PITCTR0_PORT, (uchar_t)(clkticks>>8));
usr/src/uts/i86pc/io/psm/uppc.c
580
outb(SIMR_PORT, sp->smask);
usr/src/uts/i86pc/io/psm/uppc.c
581
outb(MIMR_PORT, sp->mmask);
usr/src/uts/i86pc/io/psm/uppc.c
970
outb(MCMD_PORT, PIC_NSEOI);
usr/src/uts/i86pc/io/psm/uppc.c
972
outb(SCMD_PORT, PIC_NSEOI);
usr/src/uts/i86pc/io/psm/uppc.c
977
outb(MCMD_PORT, PIC_NSEOI);
usr/src/uts/i86pc/io/psm/uppc.c
983
outb(MCMD_PORT, PIC_NSEOI);
usr/src/uts/i86pc/io/psm/uppc.c
984
outb(SCMD_PORT, PIC_SEOI_LVL7);
usr/src/uts/i86pc/io/psm/uppc.c
986
outb(MCMD_PORT, PIC_SEOI_LVL7);
usr/src/uts/i86pc/io/todpc_subr.c
370
outb(RTC_ADDR, RTC_D); /* check if clock valid */
usr/src/uts/i86pc/io/todpc_subr.c
381
outb(RTC_ADDR, RTC_A); /* check if update in progress */
usr/src/uts/i86pc/io/todpc_subr.c
389
outb(RTC_ADDR, i);
usr/src/uts/i86pc/io/todpc_subr.c
392
outb(RTC_ADDR, century); /* do century */
usr/src/uts/i86pc/io/todpc_subr.c
396
outb(RTC_ADDR, day_alrm);
usr/src/uts/i86pc/io/todpc_subr.c
400
outb(RTC_ADDR, mon_alrm);
usr/src/uts/i86pc/io/todpc_subr.c
404
outb(RTC_ADDR, 0); /* re-read Seconds register */
usr/src/uts/i86pc/io/todpc_subr.c
434
outb(RTC_ADDR, RTC_B);
usr/src/uts/i86pc/io/todpc_subr.c
436
outb(RTC_ADDR, RTC_B);
usr/src/uts/i86pc/io/todpc_subr.c
437
outb(RTC_DATA, reg | RTC_SET); /* allow time set now */
usr/src/uts/i86pc/io/todpc_subr.c
439
outb(RTC_ADDR, i);
usr/src/uts/i86pc/io/todpc_subr.c
440
outb(RTC_DATA, buf[i]);
usr/src/uts/i86pc/io/todpc_subr.c
442
outb(RTC_ADDR, century); /* do century */
usr/src/uts/i86pc/io/todpc_subr.c
443
outb(RTC_DATA, ((struct rtc_t *)buf)->rtc_century);
usr/src/uts/i86pc/io/todpc_subr.c
446
outb(RTC_ADDR, day_alrm);
usr/src/uts/i86pc/io/todpc_subr.c
450
outb(RTC_DATA, tmp);
usr/src/uts/i86pc/io/todpc_subr.c
453
outb(RTC_ADDR, mon_alrm);
usr/src/uts/i86pc/io/todpc_subr.c
454
outb(RTC_DATA, ((struct rtc_t *)buf)->rtc_amon);
usr/src/uts/i86pc/io/todpc_subr.c
457
outb(RTC_ADDR, RTC_B);
usr/src/uts/i86pc/io/todpc_subr.c
459
outb(RTC_ADDR, RTC_B);
usr/src/uts/i86pc/io/todpc_subr.c
460
outb(RTC_DATA, reg & ~RTC_SET); /* allow time update */
usr/src/uts/i86pc/os/graphics.c
39
extern void outb(int, uchar_t);
usr/src/uts/i86pc/os/graphics.c
58
outb(0x3c4, 2);
usr/src/uts/i86pc/os/graphics.c
59
outb(0x3c5, plane);
usr/src/uts/i86pc/os/graphics.c
65
outb(0x3ce, 8);
usr/src/uts/i86pc/os/graphics.c
66
outb(0x3cf, value);
usr/src/uts/i86pc/os/pci_mech1.c
125
outb(PCI_CONFDATA | (reg & 0x3), val);
usr/src/uts/i86pc/os/pci_mech1_amd.c
167
outb(PCI_CONFDATA | (reg & 0x3), val);
usr/src/uts/i86pc/os/pci_mech2.c
132
outb(PCI_CADDR2(device, reg), val);
usr/src/uts/i86pc/os/pci_mech2.c
61
outb(PCI_CSE_PORT,
usr/src/uts/i86pc/os/pci_mech2.c
63
outb(PCI_FORW_PORT, bus);
usr/src/uts/i86pc/os/pci_mech2.c
71
outb(PCI_CSE_PORT, oldstatus);
usr/src/uts/i86pc/os/pci_neptune.c
105
outb(PCI_PMC, neptune_BIOS_cfg_method);
usr/src/uts/i86pc/os/pci_neptune.c
109
outb(PCI_PMC, neptune_BIOS_cfg_method);
usr/src/uts/i86pc/os/pci_neptune.c
120
outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
usr/src/uts/i86pc/os/pci_neptune.c
133
outb(PCI_PMC, neptune_BIOS_cfg_method);
usr/src/uts/i86pc/os/pci_neptune.c
59
outb(PCI_CSE_PORT, PCI_MECH2_CONFIG_ENABLE);
usr/src/uts/i86pc/os/pci_neptune.c
60
outb(PCI_FORW_PORT, 0);
usr/src/uts/i86pc/os/pci_neptune.c
74
outb(PCI_CSE_PORT, oldstatus);
usr/src/uts/i86pc/os/pci_neptune.c
79
outb(PCI_CSE_PORT, oldstatus);
usr/src/uts/i86pc/os/pci_neptune.c
99
outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
usr/src/uts/i86pc/os/tscc_pit.c
103
outb(PITCTL_PORT, PIT_READBACK | PIT_READBACKC0);
usr/src/uts/i86pc/os/tscc_pit.c
91
outb(PITCTL_PORT, PIT_C0 | PIT_LOADMODE | PIT_ENDSIGMODE);
usr/src/uts/i86pc/os/tscc_pit.c
93
outb(PITCTR0_PORT, 0xFF);
usr/src/uts/i86pc/os/tscc_pit.c
94
outb(PITCTR0_PORT, 0xFF);
usr/src/uts/i86xpv/io/psm/xpv_psm.c
269
outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
usr/src/uts/i86xpv/io/psm/xpv_psm.c
270
outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
usr/src/uts/intel/io/acpica/acpica_ec.c
176
outb(ec.ec_sc, EC_RD); /* output a read command */
usr/src/uts/intel/io/acpica/acpica_ec.c
184
outb(ec.ec_base, addr); /* output addr */
usr/src/uts/intel/io/acpica/acpica_ec.c
225
outb(ec.ec_sc, EC_WR); /* output a write command */
usr/src/uts/intel/io/acpica/acpica_ec.c
233
outb(ec.ec_base, addr); /* output addr */
usr/src/uts/intel/io/acpica/acpica_ec.c
241
outb(ec.ec_base, val); /* write data */
usr/src/uts/intel/io/acpica/acpica_ec.c
263
outb(ec.ec_sc, EC_QR); /* output a query command */
usr/src/uts/intel/io/acpica/osl.c
875
outb(Address, Value);
usr/src/uts/intel/io/fdc.c
1000
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1016
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1027
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1638
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1641
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1658
outb(fcp->c_regbase + FCR_DATA, *oplistp++);
usr/src/uts/intel/io/fdc.c
1683
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1686
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1796
outb(fcp->c_regbase + FCR_CCR, fcp->c_config);
usr/src/uts/intel/io/fdc.c
1867
outb(fcp->c_regbase + FCR_DOR, deselect);
usr/src/uts/intel/io/fdc.c
1901
outb(fcp->c_regbase + FCR_DOR, deselect);
usr/src/uts/intel/io/fdc.c
1907
outb(fcp->c_regbase + FCR_SRA, enable_code);
usr/src/uts/intel/io/fdc.c
1908
outb(fcp->c_regbase + FCR_SRA, enable_code);
usr/src/uts/intel/io/fdc.c
1911
outb(fcp->c_regbase + FCR_SRA, FSA_CR5);
usr/src/uts/intel/io/fdc.c
1914
outb(fcp->c_regbase + FCR_SRB, enable_code | ds_code);
usr/src/uts/intel/io/fdc.c
1917
outb(fcp->c_regbase + FCR_SRA, FSA_DISB);
usr/src/uts/intel/io/fdc.c
1919
outb(fcp->c_regbase + FCR_SRA, save);
usr/src/uts/intel/io/fdc.c
1924
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1956
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
1982
outb(fcp->c_regbase + FCR_DOR, fcp->c_digout);
usr/src/uts/intel/io/fdc.c
3149
outb(fcp->c_regbase + FCR_DATA, *oplistp++);
usr/src/uts/intel/io/fdc.c
729
outb(fcp->c_regbase + FCR_CCR, ccr);
usr/src/uts/intel/io/fdc.c
739
outb(fcp->c_regbase + FCR_CCR, 0);
usr/src/uts/intel/io/fdc.c
784
outb(fcp->c_regbase + FCR_SRA, FSA_ENA5);
usr/src/uts/intel/io/fdc.c
785
outb(fcp->c_regbase + FCR_SRA, FSA_ENA5);
usr/src/uts/intel/io/fdc.c
788
outb(fcp->c_regbase + FCR_SRA, 0x0F);
usr/src/uts/intel/io/fdc.c
792
outb(fcp->c_regbase + FCR_SRA, 0x0D);
usr/src/uts/intel/io/fdc.c
796
outb(fcp->c_regbase + FCR_SRA, 0x0E);
usr/src/uts/intel/io/fdc.c
807
outb(fcp->c_regbase + FCR_SRA, FSA_DISB);
usr/src/uts/intel/io/fdc.c
812
outb(fcp->c_regbase + FCR_SRA, FSA_ENA6);
usr/src/uts/intel/io/fdc.c
813
outb(fcp->c_regbase + FCR_SRA, FSA_ENA6);
usr/src/uts/intel/io/fdc.c
816
outb(fcp->c_regbase + FCR_SRA, 0x0F);
usr/src/uts/intel/io/fdc.c
820
outb(fcp->c_regbase + FCR_SRA, 0x0D);
usr/src/uts/intel/io/fdc.c
824
outb(fcp->c_regbase + FCR_SRA, 0x0E);
usr/src/uts/intel/io/fdc.c
835
outb(fcp->c_regbase + FCR_SRA, FSA_DISB);
usr/src/uts/intel/io/fdc.c
838
outb(fcp->c_regbase + FCR_SRA, save);
usr/src/uts/intel/io/i8237A.c
193
outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);
usr/src/uts/intel/io/i8237A.c
212
outb(chan_addr[chnl].mask_reg, chnl & 3);
usr/src/uts/intel/io/i8237A.c
295
outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);
usr/src/uts/intel/io/i8237A.c
300
outb(chan_addr[chnl].scm_reg, chnl);
usr/src/uts/intel/io/i8237A.c
387
outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
usr/src/uts/intel/io/i8237A.c
470
outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
usr/src/uts/intel/io/i8237A.c
494
outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */
usr/src/uts/intel/io/i8237A.c
513
outb(chan_addr[chnl].reqt_reg, chnl & 3); /* reset request bit */
usr/src/uts/intel/io/i8237A.c
605
outb(chan_addr[chnl].mode_reg, mode);
usr/src/uts/intel/io/i8237A.c
643
outb(chan_addr[chnl].emode_reg, emode);
usr/src/uts/intel/io/i8237A.c
687
outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
usr/src/uts/intel/io/i8237A.c
690
outb(chan_addr[chnl].addr_reg, adr_byte[0]);
usr/src/uts/intel/io/i8237A.c
691
outb(chan_addr[chnl].addr_reg, adr_byte[1]);
usr/src/uts/intel/io/i8237A.c
692
outb(chan_addr[chnl].page_reg, adr_byte[2]);
usr/src/uts/intel/io/i8237A.c
694
outb(chan_addr[chnl].hpage_reg, adr_byte[3]);
usr/src/uts/intel/io/i8237A.c
718
outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
usr/src/uts/intel/io/i8237A.c
787
outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
usr/src/uts/intel/io/i8237A.c
790
outb(chan_addr[chnl].cnt_reg, count_byte[0]);
usr/src/uts/intel/io/i8237A.c
791
outb(chan_addr[chnl].cnt_reg, count_byte[1]);
usr/src/uts/intel/io/i8237A.c
793
outb(chan_addr[chnl].hcnt_reg, count_byte[2]);
usr/src/uts/intel/io/i8237A.c
817
outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
usr/src/uts/intel/io/ipmi/ipmivars.h
186
outb((sc)->ipmi_io_address + ((sc)->ipmi_io_spacing * (x)), value)
usr/src/uts/intel/io/pic.c
40
(void) outb(MCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
usr/src/uts/intel/io/pic.c
43
(void) outb(MIMR_PORT, PIC_VECTBASE);
usr/src/uts/intel/io/pic.c
46
(void) outb(MIMR_PORT, 1 << MASTERLINE);
usr/src/uts/intel/io/pic.c
49
(void) outb(MIMR_PORT, PIC_86MODE);
usr/src/uts/intel/io/pic.c
52
(void) outb(MIMR_PORT, 0xFF);
usr/src/uts/intel/io/pic.c
55
(void) outb(MCMD_PORT, PIC_READISR);
usr/src/uts/intel/io/pic.c
59
(void) outb(SCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
usr/src/uts/intel/io/pic.c
62
outb(SIMR_PORT, PIC_VECTBASE + 8);
usr/src/uts/intel/io/pic.c
65
outb(SIMR_PORT, MASTERLINE);
usr/src/uts/intel/io/pic.c
68
outb(SIMR_PORT, PIC_86MODE);
usr/src/uts/intel/io/pic.c
71
outb(SIMR_PORT, 0xff);
usr/src/uts/intel/io/pic.c
74
outb(SCMD_PORT, PIC_READISR);
usr/src/uts/intel/io/pit_beep.c
268
outb(PITCTL_PORT, PIT_C2 | PIT_READMODE | PIT_RATEMODE);
usr/src/uts/intel/io/pit_beep.c
269
outb(PITCTR2_PORT, counter & 0xff);
usr/src/uts/intel/io/pit_beep.c
270
outb(PITCTR2_PORT, counter >> 8);
usr/src/uts/intel/io/pit_beep.c
278
outb(PITAUX_PORT, inb(PITAUX_PORT) | (PITAUX_OUT2 | PITAUX_GATE2));
usr/src/uts/intel/io/pit_beep.c
286
outb(PITAUX_PORT, inb(PITAUX_PORT) & ~(PITAUX_OUT2 | PITAUX_GATE2));
usr/src/uts/intel/os/ddi_i86.c
1127
outb((uintptr_t)addr, value);
usr/src/uts/intel/os/ddi_i86.c
1577
outb(port, *h++);
usr/src/uts/intel/os/ddi_i86.c
1580
outb(port, *h++);
usr/src/uts/intel/sys/archsystm.h
223
extern void outb(int port, uint8_t value);