PORT_MAX
if (strtonum(uport, PORT_MIN, PORT_MAX,
lo = strtonum(token, PORT_MIN, PORT_MAX, &errstr);
hi = strtonum(n, PORT_MIN, PORT_MAX, &errstr);
for (int i = 0; i < PORT_MAX; i++) {
for (int i = 0; i < PORT_MAX; i++) {
cmpci_port_t port[PORT_MAX];
#define PORT_MAX PORT_ADC
audioens_port_t port[PORT_MAX + 1];
for (int i = 0; i <= PORT_MAX; i++) {
for (i = 0; i <= PORT_MAX; i++) {
for (i = 0; i < PORT_MAX; i++) {
for (i = 0; i < PORT_MAX; i++) {
audiohd_port_t *port[PORT_MAX];
audiopci_port_t port[PORT_MAX + 1];
for (int i = 0; i <= PORT_MAX; i++) {
for (i = 0; i <= PORT_MAX; i++) {
#define PORT_MAX PORT_ADC
struct elink_phy phy[PORT_MAX];
struct elink_phy *phy_blk[PORT_MAX];
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
for (port = 0; port < PORT_MAX; port++) {
struct elink_phy phy[PORT_MAX];
struct elink_phy *phy_blk[PORT_MAX];
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
ASSERT_STATIC( 2 == PORT_MAX );
ASSERT_STATIC( 2 == PORT_MAX );
u32_t max_toe_cons[PORT_MAX] = {0,0};
u32_t max_rdma_cons[PORT_MAX] = {0,0};
u32_t max_iscsi_cons[PORT_MAX] = {0,0};
u32_t max_fcoe_cons[PORT_MAX] = {0,0};
u32_t max_eth_cons[PORT_MAX] = {0,0}; /* Includes VF connections */
u32_t max_bar_supported_cons[PORT_MAX] = {0};
u32_t max_supported_cons[PORT_MAX] = {0};
for (port = 0; port < PORT_MAX; port++)
u8_t port_max = (port_mode == LM_CHIP_PORT_MODE_2)? 1 : PORT_MAX;
ASSERT_STATIC((FIELD_SIZE(struct shm_dev_info, port_hw_config)/FIELD_SIZE(struct shm_dev_info, port_hw_config[0])) >= max(PORT_MAX,1));
port_base_aux_qzone = PORT_ID(pdev)* ((ETH_MAX_RX_CLIENTS_E2 - PXP_REG_HST_ZONE_PERMISSION_TABLE_SIZE)/PORT_MAX);
port_id = abs_func % PORT_MAX;
for (port = PORT_0; port < PORT_MAX; port++)
static const u32_t offset_base_wb[PORT_MAX] = { NIG_REG_LLH0_ACPI_BE_MEM_DATA, NIG_REG_LLH1_ACPI_BE_MEM_DATA };
ASSERT_STATIC( 2 == PORT_MAX );
DbgBreakIf( idx_port >= PORT_MAX );
port_max = PORT_MAX;
wait_itr = 240 * FW_ACK_NUM_OF_POLL * PORT_MAX * (u32_t)(IS_MULTI_VNIC(pdev) ? MAX_VNIC_NUM : 1);
PORT_MAX * sizeof(lldp_params_t) + \
struct bdn_netport netport[PORT_MAX * NVM_PATH_MAX];
struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
pNcsiChannelData_t pChannelSpecific[PATH_SUPPORTED * PORT_MAX]; //8 bytes
NcsiChannelData_t ChannelData[PORT_MAX]; // 420 bytes total 288 bytes (2 data blocks)
port_hw_cfg_t port_hw_config[PORT_MAX]; /* 0x12c(400*2=0x320) */
port_feat_cfg_t port_feature_config[PORT_MAX]; /* 0x454 (116*2=0xe8) */
upgrade_key_info_t upgrade_key_info[PORT_MAX]; /* 0x640 (100*2=0xc8) */
manuf_key_info_t manuf_key_info[PORT_MAX]; /* 0x708 (112*2=0xe0) */
struct macp_port_cfg port_cfg[NVM_PATH_MAX][PORT_MAX];
struct niv_port_cfg port_cfg[NVM_PATH_MAX][PORT_MAX]; // per port config
struct niv_port_profiles_cfg port_cfg[PORT_MAX]; // per port config
u32 dcbx_en[PORT_MAX];
struct eee_remote_vals eee_remote_vals[PORT_MAX];
u32 eee_status[PORT_MAX];
u32 lfa_host_addr[PORT_MAX];
u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
u32 link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */