#ifndef __SA_H__
#define __SA_H__
#include <dev/pms/RefTisa/sallsdk/api/sa_spec.h>
#include <dev/pms/RefTisa/sallsdk/api/sa_err.h>
#define SA_CONFIG_MDFD_REGISTRY
#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \
(bitptr)&(((STRUCT_TYPE *)0)->FEILD)
#if defined(SA_CPU_LITTLE_ENDIAN)
#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
(*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
(*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
(*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
(*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
(*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
(*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
(*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
(*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
(*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
(*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
#elif defined(SA_CPU_BIG_ENDIAN)
#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
(*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
(*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
(*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
(*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
(*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
(*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
(*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
(*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
(*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
(*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
(*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
#else
#error (Host CPU endianess undefined!!)
#endif
#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \
OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \
OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \
OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \
OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved);
#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
((((bit16)(_x))&0xFF00)>>8)))
#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
((((bit32)(_x))&0x0000FF00)<<8)| \
((((bit32)(_x))&0x00FF0000)>>8)| \
((((bit32)(_x))&0xFF000000)>>24)))
#if defined(SA_CPU_LITTLE_ENDIAN)
#ifndef LEBIT16_TO_BIT16
#define LEBIT16_TO_BIT16(_x) (_x)
#endif
#ifndef BIT16_TO_LEBIT16
#define BIT16_TO_LEBIT16(_x) (_x)
#endif
#ifndef BEBIT16_TO_BIT16
#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BIT16_TO_BEBIT16
#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef LEBIT32_TO_BIT32
#define LEBIT32_TO_BIT32(_x) (_x)
#endif
#ifndef BIT32_TO_LEBIT32
#define BIT32_TO_LEBIT32(_x) (_x)
#endif
#ifndef BEBIT32_TO_BIT32
#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT32_TO_BEBIT32
#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT8_TO_BIT32_B0
#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x))
#endif
#ifndef BIT8_TO_BIT32_B1
#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8)
#endif
#ifndef BIT8_TO_BIT32_B2
#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16)
#endif
#ifndef BIT8_TO_BIT32_B3
#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24)
#endif
#ifndef BIT32_B0_TO_BIT8
#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
#endif
#ifndef BIT32_B1_TO_BIT8
#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
#endif
#ifndef BIT32_B2_TO_BIT8
#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
#endif
#ifndef BIT32_B3_TO_BIT8
#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
#endif
#elif defined(SA_CPU_BIG_ENDIAN)
#ifndef LEBIT16_TO_BIT16
#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BIT16_TO_LEBIT16
#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BEBIT16_TO_BIT16
#define BEBIT16_TO_BIT16(_x) (_x)
#endif
#ifndef BIT16_TO_BEBIT16
#define BIT16_TO_BEBIT16(_x) (_x)
#endif
#ifndef LEBIT32_TO_BIT32
#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT32_TO_LEBIT32
#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BEBIT32_TO_BIT32
#define BEBIT32_TO_BIT32(_x) (_x)
#endif
#ifndef BIT32_TO_BEBIT32
#define BIT32_TO_BEBIT32(_x) (_x)
#endif
#ifndef BIT8_TO_BIT32_B0
#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24)
#endif
#ifndef BIT8_TO_BIT32_B1
#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16)
#endif
#ifndef BIT8_TO_BIT32_B2
#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8)
#endif
#ifndef BIT8_TO_BIT32_B3
#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x))
#endif
#ifndef BIT32_B0_TO_BIT8
#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
#endif
#ifndef BIT32_B1_TO_BIT8
#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
#endif
#ifndef BIT32_B2_TO_BIT8
#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
#endif
#ifndef BIT32_B3_TO_BIT8
#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
#endif
#else
#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
#endif
#if defined(SA_DMA_LITTLE_ENDIAN)
#ifndef DMA_BIT32_TO_BIT32
#define DMA_BIT32_TO_BIT32(_x) (_x)
#endif
#ifndef DMA_LEBIT32_TO_BIT32
#define DMA_LEBIT32_TO_BIT32(_x) (_x)
#endif
#ifndef DMA_BEBIT32_TO_BIT32
#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT32_TO_DMA_BIT32
#define BIT32_TO_DMA_BIT32(_x) (_x)
#endif
#ifndef BIT32_TO_DMA_LEBIT32
#define BIT32_TO_DMA_LEBIT32(_x) (_x)
#endif
#ifndef BIT32_TO_DMA_BEBIT32
#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef DMA_BIT16_TO_BIT16
#define DMA_BIT16_TO_BIT16(_x) (_x)
#endif
#ifndef DMA_LEBIT16_TO_BIT16
#define DMA_LEBIT16_TO_BIT16(_x) (_x)
#endif
#ifndef DMA_BEBIT16_TO_BIT16
#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BIT16_TO_DMA_BIT16
#define BIT16_TO_DMA_BIT16(_x) (_x)
#endif
#ifndef BIT16_TO_DMA_LEBIT16
#define BIT16_TO_DMA_LEBIT16(_x) (_x)
#endif
#ifndef BIT16_TO_DMA_BEBIT16
#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#if defined(SA_CPU_LITTLE_ENDIAN)
#ifndef BEBIT32_TO_DMA_BEBIT32
#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
#endif
#ifndef LEBIT32_TO_DMA_LEBIT32
#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
#endif
#ifndef DMA_LEBIT32_TO_LEBIT32
#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
#endif
#ifndef DMA_BEBIT32_TO_BEBIT32
#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
#endif
#ifndef BEBIT16_TO_DMA_BEBIT16
#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
#endif
#ifndef LEBIT16_TO_DMA_LEBIT16
#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
#endif
#ifndef DMA_LEBIT16_TO_LEBIT16
#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
#endif
#ifndef DMA_BEBIT16_TO_BEBIT16
#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
#endif
#else
#ifndef BEBIT32_TO_DMA_BEBIT32
#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef LEBIT32_TO_DMA_LEBIT32
#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef DMA_LEBIT32_TO_LEBIT32
#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef DMA_BEBIT32_TO_BEBIT32
#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BEBIT16_TO_DMA_BEBIT16
#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef LEBIT16_TO_DMA_LEBIT16
#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef DMA_LEBIT16_TO_LEBIT16
#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef DMA_BEBIT16_TO_BEBIT16
#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#endif
#ifndef BIT8_TO_DMA_BIT32_B0
#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x))
#endif
#ifndef BIT8_TO_DMA_BIT32_B1
#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8)
#endif
#ifndef BIT8_TO_DMA_BIT32_B2
#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16)
#endif
#ifndef BIT8_TO_DMA_BIT32_B3
#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24)
#endif
#ifndef DMA_BIT32_B0_TO_BIT8
#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
#endif
#ifndef DMA_BIT32_B1_TO_BIT8
#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
#endif
#ifndef DMA_BIT32_B2_TO_BIT8
#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
#endif
#ifndef DMA_BIT32_B3_TO_BIT8
#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
#endif
#elif defined(SA_DMA_BIG_ENDIAN)
#ifndef DMA_BEBIT32_TO_BIT32
#define DMA_BEBIT32_TO_BIT32(_x) (_x)
#endif
#ifndef DMA_LEBIT32_TO_BIT32
#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT32_TO_DMA_BIT32
#define BIT32_TO_DMA_BIT32(_x) (_x)
#endif
#ifndef BIT32_TO_DMA_LEBIT32
#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BIT32_TO_DMA_BEBIT32
#define BIT32_TO_DMA_BEBIT32(_x) (_x)
#endif
#ifndef DMA_BEBIT16_TO_BIT16
#define DMA_BEBIT16_TO_BIT16(_x) (_x)
#endif
#ifndef DMA_LEBIT16_TO_BIT16
#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BIT16_TO_DMA_BIT16
#define BIT16_TO_DMA_BIT16(_x) (_x)
#endif
#ifndef BIT16_TO_DMA_LEBIT16
#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef BIT16_TO_DMA_BEBIT16
#define BIT16_TO_DMA_BEBIT16(_x) (_x)
#endif
#if defined(SA_CPU_LITTLE_ENDIAN)
#ifndef BEBIT32_TO_DMA_BEBIT32
#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef LEBIT32_TO_DMA_LEBIT32
#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef DMA_LEBIT32_TO_LEBIT32
#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef DMA_BEBIT32_TO_BEBIT32
#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
#endif
#ifndef BEBIT16_TO_DMA_BEBIT16
#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef LEBIT16_TO_DMA_LEBIT16
#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef DMA_LEBIT16_TO_LEBIT16
#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#ifndef DMA_BEBIT16_TO_BEBIT16
#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
#endif
#else
#ifndef BEBIT32_TO_DMA_BEBIT32
#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
#endif
#ifndef LEBIT32_TO_DMA_LEBIT32
#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
#endif
#ifndef DMA_LEBIT32_TO_LEBIT32
#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
#endif
#ifndef DMA_BEBIT32_TO_BEBIT32
#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
#endif
#ifndef BEBIT16_TO_DMA_BEBIT16
#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
#endif
#ifndef LEBIT16_TO_DMA_LEBIT16
#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
#endif
#ifndef DMA_LEBIT16_TO_LEBIT16
#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
#endif
#ifndef DMA_BEBIT16_TO_BEBIT16
#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
#endif
#endif
#ifndef BIT8_TO_DMA_BIT32_B0
#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24)
#endif
#ifndef BIT8_TO_DMA_BIT32_B1
#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16)
#endif
#ifndef BIT8_TO_DMA_BIT32_B2
#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8)
#endif
#ifndef BIT8_TO_DMA_BIT32_B3
#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x))
#endif
#ifndef DMA_BIT32_B0_TO_BIT8
#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
#endif
#ifndef DMA_BIT32_B1_TO_BIT8
#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
#endif
#ifndef DMA_BIT32_B2_TO_BIT8
#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
#endif
#ifndef DMA_BIT32_B3_TO_BIT8
#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
#endif
#else
#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN
#endif
#define FW_THIS_VERSION_SPC12G 0x03060005
#define FW_THIS_VERSION_SPC6G 0x02092400
#define FW_THIS_VERSION_SPC 0x01110000
#define STSDK_LL_INTERFACE_VERSION 0x20A
#define STSDK_LL_OLD_INTERFACE_VERSION 0x1
#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G
#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G
#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G
#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000
#define STSDK_LL_12G_INTERFACE_VERSION 0x302
#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G
#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G
#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G
#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000
#define STSDK_LL_SPC_VERSION 0x01100000
#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC
#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502
#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00
#define AGSA_RC_SUCCESS 0x00
#define AGSA_RC_FAILURE 0x01
#define AGSA_RC_BUSY 0x02
#define AGSA_RC_HDA_NO_FW_RUNNING 0x03
#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04
#define AGSA_RC_VERSION_INCOMPATIBLE 0x05
#define AGSA_RC_VERSION_UNTESTED 0x06
#define AGSA_RC_NOT_SUPPORTED 0x07
#define AGSA_RC_COMPLETE 0x08
#define AGSA_CACHED_MEM 0x00
#define AGSA_DMA_MEM 0x01
#define AGSA_CACHED_DMA_MEM 0x02
#ifdef SA_ENABLE_TRACE_FUNCTIONS
#ifdef FAST_IO_TEST
#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
#else
#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
#endif
#else
#ifdef FAST_IO_TEST
#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
#else
#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
#endif
#endif
#define AGSA_MAX_VALID_PHYS 16
#define MAX_ESGL_ENTRIES 10
#define AGSA_MAX_INBOUND_Q 64
#define AGSA_MAX_OUTBOUND_Q 64
#define AGSA_MAX_BEST_INBOUND_Q 16
#define AGSA_PHY_LINK_RESET 0x01
#define AGSA_PHY_HARD_RESET 0x02
#define AGSA_PHY_GET_ERROR_COUNTS 0x03
#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04
#define AGSA_PHY_GET_BW_COUNTS 0x05
#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10
#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12
#define AGSA_PHY_COMINIT_OOB 0x20
#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01
#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02
#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03
#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05
#define AGSA_PHY_SNW3_PAGE 0x06
#define AGSA_PHY_RATE_CONTROL_PAGE 0x07
#define AGSA_SAS_PHY_MISC_PAGE 0x08
#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08
#define AGSA_CHIP_RESET 0x00
#define AGSA_SOFT_RESET 0x01
#define AG_SA_DISCOVERY_TYPE_SAS 0x00
#define AG_SA_DISCOVERY_TYPE_SATA 0x01
#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00
#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01
#define AG_SA_DISCOVERY_OPTION_ABORT 0x02
#define AGSA_REQTYPE_MASK 0xF0000000
#define AGSA_REQ_TYPE_UNKNOWN 0x00000000
#define AGSA_SSP_REQTYPE 0x80000000
#define AGSA_SMP_REQTYPE 0x40000000
#define AGSA_SATA_REQTYPE 0x20000000
#define AGSA_DIR_MASK 0x00000300
#define AGSA_AUTO_MASK 0x00000080
#define AGSA_SATA_ATAP_MASK 0x0000FC00
#define AGSA_DIR_NONE 0x00000000
#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100
#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200
#define AGSA_AUTO_GOOD_RESPONSE 0x00000080
#define AGSA_SSP_INIT 0x00000001
#define AGSA_SSP_TGT_MODE 0x00000003
#define AGSA_SSP_TASK_MGNT 0x00000005
#define AGSA_SSP_TGT_RSP 0x00000006
#define AGSA_SMP_INIT 0x00000007
#define AGSA_SMP_TGT 0x00000008
#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT)
#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT)
#define AGSA_MSG 0x00000010
#define AGSA_SSP_EXT_BIT 0x00000020
#define AGSA_SSP_INDIRECT_BIT 0x00000040
#define AGSA_MSG_BIT AGSA_MSG >> 2
#define AGSA_INDIRECT_CDB_BIT 0x00000008
#define AGSA_SKIP_MASK_BIT 0x00000010
#define AGSA_ENCRYPT_BIT 0x00000020
#define AGSA_DIF_BIT 0x00000040
#define AGSA_DIF_LA_BIT 0x00000080
#define AGSA_DIRECTION_BITS 0x00000300
#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000
#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000
#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000
#define AGSA_SSP_TGT_BITS_ODS 0x00008000
#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000
#define AGSA_SSP_TGT_BITS_DEE 0x00002000
#define AGSA_SSP_TGT_BITS_R 0x00001000
#define AGSA_SSP_TGT_BITS_DAD 0x00000600
#define AGSA_SSP_TGT_BITS_DIR 0x00000300
#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100
#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200
#define AGSA_SSP_TGT_BITS_AGR 0x00000080
#define AGSA_SSP_TGT_BITS_RDF 0x00000040
#define AGSA_SSP_TGT_BITS_RTE 0x00000030
#define AGSA_SSP_TGT_BITS_AN 0x00000006
#define AGSA_DIF_UPDATE_BITS 0xFC000000
#define AGSA_DIF_VERIFY_BITS 0x03F00000
#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000
#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040
#define AGSA_DIF_CRC_SEED_BIT 0x00000020
#define AGSA_DIF_CRC_INVERT_BIT 0x00000010
#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008
#define AGSA_DIF_OP_BITS 0x00000007
#define AGSA_DIF_OP_INSERT 0x00000000
#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001
#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002
#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003
#define AGSA_DIF_OP_RESERVED2 0x00000004
#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005
#define AGSA_DIF_OP_RESERVED3 0x00000006
#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007
#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000
#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010
#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C
#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002
#define AGSA_ENCRYPT_ECB_Mode 0
#define AGSA_ENCRYPT_XTS_Mode 0x6
#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0
#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F
#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT)
#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT)
#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT)
#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT)
#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP)
#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT)
#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT)
#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG)
#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG)
#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG)
#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT)
#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT)
#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT)
#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT)
#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG)
#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG)
#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF
#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400
#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800
#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00
#define AGSA_SATA_ATAP_NON_DATA 0x00001000
#define AGSA_SATA_ATAP_PIO 0x00001400
#define AGSA_SATA_ATAP_DMA 0x00001800
#define AGSA_SATA_ATAP_NCQ 0x00001C00
#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000
#define AGSA_SATA_ATAP_PKT 0x00002400
#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA)
#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO)
#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA)
#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ)
#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO)
#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA)
#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ)
#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET)
#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT)
#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT)
#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT)
#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT)
#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT)
#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG)
#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG)
#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF
#define AGSA_IBQ_PRIORITY_NORMAL 0x0
#define AGSA_IBQ_PRIORITY_HIGH 0x1
#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F
#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001
#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002
#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004
#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008
#define AGSA_PHY_MODE_MASK 0x00000030
#define AGSA_PHY_MODE_SAS 0x00000010
#define AGSA_PHY_MODE_SATA 0x00000020
#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040
#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040
#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000
#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010
#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010
#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000
#define AGSA_DEV_INFO_RATE_MASK 0x0000000F
#define AGSA_DEV_INFO_RATE_1_5G 0x00000008
#define AGSA_DEV_INFO_RATE_3_0G 0x00000009
#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A
#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B
#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0
#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020
#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040
#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060
#define AGSA_ABORT_TASK 0x01
#define AGSA_ABORT_TASK_SET 0x02
#define AGSA_CLEAR_TASK_SET 0x04
#define AGSA_LOGICAL_UNIT_RESET 0x08
#define AGSA_IT_NEXUS_RESET 0x10
#define AGSA_CLEAR_ACA 0x40
#define AGSA_QUERY_TASK 0x80
#define AGSA_QUERY_TASK_SET 0x81
#define AGSA_QUERY_UNIT_ATTENTION 0x82
#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
#define AGSA_INVALID_FRAME 0x2
#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4
#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9
#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA
#define AGSA_SATA_BSY_OVERRIDE 0x00080000
#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000
#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40
#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36
#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001
#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004
#define AGSA_SATA_ENABLE_DIF 0x000008
#define AGSA_SATA_SKIP_QWORD 0xFFFF00
#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004
#define AGSA_SAS_ENABLE_DIF 0x0008
#ifdef SAFLAG_USE_DIF_ENC_IOMB
#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010
#endif
#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010
#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0
#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1
#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2
#define AGSA_PHY_CONTROL_DISABLE 0x3
#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5
#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6
#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7
#define AGSA_SAS_DIAG_START 0x1
#define AGSA_SAS_DIAG_END 0x0
#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1
#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2
#define AGSA_PORT_IO_ABORT 0x3
#define AGSA_PORT_SET_PORT_RESET_TIME 0x4
#define AGSA_PORT_HARD_RESET 0x5
#define AGSA_PORT_CLEAN_UP 0x6
#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7
#define SA_DS_OPERATIONAL 0x1
#define SA_DS_PORT_IN_RESET 0x2
#define SA_DS_IN_RECOVERY 0x3
#define SA_DS_IN_ERROR 0x4
#define SA_DS_NON_OPERATIONAL 0x7
#define OSSA_SUCCESS 0x00
#define OSSA_FAILURE 0x01
#define OSSA_RESET_PENDING 0x03
#define OSSA_CHIP_FAILED 0x04
#define OSSA_FREEZE_FAILED 0x05
#define OSSA_PHY_CONTROL_FAILURE 0x03
#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01
#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
#define OSSA_FAILURE_INVALID_PHY_ID 0x03
#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06
#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020
#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021
#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022
#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027
#define OSSA_ERR_PORT_INVALID 0x1041
#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042
#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
#define OSSA_ERR_PHY_ID_INVALID 0x1061
#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062
#define OSSA_INVALID_HANDLE 0x02
#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023
#define OSSA_ERR_DEVICE_BUSY 0x1024
#define OSSA_RC_ACCEPT 0x00
#define OSSA_RC_REJECT 0x01
#define OSSA_INVALID_STATE 0x0001
#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025
#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026
#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049
#define OSSA_DIAG_SUCCESS 0x00
#define OSSA_DIAG_INVALID_COMMAND 0x01
#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02
#define OSSA_DIAG_FAIL 0x02
#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03
#define OSSA_DIAG_INVALID_PHY 0x04
#define OSSA_MEMORY_ALLOC_FAILURE 0x05
#define OSSA_DIAG_SE_SUCCESS 0x00
#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01
#define OSSA_DIAG_PHY_NOT_DISABLED 0x02
#define OSSA_DIAG_OTHER_FAILURE 0x03
#define OSSA_DIAG_OPCODE_INVALID 0x03
#define OSSA_PORT_CONTROL_FAILURE 0x03
#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004
#define OSSA_MPI_ERR_PORT_INVALID 0x1041
#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043
#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044
#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045
#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047
#define GET_GSM_SM_INFO 0x02
#define GET_IOST_RB_INFO 0x03
#define OSSA_HW_EVENT_RESET_START 0x01
#define OSSA_HW_EVENT_RESET_COMPLETE 0x02
#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03
#define OSSA_HW_EVENT_SAS_PHY_UP 0x04
#define OSSA_HW_EVENT_SATA_PHY_UP 0x05
#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06
#define OSSA_HW_EVENT_PHY_DOWN 0x07
#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09
#define OSSA_HW_EVENT_PHY_ERROR 0x0A
#define OSSA_HW_EVENT_BROADCAST_SES 0x0B
#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C
#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D
#define OSSA_HW_EVENT_MALFUNCTION 0x0E
#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F
#define OSSA_HW_EVENT_BROADCAST_EXP 0x10
#define OSSA_HW_EVENT_PHY_START_STATUS 0x11
#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12
#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13
#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14
#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15
#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16
#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
#define OSSA_HW_EVENT_PORT_RECOVER 0x18
#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19
#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20
#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21
#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22
#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25
#define OSSA_HW_EVENT_ENCRYPTION 0x83
#define OSSA_HW_EVENT_MODE 0x84
#define OSSA_HW_EVENT_SECURITY_MODE 0x85
#define OSSA_PORT_NOT_ESTABLISHED 0x00
#define OSSA_PORT_VALID 0x01
#define OSSA_PORT_LOSTCOMM 0x02
#define OSSA_PORT_IN_RESET 0x04
#define OSSA_PORT_3RDPARTY_RESET 0x07
#define OSSA_PORT_INVALID 0x08
#define OSSA_CTL_SUCCESS 0x0000
#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001
#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002
#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004
#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005
#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX
#define OSSA_INBOUND_V_BIT_NOT_SET 0x01
#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02
#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03
#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01
#define OSSA_FLASH_UPDATE_HDR_ERR 0x02
#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03
#define OSSA_FLASH_UPDATE_CRC_ERR 0x04
#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05
#define OSSA_FLASH_UPDATE_HW_ERR 0x06
#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E
#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
#define OSSA_FLASH_UPDATE_DISABLED 0x11
#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12
#define OSSA_DISCOVER_STARTED 0x00
#define OSSA_DISCOVER_FOUND_DEVICE 0x01
#define OSSA_DISCOVER_REMOVED_DEVICE 0x02
#define OSSA_DISCOVER_COMPLETE 0x03
#define OSSA_DISCOVER_ABORT 0x04
#define OSSA_DISCOVER_ABORT_ERROR_1 0x05
#define OSSA_DISCOVER_ABORT_ERROR_2 0x06
#define OSSA_DISCOVER_ABORT_ERROR_3 0x07
#define OSSA_DISCOVER_ABORT_ERROR_4 0x08
#define OSSA_DISCOVER_ABORT_ERROR_5 0x09
#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A
#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B
#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C
#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D
#define OSSA_DEBUG_LEVEL_0 0x00
#define OSSA_DEBUG_LEVEL_1 0x01
#define OSSA_DEBUG_LEVEL_2 0x02
#define OSSA_DEBUG_LEVEL_3 0x03
#define OSSA_DEBUG_LEVEL_4 0x04
#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF
#define OSSA_FRAME_TYPE_SSP_CMD 0x06
#define OSSA_FRAME_TYPE_SSP_TASK 0x16
#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00
#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01
#define OSSA_DEV_INFO_INVALID_HANDLE 0x01
#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02
#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03
#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04
#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00
#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01
#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02
#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03
#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04
#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05
#define AGSA_CMD_DESC_PRBS 0x00
#define AGSA_CMD_DESC_CJTPAT 0x01
#define AGSA_CMD_DESC_USR_PATTERNS 0x02
#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08
#define AGSA_CMD_DESC_PRBS_INVERT 0x09
#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A
#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B
#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C
#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E
#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10
#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11
#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12
#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00
#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01
#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02
#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05
#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06
#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09
#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A
#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B
#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C
#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E
#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19
#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A
#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B
#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C
#define AGSA_CMD_DESC_ALL 0x1F
#define AGSA_NVMD_TWI_DEVICES 0x00
#define AGSA_NVMD_CONFIG_SEEPROM 0x01
#define AGSA_NVMD_VPD_FLASH 0x04
#define AGSA_NVMD_AAP1_REG_FLASH 0x05
#define AGSA_NVMD_IOP_REG_FLASH 0x06
#define AGSA_NVMD_EXPANSION_ROM 0x07
#define AGSA_NVMD_REG_FLASH 0x05
#define OSSA_NVMD_SUCCESS 0x0000
#define OSSA_NVMD_MODE_ERROR 0x0001
#define OSSA_NVMD_LENGTH_ERROR 0x0002
#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005
#define OSSA_NVMD_TWI_NACK_ERROR 0x2001
#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002
#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021
#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081
#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082
#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF
#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001
#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002
#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003
#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004
#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005
#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006
#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007
#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008
#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009
#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A
#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B
#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C
#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D
#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E
#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000
#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001
#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002
#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003
#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004
#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005
#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006
#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007
#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008
#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000
#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000
#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001
#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002
#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021
#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022
#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023
#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060
#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005
#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B
#define agsaEncryptSMF 0x00000000
#define agsaEncryptSMA 0x00000100
#define agsaEncryptSMB 0x00000200
#define agsaEncryptReturnSMF (1 << 12)
#define agsaEncryptAuthorize (1 << 13)
#define agsaEncryptAcmMask 0x00ff0000
#define agsaEncryptEnableAES_ECB (1 << 16)
#define agsaEncryptEnableAES_XTS (1 << 22)
#define agsaEncryptCipherModeECB 0x00000001
#define agsaEncryptCipherModeXTS 0x00000002
#define agsaEncryptStatusNoNVRAM 0x00000001
#define agsaEncryptStatusNVRAMErr 0x00000002
#define agsaEncryptSectorSize512 0
#define agsaEncryptSectorSize4096 2
#define agsaEncryptSectorSize4160 3
#define agsaEncryptSectorSize4224 4
#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18)
#define agsaEncryptDIFSectorSize528 ( 0x19)
#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18)
#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18)
#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18)
#define AGSA_ENCRYPT_STORE_NVRAM 1
#define agsaModePageGet 1
#define agsaModePageSet 2
#define AGSA_READ_SGPIO_REGISTER 0x02
#define AGSA_WRITE_SGPIO_REGISTER 0x82
#define AGSA_SGPIO_CONFIG_REG 0x0
#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1
#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2
#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3
#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4
#define OSSA_SGPIO_COMMAND_SUCCESS 0x00
#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04
#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05
#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06
#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19
#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82
#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83
#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D
#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D
#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D
#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C
#define OSSA_DFE_MPI_IO_SUCCESS 0x0000
#define OSSA_DFE_DATA_OVERFLOW 0x0002
#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004
#define OSSA_DFE_CHANNEL_DOWN 0x100E
#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F
#define OSSA_DFE_CHANNEL_INVALID 0x1010
#define OSSA_DFE_DMA_FAILURE 0x1011
typedef struct agsaContext_s
{
void *osData;
void *sdkData;
} agsaContext_t;
typedef agsaContext_t agsaRoot_t;
typedef agsaContext_t agsaDevHandle_t;
typedef agsaContext_t agsaPortContext_t;
typedef agsaContext_t agsaIORequest_t;
typedef void *agsaFrameHandle_t;
typedef struct agsaSASReconfig_s {
bit32 flags;
bit16 reserved0;
bit8 reserved1;
bit8 maxPorts;
bit16 openRejectRetriesCmd;
bit16 openRejectRetriesData;
bit16 reserved2;
bit16 sataHolTmo;
} agsaSASReconfig_t;
typedef struct agsaPhyAnalogSetupRegisters_s
{
bit32 spaRegister0;
bit32 spaRegister1;
bit32 spaRegister2;
bit32 spaRegister3;
bit32 spaRegister4;
bit32 spaRegister5;
bit32 spaRegister6;
bit32 spaRegister7;
bit32 spaRegister8;
bit32 spaRegister9;
} agsaPhyAnalogSetupRegisters_t;
#define MAX_INDEX 10
typedef struct agsaPhyAnalogSetupTable_s
{
agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX];
} agsaPhyAnalogSetupTable_t;
typedef struct agsaPhyAnalogSettingsPage_s
{
bit32 Dword0;
bit32 Dword1;
bit32 Dword2;
bit32 Dword3;
bit32 Dword4;
bit32 Dword5;
bit32 Dword6;
bit32 Dword7;
bit32 Dword8;
bit32 Dword9;
} agsaPhyAnalogSettingsPage_t;
typedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s
{
bit32 Dword0;
bit32 Dword1;
bit32 Dword2;
bit32 Dword3;
} agsaSASPhyOpenRejectRetryBackOffThresholdPage_t;
typedef struct agsaPhyRateControlPage_s
{
bit32 Dword0;
bit32 Dword1;
bit32 Dword2;
} agsaPhyRateControlPage_t;
typedef struct agsaRegDumpInfo_s
{
bit8 regDumpSrc;
bit8 regDumpNum;
bit8 reserved[2];
bit32 regDumpOffset;
bit32 directLen;
void *directData;
bit32 indirectAddrUpper32;
bit32 indirectAddrLower32;
bit32 indirectLen;
} agsaRegDumpInfo_t;
#define TYPE_GSM_SPACE 1
#define TYPE_QUEUE 2
#define TYPE_FATAL 3
#define TYPE_NON_FATAL 4
#define TYPE_INBOUND_QUEUE 5
#define TYPE_OUTBOUND_QUEUE 6
#define BAR_SHIFT_GSM_OFFSET 0x400000
#define ONE_MEGABYTE 0x100000
#define SIXTYFOURKBYTE (1024 * 64)
#define TYPE_INBOUND 1
#define TYPE_OUTBOUND 2
typedef struct
{
bit32 DataType;
union
{
struct
{
bit32 directLen;
bit32 directOffset;
bit32 readLen;
void *directData;
}gsmBuf;
struct
{
bit16 queueType;
bit16 queueIndex;
bit32 directLen;
void *directData;
}queueBuf;
struct
{
bit32 directLen;
bit32 directOffset;
bit32 readLen;
void *directData;
}dataBuf;
} BufferType;
} agsaForensicData_t;
typedef struct agsaNVMDData_s
{
bit32 indirectPayload :1;
bit32 reserved :7;
bit32 TWIDeviceAddress :8;
bit32 TWIBusNumber :4;
bit32 TWIDevicePageSize :4;
bit32 TWIDeviceAddressSize :4;
bit32 NVMDevice :4;
bit32 directLen :8;
bit32 dataOffsetAddress :24;
void *directData;
bit32 indirectAddrUpper32;
bit32 indirectAddrLower32;
bit32 indirectLen;
bit32 signature;
} agsaNVMDData_t;
#define OSSA_PCIE_DIAG_SUCCESS 0x0000
#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001
#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002
#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006
#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007
#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008
#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009
#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A
#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000
#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042
#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005
typedef struct agsaPCIeDiagExecute_s
{
bit32 command;
bit32 flags;
bit16 initialIOSeed;
bit16 reserved;
bit32 rdAddrLower;
bit32 rdAddrUpper;
bit32 wrAddrLower;
bit32 wrAddrUpper;
bit32 len;
bit32 pattern;
bit8 udtArray[6];
bit8 udrtArray[6];
} agsaPCIeDiagExecute_t;
typedef struct agsaPCIeDiagResponse_s {
bit32 ERR_BLKH;
bit32 ERR_BLKL;
bit32 DWord8;
bit32 DWord9;
bit32 DWord10;
bit32 DWord11;
bit32 DIF_ERR;
} agsaPCIeDiagResponse_t;
typedef struct agsaFatalErrorInfo_s
{
bit32 errorInfo0;
bit32 errorInfo1;
bit32 errorInfo2;
bit32 errorInfo3;
bit32 regDumpBusBaseNum0;
bit32 regDumpOffset0;
bit32 regDumpLen0;
bit32 regDumpBusBaseNum1;
bit32 regDumpOffset1;
bit32 regDumpLen1;
} agsaFatalErrorInfo_t;
typedef struct agsaEventSource_s
{
agsaPortContext_t *agPortContext;
bit32 event;
bit32 param;
} agsaEventSource_t;
typedef struct agsaControllerInfo_s
{
bit32 signature;
bit32 fwInterfaceRev;
bit32 hwRevision;
bit32 fwRevision;
bit32 ilaRevision;
bit32 maxPendingIO;
bit32 maxDevices;
bit32 maxSgElements;
bit32 queueSupport;
bit8 phyCount;
bit8 controllerSetting;
bit8 PCILinkRate;
bit8 PCIWidth;
bit32 sasSpecsSupport;
bit32 sdkInterfaceRev;
bit32 sdkRevision;
} agsaControllerInfo_t;
typedef struct agsaControllerStatus_s
{
agsaFatalErrorInfo_t fatalErrorInfo;
bit32 interfaceState;
bit32 iqFreezeState0;
bit32 iqFreezeState1;
bit32 tickCount0;
bit32 tickCount1;
bit32 tickCount2;
bit32 phyStatus[8];
bit32 recoverableErrorInfo[8];
bit32 bootStatus;
bit16 bootComponentState[8];
} agsaControllerStatus_t;
typedef struct agsaGpioEventSetupInfo_s
{
bit32 gpioPinMask;
bit32 gpioEventLevel;
bit32 gpioEventRisingEdge;
bit32 gpioEventFallingEdge;
} agsaGpioEventSetupInfo_t;
typedef struct agsaGpioPinSetupInfo_t
{
bit32 gpioPinMask;
bit32 gpioInputEnabled;
bit32 gpioTypePart1;
bit32 gpioTypePart2;
} agsaGpioPinSetupInfo_t;
typedef struct agsaGpioWriteSetupInfo_s
{
bit32 gpioWritemask;
bit32 gpioWriteVal;
}agsaGpioWriteSetupInfo_t;
typedef struct agsaGpioReadInfo_s
{
bit32 gpioReadValue;
bit32 gpioInputEnabled;
bit32 gpioEventLevelChangePart1;
bit32 gpioEventLevelChangePart2;
bit32 gpioEventRisingEdgePart1;
bit32 gpioEventRisingEdgePart2;
bit32 gpioEventFallingEdgePart1;
bit32 gpioEventFallingEdgePart2;
}agsaGpioReadInfo_t;
typedef struct agsaSGpioReqResponse_s
{
bit8 smpFrameType;
bit8 function;
bit8 registerType;
bit8 registerIndex;
bit8 registerCount;
bit8 functionResult;
bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT];
} agsaSGpioReqResponse_t;
typedef struct agsaSGpioCfg0
{
bit8 reserved1;
bit8 version:4;
bit8 reserved2:4;
bit8 gpRegisterCount:4;
bit8 cfgRegisterCount:3;
bit8 gpioEnable:1;
bit8 supportedDriveCount;
} agsaSGpioCfg0_t;
typedef struct agsaSGpioCfg1{
bit8 reserved;
bit8 blinkGenA:4;
bit8 blinkGenB:4;
bit8 maxActOn:4;
bit8 forceActOff:4;
bit8 stretchActOn:4;
bit8 stretchActOff:4;
} agsaSGpioCfg1_t;
typedef struct agsaPhyConfig_s
{
bit32 phyProperties;
} agsaPhyConfig_t;
typedef struct agsaPhySNW3Page_s
{
bit32 LSNW3;
bit32 RSNW3;
} agsaPhySNW3Page_t;
typedef struct agsaPhyErrCounters_s
{
bit32 invalidDword;
bit32 runningDisparityError;
bit32 lossOfDwordSynch;
bit32 phyResetProblem;
bit32 elasticityBufferOverflow;
bit32 receivedErrorPrimitive;
bit32 inboundCRCError;
bit32 codeViolation;
} agsaPhyErrCounters_t;
typedef struct agsaPhyErrCountersPage_s
{
bit32 invalidDword;
bit32 runningDisparityError;
bit32 codeViolation;
bit32 lossOfDwordSynch;
bit32 phyResetProblem;
bit32 inboundCRCError;
} agsaPhyErrCountersPage_t;
typedef struct agsaPhyBWCountersPage_s
{
bit32 TXBWCounter;
bit32 RXBWCounter;
} agsaPhyBWCountersPage_t;
typedef struct agsaHwConfig_s
{
bit32 phyCount;
bit32 hwInterruptCoalescingTimer;
bit32 hwInterruptCoalescingControl;
bit32 intReassertionOption;
bit32 hwOption;
agsaPhyAnalogSetupTable_t phyAnalogConfig;
} agsaHwConfig_t;
typedef struct agsaSwConfig_s
{
bit32 maxActiveIOs;
bit32 numDevHandles;
bit32 smpReqTimeout;
bit32 numberOfEventRegClients;
bit32 sizefEventLog1;
bit32 sizefEventLog2;
bit32 eventLog1Option;
bit32 eventLog2Option;
bit32 fatalErrorInterruptEnable:1;
bit32 sgpioSupportEnable:1;
bit32 fatalErrorInterruptVector:8;
bit32 max_MSI_InterruptVectors:8;
bit32 max_MSIX_InterruptVectors:8;
bit32 legacyInt_X:1;
bit32 hostDirectAccessSupport:1;
bit32 hostDirectAccessMode:2;
bit32 enableDIF:1;
bit32 enableEncryption:1;
#ifdef SA_CONFIG_MDFD_REGISTRY
bit32 disableMDF;
#endif
bit32 param1;
bit32 param2;
void *param3;
void *param4;
bit32 stallUsec;
bit32 FWConfig;
bit32 PortRecoveryResetTimer;
void *mpiContextTable;
bit32 mpiContextTablelen;
#if defined(SALLSDK_DEBUG)
bit32 sallDebugLevel;
#endif
#ifdef SA_ENABLE_PCI_TRIGGER
bit32 PCI_trigger;
#endif
#ifdef SA_ENABLE_TRACE_FUNCTIONS
bit32 TraceDestination;
bit32 TraceBufferSize;
bit32 TraceMask;
#endif
} agsaSwConfig_t;
typedef struct agsaQueueInbound_s
{
bit32 elementCount:16;
bit32 elementSize:16;
bit32 priority:2;
bit32 reserved:30;
} agsaQueueInbound_t;
typedef struct agsaQueueOutbound_s
{
bit32 elementCount:16;
bit32 elementSize:16;
bit32 interruptDelay:16;
bit32 interruptCount:16;
bit32 interruptVectorIndex:8;
bit32 interruptEnable:1;
bit32 reserved:23;
} agsaQueueOutbound_t;
typedef struct agsaPhyCalibrationTbl_s
{
bit32 txPortConfig1;
bit32 txPortConfig2;
bit32 txPortConfig3;
bit32 txConfig1;
bit32 rvPortConfig1;
bit32 rvPortConfig2;
bit32 rvConfig1;
bit32 rvConfig2;
bit32 reserved[2];
} agsaPhyCalibrationTbl_t;
typedef struct agsaQueueConfig_s
{
bit16 numInboundQueues;
bit16 numOutboundQueues;
bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS];
bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS];
bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS];
bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS];
bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS];
bit8 iqNormalPriorityProcessingDepth;
bit8 iqHighPriorityProcessingDepth;
bit8 generalEventQueue;
bit8 tgtDeviceRemovedEventQueue;
bit32 queueOption;
agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q];
agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q];
} agsaQueueConfig_t;
#define OQ_SHARE_PATH_BIT 0x00000001
typedef struct agsaFwImg_s
{
bit8 *aap1Img;
bit32 aap1Len;
bit8 *ilaImg;
bit32 ilaLen;
bit8 *iopImg;
bit32 iopLen;
bit8 *istrImg;
bit32 istrLen;
} agsaFwImg_t;
typedef struct agsaMem_s
{
void *virtPtr;
void *osHandle;
bit32 phyAddrUpper;
bit32 phyAddrLower;
bit32 totalLength;
bit32 numElements;
bit32 singleElementLength;
bit32 alignment;
bit32 type;
bit32 reserved;
} agsaMem_t;
typedef struct agsaControllerEventLog_s
{
agsaMem_t eventLog1;
agsaMem_t eventLog2;
bit32 eventLog1Option;
bit32 eventLog2Option;
} agsaControllerEventLog_t;
#define DISABLE_LOGGING 0x0
#define CRITICAL_ERROR 0x1
#define WARNING 0x2
#define NOTICE 0x3
#define INFORMATION 0x4
#define DEBUGGING 0x5
typedef struct agsaSASDiagExecute_s
{
bit32 command;
bit32 param0;
bit32 param1;
bit32 param2;
bit32 param3;
bit32 param4;
bit32 param5;
} agsaSASDiagExecute_t;
typedef struct agsaSASPhyGeneralStatusPage_s
{
bit32 Dword0;
bit32 Dword1;
} agsaSASPhyGeneralStatusPage_t;
typedef struct agsaMemoryRequirement_s
{
bit32 count;
agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS];
} agsaMemoryRequirement_t;
typedef struct agsaSASAddressID_s
{
bit8 sasAddressLo[4];
bit8 sasAddressHi[4];
bit8 phyIdentifier;
} agsaSASAddressID_t;
typedef struct agsaDeviceInfo_s
{
bit16 smpTimeout;
bit16 it_NexusTimeout;
bit16 firstBurstSize;
bit8 reserved;
bit8 devType_S_Rate;
bit8 sasAddressHi[4];
bit8 sasAddressLo[4];
bit32 flag;
} agsaDeviceInfo_t;
#define DEV_INFO_MASK 0xFF
#define DEV_INFO_MCN_SHIFT 16
#define DEV_INFO_IR_SHIFT 20
#define RETRY_DEVICE_FLAG (1 << SHIFT0)
#define AWT_DEVICE_FLAG (1 << SHIFT1)
#define SSP_DEVICE_FLAG (1 << SHIFT20)
#define ATAPI_DEVICE_FLAG 0x200000
#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22)
#define DEV_LINK_RATE 0x3F
#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \
DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \
DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \
(((devInfo)->devType_S_Rate & 0xC0) >> 5)
#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \
*(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \
*(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
typedef struct agsaSATADeviceInfo_s
{
agsaDeviceInfo_t commonDevInfo;
bit8 connection;
bit8 portMultiplierField;
bit8 stpPhyIdentifier;
bit8 reserved;
bit8 signature[8];
} agsaSATADeviceInfo_t;
typedef struct agsaSASDeviceInfo_s
{
agsaDeviceInfo_t commonDevInfo;
bit8 initiator_ssp_stp_smp;
bit8 target_ssp_stp_smp;
bit32 numOfPhys;
bit8 phyIdentifier;
} agsaSASDeviceInfo_t;
#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT
#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT
#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT
#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT
#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \
(((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \
(((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \
(((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
#define SA_SASDEV_IS_SSP_TARGET(sasDev) \
(((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
#define SA_SASDEV_IS_STP_TARGET(sasDev) \
(((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
#define SA_SASDEV_IS_SMP_TARGET(sasDev) \
(((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \
(((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT)
typedef struct _SASG_DESCRIPTOR
{
bit32 sgLower;
bit32 sgUpper;
bit32 len;
} SASG_DESCRIPTOR, * PSASG_DESCRIPTOR;
typedef struct agsaSgl_s
{
bit32 sgLower;
bit32 sgUpper;
bit32 len;
bit32 extReserved;
} agsaSgl_t;
typedef struct agsaEsgl_s
{
agsaSgl_t descriptor[MAX_ESGL_ENTRIES];
} agsaEsgl_t;
#define MAX_CDB_LEN 32
typedef struct agsaSSPCmdInfoUnitExt_s
{
bit8 lun[8];
bit8 reserved1;
bit8 efb_tp_taskAttribute;
bit8 reserved2;
bit8 additionalCdbLen;
bit8 cdb[MAX_CDB_LEN];
} agsaSSPCmdInfoUnitExt_t ;
#define DIF_UDT_SIZE 6
#define AGSA_DIF_INSERT 0
#define AGSA_DIF_VERIFY_FORWARD 1
#define AGSA_DIF_VERIFY_DELETE 2
#define AGSA_DIF_VERIFY_REPLACE 3
#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5
#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7
#define agsaDIFSectorSize512 0
#define agsaDIFSectorSize520 1
#define agsaDIFSectorSize4096 2
#define agsaDIFSectorSize4160 3
typedef struct agsaDif_s
{
agBOOLEAN enableDIFPerLA;
bit32 flags;
bit16 initialIOSeed;
bit16 reserved;
bit32 DIFPerLAAddrLo;
bit32 DIFPerLAAddrHi;
bit16 DIFPerLARegion0SecCount;
bit16 Reserved2;
bit8 udtArray[DIF_UDT_SIZE];
bit8 udrtArray[DIF_UDT_SIZE];
} agsaDif_t;
#define DIF_FLAG_BITS_ACTION 0x00000007
#define DIF_FLAG_BITS_CRC_VER 0x00000008
#define DIF_FLAG_BITS_CRC_INV 0x00000010
#define DIF_FLAG_BITS_CRC_SEED 0x00000020
#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040
#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080
#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100
#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200
#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00
#define DIF_FLAG_BITS_EPRC 0x00001000
#define DIF_FLAG_BITS_Reserved 0x0000E000
#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000
#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16
#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000
#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000
#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000
#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000
#define DIF_FLAG_BITS_UDTVMASK 0x03F00000
#define DIF_FLAG_BITS_UDTV_SHIFT 20
#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000
#define DIF_FLAG_BITS_UDTUPSHIFT 26
typedef struct agsaEncryptDek_s
{
bit32 dekTable;
bit32 dekIndex;
} agsaEncryptDek_t;
typedef struct agsaEncrypt_s
{
agsaEncryptDek_t dekInfo;
bit32 kekIndex;
agBOOLEAN keyTagCheck;
agBOOLEAN enableEncryptionPerLA;
bit32 sectorSizeIndex;
bit32 cipherMode;
bit32 keyTag_W0;
bit32 keyTag_W1;
bit32 tweakVal_W0;
bit32 tweakVal_W1;
bit32 tweakVal_W2;
bit32 tweakVal_W3;
bit32 EncryptionPerLAAddrLo;
bit32 EncryptionPerLAAddrHi;
bit16 EncryptionPerLRegion0SecCount;
bit16 reserved;
} agsaEncrypt_t;
typedef struct agsaSSPInitiatorRequest_s
{
agsaSgl_t agSgl;
bit32 dataLength;
bit16 firstBurstSize;
bit16 flag;
agsaSSPCmdInfoUnit_t sspCmdIU;
agsaDif_t dif;
agsaEncrypt_t encrypt;
#ifdef SA_TESTBASE_EXTRA
bit16 bstIndex;
#endif
} agsaSSPInitiatorRequest_t;
typedef struct agsaSSPInitiatorRequestExt_s
{
agsaSgl_t agSgl;
bit32 dataLength;
bit16 firstBurstSize;
bit16 flag;
agsaSSPCmdInfoUnitExt_t sspCmdIUExt;
agsaDif_t dif;
agsaEncrypt_t encrypt;
} agsaSSPInitiatorRequestExt_t;
typedef struct agsaSSPInitiatorRequestIndirect_s
{
agsaSgl_t agSgl;
bit32 dataLength;
bit16 firstBurstSize;
bit16 flag;
bit32 sspInitiatorReqAddrUpper32;
bit32 sspInitiatorReqAddrLower32;
bit32 sspInitiatorReqLen;
agsaDif_t dif;
agsaEncrypt_t encrypt;
}agsaSSPInitiatorRequestIndirect_t;
typedef struct agsaSSPTargetRequest_s
{
agsaSgl_t agSgl;
bit32 dataLength;
bit32 offset;
bit16 agTag;
bit16 sspOption;
agsaDif_t dif;
} agsaSSPTargetRequest_t;
#define SSP_OPTION_BITS 0x3F
#define SSP_OPTION_ODS 0x8000
#define SSP_OPTION_OTHR_NO_RETRY 0
#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1
#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2
#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
#define SSP_OPTION_DATA_NO_RETRY 0
#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1
#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2
#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4)
#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5)
#define SSP_OPTION_ENCRYPT (1 << SHIFT6)
#define SSP_OPTION_DIF (1 << SHIFT7)
#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15)
typedef struct agsaSSPTargetResponse_s
{
bit32 agTag;
void *frameBuf;
bit32 respBufLength;
bit32 respBufUpper;
bit32 respBufLower;
bit32 respOption;
} agsaSSPTargetResponse_t;
#define RESP_OPTION_BITS 0x3
#define RESP_OPTION_ODS 0x8000
typedef struct agsaSMPFrame_s
{
void *outFrameBuf;
bit32 outFrameAddrUpper32;
bit32 outFrameAddrLower32;
bit32 outFrameLen;
bit32 inFrameAddrUpper32;
bit32 inFrameAddrLower32;
bit32 inFrameLen;
bit32 expectedRespLen;
bit32 flag;
} agsaSMPFrame_t;
#define smpFrameFlagDirectResponse 0
#define smpFrameFlagIndirectResponse 1
#define smpFrameFlagDirectPayload 0
#define smpFrameFlagIndirectPayload 2
typedef union agsaSASRequestBody_u
{
agsaSSPInitiatorRequest_t sspInitiatorReq;
agsaSSPInitiatorRequestExt_t sspInitiatorReqExt;
agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect;
agsaSSPTargetRequest_t sspTargetReq;
agsaSSPScsiTaskMgntReq_t sspTaskMgntReq;
agsaSSPTargetResponse_t sspTargetResponse;
agsaSMPFrame_t smpFrame;
}agsaSASRequestBody_t;
typedef struct agsaSATAInitiatorRequest_s
{
agsaSgl_t agSgl;
bit32 dataLength;
bit32 option;
agsaSATAHostFis_t fis;
agsaDif_t dif;
agsaEncrypt_t encrypt;
bit8 scsiCDB[16];
#ifdef SA_TESTBASE_EXTRA
bit16 bstIndex;
#endif
} agsaSATAInitiatorRequest_t;
#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05
#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06
#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20
#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21
#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22
#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23
#ifdef HIALEAH_ENCRYPTION
typedef struct agsaEncryptGeneralPage_s {
bit32 numberOfKeksPageCode;
bit32 KeyCardIdKekIndex;
bit32 KeyCardId3_0;
bit32 KeyCardId7_4;
bit32 KeyCardId11_8;
} agsaEncryptGeneralPage_t;
#else
typedef struct agsaEncryptGeneralPage_s {
bit32 pageCode;
bit32 numberOfDeks;
} agsaEncryptGeneralPage_t;
#endif
#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8
typedef struct agsaEncryptDekConfigPage_s {
bit32 pageCode;
bit32 table0AddrLo;
bit32 table0AddrHi;
bit32 table0Entries;
bit32 table0BFES;
bit32 table1AddrLo;
bit32 table1AddrHi;
bit32 table1Entries;
bit32 table1BFES;
} agsaEncryptDekConfigPage_t;
#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28
#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000
#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24
typedef struct agsaEncryptControlParamPage_s {
bit32 pageCode;
bit32 CORCAP;
bit32 USRCAP;
bit32 CCS;
bit32 NOPR;
} agsaEncryptControlParamPage_t;
typedef struct agsaEncryptInfo_s {
bit32 encryptionCipherMode;
bit32 encryptionSecurityMode;
bit32 status;
bit32 flag;
} agsaEncryptInfo_t;
#define OperatorAuthenticationEnable_AUT 1
#define ReturnToFactoryMode_ARF 2
typedef struct agsaEncryptSelfTestBitMap_s {
bit32 AES_Test;
bit32 KEY_WRAP_Test;
bit32 HMAC_Test;
} agsaEncryptSelfTestBitMap_t;
typedef struct agsaEncryptSelfTestStatusBitMap_s{
bit32 AES_Status;
bit32 KEY_WRAP_Status;
bit32 HMAC_Status;
} agsaEncryptSelfTestStatusBitMap_t;
typedef struct agsaEncryptHMACTestDescriptor_s
{
bit32 Dword0;
bit32 MsgAddrLo;
bit32 MsgAddrHi;
bit32 MsgLen;
bit32 DigestAddrLo;
bit32 DigestAddrHi;
bit32 KeyAddrLo;
bit32 KeyAddrHi;
bit32 KeyLen;
} agsaEncryptHMACTestDescriptor_t;
typedef struct agsaEncryptHMACTestResult_s
{
bit32 Dword0;
bit32 Dword[12];
} agsaEncryptHMACTestResult_t;
typedef struct agsaEncryptSHATestDescriptor_s
{
bit32 Dword0;
bit32 MsgAddrLo;
bit32 MsgAddrHi;
bit32 MsgLen;
bit32 DigestAddrLo;
bit32 DigestAddrHi;
} agsaEncryptSHATestDescriptor_t;
typedef struct agsaEncryptSHATestResult_s
{
bit32 Dword0;
bit32 Dword[12];
} agsaEncryptSHATestResult_t;
#define AGSA_BIST_TEST 0x1
#define AGSA_HMAC_TEST 0x2
#define AGSA_SHA_TEST 0x3
typedef struct agsaEncryptDekBlob_s {
bit8 dekBlob[80];
} agsaEncryptDekBlob_t;
typedef struct agsaEncryptKekBlob_s {
bit8 kekBlob[48];
} agsaEncryptKekBlob_t;
typedef struct agsaEncryptHMACConfigPage_s
{
bit32 PageCode;
bit32 CustomerTag;
bit32 KeyAddrLo;
bit32 KeyAddrHi;
} agsaEncryptHMACConfigPage_t;
#define AGSA_ID_SIZE 31
typedef struct agsaID_s {
bit8 ID[AGSA_ID_SIZE];
}agsaID_t;
#define SA_OPR_MGMNT_FLAG_MASK 0x00003000
#define SA_OPR_MGMNT_FLAG_SHIFT 12
typedef struct agsaSASPhyMiscPage_s {
bit32 Dword0;
bit32 Dword1;
} agsaSASPhyMiscPage_t ;
typedef struct agsaHWEventEncrypt_s {
bit32 encryptOperation;
bit32 status;
bit32 eq;
bit32 info;
void *handle;
void *param;
} agsaHWEventEncrypt_t;
typedef struct agsaHWEventMode_s {
bit32 modePageOperation;
bit32 status;
bit32 modePageLen;
void *modePage;
void *context;
} agsaHWEventMode_t;
typedef struct agsaInterruptConfigPage_s {
bit32 pageCode;
bit32 vectorMask0;
bit32 vectorMask1;
bit32 ICTC0;
bit32 ICTC1;
bit32 ICTC2;
bit32 ICTC3;
bit32 ICTC4;
bit32 ICTC5;
bit32 ICTC6;
bit32 ICTC7;
} agsaInterruptConfigPage_t;
typedef struct agsaIoGeneralPage_s {
bit32 pageCode;
bit32 ActiveMask;
bit32 QrntTime;
} agsaIoGeneralPage_t;
typedef struct agsaDifDetails_s {
bit32 UpperLBA;
bit32 LowerLBA;
bit8 sasAddressHi[4];
bit8 sasAddressLo[4];
bit32 ExpectedCRCUDT01;
bit32 ExpectedUDT2345;
bit32 ActualCRCUDT01;
bit32 ActualUDT2345;
bit32 DIFErrDevID;
bit32 ErrBoffsetEDataLen;
void * frame;
} agsaDifDetails_t;
typedef struct agsaSASProtocolTimerConfigurationPage_s{
bit32 pageCode;
bit32 MST_MSI;
bit32 STP_SSP_MCT_TMO;
bit32 STP_FRM_TMO;
bit32 STP_IDLE_TMO;
bit32 OPNRJT_RTRY_INTVL;
bit32 Data_Cmd_OPNRJT_RTRY_TMO;
bit32 Data_Cmd_OPNRJT_RTRY_THR;
bit32 MAX_AIP;
} agsaSASProtocolTimerConfigurationPage_t;
typedef struct agsaUpdateFwFlash_s
{
bit32 currentImageOffset;
bit32 currentImageLen;
bit32 totalImageLen;
agsaSgl_t agSgl;
} agsaUpdateFwFlash_t;
typedef struct agsaFlashExtExecute_s
{
bit32 command;
bit32 partOffset;
bit32 dataLen;
agsaSgl_t *agSgl;
} agsaFlashExtExecute_t;
typedef struct agsaFlashExtResponse_s
{
bit32 epart_size;
bit32 epart_sect_size;
} agsaFlashExtResponse_t;
typedef struct agsaMPIContext_s
{
bit32 MPITableType;
bit32 offset;
bit32 value;
} agsaMPIContext_t;
#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1
#define AGSA_MPI_GENERAL_STATUS_TABLE 2
#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3
#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4
#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5
#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6
#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7
#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8
#ifdef SPC_ENABLE_PROFILE
typedef struct agsaFwProfile_s
{
bit32 tcid;
bit32 processor;
bit32 cmd;
bit32 len;
bit32 codeStartAdd;
bit32 codeEndAdd;
agsaSgl_t agSgl;
} agsaFwProfile_t;
#endif
typedef void (*ossaDeviceRegistrationCB_t)(
agsaRoot_t *agRoot,
agsaContext_t *agContext,
bit32 status,
agsaDevHandle_t *agDevHandle,
bit32 deviceID
);
typedef void (*ossaDeregisterDeviceHandleCB_t)(
agsaRoot_t *agRoot,
agsaContext_t *agContext,
agsaDevHandle_t *agDevHandle,
bit32 status
);
typedef void (*ossaGenericCB_t)(void);
typedef void (*ossaGenericAbortCB_t)(
agsaRoot_t *agRoot,
agsaIORequest_t *agIORequest,
bit32 flag,
bit32 status
);
typedef void (*ossaLocalPhyControlCB_t)(
agsaRoot_t *agRoot,
agsaContext_t *agContext,
bit32 phyId,
bit32 phyOperation,
bit32 status,
void *parm
);
typedef void (*ossaSATACompletedCB_t)(
agsaRoot_t *agRoot,
agsaIORequest_t *agIORequest,
bit32 agIOStatus,
void *agFirstDword,
bit32 agIOInfoLen,
void *agParam
);
typedef void (*ossaSMPCompletedCB_t)(
agsaRoot_t *agRoot,
agsaIORequest_t *agIORequest,
bit32 agIOStatus,
bit32 agIOInfoLen,
agsaFrameHandle_t agFrameHandle
);
typedef void (*ossaSSPCompletedCB_t)(
agsaRoot_t *agRoot,
agsaIORequest_t *agIORequest,
bit32 agIOStatus,
bit32 agIOInfoLen,
void *agParam,
bit16 sspTag,
bit32 agOtherInfo
);
typedef void (*ossaSetDeviceInfoCB_t) (
agsaRoot_t *agRoot,
agsaContext_t *agContext,
agsaDevHandle_t *agDevHandle,
bit32 status,
bit32 option,
bit32 param
);
typedef struct agsaOffloadDifDetails_s
{
bit32 ExpectedCRCUDT01;
bit32 ExpectedUDT2345;
bit32 ActualCRCUDT01;
bit32 ActualUDT2345;
bit32 DIFErr;
bit32 ErrBoffset;
} agsaOffloadDifDetails_t;
typedef struct agsaDifEncPayload_s
{
agsaSgl_t SrcSgl;
bit32 SrcDL;
agsaSgl_t DstSgl;
bit32 DstDL;
agsaDif_t dif;
agsaEncrypt_t encrypt;
} agsaDifEncPayload_t;
typedef void (*ossaVhistCaptureCB_t) (
agsaRoot_t *agRoot,
agsaContext_t *agContext,
bit32 status,
bit32 len);
typedef void (*ossaDIFEncryptionOffloadStartCB_t) (
agsaRoot_t *agRoot,
agsaContext_t *agContext,
bit32 status,
agsaOffloadDifDetails_t *agsaOffloadDifDetails
);
#define SA_RESERVED_REQUEST_COUNT 16
#ifdef SA_FW_TIMER_READS_STATUS
#define SA_FW_TIMER_READS_STATUS_INTERVAL 20
#endif
#define SIZE_DW 4
#define SIZE_QW 8
#define PCIBAR0 0
#define PCIBAR1 1
#define PCIBAR2 2
#define PCIBAR3 3
#define PCIBAR4 4
#define PCIBAR5 5
typedef struct agsaBarOffset_s
{
bit32 Generic;
bit32 Bar;
bit32 Offset;
bit32 Length;
} agsaBarOffset_t;
typedef union agsabit32bit64_U
{
bit32 S32[2];
bit64 B64;
} agsabit32bit64;
typedef struct agsaIOErrorEventStats_s
{
bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS;
bit32 agOSSA_IO_ABORTED;
bit32 agOSSA_IO_OVERFLOW;
bit32 agOSSA_IO_UNDERFLOW;
bit32 agOSSA_IO_FAILED;
bit32 agOSSA_IO_ABORT_RESET;
bit32 agOSSA_IO_NOT_VALID;
bit32 agOSSA_IO_NO_DEVICE;
bit32 agOSSA_IO_ILLEGAL_PARAMETER;
bit32 agOSSA_IO_LINK_FAILURE;
bit32 agOSSA_IO_PROG_ERROR;
bit32 agOSSA_IO_DIF_IN_ERROR;
bit32 agOSSA_IO_DIF_OUT_ERROR;
bit32 agOSSA_IO_ERROR_HW_TIMEOUT;
bit32 agOSSA_IO_XFER_ERROR_BREAK;
bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY;
bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED;
bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION;
bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS;
bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION;
bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED;
bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY;
bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION;
bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR;
bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED;
bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT;
bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED;
bit32 agOSSA_IO_XFER_ERROR_RX_FRAME;
bit32 agOSSA_IO_XFER_ERROR_DMA;
bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT;
bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT;
bit32 agOSSA_IO_XFER_ERROR_SATA;
bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST;
bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE;
bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE;
bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT;
bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR;
bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE;
bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN;
bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED;
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT;
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK;
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK;
bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH;
bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN;
bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED;
bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE;
bit32 agOSSA_IO_PORT_IN_RESET;
bit32 agOSSA_IO_DS_NON_OPERATIONAL;
bit32 agOSSA_IO_DS_IN_RECOVERY;
bit32 agOSSA_IO_TM_TAG_NOT_FOUND;
bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR;
bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR;
bit32 agOSSA_IO_DS_IN_ERROR;
bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY;
bit32 agOSSA_IO_ABORT_IN_PROGRESS;
bit32 agOSSA_IO_ABORT_DELAYED;
bit32 agOSSA_IO_INVALID_LENGTH;
bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE;
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED;
bit32 agOSSA_IO_DS_INVALID;
bit32 agOSSA_IO_XFER_READ_COMPL_ERR;
bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR;
bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR;
bit32 agOSSA_MPI_IO_RQE_BUSY_FULL;
bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE;
bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY;
bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS;
bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID;
bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR;
bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM;
bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH;
bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME;
bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN;
bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS;
bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED;
bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE;
bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR;
bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED;
bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT;
bit32 agOSSA_IO_UNKNOWN_ERROR;
} agsaIOErrorEventStats_t;
#ifdef SALL_API_TEST
typedef struct agsaIOCountInfo_s
{
bit32 numSSPStarted;
bit32 numSSPAborted;
bit32 numSSPAbortedCB;
bit32 numSSPCompleted;
bit32 numSMPStarted;
bit32 numSMPAborted;
bit32 numSMPAbortedCB;
bit32 numSMPCompleted;
bit32 numSataStarted;
bit32 numSataAborted;
bit32 numSataAbortedCB;
bit32 numSataCompleted;
bit32 numEchoSent;
bit32 numEchoCB;
bit32 numUNKNWRespIOMB;
bit32 numOurIntCount;
bit32 numSpuriousInt;
} agsaIOCountInfo_t;
#define LL_COUNTERS 17
#define COUNTER_SSP_START 0x000001
#define COUNTER_SSP_ABORT 0x000002
#define COUNTER_SSPABORT_CB 0x000004
#define COUNTER_SSP_COMPLETEED 0x000008
#define COUNTER_SMP_START 0x000010
#define COUNTER_SMP_ABORT 0x000020
#define COUNTER_SMPABORT_CB 0x000040
#define COUNTER_SMP_COMPLETEED 0x000080
#define COUNTER_SATA_START 0x000100
#define COUNTER_SATA_ABORT 0x000200
#define COUNTER_SATAABORT_CB 0x000400
#define COUNTER_SATA_COMPLETEED 0x000800
#define COUNTER_ECHO_SENT 0x001000
#define COUNTER_ECHO_CB 0x002000
#define COUNTER_UNKWN_IOMB 0x004000
#define COUNTER_OUR_INT 0x008000
#define COUNTER_SPUR_INT 0x010000
#define ALL_COUNTERS 0xFFFFFF
typedef union agsaLLCountInfo_s
{
agsaIOCountInfo_t IOCounter;
bit32 arrayIOCounter[LL_COUNTERS];
} agsaLLCountInfo_t;
#endif
#define MAX_IO_DEVICE_ENTRIES 4096
#ifdef SA_ENABLE_POISION_TLP
#define SA_PTNFE_POISION_TLP 1
#else
#define SA_PTNFE_POISION_TLP 0
#endif
#ifdef SA_DISABLE_MDFD
#define SA_MDFD_MULTI_DATA_FETCH 1
#else
#define SA_MDFD_MULTI_DATA_FETCH 0
#endif
#ifdef SA_ENABLE_ARBTE
#define SA_ARBTE 1
#else
#define SA_ARBTE 0
#endif
#ifdef SA_DISABLE_OB_COAL
#define SA_OUTBOUND_COALESCE 0
#else
#define SA_OUTBOUND_COALESCE 1
#endif
#include "saosapi.h"
#ifdef FAST_IO_TEST
typedef struct agsaFastCBBuf_s
{
void *cb;
void *cbArg;
void *pSenseData;
bit8 *senseLen;
void *oneDeviceData;
} agsaFastCBBuf_t;
typedef struct agsaFastCommand_s
{
void *agRoot;
void *devHandle;
void *agSgl;
bit32 dataLength;
bit32 extDataLength;
bit8 additionalCdbLen;
bit8 *cdb;
bit8 *lun;
bit8 taskAttribute;
bit16 flag;
bit32 agRequestType;
bit32 queueNum;
agsaFastCBBuf_t *safb;
} agsaFastCommand_t;
#endif
#define EnableFPGA_TEST_ICCcontrol 0x01
#define EnableFPGA_TEST_ReadDEV 0x02
#define EnableFPGA_TEST_WriteCALAll 0x04
#define EnableFPGA_TEST_ReconfigSASParams 0x08
#define EnableFPGA_TEST_LocalPhyControl 0x10
#define EnableFPGA_TEST_PortControl 0x20
#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000
#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01
#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02
#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03
#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04
#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05
#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20
#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21
#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22
#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23
#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24
#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40
#define OSSA_ENCRYPT_AES_BIST_ERR 0x41
#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42
#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000
#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1
#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2
#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4
#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8
#define SA_ROLE_CAPABILITIES_CSP 0x001
#define SA_ROLE_CAPABILITIES_OPR 0x002
#define SA_ROLE_CAPABILITIES_SCO 0x004
#define SA_ROLE_CAPABILITIES_STS 0x008
#define SA_ROLE_CAPABILITIES_TST 0x010
#define SA_ROLE_CAPABILITIES_KEK 0x020
#define SA_ROLE_CAPABILITIES_DEK 0x040
#define SA_ROLE_CAPABILITIES_IOS 0x080
#define SA_ROLE_CAPABILITIES_FWU 0x100
#define SA_ROLE_CAPABILITIES_PRM 0x200
#include "saapi.h"
#endif
