PCIBAR1
regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE);
ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT);
ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal); /* siSpcSoftReset */
regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE);
ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT);
ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */
ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW);
#define MSGU_READ_IDR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_IBDB_REG)
#define MSGU_READ_ODMR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_MASK)
#define MSGU_READ_ODR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_REG)
#define MSGU_READ_ODCR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_CLEAR)
#define SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId))
#define SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value)
ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICTIMER,hwConfig->hwInterruptCoalescingTimer );
ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICCONTROL, hwConfig->hwInterruptCoalescingControl);
pciBar = PCIBAR1;
bar = PCIBAR1;