sys/arm/allwinner/if_emac.c
1051
uint32_t reg_val;
sys/arm/allwinner/if_emac.c
1075
reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
sys/arm/allwinner/if_emac.c
1077
reg_val &= ~EMAC_MAC_IPGT_HD;
sys/arm/allwinner/if_emac.c
1078
reg_val |= EMAC_MAC_IPGT_FD;
sys/arm/allwinner/if_emac.c
1080
reg_val &= ~EMAC_MAC_IPGT_FD;
sys/arm/allwinner/if_emac.c
1081
reg_val |= EMAC_MAC_IPGT_HD;
sys/arm/allwinner/if_emac.c
1083
EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
sys/arm/allwinner/if_emac.c
1085
reg_val = EMAC_READ_REG(sc, EMAC_CTL);
sys/arm/allwinner/if_emac.c
1086
reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
sys/arm/allwinner/if_emac.c
1087
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
sys/arm/allwinner/if_emac.c
1090
reg_val = EMAC_READ_REG(sc, EMAC_CTL);
sys/arm/allwinner/if_emac.c
1091
reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
sys/arm/allwinner/if_emac.c
1092
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
sys/arm/allwinner/if_emac.c
312
uint32_t reg_val, rxcount;
sys/arm/allwinner/if_emac.c
332
reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
sys/arm/allwinner/if_emac.c
333
if (reg_val != EMAC_PACKET_HEADER) {
sys/arm/allwinner/if_emac.c
338
reg_val = EMAC_READ_REG(sc, EMAC_CTL);
sys/arm/allwinner/if_emac.c
339
reg_val &= ~EMAC_CTL_RX_EN;
sys/arm/allwinner/if_emac.c
340
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
sys/arm/allwinner/if_emac.c
343
reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
sys/arm/allwinner/if_emac.c
344
reg_val |= EMAC_RX_FLUSH_FIFO;
sys/arm/allwinner/if_emac.c
345
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
sys/arm/allwinner/if_emac.c
360
reg_val = EMAC_READ_REG(sc, EMAC_CTL);
sys/arm/allwinner/if_emac.c
361
reg_val |= EMAC_CTL_RX_EN;
sys/arm/allwinner/if_emac.c
362
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
sys/arm/allwinner/if_emac.c
368
reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
sys/arm/allwinner/if_emac.c
369
len = reg_val & 0xffff;
sys/arm/allwinner/if_emac.c
370
status = (reg_val >> 16) & 0xffff;
sys/arm/allwinner/if_emac.c
502
uint32_t reg_val;
sys/arm/allwinner/if_emac.c
512
reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
sys/arm/allwinner/if_emac.c
513
reg_val |= EMAC_RX_FLUSH_FIFO;
sys/arm/allwinner/if_emac.c
514
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
sys/arm/allwinner/if_emac.c
518
reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
sys/arm/allwinner/if_emac.c
519
reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
sys/arm/allwinner/if_emac.c
520
EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
sys/arm/allwinner/if_emac.c
523
reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
sys/arm/allwinner/if_emac.c
524
reg_val &= (~(0xf << 2));
sys/arm/allwinner/if_emac.c
525
reg_val |= (0xd << 2);
sys/arm/allwinner/if_emac.c
526
EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
sys/arm/allwinner/if_emac.c
533
reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
sys/arm/allwinner/if_emac.c
534
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
sys/arm/allwinner/if_emac.c
538
reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
sys/arm/allwinner/if_emac.c
539
reg_val |= EMAC_TX_AB_M;
sys/arm/allwinner/if_emac.c
540
reg_val &= EMAC_TX_TM;
sys/arm/allwinner/if_emac.c
541
EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
sys/arm/allwinner/if_emac.c
544
reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
sys/arm/allwinner/if_emac.c
545
reg_val |= EMAC_RX_SETUP;
sys/arm/allwinner/if_emac.c
546
reg_val &= EMAC_RX_TM;
sys/arm/allwinner/if_emac.c
547
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
sys/arm/allwinner/if_emac.c
550
reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
sys/arm/allwinner/if_emac.c
551
reg_val |= EMAC_MAC_CTL0_SETUP;
sys/arm/allwinner/if_emac.c
552
EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
sys/arm/allwinner/if_emac.c
555
reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
sys/arm/allwinner/if_emac.c
556
reg_val |= EMAC_MAC_CTL1_SETUP;
sys/arm/allwinner/if_emac.c
557
EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
sys/arm/allwinner/if_emac.c
583
reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
sys/arm/allwinner/if_emac.c
584
reg_val |= EMAC_INT_EN;
sys/arm/allwinner/if_emac.c
585
EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
sys/arm/allwinner/if_emac.c
676
uint32_t reg_val;
sys/arm/allwinner/if_emac.c
686
reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
sys/arm/allwinner/if_emac.c
687
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
sys/arm/allwinner/if_emac.c
690
reg_val = EMAC_READ_REG(sc, EMAC_CTL);
sys/arm/allwinner/if_emac.c
691
reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
sys/arm/allwinner/if_emac.c
692
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
sys/arm/allwinner/if_emac.c
702
uint32_t reg_val;
sys/arm/allwinner/if_emac.c
710
reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
sys/arm/allwinner/if_emac.c
712
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
sys/arm/allwinner/if_emac.c
715
if (reg_val & EMAC_INT_STA_RX)
sys/arm/allwinner/if_emac.c
719
if (reg_val & EMAC_INT_STA_TX) {
sys/arm/allwinner/if_emac.c
720
emac_txeof(sc, reg_val);
sys/arm/allwinner/if_emac.c
727
reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
sys/arm/allwinner/if_emac.c
728
reg_val |= EMAC_INT_EN;
sys/arm/allwinner/if_emac.c
729
EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
sys/arm/mv/gpio.c
1015
uint32_t reg, polar_reg, reg_val, polar_reg_val;
sys/arm/mv/gpio.c
1025
reg_val = mv_gpio_reg_read(dev, reg);
sys/arm/mv/gpio.c
1029
return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin)));
sys/arm/mv/gpio.c
1031
return (reg_val & GPIO(pin));
sys/arm/mv/gpio.c
883
uint32_t reg_val;
sys/arm/mv/gpio.c
885
reg_val = mv_gpio_reg_read(dev, reg);
sys/arm/mv/gpio.c
886
reg_val |= GPIO(pin);
sys/arm/mv/gpio.c
887
mv_gpio_reg_write(dev, reg, reg_val);
sys/arm/mv/gpio.c
893
uint32_t reg_val;
sys/arm/mv/gpio.c
895
reg_val = mv_gpio_reg_read(dev, reg);
sys/arm/mv/gpio.c
896
reg_val &= ~(GPIO(pin));
sys/arm/mv/gpio.c
897
mv_gpio_reg_write(dev, reg, reg_val);
sys/arm/mv/gpio.c
939
uint32_t reg, reg_val;
sys/arm/mv/gpio.c
949
reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);
sys/arm/mv/gpio.c
950
if (reg_val)
sys/arm/qualcomm/qcom_cpu_kpssv2.c
137
reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT)
sys/arm/qualcomm/qcom_cpu_kpssv2.c
140
bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
148
reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT;
sys/arm/qualcomm/qcom_cpu_kpssv2.c
149
bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
157
reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT;
sys/arm/qualcomm/qcom_cpu_kpssv2.c
158
bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
171
reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST
sys/arm/qualcomm/qcom_cpu_kpssv2.c
173
bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
180
reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP;
sys/arm/qualcomm/qcom_cpu_kpssv2.c
181
bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
188
reg_val &= ~QCOM_APCS_CPU_PWR_CTL_COREPOR_RST;
sys/arm/qualcomm/qcom_cpu_kpssv2.c
189
bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
196
reg_val |= QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP;
sys/arm/qualcomm/qcom_cpu_kpssv2.c
197
bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
sys/arm/qualcomm/qcom_cpu_kpssv2.c
80
uint32_t reg_val;
sys/arm/ti/ti_pinmux.c
132
uint16_t reg_val;
sys/arm/ti/ti_pinmux.c
135
reg_val = (uint16_t)(state & ti_pinmux_dev->padconf_sate_mask);
sys/arm/ti/ti_pinmux.c
152
reg_val |= (uint16_t)(mode & ti_pinmux_dev->padconf_muxmode_mask);
sys/arm/ti/ti_pinmux.c
156
reg_val, muxmode);
sys/arm/ti/ti_pinmux.c
158
ti_pinmux_write_2(sc, padconf->reg_off, reg_val);
sys/arm/ti/ti_pinmux.c
212
uint16_t reg_val;
sys/arm/ti/ti_pinmux.c
223
reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off);
sys/arm/ti/ti_pinmux.c
227
*state = (reg_val & ti_pinmux_dev->padconf_sate_mask);
sys/arm/ti/ti_pinmux.c
231
*muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev->padconf_muxmode_mask)];
sys/arm/ti/ti_pinmux.c
254
uint16_t reg_val;
sys/arm/ti/ti_pinmux.c
270
reg_val = (uint16_t)(state & ti_pinmux_dev->padconf_sate_mask);
sys/arm/ti/ti_pinmux.c
273
reg_val |= (uint16_t)(padconf->gpio_mode & ti_pinmux_dev->padconf_muxmode_mask);
sys/arm/ti/ti_pinmux.c
276
ti_pinmux_write_2(ti_pinmux_sc, padconf->reg_off, reg_val);
sys/arm/ti/ti_pinmux.c
299
uint16_t reg_val;
sys/arm/ti/ti_pinmux.c
315
reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off);
sys/arm/ti/ti_pinmux.c
318
if ((reg_val & ti_pinmux_dev->padconf_muxmode_mask) != padconf->gpio_mode)
sys/arm/ti/ti_pinmux.c
323
*state = (reg_val & ti_pinmux_dev->padconf_sate_mask);
sys/dev/axgbe/xgbe-common.h
1517
uint32_t reg_val = XGMAC_IOREAD((_pdata), _reg); \
sys/dev/axgbe/xgbe-common.h
1518
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1521
XGMAC_IOWRITE((_pdata), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1543
uint32_t reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
sys/dev/axgbe/xgbe-common.h
1544
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1547
XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1568
uint32_t reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
sys/dev/axgbe/xgbe-common.h
1569
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1572
XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1626
uint16_t reg_val = XSIR0_IOREAD((_pdata), _reg); \
sys/dev/axgbe/xgbe-common.h
1627
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1630
XSIR0_IOWRITE((_pdata), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1646
uint16_t reg_val = XSIR1_IOREAD((_pdata), _reg); \
sys/dev/axgbe/xgbe-common.h
1647
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1650
XSIR1_IOWRITE((_pdata), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1669
uint16_t reg_val = XRXTX_IOREAD((_pdata), _reg); \
sys/dev/axgbe/xgbe-common.h
1670
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1673
XRXTX_IOWRITE((_pdata), _reg, reg_val); \
sys/dev/axgbe/xgbe-common.h
1703
uint32_t reg_val = XP_IOREAD((_pdata), (_reg)); \
sys/dev/axgbe/xgbe-common.h
1704
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1707
XP_IOWRITE((_pdata), (_reg), reg_val); \
sys/dev/axgbe/xgbe-common.h
1737
uint32_t reg_val = XI2C_IOREAD((_pdata), (_reg)); \
sys/dev/axgbe/xgbe-common.h
1738
SET_BITS(reg_val, \
sys/dev/axgbe/xgbe-common.h
1741
XI2C_IOWRITE((_pdata), (_reg), reg_val); \
sys/dev/axgbe/xgbe-dev.c
1237
unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
sys/dev/axgbe/xgbe-dev.c
1243
reg_val |= (1 << port);
sys/dev/axgbe/xgbe-dev.c
1251
XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
sys/dev/axgbe/xgbe-dev.c
1956
unsigned int i, j, reg, reg_val;
sys/dev/axgbe/xgbe-dev.c
1986
reg_val = 0;
sys/dev/axgbe/xgbe-dev.c
2001
reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
sys/dev/axgbe/xgbe-dev.c
2006
XGMAC_IOWRITE(pdata, reg, reg_val);
sys/dev/axgbe/xgbe-dev.c
2008
reg_val = 0;
sys/dev/axgbe/xgbe-dev.c
2013
reg_val = 0;
sys/dev/axgbe/xgbe-dev.c
2015
reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
sys/dev/axgbe/xgbe-dev.c
2020
XGMAC_IOWRITE(pdata, reg, reg_val);
sys/dev/axgbe/xgbe-dev.c
2023
reg_val = 0;
sys/dev/axgbe/xgbe-dev.c
2606
unsigned int reg_val, i;
sys/dev/axgbe/xgbe-dev.c
2617
reg_val = 0;
sys/dev/axgbe/xgbe-dev.c
2619
reg_val |= (0x02 << (i << 1));
sys/dev/axgbe/xgbe-dev.c
2620
XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
sys/dev/axgbe/xgbe-dev.c
491
unsigned int reg, reg_val;
sys/dev/axgbe/xgbe-dev.c
503
reg_val = XGMAC_IOREAD(pdata, reg);
sys/dev/axgbe/xgbe-dev.c
504
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
sys/dev/axgbe/xgbe-dev.c
505
XGMAC_IOWRITE(pdata, reg, reg_val);
sys/dev/axgbe/xgbe-dev.c
517
unsigned int reg, reg_val;
sys/dev/axgbe/xgbe-dev.c
541
reg_val = XGMAC_IOREAD(pdata, reg);
sys/dev/axgbe/xgbe-dev.c
544
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
sys/dev/axgbe/xgbe-dev.c
547
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
sys/dev/axgbe/xgbe-dev.c
549
XGMAC_IOWRITE(pdata, reg, reg_val);
sys/dev/bxe/bxe.c
18893
uint32_t reg_val;
sys/dev/bxe/bxe.c
19059
reg_val = REG_RD(sc, reg_addr);
sys/dev/bxe/bxe.c
19061
reg_addr, reg_val);
sys/dev/bxe/bxe.c
19360
reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);
sys/dev/bxe/bxe.c
19364
REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val);
sys/dev/bxe/bxe_elink.c
5872
uint16_t reg_val;
sys/dev/bxe/bxe_elink.c
5877
MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
sys/dev/bxe/bxe_elink.c
5881
reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
sys/dev/bxe/bxe_elink.c
5883
reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
sys/dev/bxe/bxe_elink.c
5888
MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
sys/dev/bxe/bxe_elink.c
5894
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
sys/dev/bxe/bxe_elink.c
5895
reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
sys/dev/bxe/bxe_elink.c
5897
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
sys/dev/bxe/bxe_elink.c
5899
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
sys/dev/bxe/bxe_elink.c
5901
reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
sys/dev/bxe/bxe_elink.c
5905
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
sys/dev/bxe/bxe_elink.c
5911
®_val);
sys/dev/bxe/bxe_elink.c
5914
reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
sys/dev/bxe/bxe_elink.c
5918
reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
sys/dev/bxe/bxe_elink.c
5924
reg_val);
sys/dev/bxe/bxe_elink.c
5945
®_val);
sys/dev/bxe/bxe_elink.c
5948
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
sys/dev/bxe/bxe_elink.c
5951
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
sys/dev/bxe/bxe_elink.c
5956
reg_val);
sys/dev/bxe/bxe_elink.c
5959
reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
sys/dev/bxe/bxe_elink.c
5962
reg_val = 0;
sys/dev/bxe/bxe_elink.c
5966
MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
sys/dev/bxe/bxe_elink.c
5975
uint16_t reg_val;
sys/dev/bxe/bxe_elink.c
5980
MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
sys/dev/bxe/bxe_elink.c
5981
reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
sys/dev/bxe/bxe_elink.c
5985
reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
sys/dev/bxe/bxe_elink.c
5988
MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
sys/dev/bxe/bxe_elink.c
5995
MDIO_SERDES_DIGITAL_MISC1, ®_val);
sys/dev/bxe/bxe_elink.c
5997
ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
sys/dev/bxe/bxe_elink.c
5999
reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
sys/dev/bxe/bxe_elink.c
6006
reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
sys/dev/bxe/bxe_elink.c
6009
reg_val |=
sys/dev/bxe/bxe_elink.c
6015
MDIO_SERDES_DIGITAL_MISC1, reg_val);
sys/dev/bxe/bxe_ioctl.h
98
uint32_t reg_val;
sys/dev/bxe/ecore_init.h
747
uint32_t reg_val;
sys/dev/bxe/ecore_init.h
750
reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
sys/dev/bxe/ecore_init.h
753
reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
sys/dev/bxe/ecore_init.h
755
reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
sys/dev/bxe/ecore_init.h
757
REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
sys/dev/bxe/ecore_init.h
799
uint32_t reg_val, mcp_aeu_bits =
sys/dev/bxe/ecore_init.h
815
reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
sys/dev/bxe/ecore_init.h
817
if (reg_val & reg_mask)
sys/dev/bxe/ecore_init.h
821
reg_val & reg_mask);
sys/dev/bxe/ecore_init.h
826
reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
sys/dev/bxe/ecore_init.h
827
if (reg_val & mcp_aeu_bits)
sys/dev/bxe/ecore_init.h
829
reg_val & mcp_aeu_bits);
sys/dev/cxgb/common/cxgb_ael1002.c
1253
static struct reg_val regs0[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1263
static struct reg_val regs1[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1408
static struct reg_val regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1434
static struct reg_val uCclock40MHz[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1440
static struct reg_val uCclockActivate[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1445
static struct reg_val uCactivate[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1940
struct reg_val regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
1971
struct reg_val regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
2004
static struct reg_val ael2020_reset_regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
526
static struct reg_val regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
823
static struct reg_val regs[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
827
static struct reg_val preemphasis[] = {
sys/dev/cxgb/common/cxgb_ael1002.c
99
static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
sys/dev/e1000/e1000_82575.c
2040
u32 reg_val, reg_offset;
sys/dev/e1000/e1000_82575.c
2054
reg_val = E1000_READ_REG(hw, reg_offset);
sys/dev/e1000/e1000_82575.c
2056
reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
sys/dev/e1000/e1000_82575.c
2061
reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
sys/dev/e1000/e1000_82575.c
2063
reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
sys/dev/e1000/e1000_82575.c
2066
E1000_WRITE_REG(hw, reg_offset, reg_val);
sys/dev/e1000/e1000_i210.c
711
u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;
sys/dev/e1000/e1000_i210.c
720
reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
sys/dev/e1000/e1000_i210.c
721
E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);
sys/dev/e1000/e1000_i210.c
753
reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
sys/dev/e1000/e1000_i210.c
754
E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
sys/dev/e1000/e1000_i210.c
762
reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
sys/dev/e1000/e1000_i210.c
763
E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.c
104
reg_val);
sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.c
92
uint16_t mmd_num, uint16_t reg_id, uint16_t reg_val)
sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.h
35
uint16_t mmd_num, uint16_t reg_id, uint16_t reg_val);
sys/dev/iicbus/controller/vybrid/vf_i2c.c
119
uint32_t reg_val;
sys/dev/iicbus/controller/vybrid/vf_i2c.c
413
div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
sys/dev/iicbus/controller/vybrid/vf_i2c.c
418
div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
sys/dev/iicbus/controller/vybrid/vf_i2c.c
427
div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
sys/dev/iicbus/controller/vybrid/vf_i2c.c
433
div_reg = vf610_div_table[i].reg_val;
sys/dev/irdma/icrdma_hw.c
135
u32 reg_val;
sys/dev/irdma/icrdma_hw.c
137
reg_val = enable ? IRDMA_GLINT_CEQCTL_CAUSE_ENA : 0;
sys/dev/irdma/icrdma_hw.c
138
reg_val |= (idx << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) |
sys/dev/irdma/icrdma_hw.c
141
writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
sys/dev/irdma/irdma_ctrl.c
5391
u32 reg_val;
sys/dev/irdma/irdma_ctrl.c
5393
reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) |
sys/dev/irdma/irdma_ctrl.c
5397
writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
sys/dev/isci/scil/scic_sds_phy.c
253
U32 reg_val = scu_afe_register_read(
sys/dev/isci/scil/scic_sds_phy.c
257
reg_val |= (0x00100000 | (((U32)sas_type) << 19));
sys/dev/isci/scil/scic_sds_phy.c
261
reg_val);
sys/dev/isci/scil/scic_sds_phy.c
263
reg_val = scu_afe_register_read(
sys/dev/isci/scil/scic_sds_phy.c
267
reg_val |= (((U32)(sas_spread)) << 8);
sys/dev/isci/scil/scic_sds_phy.c
271
reg_val);
sys/dev/isci/scil/scic_sds_phy.c
279
U32 reg_val = scu_afe_register_read(
sys/dev/isci/scil/scic_sds_phy.c
283
reg_val |= (U32)sata_spread;
sys/dev/isci/scil/scic_sds_phy.c
287
reg_val);
sys/dev/isci/scil/scic_sds_phy.c
289
reg_val = scu_link_layer_register_read(
sys/dev/isci/scil/scic_sds_phy.c
292
reg_val |= (U32)(1 << 12);
sys/dev/isci/scil/scic_sds_phy.c
296
reg_val);
sys/dev/iwm/if_iwm.c
1390
uint32_t reg_val = 0;
sys/dev/iwm/if_iwm.c
1401
reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) <<
sys/dev/iwm/if_iwm.c
1403
reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) <<
sys/dev/iwm/if_iwm.c
1407
reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE;
sys/dev/iwm/if_iwm.c
1408
reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;
sys/dev/iwm/if_iwm.c
1409
reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
sys/dev/iwm/if_iwm.c
1419
reg_val);
sys/dev/iwx/if_iwx.c
2863
uint32_t mask, val, reg_val = 0;
sys/dev/iwx/if_iwx.c
2872
reg_val |= IWX_CSR_HW_REV_STEP(sc->sc_hw_rev) <<
sys/dev/iwx/if_iwx.c
2874
reg_val |= IWX_CSR_HW_REV_DASH(sc->sc_hw_rev) <<
sys/dev/iwx/if_iwx.c
2878
reg_val |= radio_cfg_type << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE;
sys/dev/iwx/if_iwx.c
2879
reg_val |= radio_cfg_step << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;
sys/dev/iwx/if_iwx.c
2880
reg_val |= radio_cfg_dash << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
sys/dev/iwx/if_iwx.c
2892
val |= reg_val;
sys/dev/ixgbe/ixgbe_82599.c
250
s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
sys/dev/ixgbe/ixgbe_82599.c
265
*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
sys/dev/ixgbe/ixgbe_82599.h
63
s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
sys/dev/ixgbe/ixgbe_82599.h
64
s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
sys/dev/ixgbe/ixgbe_common.c
1122
u32 reg_val;
sys/dev/ixgbe/ixgbe_common.c
1148
reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
sys/dev/ixgbe/ixgbe_common.c
1149
reg_val &= ~IXGBE_RXDCTL_ENABLE;
sys/dev/ixgbe/ixgbe_common.c
1150
reg_val |= IXGBE_RXDCTL_SWFLSH;
sys/dev/ixgbe/ixgbe_common.c
1151
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
sys/dev/ixgbe/ixgbe_common.c
3402
s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
sys/dev/ixgbe/ixgbe_common.c
3405
*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
sys/dev/ixgbe/ixgbe_common.c
3418
s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
sys/dev/ixgbe/ixgbe_common.c
3422
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
sys/dev/ixgbe/ixgbe_common.h
123
s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
sys/dev/ixgbe/ixgbe_common.h
124
s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
sys/dev/ixgbe/ixgbe_vf.c
253
u32 reg_val;
sys/dev/ixgbe/ixgbe_vf.c
274
reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));
sys/dev/ixgbe/ixgbe_vf.c
275
reg_val &= ~IXGBE_RXDCTL_ENABLE;
sys/dev/ixgbe/ixgbe_vf.c
276
IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2088
u32 reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2092
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2096
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
sys/dev/ixgbe/ixgbe_x550.c
2097
reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
sys/dev/ixgbe/ixgbe_x550.c
2102
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
sys/dev/ixgbe/ixgbe_x550.c
2106
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
sys/dev/ixgbe/ixgbe_x550.c
2110
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2116
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2121
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
sys/dev/ixgbe/ixgbe_x550.c
2122
reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
sys/dev/ixgbe/ixgbe_x550.c
2123
reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
sys/dev/ixgbe/ixgbe_x550.c
2124
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
sys/dev/ixgbe/ixgbe_x550.c
2125
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
sys/dev/ixgbe/ixgbe_x550.c
2129
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2568
u16 reg_slice, reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2592
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
sys/dev/ixgbe/ixgbe_x550.c
2594
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
sys/dev/ixgbe/ixgbe_x550.c
2596
reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2612
u32 reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2617
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2621
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
sys/dev/ixgbe/ixgbe_x550.c
2622
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
sys/dev/ixgbe/ixgbe_x550.c
2623
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
sys/dev/ixgbe/ixgbe_x550.c
2624
reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
sys/dev/ixgbe/ixgbe_x550.c
2629
reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
sys/dev/ixgbe/ixgbe_x550.c
2632
reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
sys/dev/ixgbe/ixgbe_x550.c
2641
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2764
u32 reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2769
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2772
reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
sys/dev/ixgbe/ixgbe_x550.c
2775
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2782
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2785
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
sys/dev/ixgbe/ixgbe_x550.c
2786
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
sys/dev/ixgbe/ixgbe_x550.c
2787
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
sys/dev/ixgbe/ixgbe_x550.c
2790
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2795
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2798
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
sys/dev/ixgbe/ixgbe_x550.c
2799
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
sys/dev/ixgbe/ixgbe_x550.c
2800
reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
sys/dev/ixgbe/ixgbe_x550.c
2803
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2810
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2813
reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
sys/dev/ixgbe/ixgbe_x550.c
2814
reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
sys/dev/ixgbe/ixgbe_x550.c
2815
reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
sys/dev/ixgbe/ixgbe_x550.c
2816
reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
sys/dev/ixgbe/ixgbe_x550.c
2819
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2835
u32 reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2844
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
2848
reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
sys/dev/ixgbe/ixgbe_x550.c
2849
reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
sys/dev/ixgbe/ixgbe_x550.c
2854
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
sys/dev/ixgbe/ixgbe_x550.c
2857
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
sys/dev/ixgbe/ixgbe_x550.c
2866
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
2993
u32 reg_val;
sys/dev/ixgbe/ixgbe_x550.c
2998
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
3001
reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
sys/dev/ixgbe/ixgbe_x550.c
3002
reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
sys/dev/ixgbe/ixgbe_x550.c
3003
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
sys/dev/ixgbe/ixgbe_x550.c
3006
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
3013
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
3016
reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
sys/dev/ixgbe/ixgbe_x550.c
3017
reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
sys/dev/ixgbe/ixgbe_x550.c
3020
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
3027
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
3030
reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
sys/dev/ixgbe/ixgbe_x550.c
3033
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
3040
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
3043
reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
sys/dev/ixgbe/ixgbe_x550.c
3046
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixgbe/ixgbe_x550.c
3861
u32 pause, asm_dir, reg_val;
sys/dev/ixgbe/ixgbe_x550.c
3915
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
sys/dev/ixgbe/ixgbe_x550.c
3918
reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
sys/dev/ixgbe/ixgbe_x550.c
3921
reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
sys/dev/ixgbe/ixgbe_x550.c
3923
reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
sys/dev/ixgbe/ixgbe_x550.c
3926
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
sys/dev/ixl/i40e_common.c
1159
u32 reg_val;
sys/dev/ixl/i40e_common.c
1166
reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
sys/dev/ixl/i40e_common.c
1167
reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
sys/dev/ixl/i40e_common.c
1168
reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
sys/dev/ixl/i40e_common.c
1171
reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
sys/dev/ixl/i40e_common.c
1173
reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
sys/dev/ixl/i40e_common.c
1175
wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
sys/dev/ixl/i40e_common.c
3417
u32 reg_addr, u64 *reg_val,
sys/dev/ixl/i40e_common.c
3425
if (reg_val == NULL)
sys/dev/ixl/i40e_common.c
3435
*reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
sys/dev/ixl/i40e_common.c
3452
u32 reg_addr, u64 reg_val,
sys/dev/ixl/i40e_common.c
3463
cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
sys/dev/ixl/i40e_common.c
3464
cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
sys/dev/ixl/i40e_common.c
6737
u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
sys/dev/ixl/i40e_common.c
6739
return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
sys/dev/ixl/i40e_common.c
6823
u32 *reg_val)
sys/dev/ixl/i40e_common.c
6828
*reg_val = 0;
sys/dev/ixl/i40e_common.c
6834
reg_val, NULL);
sys/dev/ixl/i40e_common.c
6840
(u16 *)reg_val);
sys/dev/ixl/i40e_common.c
6852
u32 reg_val)
sys/dev/ixl/i40e_common.c
6862
reg_val, NULL);
sys/dev/ixl/i40e_common.c
6868
(u16)reg_val);
sys/dev/ixl/i40e_common.c
6889
u16 reg_val;
sys/dev/ixl/i40e_common.c
6908
®_val);
sys/dev/ixl/i40e_common.c
6911
*val = reg_val;
sys/dev/ixl/i40e_common.c
6912
if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
sys/dev/ixl/i40e_common.c
7177
u32 reg_addr, u32 *reg_val,
sys/dev/ixl/i40e_common.c
7185
if (reg_val == NULL)
sys/dev/ixl/i40e_common.c
7195
*reg_val = LE32_TO_CPU(cmd_resp->value);
sys/dev/ixl/i40e_common.c
7243
u32 reg_addr, u32 reg_val,
sys/dev/ixl/i40e_common.c
7254
cmd->value = CPU_TO_LE32(reg_val);
sys/dev/ixl/i40e_common.c
7267
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
sys/dev/ixl/i40e_common.c
7279
reg_val, NULL);
sys/dev/ixl/i40e_common.c
7289
wr32(hw, reg_addr, reg_val);
sys/dev/ixl/i40e_common.c
7336
u32 reg_addr, u32 reg_val,
sys/dev/ixl/i40e_common.c
7350
cmd->reg_value = CPU_TO_LE32(reg_val);
sys/dev/ixl/i40e_common.c
7382
u32 reg_addr, u32 *reg_val,
sys/dev/ixl/i40e_common.c
7404
*reg_val = LE32_TO_CPU(cmd->reg_value);
sys/dev/ixl/i40e_prototype.h
103
u32 *reg_val);
sys/dev/ixl/i40e_prototype.h
105
u32 reg_val);
sys/dev/ixl/i40e_prototype.h
125
u32 reg_addr, u64 reg_val,
sys/dev/ixl/i40e_prototype.h
128
u32 reg_addr, u64 *reg_val,
sys/dev/ixl/i40e_prototype.h
576
u32 reg_addr, u32 *reg_val,
sys/dev/ixl/i40e_prototype.h
580
u32 reg_addr, u32 reg_val,
sys/dev/ixl/i40e_prototype.h
582
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
sys/dev/ixl/i40e_prototype.h
587
u32 reg_addr, u32 reg_val,
sys/dev/ixl/i40e_prototype.h
593
u32 reg_addr, u32 *reg_val,
sys/dev/liquidio/base/cn23xx_pf_device.c
142
uint64_t reg_val;
sys/dev/liquidio/base/cn23xx_pf_device.c
150
reg_val =
sys/dev/liquidio/base/cn23xx_pf_device.c
154
reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS;
sys/dev/liquidio/base/cn23xx_pf_device.c
157
reg_val = reg_val |
sys/dev/liquidio/base/cn23xx_pf_device.c
162
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
197
volatile uint64_t reg_val =
sys/dev/liquidio/base/cn23xx_pf_device.c
200
while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) &&
sys/dev/liquidio/base/cn23xx_pf_device.c
201
!(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) &&
sys/dev/liquidio/base/cn23xx_pf_device.c
203
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
215
reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST;
sys/dev/liquidio/base/cn23xx_pf_device.c
217
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
219
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
221
if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
sys/dev/liquidio/base/cn23xx_pf_device.c
237
uint64_t pf_num, reg_val;
sys/dev/liquidio/base/cn23xx_pf_device.c
255
reg_val = oct->pcie_port <<
sys/dev/liquidio/base/cn23xx_pf_device.c
258
reg_val |= pf_num << LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
sys/dev/liquidio/base/cn23xx_pf_device.c
261
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
277
reg_val =
sys/dev/liquidio/base/cn23xx_pf_device.c
280
reg_val |= LIO_CN23XX_PKT_INPUT_CTL_MASK;
sys/dev/liquidio/base/cn23xx_pf_device.c
283
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
305
uint32_t ern, q_no, reg_val, srn;
sys/dev/liquidio/base/cn23xx_pf_device.c
318
reg_val = lio_read_csr32(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
322
reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_DPTR;
sys/dev/liquidio/base/cn23xx_pf_device.c
325
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_BMODE);
sys/dev/liquidio/base/cn23xx_pf_device.c
331
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P);
sys/dev/liquidio/base/cn23xx_pf_device.c
332
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P);
sys/dev/liquidio/base/cn23xx_pf_device.c
335
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
sys/dev/liquidio/base/cn23xx_pf_device.c
337
reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
sys/dev/liquidio/base/cn23xx_pf_device.c
344
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR);
sys/dev/liquidio/base/cn23xx_pf_device.c
345
reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR);
sys/dev/liquidio/base/cn23xx_pf_device.c
347
reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES);
sys/dev/liquidio/base/cn23xx_pf_device.c
351
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
456
uint32_t reg_val;
sys/dev/liquidio/base/cn23xx_pf_device.c
476
reg_val =
sys/dev/liquidio/base/cn23xx_pf_device.c
478
reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_TENB;
sys/dev/liquidio/base/cn23xx_pf_device.c
480
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
486
reg_val =
sys/dev/liquidio/base/cn23xx_pf_device.c
488
reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_CENB;
sys/dev/liquidio/base/cn23xx_pf_device.c
490
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
505
uint64_t reg_val;
sys/dev/liquidio/base/cn23xx_pf_device.c
515
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
517
reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_IS_64B;
sys/dev/liquidio/base/cn23xx_pf_device.c
520
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
528
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
531
if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
sys/dev/liquidio/base/cn23xx_pf_device.c
532
while ((reg_val &
sys/dev/liquidio/base/cn23xx_pf_device.c
534
!(reg_val &
sys/dev/liquidio/base/cn23xx_pf_device.c
537
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
546
reg_val = reg_val &
sys/dev/liquidio/base/cn23xx_pf_device.c
550
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
552
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
554
if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
sys/dev/liquidio/base/cn23xx_pf_device.c
560
reg_val = lio_read_csr64(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
562
reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_RING_ENB;
sys/dev/liquidio/base/cn23xx_pf_device.c
565
reg_val);
sys/dev/liquidio/base/cn23xx_pf_device.c
569
uint32_t reg_val;
sys/dev/liquidio/base/cn23xx_pf_device.c
572
reg_val = lio_read_csr32(oct,
sys/dev/liquidio/base/cn23xx_pf_device.c
574
reg_val = reg_val | LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB;
sys/dev/liquidio/base/cn23xx_pf_device.c
577
reg_val);
sys/dev/mge/if_mge.c
1063
volatile uint32_t reg_val;
sys/dev/mge/if_mge.c
1118
reg_val = mge_set_port_serial_control(media_status);
sys/dev/mge/if_mge.c
1119
MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
sys/dev/mge/if_mge.c
1152
reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
sys/dev/mge/if_mge.c
1153
reg_val |= PORT_SERIAL_ENABLE;
sys/dev/mge/if_mge.c
1154
MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
sys/dev/mge/if_mge.c
1157
reg_val = MGE_READ(sc, MGE_PORT_STATUS);
sys/dev/mge/if_mge.c
1158
if (reg_val & MGE_STATUS_LINKUP)
sys/dev/mge/if_mge.c
1727
uint32_t reg_val, queued = 0;
sys/dev/mge/if_mge.c
1776
reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
sys/dev/mge/if_mge.c
1777
MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_ENABLE_TXQ);
sys/dev/mge/if_mge.c
1786
volatile uint32_t reg_val, status;
sys/dev/mge/if_mge.c
1807
reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
sys/dev/mge/if_mge.c
1808
MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_DISABLE_TXQ);
sys/dev/mge/if_mge.c
1841
reg_val = MGE_READ(sc, MGE_PORT_STATUS);
sys/dev/mge/if_mge.c
1842
if ( !(reg_val & MGE_STATUS_TX_IN_PROG) &&
sys/dev/mge/if_mge.c
1843
(reg_val & MGE_STATUS_TX_FIFO_EMPTY))
sys/dev/mge/if_mge.c
1853
reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
sys/dev/mge/if_mge.c
1854
reg_val &= ~(PORT_SERIAL_ENABLE);
sys/dev/mge/if_mge.c
1855
MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL ,reg_val);
sys/dev/mge/if_mge.c
439
uint32_t reg_idx, reg_off, reg_val, i;
sys/dev/mge/if_mge.c
444
reg_val = (1 | (queue << 1)) << reg_off;
sys/dev/mge/if_mge.c
448
MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
sys/dev/mge/if_mge.c
458
uint32_t reg_val, i;
sys/dev/mge/if_mge.c
466
reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 |
sys/dev/mge/if_mge.c
470
MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val);
sys/dev/mge/if_mge.c
471
MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val);
sys/dev/mge/if_mge.c
475
MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2176
uint64_t reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2189
reg_val = intel_ntb_reg_read(4, base_reg);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2190
(void)reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2193
reg_val = intel_ntb_reg_read(4, lmt_reg);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2194
(void)reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2197
reg_val = intel_ntb_reg_read(8, base_reg);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2198
(void)reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2201
reg_val = intel_ntb_reg_read(8, lmt_reg);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2202
(void)reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2815
uint16_t reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2821
reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2822
if (reg_val == ntb->lnk_sta)
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2825
ntb->lnk_sta = reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2845
uint16_t reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2854
reg_val = intel_ntb_reg_read(2, ntb->reg->lnk_sta);
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2855
if (reg_val == ntb->lnk_sta)
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
2858
ntb->lnk_sta = reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3599
uint64_t base, limit, reg_val;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3640
reg_val = intel_ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3641
if (reg_val != addr) {
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3648
reg_val = intel_ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3649
if (reg_val != limit) {
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3671
reg_val = intel_ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3672
if (reg_val != addr) {
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3679
reg_val = intel_ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK;
sys/dev/ntb/ntb_hw/ntb_hw_intel.c
3680
if (reg_val != limit) {
sys/dev/pms/freebsd/driver/common/lxencrypt.c
802
u32 reg_val = 0, new_cipher_mode = 0;
sys/dev/pms/freebsd/driver/common/lxencrypt.c
810
reg_val |= TI_ENCRYPT_SEC_MODE_FACT_INIT;
sys/dev/pms/freebsd/driver/common/lxencrypt.c
814
reg_val |= TI_ENCRYPT_SEC_MODE_A;
sys/dev/pms/freebsd/driver/common/lxencrypt.c
817
reg_val |= TI_ENCRYPT_SEC_MODE_B;
sys/dev/pms/freebsd/driver/common/lxencrypt.c
823
reg_val |= TI_ENCRYPT_ATTRIB_CIPHER_XTS;
sys/dev/pms/freebsd/driver/common/lxencrypt.c
827
printf("%s: Setting security cipher mode to: 0x%08x\n", __FUNCTION__, reg_val);
sys/dev/pms/freebsd/driver/common/lxencrypt.c
830
rc = tiCOMEncryptSetMode(tiRoot, reg_val);
sys/dev/qat/qat_common/adf_aer.c
124
u32 aer_offset, reg_val = 0;
sys/dev/qat/qat_common/adf_aer.c
127
reg_val =
sys/dev/qat/qat_common/adf_aer.c
129
reg_val |= ADF_PPAERUCM_MASK;
sys/dev/qat/qat_common/adf_aer.c
132
reg_val,
sys/dev/qat/qat_common/adf_aer.c
51
unsigned int aer_offset, reg_val = 0;
sys/dev/qat/qat_common/adf_aer.c
57
reg_val =
sys/dev/qat/qat_common/adf_aer.c
60
hw_data->aerucm_mask = reg_val;
sys/dev/qat/qat_common/adf_freebsd_admin.c
464
u64 reg_val = 0;
sys/dev/qat/qat_common/adf_freebsd_admin.c
570
reg_val = (u64)admin->phy_addr;
sys/dev/qat/qat_common/adf_freebsd_admin.c
571
ADF_CSR_WR(csr, adminmsg_u, reg_val >> 32);
sys/dev/qat/qat_common/adf_freebsd_admin.c
572
ADF_CSR_WR(csr, adminmsg_l, reg_val);
sys/dev/qat/qat_common/qat_hal.c
1001
reg_val = pci_read_config(dev, 0x04, 1);
sys/dev/qat/qat_common/qat_hal.c
1006
if ((reg_val & 0x2) && GET_FCU_CSR(handle, FCU_RAMBASE_ADDR_LO))
sys/dev/qat/qat_common/qat_hal.c
993
u8 reg_val = 0;
sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
137
reg_val = pci_read_config(dev, ADF_200XX_PFIEERRUNCSTSR, 4);
sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
138
if (reg_val) {
sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
142
reg_val);
sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
143
pci_write_config(dev, ADF_200XX_PFIEERRUNCSTSR, reg_val, 4);
sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
86
unsigned int i = 0, bar_nr = 0, reg_val = 0;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1003
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_JABBER) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1011
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_OVERSIZE) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1019
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_FCS)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1022
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_FRAME)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1028
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_CODE)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1034
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_PREAMBLE)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1040
if (reg_val & ADF_C4XXX_MAC_RX_LINK_UP)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1043
if (reg_val & ADF_C4XXX_MAC_INVALID_SPEED)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1049
if (reg_val & ADF_C4XXX_MAC_PIA_RX_FIFO_OVERRUN) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1057
if (reg_val & ADF_C4XXX_MAC_PIA_TX_FIFO_OVERRUN) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1065
if (reg_val & ADF_C4XXX_MAC_PIA_TX_FIFO_UNDERRUN) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1074
ADF_CSR_WR64(aram_base_addr, ADF_C4XXX_MAC_IP + offset, reg_val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1085
u32 reg_val;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1091
reg_val = ADF_CSR_RD(aram_base_addr, rf_par_addr + offset);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1092
intr_status = reg_val & rf_par_msk;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1117
ADF_CSR_WR(aram_base_addr, rf_par_addr + offset, reg_val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1198
u32 reg_val;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1200
reg_val = ADF_CSR_RD(aram_base_addr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1207
if (reg_val & ADF_C4XXX_CONGESTION_MGMT_CTPB_GLOBAL_CROSSED) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1216
if (reg_val & ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_OUT) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1223
if (reg_val & ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_IN) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
1233
reg_val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
932
u32 reg_val = 0;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
934
reg_val = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_IC_PARSER_UERR + offset);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
935
if (reg_val & ADF_C4XXX_PARSER_UERR_INTR) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
937
reg_val &= ~ADF_C4XXX_PARSER_DESC_UERR_INTR_ENA;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
940
reg_val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
959
u64 reg_val;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
961
reg_val = ADF_CSR_RD64(aram_base_addr, ADF_C4XXX_MAC_IP + offset);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
964
if (reg_val & ADF_C4XXX_MAC_ERROR_TX_UNDERRUN)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
970
if (reg_val & ADF_C4XXX_MAC_ERROR_TX_FCS)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
973
if (reg_val & ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT)
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
979
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_OVERRUN) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
987
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_RUNT) {
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
995
if (reg_val & ADF_C4XXX_MAC_ERROR_RX_UNDERSIZE) {
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2226
u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2232
reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr);
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2238
dev_data->block_in_reset[i] = block->has_reset_bit && !(reg_val[block->reset_reg] & (1 << block->reset_bit_offset));
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2854
u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2862
reg_val[block->reset_reg] |= (1 << block->reset_bit_offset);
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2870
reg_val[i] |= s_reset_regs_defs[i].unreset_val[dev_data->chip_id];
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2872
if (reg_val[i])
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
2873
ecore_wr(p_hwfn, p_ptt, s_reset_regs_defs[i].addr + RESET_REG_UNRESET_OFFSET, reg_val[i]);
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
3826
u32 block_size, ram_size, offset = 0, reg_val, i;
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
3834
reg_val = ecore_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr);
sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
3835
block_size = reg_val & (1 << big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 : 128;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1290
u32 reg_val;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1293
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1294
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1295
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1296
if (reg_val) /* TODO: handle E5 init */
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1298
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1301
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1308
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1309
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT, vxlan_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1310
ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1321
u32 reg_val;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1324
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1325
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT, eth_gre_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1326
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1327
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1328
if (reg_val) /* TODO: handle E5 init */
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1330
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1333
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1340
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1341
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT, eth_gre_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1342
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1343
ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1370
u32 reg_val;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1373
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1374
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT, eth_geneve_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1375
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT, ip_geneve_enable);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1376
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1377
if (reg_val) /* TODO: handle E5 init */
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1379
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1382
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1408
u32 reg_val, cfg_mask;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1411
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1419
reg_val |= cfg_mask;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1427
reg_val &= ~cfg_mask;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1431
ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1482
u32 reg_val, cam_line, ram_line_lo, ram_line_hi;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1492
reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID << PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1493
reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1494
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1791
u32 * reg_val;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1820
reg_val = (u32*)rss_ind_mask;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1821
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK, reg_val[0]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1822
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 4, reg_val[1]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1823
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 8, reg_val[2]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1824
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 12, reg_val[3]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1826
reg_val = (u32*)rss_ind_entry;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1827
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA, reg_val[0]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1828
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 4, reg_val[1]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1829
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 8, reg_val[2]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
1830
ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 12, reg_val[3]);
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
658
u32 reg_val, i;
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
660
for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) {
sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
662
reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
sys/dev/qlxge/qls_dump.c
1575
uint32_t reg, reg_val;
sys/dev/qlxge/qls_dump.c
1910
ret = qls_mpi_risc_rd_reg(ha, reg, ®_val);
sys/dev/qlxge/qls_dump.c
1911
mpi_dump->sem_regs[i] = reg_val;
sys/dev/usb/net/if_smsc.c
1337
uint32_t reg_val;
sys/dev/usb/net/if_smsc.c
1369
if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) != 0) {
sys/dev/usb/net/if_smsc.c
1373
reg_val |= SMSC_HW_CFG_BIR;
sys/dev/usb/net/if_smsc.c
1374
smsc_write_reg(sc, SMSC_HW_CFG, reg_val);
sys/dev/usb/net/if_smsc.c
1402
if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) < 0) {
sys/dev/usb/net/if_smsc.c
1410
reg_val &= ~SMSC_HW_CFG_RXDOFF;
sys/dev/usb/net/if_smsc.c
1411
reg_val |= (ETHER_ALIGN << 9) & SMSC_HW_CFG_RXDOFF;
sys/dev/usb/net/if_smsc.c
1417
reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE);
sys/dev/usb/net/if_smsc.c
1419
smsc_write_reg(sc, SMSC_HW_CFG, reg_val);
sys/dev/usb/net/if_smsc.c
1435
reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED |
sys/dev/usb/net/if_smsc.c
1437
smsc_write_reg(sc, SMSC_LED_GPIO_CFG, reg_val);
sys/dev/vnic/nicvf_queues.c
126
uint64_t reg_val;
sys/dev/vnic/nicvf_queues.c
133
reg_val = nicvf_queue_reg_read(nic, reg, qidx);
sys/dev/vnic/nicvf_queues.c
134
if (((reg_val & bit_mask) >> bit_pos) == val)
sys/dev/vnic/nicvf_queues.c
2049
uint64_t reg_val;
sys/dev/vnic/nicvf_queues.c
2051
reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S);
sys/dev/vnic/nicvf_queues.c
2055
reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2058
reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2061
reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2064
reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT);
sys/dev/vnic/nicvf_queues.c
2067
reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
sys/dev/vnic/nicvf_queues.c
2070
reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT);
sys/dev/vnic/nicvf_queues.c
2073
reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2081
nicvf_reg_write(nic, NIC_VF_ENA_W1S, reg_val);
sys/dev/vnic/nicvf_queues.c
2088
uint64_t reg_val = 0;
sys/dev/vnic/nicvf_queues.c
2092
reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2095
reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2098
reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2101
reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT);
sys/dev/vnic/nicvf_queues.c
2104
reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
sys/dev/vnic/nicvf_queues.c
2107
reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT);
sys/dev/vnic/nicvf_queues.c
2110
reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2118
nicvf_reg_write(nic, NIC_VF_ENA_W1C, reg_val);
sys/dev/vnic/nicvf_queues.c
2125
uint64_t reg_val = 0;
sys/dev/vnic/nicvf_queues.c
2129
reg_val = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2132
reg_val = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
sys/dev/vnic/nicvf_queues.c
2135
reg_val = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2138
reg_val = (1UL << NICVF_INTR_PKT_DROP_SHIFT);
sys/dev/vnic/nicvf_queues.c
2141
reg_val = (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
sys/dev/vnic/nicvf_queues.c
2144
reg_val = (1UL << NICVF_INTR_MBOX_SHIFT);
sys/dev/vnic/nicvf_queues.c
2147
reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
sys/dev/vnic/nicvf_queues.c
2155
nicvf_reg_write(nic, NIC_VF_INT, reg_val);
sys/dev/vnic/nicvf_queues.c
2162
uint64_t reg_val;
sys/dev/vnic/nicvf_queues.c
2165
reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S);
sys/dev/vnic/nicvf_queues.c
2195
return (reg_val & mask);
sys/dev/vnic/thunder_bgx.c
248
uint64_t reg_val;
sys/dev/vnic/thunder_bgx.c
251
reg_val = bgx_reg_read(bgx, lmac, reg);
sys/dev/vnic/thunder_bgx.c
252
if (zero && !(reg_val & mask))
sys/dev/vnic/thunder_bgx.c
254
if (!zero && (reg_val & mask))
tools/tools/cxgbtool/cxgbtool.c
246
uint32_t reg_val = 0; // silence compiler warning
tools/tools/cxgbtool/cxgbtool.c
250
reg_val = regs[reg_array->addr / 4];
tools/tools/cxgbtool/cxgbtool.c
252
reg_array->name, reg_val, reg_val);
tools/tools/cxgbtool/cxgbtool.c
254
uint32_t v = xtract(reg_val, reg_array->addr,
usr.sbin/bluetooth/rtlbtfw/main.c
459
uint8_t key_id, reg_val[2];
usr.sbin/bluetooth/rtlbtfw/main.c
460
r = rtlbt_read_reg16(hdl, RTLBT_SEC_PROJ, reg_val);
usr.sbin/bluetooth/rtlbtfw/main.c
465
key_id = reg_val[0];
usr.sbin/cxgbetool/cxgbetool.c
271
uint32_t reg_val = 0;
usr.sbin/cxgbetool/cxgbetool.c
275
reg_val = regs[reg_array->addr / 4];
usr.sbin/cxgbetool/cxgbetool.c
277
reg_array->name, reg_val, reg_val);
usr.sbin/cxgbetool/cxgbetool.c
279
uint32_t v = xtract(reg_val, reg_array->addr,
