bus_space_write_1
bus_space_write_1(t, h, offset, temp);
void bus_space_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset, uint8_t data);
bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val)
bus_space_write_1(_sc->bst[_mux], _sc->bsh[_mux], _reg, _val)
bus_space_write_1(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
__generate_inline_bs_ws(bus_space_write_1, bs_w_1, uint8_t);
bus_space_write_1(sc->sc_bst, sc->sc_bsh,
bus_space_write_1(t, h, reg, val);
#define AAC_MEM0_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag0, \
#define AAC_MEM1_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag1, \
#define AAC_MEM0_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag0, \
#define AAC_MEM1_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag1, \
bus_space_write_1((sc)->ec_data_tag, (sc)->ec_data_handle, 0, (v))
bus_space_write_1((sc)->ec_csr_tag, (sc)->ec_csr_handle, 0, (v))
bus_space_write_1(tag, bsh, HCNTRL, hcntrl | PAUSE);
bus_space_write_1(tag, bsh, 0x80, 0x80 + i);
bus_space_write_1((ahd)->tags[(port) >> 8], \
bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value)
(bus_space_write_1(alpm->smbst, alpm->smbsh, register, value))
(bus_space_write_1((k)->iot, (k)->ioh0, 0, (d)))
(bus_space_write_1((k)->iot, (k)->ioh1, 0, (d)))
bus_space_write_1(sc->bar[BAR0].tag, \
bus_space_write_1(sc->bar[BAR0].tag,
bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
bus_space_write_1(sc->sc_tag, sc->sc_handle,
(bus_space_write_1(rman_get_bustag((reg)), \
bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
bus_space_write_1(sc->bst, sc->bsh, sc->offset + reg, val);
bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);
bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);
bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_DATA, val);
bus_space_write_1(exca->bst, exca->bsh, EXCA_REG_INDEX,
bus_space_write_1(exca->bst, exca->bsh, EXCA_REG_INDEX,
#define outb_p(value, offset) bus_space_write_1(sc->st, sc->sh, offset, value)
#define outb_enh(value, offset) bus_space_write_1(sc->enh_st, sc->enh_sh, \
bus_space_write_1(fdc->iot, fdc->ioh[reg], fdc->ioff[reg], v);
bus_space_write_1(hba->bar0t, hba->bar0h, bus + i, byte);
bus_space_write_1(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
#define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\
bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val);\
bus_space_write_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
bus_space_write_1(oct->mem_bus_space[0].tag,
bus_space_write_1(oct->mem_bus_space[1].tag,
#define MFI_WRITE1(sc, reg, val) bus_space_write_1((sc)->mfi_btag, \
bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)
((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
: (bus_space_write_1((sc)->devcfg_btag, \
return bus_space_write_1(reg->btag, reg->bhandle, off, val);
bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
bus_space_write_1(pc->pc_st, pc->pc_sh, addr, val);
bus_space_write_1(
bus_space_write_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg), value)
bus_space_write_1(btag, 0x0, 0x70, i + off);
bus_space_write_1(sc->st, sc->sh, ALS_GCR_INDEX, index);
bus_space_write_1(sc->st, sc->sh, ALS_GCR_INDEX, index);
bus_space_write_1(sc->st, sc->sh, ALS_SB_MPU_IRQ, data);
bus_space_write_1(sc->st, sc->sh, ALS_MIXER_INDEX, index);
bus_space_write_1(sc->st, sc->sh, ALS_MIXER_INDEX, index);
bus_space_write_1(sc->st, sc->sh, ALS_MIXER_DATA, data);
bus_space_write_1(sc->st, sc->sh, ALS_ESP_WR_DATA, data);
bus_space_write_1(sc->st, sc->sh, ALS_ESP_RST, 1);
bus_space_write_1(sc->st, sc->sh, ALS_ESP_RST, 0);
bus_space_write_1(sc->st, sc->sh, regno, data);
bus_space_write_1(0,0,0x330 + reg , b);
bus_space_write_1(sc->st, sc->sh, regno, data);
bus_space_write_1(sc->st, sc->sh, regno, data);
bus_space_write_1(sc->cst, sc->csh, regno, data);
bus_space_write_1(sc->mtt, sc->mth, regno, data);
bus_space_write_1(sc->cst, sc->csh, regno, data);
bus_space_write_1(sc->mtt, sc->mth, regno, data);
bus_space_write_1(es->st, es->sh, regno, data);
bus_space_write_1(fm801->st, fm801->sh, regno, data);
bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
#define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
bus_space_write_1(st, sh, regno, data);
bus_space_write_1(st, sh, regno, data);
bus_space_write_1(st, sh, regno, data);
bus_space_write_1(tr->st, tr->sh, regno, data);
bus_space_write_1(via->st, via->sh, regno, data);
bus_space_write_1(via->st, via->sh, regno, data);
bus_space_write_1(sc->enh_st, sc->enh_sh, reg, val);
bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);
bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);
bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_DATA, val);
bus_space_write_1(st, sh, SV_DMA_MODE, mode);
bus_space_write_1(iot, ioh, r, 1);
bus_space_write_1(iot, ioh, v, 0);
bus_space_write_1(sc->sc_batm, sc->sc_bahm, 1,
bus_space_write_1(sc->sc_batm, sc->sc_bahm, 0, *p++);
bus_space_write_1(sc->sc_batm, sc->sc_bahm, 1, TPM_LEGACY_ABRT);
bus_space_write_1(bt, bh, TPM_ACCESS, TPM_ACCESS_REQUEST_USE);
bus_space_write_1(bt, bh, TPM_ACCESS, save);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_INT_VECTOR, irq);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS,
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_DATA, *p++);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_DATA, *p++);
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,
bus_space_write_1(sc->sc_bt, sc->sc_bh,TPM_ACCESS,
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,
bus_space_write_1(iot, ioh, 0, reg);
bus_space_write_1(iot, ioh, 0, reg);
bus_space_write_1(iot, ioh, 1, v);
bus_space_write_1(sc->bus_mfa_tag, sc->bus_mfa_handle,i,
bus_space_write_1(bus_tag, bus_handle, offset, (u_int8_t)value);
bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (a), (x))
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a), (x))
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
bus_space_write_1(bs_parent_space(bs), h, awusbdrd_reg(o), v);
do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0)
do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE, (data))
bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val)
bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val)
bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
#define bus_space_write_stream_1 bus_space_write_1
bus_space_write_1(sc->sc_bst, sc->sc_bsh, off, val);
bus_space_write_1(sc->bst, sc->bsh, off, val);
bus_space_write_1(sc->sc_bst, sc->sc_bsh,
bus_space_write_1((r)->r_bustag, (r)->r_bushandle, (o), (v))
bus_space_write_1((t), (h), (o), (v))
static __inline void bus_space_write_1(bus_space_tag_t tag,