crypto/libecc/src/nn/nn_div.c

625

#define WORD_CND_SUB_21(cnd, ah, al, b) do { \

crypto/libecc/src/nn/nn_div.c

629

(ah) = (word_t)((ah) - (tmp > (al))); \

crypto/libecc/src/nn/nn_div.c

633

#define WORD_CND_SUB_22(cnd, ah, al, bh, bl) do { \

crypto/libecc/src/nn/nn_div.c

637

(ah) = (word_t)((ah) - (tmp > (al))); \

crypto/libecc/src/nn/nn_div.c

639

(ah) = (word_t)((ah) - ((bh) & mask)); \

crypto/libecc/src/nn/nn_div.c

649

ATTRIBUTE_WARN_UNUSED_RET static int _word_divrem(word_t *q, word_t *r, word_t ah, word_t al, word_t b)

crypto/libecc/src/nn/nn_div.c

658

rhl[1] = ah;

crypto/openssl/crypto/sha/sha512.c

540

_asm mov edx, [ecx + 0] _asm mov eax, [ecx + 4] _asm xchg dh, dl _asm xchg ah, al _asm rol edx, 16 _asm rol eax, 16 _asm xchg dh, dl _asm xchg ah, al

sbin/ping/ping6.c

2563

struct ah ah;

sbin/ping/ping6.c

2590

memcpy(&ah, cp, sizeof(ah));

sbin/ping/ping6.c

2591

hlen = (ah.ah_len+2) << 2;

sbin/ping/ping6.c

2592

nh = ah.ah_nxt;

stand/libsa/arp.c

100

ah->arp_pro = htons(ETHERTYPE_IP);

stand/libsa/arp.c

101

ah->arp_hln = sizeof(ah->arp_sha); /* hardware address length */

stand/libsa/arp.c

102

ah->arp_pln = sizeof(ah->arp_spa); /* protocol address length */

stand/libsa/arp.c

103

ah->arp_op = htons(ARPOP_REQUEST);

stand/libsa/arp.c

104

MACPY(d->myea, ah->arp_sha);

stand/libsa/arp.c

105

bcopy(&d->myip, ah->arp_spa, sizeof(ah->arp_spa));

stand/libsa/arp.c

107

bcopy(&addr, ah->arp_tpa, sizeof(ah->arp_tpa));

stand/libsa/arp.c

113

ah = NULL;

stand/libsa/arp.c

116

arprecv, &pkt, (void **)&ah, NULL);

stand/libsa/arp.c

131

inet_ntoa(addr), ether_sprintf(ah->arp_sha));

stand/libsa/arp.c

134

MACPY(ah->arp_sha, al->ea);

stand/libsa/arp.c

161

struct ether_arp *ah;

stand/libsa/arp.c

171

n = readether(d, &ptr, (void **)&ah, tleft, &etype);

stand/libsa/arp.c

192

if (ah->arp_hrd != htons(ARPHRD_ETHER) ||

stand/libsa/arp.c

193

ah->arp_pro != htons(ETHERTYPE_IP) ||

stand/libsa/arp.c

194

ah->arp_hln != sizeof(ah->arp_sha) ||

stand/libsa/arp.c

195

ah->arp_pln != sizeof(ah->arp_spa) )

stand/libsa/arp.c

205

if (ah->arp_op == htons(ARPOP_REQUEST)) {

stand/libsa/arp.c

210

arp_reply(d, ah);

stand/libsa/arp.c

215

if (ah->arp_op != htons(ARPOP_REPLY)) {

stand/libsa/arp.c

226

ah->arp_spa, sizeof(ah->arp_spa)))

stand/libsa/arp.c

243

*payload = ah;

stand/libsa/arp.c

70

struct ether_arp *ah;

stand/libsa/arp.c

98

ah = &wbuf.data.arp;

stand/libsa/arp.c

99

ah->arp_hrd = htons(ARPHRD_ETHER);

stand/libsa/ip.c

420

struct arphdr *ah = data;

stand/libsa/ip.c

424

if (ah->ar_op == htons(ARPOP_REQUEST)) {

stand/libsa/ip.c

426

arp_reply(d, ah);

sys/dev/acpica/acpi_ged.c

105

AcpiEvaluateObject(evt->ah, NULL, &evt->args, NULL);

sys/dev/acpica/acpi_ged.c

223

name, &sc->evts[i].ah))) {

sys/dev/acpica/acpi_ged.c

226

sc->evts[i].ah = NULL; /* ensure */

sys/dev/acpica/acpi_ged.c

230

if (sc->evts[i].ah == NULL) {

sys/dev/acpica/acpi_ged.c

232

sc->evts[i].ah = evt_method;

sys/dev/acpica/acpi_ged.c

51

ACPI_HANDLE ah;

sys/dev/acpica/acpi_ged.c

94

AcpiEvaluateObject(evt->ah, NULL, &evt->args, NULL);

sys/dev/ath/ah_osdep.c

119

ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)

sys/dev/ath/ah_osdep.c

125

ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)

sys/dev/ath/ah_osdep.c

129

ath_hal_vprintf(ah, fmt, ap);

sys/dev/ath/ah_osdep.c

147

ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg)

sys/dev/ath/ah_osdep.c

160

DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)

sys/dev/ath/ah_osdep.c

163

(ah != NULL && ah->ah_config.ah_debug & mask) ||

sys/dev/ath/ah_osdep.c

167

ath_hal_vprintf(ah, fmt, ap);

sys/dev/ath/ah_osdep.c

247

ath_hal_alq_get(struct ath_hal *ah)

sys/dev/ath/ah_osdep.c

258

r->val = ah->ah_devid;

sys/dev/ath/ah_osdep.c

271

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/ath/ah_osdep.c

273

bus_space_tag_t tag = BUSTAG(ah);

sys/dev/ath/ah_osdep.c

274

bus_space_handle_t h = ah->ah_sh;

sys/dev/ath/ah_osdep.c

278

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

279

ah->ah_powerMode != HAL_PM_AWAKE) {

sys/dev/ath/ah_osdep.c

280

ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",

sys/dev/ath/ah_osdep.c

281

__func__, reg, val, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

286

struct ale *ale = ath_hal_alq_get(ah);

sys/dev/ath/ah_osdep.c

296

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

299

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/ath/ah_osdep.c

300

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

305

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/ath/ah_osdep.c

307

bus_space_tag_t tag = BUSTAG(ah);

sys/dev/ath/ah_osdep.c

308

bus_space_handle_t h = ah->ah_sh;

sys/dev/ath/ah_osdep.c

313

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

314

ah->ah_powerMode != HAL_PM_AWAKE) {

sys/dev/ath/ah_osdep.c

315

ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",

sys/dev/ath/ah_osdep.c

316

__func__, reg, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

320

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

322

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/ath/ah_osdep.c

324

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

327

struct ale *ale = ath_hal_alq_get(ah);

sys/dev/ath/ah_osdep.c

341

OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)

sys/dev/ath/ah_osdep.c

344

struct ale *ale = ath_hal_alq_get(ah);

sys/dev/ath/ah_osdep.c

369

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/ath/ah_osdep.c

371

bus_space_tag_t tag = BUSTAG(ah);

sys/dev/ath/ah_osdep.c

372

bus_space_handle_t h = ah->ah_sh;

sys/dev/ath/ah_osdep.c

376

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

377

ah->ah_powerMode != HAL_PM_AWAKE) {

sys/dev/ath/ah_osdep.c

378

ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",

sys/dev/ath/ah_osdep.c

379

__func__, reg, val, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

383

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

386

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/ath/ah_osdep.c

387

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

392

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/ath/ah_osdep.c

394

bus_space_tag_t tag = BUSTAG(ah);

sys/dev/ath/ah_osdep.c

395

bus_space_handle_t h = ah->ah_sh;

sys/dev/ath/ah_osdep.c

400

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

401

ah->ah_powerMode != HAL_PM_AWAKE) {

sys/dev/ath/ah_osdep.c

402

ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",

sys/dev/ath/ah_osdep.c

403

__func__, reg, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

407

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

409

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/ath/ah_osdep.c

411

if (ah->ah_config.ah_serialise_reg_war)

sys/dev/ath/ah_osdep.c

60

#define BUSTAG(ah) \

sys/dev/ath/ah_osdep.c

61

((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)

sys/dev/ath/ah_osdep.c

63

#define BUSTAG(ah) ((ah)->ah_st)

sys/dev/ath/ah_osdep.c

89

extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);

sys/dev/ath/ah_osdep.h

140

extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);

sys/dev/ath/ah_osdep.h

141

extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);

sys/dev/ath/ath_hal/ah.c

1000

*result = &AH_PRIVATE(ah)->ah_fatalState[0];

sys/dev/ath/ath_hal/ah.c

1001

*resultsize = sizeof(AH_PRIVATE(ah)->ah_fatalState);

sys/dev/ath/ath_hal/ah.c

1006

if (!ath_hal_eepromRead(ah, *(const uint16_t *)args, *result))

sys/dev/ath/ath_hal/ah.c

101

if (ah != AH_NULL) {

sys/dev/ath/ath_hal/ah.c

1017

return ah->ah_setKeyCacheEntry(ah, dk->dk_keyix,

sys/dev/ath/ath_hal/ah.c

1023

return ah->ah_resetKeyCacheEntry(ah, *(const uint16_t *)args);

sys/dev/ath/ath_hal/ah.c

103

ah->ah_devid = AH_PRIVATE(ah)->ah_devid;

sys/dev/ath/ath_hal/ah.c

1030

return ath_hal_eepromWrite(ah, ee->ee_off, ee->ee_data);

sys/dev/ath/ath_hal/ah.c

1038

AH_PRIVATE(ah)->ah_11nCompat;

sys/dev/ath/ath_hal/ah.c

104

ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid;

sys/dev/ath/ath_hal/ah.c

1040

AH_PRIVATE(ah)->ah_11nCompat = *(const uint32_t *)args;

sys/dev/ath/ath_hal/ah.c

1045

*result = &AH_PRIVATE(ah)->ah_chansurvey;

sys/dev/ath/ath_hal/ah.c

105

ah->ah_macVersion = AH_PRIVATE(ah)->ah_macVersion;

sys/dev/ath/ath_hal/ah.c

1057

ath_hal_setTxQProps(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.c

106

ah->ah_macRev = AH_PRIVATE(ah)->ah_macRev;

sys/dev/ath/ath_hal/ah.c

1063

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ah.c

107

ah->ah_phyRev = AH_PRIVATE(ah)->ah_phyRev;

sys/dev/ath/ath_hal/ah.c

108

ah->ah_analog5GhzRev = AH_PRIVATE(ah)->ah_analog5GhzRev;

sys/dev/ath/ath_hal/ah.c

109

ah->ah_analog2GhzRev = AH_PRIVATE(ah)->ah_analog2GhzRev;

sys/dev/ath/ath_hal/ah.c

110

return ah;

sys/dev/ath/ath_hal/ah.c

1118

ath_hal_getTxQProps(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.c

1122

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ah.c

1156

ath_hal_getChanNoise(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ah.c

1160

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ah.c

1162

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ah.c

1168

WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);

sys/dev/ath/ath_hal/ah.c

117

struct ath_hal *ah;

sys/dev/ath/ath_hal/ah.c

1171

return NOISE_FLOOR[mode] + ath_hal_getNfAdjust(ah, ichan);

sys/dev/ath/ath_hal/ah.c

1186

ath_hal_get_mimo_chan_noise(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.c

1193

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ah.c

1195

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ah.c

1212

WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);

sys/dev/ath/ath_hal/ah.c

122

ah = chip->attach(devid, sc, st, sh, eepromdata, ah_config,

sys/dev/ath/ath_hal/ah.c

1221

ath_hal_getNfAdjust(ah, ichan);

sys/dev/ath/ath_hal/ah.c

1239

nf_ctl[i] = ichan->noiseFloorCtl[i] + ath_hal_getNfAdjust(ah, ichan);

sys/dev/ath/ath_hal/ah.c

124

if (ah != AH_NULL) {

sys/dev/ath/ath_hal/ah.c

1240

nf_ext[i] = ichan->noiseFloorExt[i] + ath_hal_getNfAdjust(ah, ichan);

sys/dev/ath/ath_hal/ah.c

1253

ath_hal_process_noisefloor(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.c

126

ah->ah_devid = AH_PRIVATE(ah)->ah_devid;

sys/dev/ath/ath_hal/ah.c

1266

for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {

sys/dev/ath/ath_hal/ah.c

127

ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid;

sys/dev/ath/ath_hal/ah.c

1270

c = &AH_PRIVATE(ah)->ah_channels[i];

sys/dev/ath/ath_hal/ah.c

1276

ath_hal_getNfAdjust(ah, c);

sys/dev/ath/ath_hal/ah.c

128

ah->ah_macVersion = AH_PRIVATE(ah)->ah_macVersion;

sys/dev/ath/ath_hal/ah.c

1281

(c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));

sys/dev/ath/ath_hal/ah.c

1287

(c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));

sys/dev/ath/ath_hal/ah.c

129

ah->ah_macRev = AH_PRIVATE(ah)->ah_macRev;

sys/dev/ath/ath_hal/ah.c

1293

for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {

sys/dev/ath/ath_hal/ah.c

1294

c = &AH_PRIVATE(ah)->ah_channels[i];

sys/dev/ath/ath_hal/ah.c

1298

c->noiseFloorAdjust = ath_hal_getNfAdjust(ah, c) +

sys/dev/ath/ath_hal/ah.c

130

ah->ah_phyRev = AH_PRIVATE(ah)->ah_phyRev;

sys/dev/ath/ath_hal/ah.c

1300

HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u raw nf %d adjust %d\n",

sys/dev/ath/ath_hal/ah.c

131

ah->ah_analog5GhzRev = AH_PRIVATE(ah)->ah_analog5GhzRev;

sys/dev/ath/ath_hal/ah.c

1310

ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ah.c

1317

OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0),

sys/dev/ath/ath_hal/ah.c

132

ah->ah_analog2GhzRev = AH_PRIVATE(ah)->ah_analog2GhzRev;

sys/dev/ath/ath_hal/ah.c

133

return ah;

sys/dev/ath/ath_hal/ah.c

1340

ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ah.c

1346

OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), data[r]);

sys/dev/ath/ath_hal/ah.c

141

ath_hal_mac_name(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.c

143

switch (ah->ah_macVersion) {

sys/dev/ath/ath_hal/ah.c

1468

ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)

sys/dev/ath/ath_hal/ah.c

1471

OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta);

sys/dev/ath/ath_hal/ah.c

1478

ath_hal_setcca(struct ath_hal *ah, int ena)

sys/dev/ath/ath_hal/ah.c

1493

ath_hal_getcca(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.c

1496

if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK)

sys/dev/ath/ath_hal/ah.c

1508

ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena)

sys/dev/ath/ath_hal/ah.c

1511

if (ah->ah_setDfsCacTxQuiet == NULL)

sys/dev/ath/ath_hal/ah.c

1513

ah->ah_setDfsCacTxQuiet(ah, ena);

sys/dev/ath/ath_hal/ah.c

1525

ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data)

sys/dev/ath/ath_hal/ah.c

1527

if (ah->ah_eepromdata == AH_NULL) {

sys/dev/ath/ath_hal/ah.c

1528

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no eeprom data!\n", __func__);

sys/dev/ath/ath_hal/ah.c

1532

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: offset %x > %x\n",

sys/dev/ath/ath_hal/ah.c

1536

(*data) = ah->ah_eepromdata[off];

sys/dev/ath/ath_hal/ah.c

1547

ath_hal_mhz2ieee_2ghz(struct ath_hal *ah, int freq)

sys/dev/ath/ath_hal/ah.c

1564

ath_hal_survey_clear(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.c

1567

OS_MEMZERO(&AH_PRIVATE(ah)->ah_chansurvey,

sys/dev/ath/ath_hal/ah.c

1568

sizeof(AH_PRIVATE(ah)->ah_chansurvey));

sys/dev/ath/ath_hal/ah.c

1575

ath_hal_survey_add_sample(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)

sys/dev/ath/ath_hal/ah.c

1579

cs = &AH_PRIVATE(ah)->ah_chansurvey;

sys/dev/ath/ath_hal/ah.c

173

if (AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ah.c

179

if (AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ah.c

183

if (ah->ah_macRev >= AR_SREV_REVISION_AR9580_10)

sys/dev/ath/ath_hal/ah.c

208

ath_hal_getwirelessmodes(struct ath_hal*ah)

sys/dev/ath/ath_hal/ah.c

210

return ath_hal_getWirelessModes(ah);

sys/dev/ath/ath_hal/ah.c

238

ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)

sys/dev/ath/ath_hal/ah.c

245

if (rf->probe(ah))

sys/dev/ath/ath_hal/ah.c

250

if (rf->probe(ah))

sys/dev/ath/ath_hal/ah.c

258

ath_hal_rf_name(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.c

260

switch (ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ah.c

303

ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)

sys/dev/ath/ath_hal/ah.c

306

return ath_hal_waitfor(ah, reg, mask, val, AH_TIMEOUT);

sys/dev/ath/ath_hal/ah.c

311

ath_hal_waitfor(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val, uint32_t timeout)

sys/dev/ath/ath_hal/ah.c

316

if ((OS_REG_READ(ah, reg) & mask) == val)

sys/dev/ath/ath_hal/ah.c

320

HALDEBUG(ah, HAL_DEBUG_REGIO | HAL_DEBUG_PHYIO,

sys/dev/ath/ath_hal/ah.c

322

__func__, reg, OS_REG_READ(ah, reg), mask, val);

sys/dev/ath/ath_hal/ah.c

361

ath_hal_pkt_txtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t frameLen,

sys/dev/ath/ath_hal/ah.c

372

return ath_hal_computetxtime(ah, rates, frameLen, rateix,

sys/dev/ath/ath_hal/ah.c

430

ath_hal_computetxtime(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.c

439

ath_hal_printf(ah, "%s: MCS rate? (index %d; hwrate 0x%x)\n",

sys/dev/ath/ath_hal/ah.c

505

HALDEBUG(ah, HAL_DEBUG_PHYIO,

sys/dev/ath/ath_hal/ah.c

515

ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ah.c

573

ath_hal_chan2wmode(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ah.c

595

ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)

sys/dev/ath/ath_hal/ah.c

597

const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ah.c

602

if (c != AH_NULL && IS_5GHZ_FAST_CLOCK_EN(ah, c)) {

sys/dev/ath/ath_hal/ah.c

607

clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];

sys/dev/ath/ath_hal/ah.c

623

ath_hal_mac_usec(struct ath_hal *ah, u_int clks)

sys/dev/ath/ath_hal/ah.c

627

psec = ath_hal_mac_psec(ah, clks);

sys/dev/ath/ath_hal/ah.c

635

ath_hal_mac_psec(struct ath_hal *ah, u_int clks)

sys/dev/ath/ath_hal/ah.c

637

const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ah.c

642

if (c != AH_NULL && IS_5GHZ_FAST_CLOCK_EN(ah, c)) {

sys/dev/ath/ath_hal/ah.c

647

psec = (clks * 1000000ULL) / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];

sys/dev/ath/ath_hal/ah.c

667

ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)

sys/dev/ath/ath_hal/ah.c

691

rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt,

sys/dev/ath/ath_hal/ah.c

693

rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt,

sys/dev/ath/ath_hal/ah.c

700

ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ah.c

703

const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ah.c

707

*result = AH_PRIVATE(ah)->ah_currentRD;

sys/dev/ath/ath_hal/ah.c

710

*result = AH_PRIVATE(ah)->ah_dfsDomain;

sys/dev/ath/ath_hal/ah.c

740

*result = AH_PRIVATE(ah)->ah_diagreg;

sys/dev/ath/ath_hal/ah.c

747

*result = AH_PRIVATE(ah)->ah_powerLimit;

sys/dev/ath/ath_hal/ah.c

750

*result = AH_PRIVATE(ah)->ah_maxPowerLevel;

sys/dev/ath/ath_hal/ah.c

753

*result = AH_PRIVATE(ah)->ah_tpScale;

sys/dev/ath/ath_hal/ah.c

768

return AH_PRIVATE(ah)->ah_rfkillEnabled ?

sys/dev/ath/ath_hal/ah.c

771

*result = AH_PRIVATE(ah)->ah_rfsilent;

sys/dev/ath/ath_hal/ah.c

815

*result = AH_PRIVATE(ah)->ah_currentRDext;

sys/dev/ath/ath_hal/ah.c

863

return AH_PRIVATE(ah)->ah_rxornIsFatal ? HAL_OK : HAL_ENOTSUPP;

sys/dev/ath/ath_hal/ah.c

902

ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ah.c

911

AH_PRIVATE(ah)->ah_tpScale = setting;

sys/dev/ath/ath_hal/ah.c

924

AH_PRIVATE(ah)->ah_rfkillEnabled = (setting != 0);

sys/dev/ath/ath_hal/ah.c

928

AH_PRIVATE(ah)->ah_rfsilent = setting;

sys/dev/ath/ath_hal/ah.c

933

AH_PRIVATE(ah)->ah_currentRD = setting;

sys/dev/ath/ath_hal/ah.c

936

AH_PRIVATE(ah)->ah_rxornIsFatal = setting;

sys/dev/ath/ath_hal/ah.c

94

struct ath_hal *ah;

sys/dev/ath/ath_hal/ah.c

951

ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,

sys/dev/ath/ath_hal/ah.c

964

*dp++ = OS_REG_READ(ah, r);

sys/dev/ath/ath_hal/ah.c

973

ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space)

sys/dev/ath/ath_hal/ah.c

976

OS_REG_WRITE(ah, regs->addr, regs->value);

sys/dev/ath/ath_hal/ah.c

982

ath_hal_getdiagstate(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah.c

989

*result = &AH_PRIVATE(ah)->ah_devid;

sys/dev/ath/ath_hal/ah.c

99

ah = chip->attach(devid, sc, st, sh, eepromdata, ah_config,

sys/dev/ath/ath_hal/ah.c

993

*resultsize = ath_hal_getregdump(ah, args, *result,*resultsize);

sys/dev/ath/ath_hal/ah.c

996

ath_hal_setregs(ah, args, argsize);

sys/dev/ath/ath_hal/ah.h

1280

HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ah.h

1281

HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ah.h

1309

void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ah.h

1311

void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ah.h

1313

void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ah.h

1400

HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,

sys/dev/ath/ath_hal/ah.h

1409

void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1411

void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1413

HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1415

HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1418

HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah.h

1422

void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1424

void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1506

HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah.h

1626

extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1634

extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah.h

1644

extern int ath_hal_get_curmode(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1650

extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1672

extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta);

sys/dev/ath/ath_hal/ah.h

1677

void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena);

sys/dev/ath/ath_hal/ah.h

1682

int __ahdecl ath_hal_getcca(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah.h

1687

void __ahdecl ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena);

sys/dev/ath/ath_hal/ah.h

1692

HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah.h

1699

ath_hal_get_mfp_qos(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah.h

1708

extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);

sys/dev/ath/ath_hal/ah.h

1709

extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);

sys/dev/ath/ath_hal/ah.h

1710

extern uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks);

sys/dev/ath/ath_hal/ah_eeprom.h

163

HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_eeprom.h

164

HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_eeprom.h

165

HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_eeprom.h

166

HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_eeprom.h

167

HAL_STATUS ath_hal_9287EepromAttach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_eeprom_9287.c

124

v9287EepromSet(struct ath_hal *ah, int param, int v)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

126

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

138

v9287EepromDiag(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

141

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

205

v9287EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

207

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

243

v9287EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_9287 *ee)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

268

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

27

v9287EepromGet(struct ath_hal *ah, int param, void *val)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

276

v9287EepromDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

278

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

281

AH_PRIVATE(ah)->ah_eeprom = AH_NULL;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

290

ath_hal_9287EepromAttach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_9287.c

293

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

306

if (ah->ah_eepromdata == NULL) {

sys/dev/ath/ath_hal/ah_eeprom_9287.c

307

if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {

sys/dev/ath/ath_hal/ah_eeprom_9287.c

308

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

312

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_9287.c

315

HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");

sys/dev/ath/ath_hal/ah_eeprom_9287.c

32

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

329

if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {

sys/dev/ath/ath_hal/ah_eeprom_9287.c

330

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

341

if (ah->ah_eepromdata == NULL && isBigEndian()) {

sys/dev/ath/ath_hal/ah_eeprom_9287.c

352

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

372

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

385

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

391

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_9287.c

396

v9287EepromReadCTLInfo(ah, ee); /* Get CTLs */

sys/dev/ath/ath_hal/ah_eeprom_9287.c

398

AH_PRIVATE(ah)->ah_eeprom = ee;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

399

AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

400

AH_PRIVATE(ah)->ah_eepromDetach = v9287EepromDetach;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

401

AH_PRIVATE(ah)->ah_eepromGet = v9287EepromGet;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

402

AH_PRIVATE(ah)->ah_eepromSet = v9287EepromSet;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

403

AH_PRIVATE(ah)->ah_getSpurChan = v9287EepromGetSpurChan;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

404

AH_PRIVATE(ah)->ah_eepromDiag = v9287EepromDiag;

sys/dev/ath/ath_hal/ah_eeprom_9287.c

51

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",

sys/dev/ath/ath_hal/ah_eeprom_9287.h

22

#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \

sys/dev/ath/ath_hal/ah_eeprom_9287.h

23

ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))

sys/dev/ath/ath_hal/ah_eeprom_v1.c

102

v1EepromDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v1.c

104

HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

107

AH_PRIVATE(ah)->ah_eeprom = AH_NULL;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

111

ath_hal_v1EepromAttach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v1.c

113

HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

121

if (!ath_hal_eepromRead(ah, AR_EEPROM_MAGIC, &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v1.c

122

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

127

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

132

if (!ath_hal_eepromRead(ah, AR_EEPROM_PROTECT, &protect)) {

sys/dev/ath/ath_hal/ah_eeprom_v1.c

133

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

138

HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", protect);

sys/dev/ath/ath_hal/ah_eeprom_v1.c

141

if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &eeprom_version)) {

sys/dev/ath/ath_hal/ah_eeprom_v1.c

142

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

150

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

161

if (!ath_hal_eepromRead(ah, AR_EEPROM_ATHEROS(i), &athvals[i]))

sys/dev/ath/ath_hal/ah_eeprom_v1.c

166

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad EEPROM checksum 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v1.c

174

if (!ath_hal_eepromRead(ah, AR_EEPROM_REG_DOMAIN, &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v1.c

175

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

245

AH_PRIVATE(ah)->ah_eeprom = ee;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

246

AH_PRIVATE(ah)->ah_eeversion = eeprom_version;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

247

AH_PRIVATE(ah)->ah_eepromDetach = v1EepromDetach;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

248

AH_PRIVATE(ah)->ah_eepromGet = v1EepromGet;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

249

AH_PRIVATE(ah)->ah_eepromSet = v1EepromSet;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

250

AH_PRIVATE(ah)->ah_getSpurChan = v1EepromGetSpurChan;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

251

AH_PRIVATE(ah)->ah_eepromDiag = v1EepromDiag;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

26

v1EepromGet(struct ath_hal *ah, int param, void *val)

sys/dev/ath/ath_hal/ah_eeprom_v1.c

28

HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

39

if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(i), &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v1.c

40

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

50

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",

sys/dev/ath/ath_hal/ah_eeprom_v1.c

72

v1EepromSet(struct ath_hal *ah, int param, int v)

sys/dev/ath/ath_hal/ah_eeprom_v1.c

78

v1EepromDiag(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_eeprom_v1.c

81

HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v1.c

93

v1EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

160

v14EepromSet(struct ath_hal *ah, int param, int v)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

162

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

176

v14EepromDiag(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

179

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

247

v14EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

249

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

26

v14EepromGet(struct ath_hal *ah, int param, void *val)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

281

v14EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v14 *ee)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

306

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

31

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

314

v14EepromDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

316

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

319

AH_PRIVATE(ah)->ah_eeprom = AH_NULL;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

333

ath_hal_v14EepromAttach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v14.c

336

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

349

if (ah->ah_eepromdata == NULL) {

sys/dev/ath/ath_hal/ah_eeprom_v14.c

350

if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {

sys/dev/ath/ath_hal/ah_eeprom_v14.c

351

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

355

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v14.c

358

HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");

sys/dev/ath/ath_hal/ah_eeprom_v14.c

372

if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {

sys/dev/ath/ath_hal/ah_eeprom_v14.c

373

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

381

if (ah->ah_eepromdata == NULL && isBigEndian()) {

sys/dev/ath/ath_hal/ah_eeprom_v14.c

392

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

412

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

425

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

431

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v14.c

436

v14EepromReadCTLInfo(ah, ee); /* Get CTLs */

sys/dev/ath/ath_hal/ah_eeprom_v14.c

438

AH_PRIVATE(ah)->ah_eeprom = ee;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

439

AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

440

AH_PRIVATE(ah)->ah_eepromDetach = v14EepromDetach;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

441

AH_PRIVATE(ah)->ah_eepromGet = v14EepromGet;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

442

AH_PRIVATE(ah)->ah_eepromSet = v14EepromSet;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

443

AH_PRIVATE(ah)->ah_getSpurChan = v14EepromGetSpurChan;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

444

AH_PRIVATE(ah)->ah_eepromDiag = v14EepromDiag;

sys/dev/ath/ath_hal/ah_eeprom_v14.c

53

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1013

readEepromCTLInfo(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1016

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1110

readHeaderInfo(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1113

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

137

eepromAllocExpnPower5112(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1500

legacyEepromReadContents(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1503

if (!readHeaderInfo(ah, ee))

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1507

if (IS_5112(ah) && !ee->ee_eepMap) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1508

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

151

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1522

if (!readEepromFreqPierInfo(ah, ee))

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1532

if (!readEepromRawPowerCalInfo(ah, ee))

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1542

if (!readEepromTargetPowerCalInfo(ah, ee))

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1553

return readEepromCTLInfo(ah, ee);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1557

legacyEepromGet(struct ath_hal *ah, int param, void *val)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1559

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1573

if (!ath_hal_eepromRead(ah, AR_EEPROM_RFSILENT, &eeval))

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1581

if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(2-i), &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1582

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1592

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1619

ath_hal_eepromRead(ah, 0x0b, &eeval) && eeval == 1) ?

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1669

legacyEepromSet(struct ath_hal *ah, int param, int v)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1671

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1718

legacyEepromDiag(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1721

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1745

legacyEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1747

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1757

legacyEepromDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1759

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1762

freeEepromRawPowerCalInfo5112(ah, ee);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1764

AH_PRIVATE(ah)->ah_eeprom = AH_NULL;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1775

ath_hal_legacyEepromAttach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1777

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1784

if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &eeversion)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1785

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

179

eepromExpandPower5112(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1790

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM version "

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1795

if (!ath_hal_eepromRead(ah, AR_EEPROM_PROTECT, &eeprotect)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1796

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cannot read EEPROM protection "

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1800

HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", eeprotect);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1806

if (!ath_hal_eepromRead(ah, AR_EEPROM_SIZE_UPPER, &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1807

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1814

if (!ath_hal_eepromRead(ah, AR_EEPROM_SIZE_LOWER, &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1815

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1824

if (!ath_hal_eepromRead(ah, AR_EEPROM_ATHEROS(i), &eeval)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1830

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad EEPROM checksum 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1854

if (ah->ah_magic == 0x19570405)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1862

if (!legacyEepromReadContents(ah, ee)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1868

AH_PRIVATE(ah)->ah_eeprom = ee;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1869

AH_PRIVATE(ah)->ah_eeversion = eeversion;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1870

AH_PRIVATE(ah)->ah_eepromDetach = legacyEepromDetach;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1871

AH_PRIVATE(ah)->ah_eepromGet = legacyEepromGet;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1872

AH_PRIVATE(ah)->ah_eepromSet = legacyEepromSet;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1873

AH_PRIVATE(ah)->ah_getSpurChan = legacyEepromGetSpurChan;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

1874

AH_PRIVATE(ah)->ah_eepromDiag = legacyEepromDiag;

sys/dev/ath/ath_hal/ah_eeprom_v3.c

200

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

211

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no channels\n", __func__);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

275

readEepromRawPowerCalInfo5112(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

278

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

328

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v3.c

383

if (!eepromAllocExpnPower5112(ah, &eePower, &ee->ee_modePowerArray5112[mode])) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

384

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

388

if (!eepromExpandPower5112(ah, &eePower, &ee->ee_modePowerArray5112[mode])) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

389

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

399

freeEepromRawPowerCalInfo5112(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

441

ar2413ReadCalDataset(struct ath_hal *ah, HAL_EEPROM *ee,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

446

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

678

ar2413EepromToRawDataset(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

69

readEepromFreqPierInfo(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

72

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

731

readEepromRawPowerCalInfo2413(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

752

if (!ar2413ReadCalDataset(ah, ee, pCal, off,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

759

if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

770

if (!ar2413ReadCalDataset(ah, ee, pCal, off,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

777

if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

788

if (!ar2413ReadCalDataset(ah, ee, pCal, off,

sys/dev/ath/ath_hal/ah_eeprom_v3.c

795

if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {

sys/dev/ath/ath_hal/ah_eeprom_v3.c

811

readEepromRawPowerCalInfo(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

814

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

822

return readEepromRawPowerCalInfo5112(ah, ee);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

824

return readEepromRawPowerCalInfo2413(ah, ee);

sys/dev/ath/ath_hal/ah_eeprom_v3.c

863

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v3.c

917

readEepromTargetPowerCalInfo(struct ath_hal *ah, HAL_EEPROM *ee)

sys/dev/ath/ath_hal/ah_eeprom_v3.c

920

if (!ath_hal_eepromRead(ah, _off, &eeval)) \

sys/dev/ath/ath_hal/ah_eeprom_v3.c

960

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

119

v4kEepromSet(struct ath_hal *ah, int param, int v)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

121

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

132

v4kEepromDiag(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

135

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

198

v4kEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

200

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

233

v4kEepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v4k *ee)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

258

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

266

v4kEepromDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

268

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

271

AH_PRIVATE(ah)->ah_eeprom = AH_NULL;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

28

v4kEepromGet(struct ath_hal *ah, int param, void *val)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

280

ath_hal_v4kEepromAttach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

283

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

295

if (ah->ah_eepromdata == NULL) {

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

296

if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

297

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

301

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

304

HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

318

if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

319

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

33

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

330

if (ah->ah_eepromdata == NULL && isBigEndian()) {

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

341

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

362

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

375

HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

381

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

386

v4kEepromReadCTLInfo(ah, ee); /* Get CTLs */

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

388

AH_PRIVATE(ah)->ah_eeprom = ee;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

389

AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

390

AH_PRIVATE(ah)->ah_eepromDetach = v4kEepromDetach;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

391

AH_PRIVATE(ah)->ah_eepromGet = v4kEepromGet;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

392

AH_PRIVATE(ah)->ah_eepromSet = v4kEepromSet;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

393

AH_PRIVATE(ah)->ah_getSpurChan = v4kEepromGetSpurChan;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

394

AH_PRIVATE(ah)->ah_eepromDiag = v4kEepromDiag;

sys/dev/ath/ath_hal/ah_eeprom_v4k.c

52

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",

sys/dev/ath/ath_hal/ah_internal.h

1007

struct ath_hal *ah = &ahp->h;

sys/dev/ath/ath_hal/ah_internal.h

1010

ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);

sys/dev/ath/ath_hal/ah_internal.h

1020

ath_hal_getantennaallowed(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

1038

extern void ath_hal_survey_clear(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_internal.h

1043

extern void ath_hal_survey_add_sample(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

121

HAL_BOOL (*probe)(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_internal.h

122

HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);

sys/dev/ath/ath_hal/ah_internal.h

135

struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);

sys/dev/ath/ath_hal/ah_internal.h

177

#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)

sys/dev/ath/ath_hal/ah_internal.h

180

#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)

sys/dev/ath/ath_hal/ah_internal.h

541

extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

543

extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

653

extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)

sys/dev/ath/ath_hal/ah_internal.h

692

u_int ath_hal_getantennareduction(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

709

ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)

sys/dev/ath/ath_hal/ah_internal.h

713

HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);

sys/dev/ath/ath_hal/ah_internal.h

714

cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];

sys/dev/ath/ath_hal/ah_internal.h

730

ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)

sys/dev/ath/ath_hal/ah_internal.h

732

return ath_hal_checkchannel(ah, c)->channel;

sys/dev/ath/ath_hal/ah_internal.h

739

extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

742

extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_internal.h

886

extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ah_internal.h

893

extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);

sys/dev/ath/ath_hal/ah_internal.h

925

#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \

sys/dev/ath/ath_hal/ah_internal.h

928

OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \

sys/dev/ath/ath_hal/ah_internal.h

933

#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \

sys/dev/ath/ath_hal/ah_internal.h

936

OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \

sys/dev/ath/ath_hal/ah_internal.h

941

extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ah_internal.h

945

extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ah_internal.h

95

HAL_OPS_CONFIG *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

130

static void ath_hal_update_dfsdomain(struct ath_hal *ah);

sys/dev/ath/ath_hal/ah_regdomain.c

133

getEepromRD(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_regdomain.c

135

return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG;

sys/dev/ath/ath_hal/ah_regdomain.c

159

isEepromValid(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_regdomain.c

161

uint16_t rd = getEepromRD(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

179

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

230

getDefaultCountry(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_regdomain.c

235

rd = getEepromRD(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

263

getregstate(struct ath_hal *ah, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,

sys/dev/ath/ath_hal/ah_regdomain.c

274

if (!isEepromValid(ah)) {

sys/dev/ath/ath_hal/ah_regdomain.c

279

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

284

cc = getDefaultCountry(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

287

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

292

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM cc %u rd 0x%x\n",

sys/dev/ath/ath_hal/ah_regdomain.c

300

uint16_t rdnum = getEepromRD(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

305

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

312

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

318

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u rd 0x%x\n",

sys/dev/ath/ath_hal/ah_regdomain.c

328

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

335

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

342

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

350

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

420

addchan(struct ath_hal *ah, struct ieee80211_channel chans[],

sys/dev/ath/ath_hal/ah_regdomain.c

429

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

438

ath_hal_getpowerlimits(ah, c);

sys/dev/ath/ath_hal/ah_regdomain.c

445

copychan_prev(struct ath_hal *ah, struct ieee80211_channel chans[],

sys/dev/ath/ath_hal/ah_regdomain.c

456

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

464

ath_hal_getpowerlimits(ah, c);

sys/dev/ath/ath_hal/ah_regdomain.c

470

add_chanlist_band(struct ath_hal *ah, struct ieee80211_channel chans[],

sys/dev/ath/ath_hal/ah_regdomain.c

480

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

484

error = addchan(ah, chans, maxchans, nchans, freq, flags, fband, rd);

sys/dev/ath/ath_hal/ah_regdomain.c

486

error = copychan_prev(ah, chans, maxchans, nchans, freq, flags);

sys/dev/ath/ath_hal/ah_regdomain.c

513

add_chanlist_mode(struct ath_hal *ah, struct ieee80211_channel chans[],

sys/dev/ath/ath_hal/ah_regdomain.c

521

if (!ath_hal_getChannelEdges(ah, cm->flags, &freq_lo, &freq_hi)) {

sys/dev/ath/ath_hal/ah_regdomain.c

523

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

550

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

558

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

602

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

618

error = add_chanlist_band(ah, chans, maxchans, nchans,

sys/dev/ath/ath_hal/ah_regdomain.c

621

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

630

getmodesmask(struct ath_hal *ah, REG_DOMAIN *rd5GHz, u_int modeSelect)

sys/dev/ath/ath_hal/ah_regdomain.c

638

modesMask = ath_hal_getWirelessModes(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

643

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

656

getchannels(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

668

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u regDmn 0x%x mode 0x%x%s\n",

sys/dev/ath/ath_hal/ah_regdomain.c

672

status = getregstate(ah, cc, regDmn, pcountry, &rd2GHz, &rd5GHz);

sys/dev/ath/ath_hal/ah_regdomain.c

676

modesMask = getmodesmask(ah, rd5GHz, modeSelect);

sys/dev/ath/ath_hal/ah_regdomain.c

685

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

696

ath_hal_printf(ah, "%s: Unknown HAL flags 0x%x\n",

sys/dev/ath/ath_hal/ah_regdomain.c

701

add_chanlist_mode(ah, chans, maxchans, nchans, cm,

sys/dev/ath/ath_hal/ah_regdomain.c

719

ath_hal_getchannels(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

724

return getchannels(ah, chans, maxchans, nchans, modeSelect,

sys/dev/ath/ath_hal/ah_regdomain.c

757

assignPrivateChannels(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

773

if (next >= N(AH_PRIVATE(ah)->ah_channels)) {

sys/dev/ath/ath_hal/ah_regdomain.c

774

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_regdomain.c

776

__func__, N(AH_PRIVATE(ah)->ah_channels));

sys/dev/ath/ath_hal/ah_regdomain.c

788

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,

sys/dev/ath/ath_hal/ah_regdomain.c

792

ic = &AH_PRIVATE(ah)->ah_channels[next];

sys/dev/ath/ath_hal/ah_regdomain.c

804

AH_PRIVATE(ah)->ah_nchan = next;

sys/dev/ath/ath_hal/ah_regdomain.c

805

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: %u public, %u private channels\n",

sys/dev/ath/ath_hal/ah_regdomain.c

814

ath_hal_init_channels(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

823

status = getchannels(ah, chans, maxchans, nchans, modeSelect,

sys/dev/ath/ath_hal/ah_regdomain.c

826

assignPrivateChannels(ah, chans, *nchans, AH_PRIVATE(ah)->ah_currentRD)) {

sys/dev/ath/ath_hal/ah_regdomain.c

827

AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz;

sys/dev/ath/ath_hal/ah_regdomain.c

828

AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz;

sys/dev/ath/ath_hal/ah_regdomain.c

830

ah->ah_countryCode = country->countryCode;

sys/dev/ath/ath_hal/ah_regdomain.c

831

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n",

sys/dev/ath/ath_hal/ah_regdomain.c

832

__func__, ah->ah_countryCode);

sys/dev/ath/ath_hal/ah_regdomain.c

835

ath_hal_update_dfsdomain(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

846

ath_hal_set_channels(struct ath_hal *ah,

sys/dev/ath/ath_hal/ah_regdomain.c

866

status = getregstate(ah, CTRY_DEFAULT, SKU_FCC,

sys/dev/ath/ath_hal/ah_regdomain.c

870

status = getregstate(ah, cc, rd,

sys/dev/ath/ath_hal/ah_regdomain.c

872

rd = AH_PRIVATE(ah)->ah_currentRD;

sys/dev/ath/ath_hal/ah_regdomain.c

875

if (status == HAL_OK && assignPrivateChannels(ah, chans, nchans, rd)) {

sys/dev/ath/ath_hal/ah_regdomain.c

876

AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz;

sys/dev/ath/ath_hal/ah_regdomain.c

877

AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz;

sys/dev/ath/ath_hal/ah_regdomain.c

879

ah->ah_countryCode = country->countryCode;

sys/dev/ath/ath_hal/ah_regdomain.c

880

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n",

sys/dev/ath/ath_hal/ah_regdomain.c

881

__func__, ah->ah_countryCode);

sys/dev/ath/ath_hal/ah_regdomain.c

887

(void) ath_hal_update_dfsdomain(ah);

sys/dev/ath/ath_hal/ah_regdomain.c

898

ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)

sys/dev/ath/ath_hal/ah_regdomain.c

900

HAL_CHANNEL_INTERNAL *cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];

sys/dev/ath/ath_hal/ah_regdomain.c

902

if (c->ic_devdata < AH_PRIVATE(ah)->ah_nchan &&

sys/dev/ath/ath_hal/ah_regdomain.c

905

if (c->ic_devdata >= AH_PRIVATE(ah)->ah_nchan) {

sys/dev/ath/ath_hal/ah_regdomain.c

906

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_regdomain.c

908

__func__, c->ic_devdata, AH_PRIVATE(ah)->ah_nchan);

sys/dev/ath/ath_hal/ah_regdomain.c

909

HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);

sys/dev/ath/ath_hal/ah_regdomain.c

911

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ah_regdomain.c

930

ath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c)

sys/dev/ath/ath_hal/ah_regdomain.c

934

if (AH_PRIVATE(ah)->ah_rd2GHz == AH_PRIVATE(ah)->ah_rd5GHz ||

sys/dev/ath/ath_hal/ah_regdomain.c

935

(ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)))

sys/dev/ath/ath_hal/ah_regdomain.c

938

ctl = AH_PRIVATE(ah)->ah_rd2GHz->conformanceTestLimit;

sys/dev/ath/ath_hal/ah_regdomain.c

940

ctl = AH_PRIVATE(ah)->ah_rd5GHz->conformanceTestLimit;

sys/dev/ath/ath_hal/ah_regdomain.c

963

ath_hal_update_dfsdomain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ah_regdomain.c

965

const REG_DOMAIN *rd5GHz = AH_PRIVATE(ah)->ah_rd5GHz;

sys/dev/ath/ath_hal/ah_regdomain.c

974

AH_PRIVATE(ah)->ah_dfsDomain = dfsDomain;

sys/dev/ath/ath_hal/ah_regdomain.c

975

HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s ah_dfsDomain: %d\n",

sys/dev/ath/ath_hal/ah_regdomain.c

976

__func__, AH_PRIVATE(ah)->ah_dfsDomain);

sys/dev/ath/ath_hal/ah_regdomain.c

989

ath_hal_getantennareduction(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210.h

126

#define AH5210(ah) ((struct ath_hal_5210 *)(ah))

sys/dev/ath/ath_hal/ar5210/ar5210.h

130

extern void ar5210Detach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5210/ar5210.h

139

extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5210/ar5210.h

141

extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);

sys/dev/ath/ath_hal/ar5210/ar5210.h

151

extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5210/ar5210.h

153

extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5210/ar5210.h

155

extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5210/ar5210.h

157

extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5210/ar5210.h

158

extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5210/ar5210.h

181

extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);

sys/dev/ath/ath_hal/ar5210/ar5210.h

182

extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);

sys/dev/ath/ath_hal/ar5210/ar5210.h

183

extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210.h

185

extern void ar5210SetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5210/ar5210.h

187

extern void ar5210GetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5210/ar5210.h

189

extern void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5210/ar5210.h

211

extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);

sys/dev/ath/ath_hal/ar5210/ar5210.h

218

extern u_int ar5210GetWirelessModes(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5210/ar5210.h

260

extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5210/ar5210.h

269

extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);

sys/dev/ath/ath_hal/ar5210/ar5210.h

270

extern void ar5210SetNav(struct ath_hal *ah, u_int val);

sys/dev/ath/ath_hal/ar5210/ar5210.h

271

extern u_int ar5210GetNav(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

182

static HAL_BOOL ar5210FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

193

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

211

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

214

ah->ah_sc = sc;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

215

ah->ah_st = st;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

216

ah->ah_sh = sh;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

218

ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

219

AH_PRIVATE(ah)->ah_devid = devid;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

220

AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

222

AH_PRIVATE(ah)->ah_powerLimit = AR5210_MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

223

AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

225

ah->ah_powerMode = HAL_PM_UNDEFINED;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

233

if (!ar5210ChipReset(ah, AH_NULL)) { /* reset chip */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

234

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

241

AH_PRIVATE(ah)->ah_macVersion = 1;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

242

AH_PRIVATE(ah)->ah_macRev = OS_REG_READ(ah, AR_SREV) & 0xff;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

243

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIPID);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

244

AH_PRIVATE(ah)->ah_analog2GhzRev = 0;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

247

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

249

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

250

revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

253

AH_PRIVATE(ah)->ah_analog5GhzRev = ath_hal_reverseBits(revid, 4) + 1;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

259

pcicfg = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

260

OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

261

ecode = ath_hal_v1EepromAttach(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

265

ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

267

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

272

AH_PRIVATE(ah)->ah_currentRD = eeval;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

273

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

275

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

279

OS_REG_WRITE(ah, AR_PCICFG, pcicfg); /* disable EEPROM access */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

281

AH_PRIVATE(ah)->ah_getNfAdjust = ar5210GetNfAdjust;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

286

(void) ar5210FillCapabilityInfo(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

288

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

290

return ah;

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

292

OS_REG_WRITE(ah, AR_PCICFG, pcicfg); /* disable EEPROM access */

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

303

ar5210Detach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

305

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

307

HALASSERT(ah != AH_NULL);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

308

HALASSERT(ah->ah_magic == AR5210_MAGIC);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

310

ath_hal_eepromDetach(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

311

ath_hal_free(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

318

ar5210GetChannelEdges(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

33

static HAL_BOOL ar5210GetChipPowerLimits(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

331

ar5210GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

334

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

343

ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

348

ar5210DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

356

ar5210FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

358

struct ath_hal_private *ahpriv = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

36

static void ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

38

static void ar5210DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

384

if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL)) {

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

102

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

104

OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

116

ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

118

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

120

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

126

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

127

(OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

131

OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

134

OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

137

OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

140

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

141

OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

147

OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

156

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

157

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

171

if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

178

if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE &&

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

181

ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

200

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

33

ar5210GetNextTBTT(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

36

return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

44

ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

47

OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

48

OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

49

OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

50

OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

54

OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

61

ar5210BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

68

if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

70

ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

72

ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

90

ar5210SetBeaconTimers(ah, &bt);

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

94

ar5210ResetStaBeaconTimers(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

98

OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

99

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

104

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

105

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

123

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

124

OS_REG_WRITE(ah, AR_IMR, mask);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

129

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

130

OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

31

ar5210IsInterruptPending(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

33

return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

42

ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

46

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

49

isr = OS_REG_READ(ah, AR_ISR);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

75

AH_PRIVATE(ah)->ah_fatalState[0] = isr;

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

83

ar5210GetInterrupts(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

85

return AH5210(ah)->ah_maskReg;

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

89

ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

91

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c

95

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

109

ar5210SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

120

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

149

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

150

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

151

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

152

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

153

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

154

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

155

return ar5210SetKeyCacheEntryMac(ah, entry, mac);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

34

ar5210GetKeyCacheSize(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

43

ar5210IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

46

uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

57

ar5210ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

60

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

61

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

62

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

63

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

64

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

65

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

66

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

67

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

77

ar5210SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

97

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);

sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c

98

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry),

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

101

if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

110

if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

129

ar5210GetWirelessModes(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

140

ar5210EnableRfKill(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

142

uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

154

ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

161

ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

165

OS_REG_WRITE(ah, AR_GPIOCR,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

166

(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

176

ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

180

OS_REG_WRITE(ah, AR_GPIOCR,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

181

(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

191

ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

197

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

201

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

209

ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

212

uint32_t val = OS_REG_READ(ah, AR_GPIODI);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

224

ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

226

uint32_t val = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

237

OS_REG_WRITE(ah, AR_GPIOCR, val);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

240

ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

247

ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

251

val = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

266

OS_REG_WRITE(ah, AR_PCICFG, val);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

273

ar5210GetDefAntenna(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

275

uint32_t val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

280

ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

282

uint32_t val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

288

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

293

ar5210GetAntennaSwitch(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

299

ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

312

ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

314

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

319

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

320

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

323

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

325

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

332

ar5210GetTsf64(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

337

low1 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

338

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

339

low2 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

34

ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

36

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

360

ar5210GetTsf32(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

362

return OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

369

ar5210ResetTsf(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

371

uint32_t val = OS_REG_READ(ah, AR_BEACON);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

373

OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

381

ar5210GetRandomSeed(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

385

nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

388

return (OS_REG_READ(ah, AR_TSF_U32) ^

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

389

OS_REG_READ(ah, AR_TSF_L32) ^ nf);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

396

ar5210DetectCardPresent(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

403

return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

410

ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

412

stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

413

stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

414

stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

415

stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

416

stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

42

ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

420

ar5210SetSifsTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

422

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

424

if (us > ath_hal_mac_usec(ah, 0x7ff)) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

425

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

431

OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

432

ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

439

ar5210GetSifsTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

44

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

441

u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

442

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

446

ar5210SetSlotTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

448

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

450

if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

451

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

457

OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

464

ar5210GetSlotTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

466

u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

467

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

471

ar5210SetAckTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

473

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

475

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

476

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

482

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

483

AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

490

ar5210GetAckTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

492

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

493

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

497

ar5210GetAckCTSRate(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

499

return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

503

ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

505

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

508

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

51

ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

511

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

518

ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

520

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

522

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

523

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

529

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

530

AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

537

ar5210GetCTSTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

539

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

540

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

544

ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

551

ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

556

ar5210SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

566

ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

572

ar5210RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

578

ar5210AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

583

ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

588

ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

59

ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

600

return ath_hal_getcapability(ah, type, capability, result);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

605

ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

617

AH_PRIVATE(ah)->ah_diagreg = setting;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

619

AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

621

ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

626

return ath_hal_setcapability(ah, type, capability,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

632

ar5210GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

647

pcicfg = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

648

OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

649

ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

650

OS_REG_WRITE(ah, AR_PCICFG, pcicfg);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

656

return ath_hal_getdiagstate(ah, request,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

665

ar5210Get11nExtBusy(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

675

ar5210GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

68

ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

682

ar5210SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

688

ar5210EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

693

ar5210GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

70

(void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

704

ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

709

OS_REG_WRITE(ah, AR_DIAG_SW, val);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

71

if (!ath_hal_wait(ah, AR_EP_STA,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

716

ar5210GetNav(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

720

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

728

ar5210SetNav(struct ath_hal *ah, u_int val)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

73

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

731

OS_REG_WRITE(ah, AR_NAV, val);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

77

*data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

86

ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

96

ar5210SetRegulatoryDomain(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_phy.c

68

ar5210GetRateTable(struct ath_hal *ah, u_int mode)

sys/dev/ath/ath_hal/ar5210/ar5210_phy.c

79

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_phy.c

83

ath_hal_setupratetable(ah, rt);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

106

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

107

modes[ah->ah_powerMode], modes[mode],

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

112

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

113

status = ar5210SetPowerModeAwake(ah, setChip);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

116

ar5210SetPowerModeSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

118

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

121

ar5210SetPowerModeAuto(ah, setChip);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

123

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

126

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

134

ar5210GetPowerMode(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

137

return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

32

ar5210SetPowerModeAuto(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

34

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

36

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_ALLOW);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

49

ar5210SetPowerModeAwake(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

56

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

60

val = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

64

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

69

ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

76

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

86

ar5210SetPowerModeSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

88

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

90

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

94

ar5210SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

107

ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

109

OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

110

OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

117

ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

124

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

125

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

127

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

128

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

137

ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

144

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

145

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

147

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

148

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

157

ar5210GetRxFilter(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

160

return OS_REG_READ(ah, AR_RX_FILTER);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

167

ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

173

OS_REG_WRITE(ah, AR_RX_FILTER, bits);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

182

ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

192

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

212

ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

227

if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

236

now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff;

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

33

ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

37

return OS_REG_READ(ah, AR_RXDP);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

44

ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

48

OS_REG_WRITE(ah, AR_RXDP, rxdp);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

55

ar5210EnableReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

57

OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

64

ar5210StopDmaReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

68

OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

70

if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

75

ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n");

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

76

ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

77

ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

86

ar5210StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

88

ar5210UpdateDiagReg(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

89

OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

96

ar5210StopPcuReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

98

ar5210UpdateDiagReg(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_recv.c

99

OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

1002

ar5210GetRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

111

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

117

ledstate = OS_REG_READ(ah, AR_PCICFG) &

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

120

if (!ar5210ChipReset(ah, chan)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

121

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

126

OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

127

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

128

ar5210SetOperatingMode(ah, opmode);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

132

OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

133

OS_REG_WRITE(ah, AR_PCICFG,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

137

OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

138

OS_REG_WRITE(ah, AR_PCICFG,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

142

OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

143

OS_REG_WRITE(ah, AR_PCICFG,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

147

OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

148

OS_REG_WRITE(ah, AR_PCICFG,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

154

OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

157

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

158

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

161

ar5210WriteAssocid(ah, ahp->ah_bssid, ahp->ah_associd);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

163

OS_REG_WRITE(ah, AR_TXDP0, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

164

OS_REG_WRITE(ah, AR_TXDP1, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

165

OS_REG_WRITE(ah, AR_RXDP, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

170

(void) OS_REG_READ(ah, AR_ISR); /* cleared on read */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

171

OS_REG_WRITE(ah, AR_IMR, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

172

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

175

(void) OS_REG_READ(ah, AR_BSR); /* cleared on read */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

176

OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

177

OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

179

OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

180

OS_REG_WRITE(ah, AR_RXNOFRM, 8); /* RX no frame timeout */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

181

OS_REG_WRITE(ah, AR_RPGTO, 0); /* RX frame gap timeout */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

182

OS_REG_WRITE(ah, AR_TXNOFRM, 0); /* TX no frame timeout */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

184

OS_REG_WRITE(ah, AR_SFR, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

185

OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

186

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

187

OS_REG_WRITE(ah, AR_CFP_DUR, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

189

ar5210SetRxFilter(ah, 0); /* nothing for now */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

190

OS_REG_WRITE(ah, AR_MCAST_FIL0, 0); /* multicast filter */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

191

OS_REG_WRITE(ah, AR_MCAST_FIL1, 0); /* XXX was 2 */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

193

OS_REG_WRITE(ah, AR_TX_MASK0, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

194

OS_REG_WRITE(ah, AR_TX_MASK1, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

195

OS_REG_WRITE(ah, AR_CLR_TMASK, 1);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

196

OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

198

ar5210UpdateDiagReg(ah, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

200

OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

201

OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

202

OS_REG_WRITE(ah, AR_TSF_L32, 0); /* local clock */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

203

OS_REG_WRITE(ah, AR_TIMER1, ~0); /* next DMA beacon alert */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

204

OS_REG_WRITE(ah, AR_TIMER2, ~0); /* next SW beacon alert */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

205

OS_REG_WRITE(ah, AR_TIMER3, 1); /* next ATIM window */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

212

OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

216

if (!ar5210SetTransmitPower(ah, chan)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

217

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

222

OS_REG_WRITE(ah, AR_PHY(10),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

223

(OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

225

OS_REG_WRITE(ah, AR_PHY(13),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

228

OS_REG_WRITE(ah, AR_PHY(17),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

229

(OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

231

OS_REG_WRITE(ah, AR_PHY(18),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

232

(OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

234

OS_REG_WRITE(ah, AR_PHY(25),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

235

(OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

237

OS_REG_WRITE(ah, AR_PHY(68),

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

238

(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

241

if (!ar5210SetChannel(ah, chan)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

242

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

250

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

255

OS_REG_WRITE(ah, AR_PHY_AGCCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

256

OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

257

(void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

260

if (!ar5210CalNoiseFloor(ah, ichan)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

262

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

268

ar5210ResetTxQueue(ah, q);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

270

if (AH_PRIVATE(ah)->ah_rfkillEnabled)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

271

ar5210EnableRfKill(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

279

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

280

(OS_REG_READ(ah, AR_BEACON) &

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

285

ar5210SetSifsTime(ah, ahp->ah_sifstime);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

287

ar5210SetSlotTime(ah, ahp->ah_slottime);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

289

ar5210SetAckTimeout(ah, ahp->ah_acktimeout);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

291

ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

292

if (AH_PRIVATE(ah)->ah_diagreg != 0)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

293

ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

295

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

297

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

309

ar5210SetOperatingMode(struct ath_hal *ah, int opmode)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

311

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

314

val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

317

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

324

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

331

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

337

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

345

ar5210SetPCUConfig(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

347

ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

357

ar5210PhyDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

359

return ar5210SetResetReg(ah, AR_RC_RPHY, 10);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

366

ar5210Disable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

369

if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

376

if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

379

(void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

390

ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

394

HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

398

if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

402

OS_REG_WRITE(ah, AR_PHY_FRCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

409

if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

412

if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

424

if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

428

return ar5210SetResetReg(ah, 0, 10);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

450

ar5210PerCalibrationN(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

458

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

462

ar5210UpdateDiagReg(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

463

OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

466

regBeacon = OS_REG_READ(ah, AR_BEACON);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

467

OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

473

OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

478

if (!ar5210SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

485

OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

498

reg9858 = OS_REG_READ(ah, 0x9858);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

499

reg985c = OS_REG_READ(ah, 0x985c);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

500

reg9868 = OS_REG_READ(ah, 0x9868);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

502

OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) |

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

504

OS_REG_WRITE(ah, 0x985c,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

508

OS_REG_WRITE(ah, 0x9868,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

523

OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

525

OS_REG_WRITE(ah, 0x98D4, 0x21);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

526

OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

532

OS_REG_WRITE(ah, AR_PHY_AGCCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

533

OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

534

if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

535

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

540

OS_REG_WRITE(ah, 0x9858, reg9858);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

541

OS_REG_WRITE(ah, 0x985c, reg985c);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

542

OS_REG_WRITE(ah, 0x9868, reg9868);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

545

if (!ar5210CalNoiseFloor(ah, ichan)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

551

HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

554

if (!ar5210CalNoiseFloor(ah, ichan))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

559

ar5210UpdateDiagReg(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

560

OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

563

OS_REG_WRITE(ah, AR_BEACON, regBeacon);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

571

ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

574

return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

578

ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

587

ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

592

OS_REG_WRITE(ah, AR_RC, resetMask);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

598

rt = ath_hal_wait(ah, AR_RC, mask, resetMask);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

605

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

607

OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

616

getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

650

ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

659

getGainF(struct ath_hal *ah, const struct tpcMap *pRD,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

689

ath_hal_printf(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

70

ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

720

ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

722

AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

731

setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

734

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

735

const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

746

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

756

if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd])

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

760

ath_hal_printf(ah,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

763

AH_PRIVATE(ah)->ah_currentRD);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

77

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

78

const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

785

gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

786

gainF36 = getGainF(ah, pRD, cp[9], &dBm36);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

787

gainF48 = getGainF(ah, pRD, cp[8], &dBm48);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

788

gainF54 = getGainF(ah, pRD, cp[7], &dBm54);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

791

if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

796

tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

801

cp[14] = getPcdac(ah, pRD, dBmRD);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

802

gainFRD = getGainF(ah, pRD, cp[14], &dontcare);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

804

cp[9] = getPcdac(ah, pRD, dBm36);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

805

gainF36 = getGainF(ah, pRD, cp[9], &dontcare);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

807

cp[8] = getPcdac(ah, pRD, dBm48);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

808

gainF48 = getGainF(ah, pRD, cp[8], &dontcare);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

810

cp[7] = getPcdac(ah, pRD, dBm54);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

811

gainF54 = getGainF(ah, pRD, cp[7], &dontcare);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

814

AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

833

ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

84

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

852

if (!setupPowerSettings(ah, chan, cp)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

854

ath_hal_printf(ah, "%s: unable to setup power settings\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

861

ath_hal_printf(ah, "%s: OB out of range (%u)\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

868

ath_hal_printf(ah, "%s: DB out of range (%u)\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

906

OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

908

OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

91

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

921

ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

923

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

929

OS_REG_WRITE(ah, AR_PHY(0x27), data);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

930

OS_REG_WRITE(ah, AR_PHY(0x30), 0);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

931

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

936

ar5210GetNoiseFloor(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

940

nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

954

ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

959

OS_REG_WRITE(ah, AR_PHY_AGCCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

960

OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

963

if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

965

ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

966

OS_REG_READ(ah, AR_PHY_AGCCTL));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

967

ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

968

OS_REG_READ(ah, AR_RC));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

969

ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

97

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

970

OS_REG_READ(ah, AR_PHY_ACTIVE));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

979

nf = ar5210GetNoiseFloor(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

983

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

99

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

996

ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

114

(void) ar5210SetTxQueueProps(ah, q, qInfo);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

123

ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

125

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

129

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

135

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

140

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

154

ar5210ResetTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

156

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

157

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

162

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

168

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

181

OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

182

OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

183

OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

184

OS_REG_WRITE(ah, AR_IFS0,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

188

OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

189

OS_REG_WRITE(ah, AR_PHY(17),

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

190

(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x38);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

191

OS_REG_WRITE(ah, AR_PHY_FRCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

198

OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

199

OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

200

OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

201

OS_REG_WRITE(ah, AR_IFS0,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

205

OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

206

OS_REG_WRITE(ah, AR_PHY(17),

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

207

(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x1C);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

208

OS_REG_WRITE(ah, AR_PHY_FRCTL,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

220

OS_REG_WRITE(ah, AR_RETRY_LMT,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

257

ar5210GetTxDP(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

259

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

267

return OS_REG_READ(ah, AR_TXDP0);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

269

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

282

ar5210SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

284

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

289

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u 0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

300

if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

301

ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

302

__func__, OS_REG_READ(ah, AR_CR));

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

304

OS_REG_WRITE(ah, AR_TXDP0, txdp);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

308

OS_REG_WRITE(ah, AR_TXDP1, txdp);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

311

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

329

ar5210UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

332

HAL_INT ints = ar5210GetInterrupts(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

338

(void) ar5210SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

339

curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

352

ar5210SetInterrupts(ah, ints);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

357

OS_REG_WRITE(ah, AR_TRIG_LEV, curTrigLevel);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

359

ar5210SetInterrupts(ah, ints);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

36

ar5210SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

367

ar5210StartTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

369

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

374

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

378

OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

38

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

381

OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

382

OS_REG_WRITE(ah, AR_BCR,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

387

OS_REG_WRITE(ah, AR_BCR, AR_BCR_TQ1V | AR_BCR_BDMAE);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

390

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

400

ar5210NumTxPending(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

402

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

408

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

41

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

412

v = OS_REG_READ(ah, AR_CFG);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

415

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

428

ar5210StopTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

430

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

435

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

440

OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

442

if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

446

OS_REG_WRITE(ah, AR_CR, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

45

return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

450

return ath_hal_wait(ah, AR_BSR, AR_BSR_TXQ1F, 0);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

452

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

477

ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

52

ar5210GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

528

ar5210SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

533

(void) ah; (void) ds;

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

54

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

541

ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

549

ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

57

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

590

ar5210ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

61

return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

625

ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

634

ar5210GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

643

ar5210SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

654

ar5210GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

665

ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

68

ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

71

struct ath_hal_5210 *ahp = AH5210(ah);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

86

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

91

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c

95

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",

sys/dev/ath/ath_hal/ar5211/ar5211.h

142

#define AH5211(ah) ((struct ath_hal_5211 *)(ah))

sys/dev/ath/ath_hal/ar5211/ar5211.h

157

extern HAL_BOOL ar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5211/ar5211.h

159

extern HAL_BOOL ar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);

sys/dev/ath/ath_hal/ar5211/ar5211.h

172

extern HAL_BOOL ar5211SetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5211/ar5211.h

174

extern HAL_BOOL ar5211GetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5211/ar5211.h

176

extern int ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5211/ar5211.h

178

extern HAL_BOOL ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5211/ar5211.h

179

extern HAL_BOOL ar5211ResetTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5211/ar5211.h

204

extern void ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *);

sys/dev/ath/ath_hal/ar5211/ar5211.h

205

extern void ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);

sys/dev/ath/ath_hal/ar5211/ar5211.h

206

extern HAL_BOOL ar5211GetTxCompletionRates(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211.h

208

extern void ar5211SetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5211/ar5211.h

210

extern void ar5211GetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5211/ar5211.h

212

extern void ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5211/ar5211.h

234

extern HAL_BOOL ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *);

sys/dev/ath/ath_hal/ar5211/ar5211.h

278

extern void ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna);

sys/dev/ath/ath_hal/ar5211/ar5211.h

285

extern HAL_BOOL ar5211GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5211/ar5211.h

291

extern void ar5211SetChainMasks(struct ath_hal *ah, uint32_t, uint32_t);

sys/dev/ath/ath_hal/ar5211/ar5211.h

292

extern void ar5211SetNav(struct ath_hal *ah, u_int);

sys/dev/ath/ath_hal/ar5211/ar5211.h

293

extern u_int ar5211GetNav(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

183

static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

190

ar5211GetRadioRev(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

195

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

197

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

198

val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

213

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

229

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

232

ah->ah_sc = sc;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

233

ah->ah_st = st;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

234

ah->ah_sh = sh;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

236

ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

237

AH_PRIVATE(ah)->ah_devid = devid;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

238

AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

240

AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

241

AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

251

if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

252

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

256

if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

258

OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

259

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

264

val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

265

AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

266

AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

268

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 ||

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

269

AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

270

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

272

__func__, AH_PRIVATE(ah)->ah_macVersion);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

277

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

279

if (!ar5211ChipTest(ah)) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

280

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

287

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

288

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

290

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

295

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

296

if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

297

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

299

"driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

304

val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >>

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

307

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size "

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

31

static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

312

ecode = ath_hal_legacyEepromAttach(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

318

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU &&

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

319

ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

321

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

323

AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

326

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

328

if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

329

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

33

static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

332

AH_PRIVATE(ah)->ah_analog2GhzRev);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

337

ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

340

ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

342

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

347

AH_PRIVATE(ah)->ah_currentRD = eeval;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

348

AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

353

(void) ar5211FillCapabilityInfo(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

356

ar5211InitializeGainValues(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

358

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

36

static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

360

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

365

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

367

return ah;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

378

ar5211Detach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

38

static void ar5211DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

380

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

382

HALASSERT(ah != AH_NULL);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

383

HALASSERT(ah->ah_magic == AR5211_MAGIC);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

385

ath_hal_eepromDetach(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

386

ath_hal_free(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

390

ar5211ChipTest(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

403

regHold[i] = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

406

OS_REG_WRITE(ah, addr, wrData);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

407

rdData = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

409

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

417

OS_REG_WRITE(ah, addr, wrData);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

418

rdData = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

420

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

426

OS_REG_WRITE(ah, regAddr[i], regHold[i]);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

436

ar5211GetChannelEdges(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

445

ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

454

ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

457

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

466

ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

471

ar5211DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

479

ar5211FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

481

struct ath_hal_private *ahpriv = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

486

if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

488

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

491

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

519

if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

520

ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

103

ar5211ResetStaBeaconTimers(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

107

OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

108

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

111

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

113

OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

122

ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

124

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

126

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

132

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

133

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

136

OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

139

OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

142

OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

145

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

146

OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

152

OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

161

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

162

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

175

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

181

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

36

ar5211GetNextTBTT(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

39

return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

47

ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

50

OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

51

OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

52

OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

53

OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

57

OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

64

ar5211BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

76

switch (AH_PRIVATE(ah)->ah_opmode) {

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

85

ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

87

ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

99

ar5211SetBeaconTimers(ah, &bt);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

106

ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints)

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

108

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

112

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

121

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

122

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

124

(void) OS_REG_READ(ah, AR_IER); /* flush write to HW */

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

149

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

150

OS_REG_WRITE(ah, AR_IMR, mask);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

155

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

156

OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

34

ar5211IsInterruptPending(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

36

return OS_REG_READ(ah, AR_INTPEND) != 0;

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

49

ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

53

isr = OS_REG_READ(ah, AR_ISR_RAC);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

72

if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

73

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

82

AH_PRIVATE(ah)->ah_fatalState[0] = isr;

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

83

AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

84

AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

85

AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

86

AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

87

AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

88

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

90

__func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

96

ar5211GetInterrupts(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c

98

return AH5211(ah)->ah_maskReg;

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

106

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

107

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

115

ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

125

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

135

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

151

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

170

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

171

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

172

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

173

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

174

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

175

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

176

return ar5211SetKeyCacheEntryMac(ah, entry, mac);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

38

ar5211GetKeyCacheSize(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

47

ar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

50

uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

61

ar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

64

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

65

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

66

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

67

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

68

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

69

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

70

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

71

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

81

ar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c

86

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

104

if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

113

if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

118

if (ar5211EepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

119

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

122

AH_PRIVATE(ah)->ah_currentRD = regDomain;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

141

ar5211GetWirelessModes(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

145

if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

147

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

150

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

157

ar5211GetTurboDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

159

return (AH5211(ah)->ah_turboDisable != 0);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

168

ar5211EnableRfKill(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

170

uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

178

ar5211GpioCfgInput(ah, select);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

179

OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

188

ar5211GpioSetIntr(ah, select, (ar5211GpioGet(ah, select) != polarity));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

195

ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

201

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

205

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

213

ar5211GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

219

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

223

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

231

ar5211GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

237

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

241

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

249

ar5211GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

252

uint32_t val = OS_REG_READ(ah, AR_GPIODI);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

264

ar5211GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

266

uint32_t val = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

277

OS_REG_WRITE(ah, AR_GPIOCR, val);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

280

ar5211SetInterrupts(ah, AH5211(ah)->ah_maskReg | HAL_INT_GPIO);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

287

ar5211SetLedState(struct ath_hal *ah, HAL_LED_STATE state)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

299

OS_REG_WRITE(ah, AR_PCICFG,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

300

(OS_REG_READ(ah, AR_PCICFG) &~

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

313

ar5211WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

315

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

319

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

320

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

328

ar5211GetTsf64(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

333

low1 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

334

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

335

low2 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

34

ar5211GetMacAddress(struct ath_hal *ah, uint8_t *mac)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

356

ar5211GetTsf32(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

358

return OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

36

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

365

ar5211ResetTsf(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

367

uint32_t val = OS_REG_READ(ah, AR_BEACON);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

369

OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

377

ar5211GetRandomSeed(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

381

nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

384

return (OS_REG_READ(ah, AR_TSF_U32) ^

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

385

OS_REG_READ(ah, AR_TSF_L32) ^ nf);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

392

ar5211DetectCardPresent(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

402

v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

405

return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

406

AH_PRIVATE(ah)->ah_macRev == macRev);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

413

ar5211UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

415

stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

416

stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

417

stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

418

stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

419

stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

42

ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

423

ar5211SetSifsTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

425

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

427

if (us > ath_hal_mac_usec(ah, 0xffff)) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

428

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

434

OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

44

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

441

ar5211GetSifsTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

443

u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

444

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

448

ar5211SetSlotTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

450

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

452

if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

453

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

459

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

466

ar5211GetSlotTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

468

u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

469

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

473

ar5211SetAckTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

475

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

477

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

478

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

484

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

485

AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

492

ar5211GetAckTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

494

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

495

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

499

ar5211GetAckCTSRate(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

501

return ((AH5211(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

505

ar5211SetAckCTSRate(struct ath_hal *ah, u_int high)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

507

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

51

ar5211GetBssIdMask(struct ath_hal *ah, uint8_t *mask)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

510

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

513

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

520

ar5211SetCTSTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

522

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

524

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

525

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

531

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

532

AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

539

ar5211GetCTSTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

541

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

542

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

546

ar5211SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

553

ar5211SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

558

ar5211SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

568

ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

574

ar5211AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

579

ar5211RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

585

ar5211MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

59

ar5211SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

593

ar5211GetCurRssi(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

595

return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

599

ar5211GetDefAntenna(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

601

return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

605

ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

607

OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

611

ar5211GetAntennaSwitch(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

613

return AH5211(ah)->ah_diversityControl;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

617

ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

619

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

622

AH5211(ah)->ah_diversityControl = settings;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

625

return ar5211SetAntennaSwitchInternal(ah, settings, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

629

ar5211GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

644

return ath_hal_getcapability(ah, type, capability, result);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

649

ar5211SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

660

AH_PRIVATE(ah)->ah_diagreg = setting;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

662

AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

664

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

667

return ath_hal_setcapability(ah, type, capability,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

673

ar5211GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

677

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

68

ar5211EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

680

if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

684

return ath_hal_eepromDiag(ah, request,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

70

OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

704

ar5211Get11nExtBusy(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

71

OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

713

ar5211GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

720

ar5211SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

726

ar5211EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

73

if (!ath_hal_wait(ah, AR_EEPROM_STS,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

731

ar5211GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

739

ar5211GetNav(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

743

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

751

ar5211SetNav(struct ath_hal *ah, u_int val)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

754

OS_REG_WRITE(ah, AR_NAV, val);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

76

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

80

*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

89

ar5211EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

99

ar5211SetRegulatoryDomain(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_phy.c

101

ath_hal_setupratetable(ah, rt);

sys/dev/ath/ath_hal/ar5211/ar5211_phy.c

83

ar5211GetRateTable(struct ath_hal *ah, u_int mode)

sys/dev/ath/ath_hal/ar5211/ar5211_phy.c

97

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

108

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

109

modes[ah->ah_powerMode], modes[mode],

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

114

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

115

status = ar5211SetPowerModeAwake(ah, setChip);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

118

ar5211SetPowerModeSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

120

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

123

ar5211SetPowerModeNetworkSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

125

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

128

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

136

ar5211GetPowerMode(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

139

return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

38

ar5211SetPowerModeAwake(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

45

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

49

val = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

53

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

58

ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

65

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

75

ar5211SetPowerModeSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

77

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

79

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

88

ar5211SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

90

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

92

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

96

ar5211SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

100

OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

108

ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

110

OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

111

OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

118

ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

125

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

126

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

128

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

129

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

138

ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

145

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

146

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

148

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

149

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

158

ar5211GetRxFilter(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

160

return OS_REG_READ(ah, AR_RX_FILTER);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

167

ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

169

OS_REG_WRITE(ah, AR_RX_FILTER, bits);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

178

ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

186

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

206

ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

220

if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

33

ar5211GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

37

return OS_REG_READ(ah, AR_RXDP);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

44

ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

48

OS_REG_WRITE(ah, AR_RXDP, rxdp);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

49

HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

56

ar5211EnableReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

58

OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

65

ar5211StopDmaReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

67

OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

68

if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

70

ath_hal_printf(ah, "%s failed to stop in 10ms\n"

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

73

, OS_REG_READ(ah, AR_CR)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

74

, OS_REG_READ(ah, AR_DIAG_SW)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

87

ar5211StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

89

OS_REG_WRITE(ah, AR_DIAG_SW,

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

90

OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

97

ar5211StopPcuReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_recv.c

99

OS_REG_WRITE(ah, AR_DIAG_SW,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1001

ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1033

ar5211SetRf6and7(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1036

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1037

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1038

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

107

static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1099

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1129

OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1139

ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1144

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1145

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1154

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1184

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1190

OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1191

OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1203

ar5211SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1205

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1206

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1212

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1222

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1228

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1229

OS_REG_WRITE(ah, AR_PHY(68),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1230

(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1232

OS_REG_WRITE(ah, AR_PHY(68),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1233

(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1236

ar5211SetAntennaSwitchInternal(ah,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1240

OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1243

OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1244

(OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1246

OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1247

(OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1249

OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1250

(OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1253

OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1258

OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1259

(OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1261

OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1262

(OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1273

if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1274

if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1278

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1284

OS_REG_WRITE(ah, 0x9924,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1285

(OS_REG_READ(ah, 0x9924) & 0xFFFFFF01)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1300

ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1303

AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1304

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1313

ar5211SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1315

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1316

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1347

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1352

ar5211SetPowerTable(ah, &eepromPcdacs, freq);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1356

cfgCtl = ath_hal_getctl(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1362

ar5211SetRateTable(ah, rep, pi, nchan, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1374

ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1482

OS_REG_WRITE(ah, addr, temp32);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1493

ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1497

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1498

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1499

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1526

twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

155

ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1624

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1626

&& AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

163

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1639

(tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1651

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1654

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1657

HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1658

tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1661

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1662

HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1664

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1672

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1677

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1684

ar5211SetTxPowerLimit(ah, pRatesPower[0]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1686

AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0];

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

176

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

181

OS_MARK(ah, AH_MARK_RESET, bChannelChange);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

185

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1909

ar5211InitializeGainValues(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1911

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1923

ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1925

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

195

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1957

ar5211RequestRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1959

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1962

OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1974

ar5211GetRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1976

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1985

rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1993

if (!ar5211InvalidGainReadback(ah, gv) &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1994

ar5211IsGainAdjustNeeded(ah, gv) &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1995

ar5211AdjustGain(ah, gv) > 0) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

200

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2000

ar5211SetRfgain(ah, gv);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2013

ar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2022

ar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2031

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2035

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2044

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2050

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2054

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2064

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2075

ar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2077

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2088

ar5211SetOperatingMode(struct ath_hal *ah, int opmode)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2090

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2093

val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2096

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2102

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2109

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2117

ar5211SetPCUConfig(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2119

ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

219

saveTsfLow = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

220

saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

223

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

224

saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

227

saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

236

saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

241

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

244

ledstate = OS_REG_READ(ah, AR_PCICFG) &

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

247

softLedCfg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

248

softLedState = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

250

if (!ar5211ChipReset(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

251

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

263

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

275

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

283

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

284

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

286

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

290

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

292

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

293

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

314

OS_REG_WRITE(ah, ar5211Mode2_4[i][0],

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

319

ar5211SetRf6and7(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

323

OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

327

OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

334

OS_REG_WRITE(ah, reg, ar5211Common[i][1]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

338

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

345

data = OS_REG_READ(ah, AR_USEC);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

348

OS_REG_WRITE(ah, AR_USEC,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

352

OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

355

OS_REG_WRITE(ah, 0x00009878, 0x00000008);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

358

OS_REG_WRITE(ah, AR_DIAG_SW,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

359

OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

365

OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

366

OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

368

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

369

OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

372

OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

376

OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

377

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

380

ar5211SetOperatingMode(ah, opmode);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

383

OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

384

OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

385

OS_REG_WRITE(ah, AR_GPIODO, softLedState);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

388

OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

390

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

391

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

394

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

396

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

403

if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

404

AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

405

OS_REG_WRITE(ah, AR_CFG,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

406

OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

410

if (!ar5211SetTransmitPower(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

411

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

421

(AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

423

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

425

MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

429

ar5211SetBoardValues(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

431

if (!ar5211SetChannel(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

432

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

438

if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

440

OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

441

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

448

data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

463

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

464

OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

465

(void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

468

if (!ar5211CalNoiseFloor(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

471

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

478

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

485

OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

488

ar5211ResetTxQueue(ah, q);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

491

OS_REG_WRITE(ah, AR_IMR_S0,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

494

OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

495

OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

501

OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

504

OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

508

OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

513

OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

517

if (AH_PRIVATE(ah)->ah_rfkillEnabled)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

518

ar5211EnableRfKill(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

526

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

527

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

531

ar5211SetSifsTime(ah, ahp->ah_sifstime);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

533

ar5211SetSlotTime(ah, ahp->ah_slottime);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

535

ar5211SetAckTimeout(ah, ahp->ah_acktimeout);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

537

ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

538

if (AH_PRIVATE(ah)->ah_diagreg != 0)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

539

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

541

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

543

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

561

ar5211PhyDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

563

return ar5211SetResetReg(ah, AR_RC_BB);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

570

ar5211Disable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

572

if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

578

if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

594

ar5211ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

596

if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

602

OS_REG_WRITE(ah, AR_PHY_TURBO, IEEE80211_IS_CHAN_TURBO(chan) ?

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

605

OS_REG_WRITE(ah, AR5211_PHY_MODE,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

607

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

610

} else if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

611

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

613

OS_REG_WRITE(ah, AR5211_PHY_MODE,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

624

if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

629

if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

633

return ar5211SetResetReg(ah, 0);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

641

ar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

644

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

652

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

654

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

661

!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

666

powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

667

powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

668

iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

687

HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

689

HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

691

HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

693

HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

695

HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

699

data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

703

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

710

if (!ar5211IsNfGood(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

715

if (!ar5211CalNoiseFloor(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

722

if (!ar5211CalNoiseFloor(ah, chan)) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

728

ar5211RequestRfgain(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

734

ar5211PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

737

return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

741

ar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

751

ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

756

(void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

757

OS_REG_WRITE(ah, AR_RC, resetMask);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

764

rt = ath_hal_wait(ah, AR_RC, mask, resetMask);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

771

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

773

OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

785

ar5211SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

814

OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

816

OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

818

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

823

ar5211GetNoiseFloor(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

827

nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

840

ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

847

OS_REG_WRITE(ah, AR_PHY(25),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

848

(OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

851

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

852

OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

871

if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

876

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

878

runTime, AH_PRIVATE(ah)->ah_curchan->ic_freq);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

879

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

881

OS_REG_READ(ah, AR_PHY_AGC_CONTROL));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

882

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

884

OS_REG_READ(ah, AR_PHY_ACTIVE));

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

888

return ar5211GetNoiseFloor(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

892

getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

895

HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

908

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

921

ar5211IsNfGood(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

923

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

926

if (!getNoiseFloorThresh(ah, chan, &nfThresh))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

928

if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

929

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

932

nf = ar5211GetNoiseFloor(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

934

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

958

ar5211CalNoiseFloor(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

962

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

965

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

969

if (!getNoiseFloorThresh(ah, chan, &nfThresh))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

976

nf = ar5211RunNoiseFloor(ah, runtime[i], 0);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

978

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

989

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

990

OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

101

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

105

return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

112

ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

115

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

132

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

137

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

141

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

161

(void) ar5211SetTxQueueProps(ah, q, qInfo);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

169

setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

171

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

173

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

182

OS_REG_WRITE(ah, AR_IMR_S0,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

186

OS_REG_WRITE(ah, AR_IMR_S1,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

190

OS_REG_RMW_FIELD(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

198

ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

200

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

204

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

210

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

215

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

223

setTxQInterrupts(ah, qi);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

232

ar5211ResetTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

234

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

235

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

240

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

246

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

267

OS_REG_WRITE(ah, AR_DLCL_IFS(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

273

OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

281

OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

283

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

285

OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

289

OS_REG_WRITE(ah, AR_QCBRCFG(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

292

OS_REG_WRITE(ah, AR_QMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

293

OS_REG_READ(ah, AR_QMISC(q)) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

299

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

304

OS_REG_WRITE(ah, AR_DCHNTIME(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

308

OS_REG_WRITE(ah, AR_QMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

309

OS_REG_READ(ah, AR_QMISC(q)) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

315

OS_REG_WRITE(ah, AR_DMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

316

OS_REG_READ(ah, AR_DMISC(q)) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

320

OS_REG_WRITE(ah, AR_DMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

321

OS_REG_READ(ah, AR_DMISC(q)) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

327

OS_REG_WRITE(ah, AR_QMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

328

OS_REG_READ(ah, AR_QMISC(q))

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

335

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

337

OS_REG_WRITE(ah, AR_DMISC(q), value);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

341

OS_REG_WRITE(ah, AR_QMISC(q),

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

342

OS_REG_READ(ah, AR_QMISC(q))

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

347

- (ah->ah_config.ah_sw_beacon_response_time

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

348

- ah->ah_config.ah_dma_beacon_response_time)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

349

- ah->ah_config.ah_additional_swba_backoff) * 1024;

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

350

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

354

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

356

OS_REG_WRITE(ah, AR_QMISC(q), value);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

38

ar5211UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

393

setTxQInterrupts(ah, qi);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

402

ar5211GetTxDP(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

405

return OS_REG_READ(ah, AR_QTXDP(q));

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

41

HAL_INT ints = ar5211GetInterrupts(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

412

ar5211SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

415

HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

421

HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

423

OS_REG_WRITE(ah, AR_QTXDP(q), txdp);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

432

ar5211StartTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

435

HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

438

HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1<<q)) == 0);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

440

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

443

HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

445

OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

453

ar5211NumTxPending(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

458

HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

460

n = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT_M;

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

466

if (n == 0 && (OS_REG_READ(ah, AR_Q_TXE) & (1<<q)))

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

47

ar5211SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

475

ar5211StopTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

48

txcfg = OS_REG_READ(ah, AR_TXCFG);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

480

HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

482

OS_REG_WRITE(ah, AR_Q_TXD, 1<<q);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

484

if (ar5211NumTxPending(ah, q) == 0)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

488

OS_REG_WRITE(ah, AR_Q_TXD, 0);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

509

ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

557

ar5211SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

562

(void) ah; (void) ds;

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

570

ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

578

ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

619

ar5211ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

62

ar5211SetInterrupts(ah, ints);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

663

ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

67

OS_REG_WRITE(ah, AR_TXCFG, (txcfg &~ AR_TXCFG_FTRIG_M) |

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

672

ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

678

ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

686

ar5211GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

694

ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

70

ar5211SetInterrupts(ah, ints);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

80

ar5211SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

82

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

85

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

89

return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

96

ar5211GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c

98

struct ath_hal_5211 *ahp = AH5211(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

111

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2316.c

120

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar2316.c

123

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2316.c

126

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2316.c

142

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar2316.c

149

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar2316.c

152

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar2316.c

154

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar2316.c

165

ar2316SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar2316.c

173

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

174

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2316.c

176

struct ar2316State *priv = AR2316(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

179

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar2316.c

212

HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

213

HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

214

HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

215

HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

216

HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

229

ar2316GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar2316.c

231

struct ar2316State *priv = AR2316(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

241

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar2316.c

357

ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

sys/dev/ath/ath_hal/ar5212/ar2316.c

363

struct ar2316State *priv = AR2316(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

437

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2316.c

502

ar2316SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2316.c

507

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

508

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2316.c

520

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar2316.c

528

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2316.c

532

pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar5212/ar2316.c

535

numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,

sys/dev/ath/ath_hal/ar5212/ar2316.c

547

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar5212/ar2316.c

550

tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);

sys/dev/ath/ath_hal/ar5212/ar2316.c

568

if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))

sys/dev/ath/ath_hal/ar5212/ar2316.c

569

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "

sys/dev/ath/ath_hal/ar5212/ar2316.c

571

__func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2316.c

573

OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2316.c

593

OS_REG_WRITE(ah, regoffset, reg32);

sys/dev/ath/ath_hal/ar5212/ar2316.c

597

OS_REG_WRITE(ah, AR_PHY_TPCRG5,

sys/dev/ath/ath_hal/ar5212/ar2316.c

608

ar2316GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)

sys/dev/ath/ath_hal/ar5212/ar2316.c

62

#define AR2316(ah) ((struct ar2316State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar2316.c

626

ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)

sys/dev/ath/ath_hal/ar5212/ar2316.c

643

ar2316GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2316.c

648

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2316.c

675

*maxPow = ar2316GetMaxPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

676

*minPow = ar2316GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

679

*maxPow = ar2316GetMaxPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

68

ar2316WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar2316.c

680

*minPow = ar2316GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

690

totalF = ar2316GetMaxPower(ah, &data[i]) - ar2316GetMaxPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

692

ar2316GetMaxPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2316.c

693

totalMin = ar2316GetMinPower(ah, &data[i]) - ar2316GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

695

ar2316GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2316.c

699

*maxPow = ar2316GetMaxPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

700

*minPow = ar2316GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2316.c

71

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

711

ar2316RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2316.c

713

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

725

ar2316RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar2316.c

727

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

73

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2316, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

730

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar2316.c

735

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2316.c

74

HAL_INI_WRITE_ARRAY(ah, ar5212Common_2316, 1, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

75

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2316, freqIndex, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2316.c

759

ar2316Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2316.c

761

return IS_2316(ah);

sys/dev/ath/ath_hal/ar5212/ar2316.c

79

OS_REG_WRITE(ah, 0xa358, (OS_REG_READ(ah, 0xa358) & ~0x2));

sys/dev/ath/ath_hal/ar5212/ar2316.c

91

ar2316SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar2316.c

93

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2316.c

99

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar2317.c

100

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2317.c

103

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2317.c

119

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar2317.c

126

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar2317.c

129

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar2317.c

131

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar2317.c

142

ar2317SetRfRegs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2317.c

151

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

152

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2317.c

154

struct ar2317State *priv = AR2317(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

157

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar2317.c

190

HAL_INI_WRITE_BANK(ah, ar5212Bank1_2317, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2317.c

191

HAL_INI_WRITE_BANK(ah, ar5212Bank2_2317, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2317.c

192

HAL_INI_WRITE_BANK(ah, ar5212Bank3_2317, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2317.c

193

HAL_INI_WRITE_BANK(ah, ar5212Bank6_2317, priv->Bank6Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2317.c

194

HAL_INI_WRITE_BANK(ah, ar5212Bank7_2317, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2317.c

206

ar2317GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar2317.c

208

struct ar2317State *priv = AR2317(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

218

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar2317.c

334

ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

sys/dev/ath/ath_hal/ar5212/ar2317.c

340

struct ar2317State *priv = AR2317(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

415

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2317.c

480

ar2317SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2317.c

485

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

486

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2317.c

498

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar2317.c

506

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2317.c

510

pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar5212/ar2317.c

513

numPdGainsUsed = ar2317getGainBoundariesAndPdadcsForPowers(ah,

sys/dev/ath/ath_hal/ar5212/ar2317.c

525

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar5212/ar2317.c

528

tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);

sys/dev/ath/ath_hal/ar5212/ar2317.c

546

if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))

sys/dev/ath/ath_hal/ar5212/ar2317.c

547

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "

sys/dev/ath/ath_hal/ar5212/ar2317.c

549

__func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2317.c

551

OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2317.c

571

OS_REG_WRITE(ah, regoffset, reg32);

sys/dev/ath/ath_hal/ar5212/ar2317.c

575

OS_REG_WRITE(ah, AR_PHY_TPCRG5,

sys/dev/ath/ath_hal/ar5212/ar2317.c

586

ar2317GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)

sys/dev/ath/ath_hal/ar5212/ar2317.c

604

ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)

sys/dev/ath/ath_hal/ar5212/ar2317.c

62

#define AR2317(ah) ((struct ar2317State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar2317.c

623

ar2317GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2317.c

628

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2317.c

655

*maxPow = ar2317GetMaxPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

656

*minPow = ar2317GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

659

*maxPow = ar2317GetMaxPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

660

*minPow = ar2317GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

670

totalF = ar2317GetMaxPower(ah, &data[i]) - ar2317GetMaxPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

672

ar2317GetMaxPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2317.c

673

totalMin = ar2317GetMinPower(ah, &data[i]) - ar2317GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

675

ar2317GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2317.c

679

*maxPow = ar2317GetMaxPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

68

ar2317WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar2317.c

680

*minPow = ar2317GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2317.c

691

ar2317RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2317.c

693

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

705

ar2317RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar2317.c

707

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

71

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2317, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2317.c

710

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar2317.c

715

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2317.c

72

HAL_INI_WRITE_ARRAY(ah, ar5212Common_2317, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar2317.c

73

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2317, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2317.c

737

ar2317Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2317.c

739

return IS_2317(ah);

sys/dev/ath/ath_hal/ar5212/ar2317.c

82

ar2317SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar2317.c

84

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2317.c

90

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar2317.c

97

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar2413.c

107

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar2413.c

110

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2413.c

113

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2413.c

134

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar2413.c

141

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar2413.c

144

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar2413.c

146

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar2413.c

158

ar2413SetRfRegs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2413.c

167

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

168

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2413.c

170

struct ar2413State *priv = AR2413(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

173

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar2413.c

206

HAL_INI_WRITE_BANK(ah, ar5212Bank1_2413, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2413.c

207

HAL_INI_WRITE_BANK(ah, ar5212Bank2_2413, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2413.c

208

HAL_INI_WRITE_BANK(ah, ar5212Bank3_2413, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2413.c

209

HAL_INI_WRITE_BANK(ah, ar5212Bank6_2413, priv->Bank6Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2413.c

210

HAL_INI_WRITE_BANK(ah, ar5212Bank7_2413, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2413.c

223

ar2413GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar2413.c

225

struct ar2413State *priv = AR2413(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

235

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar2413.c

351

ar2413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

sys/dev/ath/ath_hal/ar5212/ar2413.c

357

struct ar2413State *priv = AR2413(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

431

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2413.c

496

ar2413SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2413.c

501

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2413.c

502

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

503

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2413.c

515

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar2413.c

523

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2413.c

527

pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar5212/ar2413.c

530

numPdGainsUsed = ar2413getGainBoundariesAndPdadcsForPowers(ah,

sys/dev/ath/ath_hal/ar5212/ar2413.c

542

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar5212/ar2413.c

545

tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);

sys/dev/ath/ath_hal/ar5212/ar2413.c

563

if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))

sys/dev/ath/ath_hal/ar5212/ar2413.c

564

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "

sys/dev/ath/ath_hal/ar5212/ar2413.c

566

__func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2413.c

568

OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar2413.c

58

#define AR2413(ah) ((struct ar2413State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar2413.c

588

OS_REG_WRITE(ah, regoffset, reg32);

sys/dev/ath/ath_hal/ar5212/ar2413.c

592

OS_REG_WRITE(ah, AR_PHY_TPCRG5,

sys/dev/ath/ath_hal/ar5212/ar2413.c

603

ar2413GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar2413.c

621

ar2413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar2413.c

638

ar2413GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2413.c

64

ar2413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar2413.c

643

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2413.c

67

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2413, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2413.c

670

*maxPow = ar2413GetMaxPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

671

*minPow = ar2413GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

674

*maxPow = ar2413GetMaxPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

675

*minPow = ar2413GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

68

HAL_INI_WRITE_ARRAY(ah, ar5212Common_2413, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar2413.c

685

totalF = ar2413GetMaxPower(ah, &data[i]) - ar2413GetMaxPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

687

ar2413GetMaxPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2413.c

688

totalMin = ar2413GetMinPower(ah, &data[i]) - ar2413GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

69

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2413, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2413.c

690

ar2413GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2413.c

694

*maxPow = ar2413GetMaxPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

695

*minPow = ar2413GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2413.c

706

ar2413RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2413.c

708

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

720

ar2413RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar2413.c

722

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

725

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar2413.c

730

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2413.c

752

ar2413Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2413.c

754

return IS_2413(ah);

sys/dev/ath/ath_hal/ar5212/ar2413.c

78

ar2413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar2413.c

80

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2413.c

86

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar2413.c

98

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2425.c

101

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar2425.c

104

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2425.c

107

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar2425.c

129

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar2425.c

136

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar2425.c

139

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar2425.c

141

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar2425.c

152

ar2425SetRfRegs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2425.c

161

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

162

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2425.c

163

struct ar2425State *priv = AR2425(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

167

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar2425.c

200

HAL_INI_WRITE_BANK(ah, ar5212Bank1_2425, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2425.c

201

HAL_INI_WRITE_BANK(ah, ar5212Bank2_2425, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2425.c

202

HAL_INI_WRITE_BANK(ah, ar5212Bank3_2425, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2425.c

203

if (IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar2425.c

205

HAL_INI_WRITE_BANK(ah, ar5212Bank6_2417, priv->Bank6Data,

sys/dev/ath/ath_hal/ar5212/ar2425.c

208

HAL_INI_WRITE_BANK(ah, ar5212Bank6_2425, priv->Bank6Data,

sys/dev/ath/ath_hal/ar5212/ar2425.c

210

HAL_INI_WRITE_BANK(ah, ar5212Bank7_2425, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar2425.c

215

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2425.c

224

ar2425GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar2425.c

226

struct ar2425State *priv = AR2425(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

236

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar2425.c

353

ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

sys/dev/ath/ath_hal/ar5212/ar2425.c

383

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "==>%s:\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2425.c

46

#define AR2425(ah) ((struct ar2425State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar2425.c

490

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2425.c

495

ar2425SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2425.c

500

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2425.c

501

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

502

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2425.c

510

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s:chan 0x%x flag 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar2425.c

518

HALDEBUG(ah, HAL_DEBUG_ANY, "%s:illegal mode\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar2425.c

52

ar2425WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar2425.c

522

pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar5212/ar2425.c

525

ar2425getGainBoundariesAndPdadcsForPowers(ah, freq,

sys/dev/ath/ath_hal/ar5212/ar2425.c

529

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar5212/ar2425.c

549

OS_REG_WRITE(ah, regoffset, reg32);

sys/dev/ath/ath_hal/ar5212/ar2425.c

55

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2425, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2425.c

553

OS_REG_WRITE(ah, AR_PHY_TPCRG5,

sys/dev/ath/ath_hal/ar5212/ar2425.c

56

HAL_INI_WRITE_ARRAY(ah, ar5212Common_2425, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar2425.c

564

ar2425GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar2425.c

57

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2425, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar2425.c

582

ar2425GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar2425.c

600

ar2425GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar2425.c

605

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar2425.c

632

*maxPow = ar2425GetMaxPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

633

*minPow = ar2425GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

636

*maxPow = ar2425GetMaxPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

637

*minPow = ar2425GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

64

if (AH_PRIVATE(ah)->ah_ispcie && && ath_hal_pcieL1SKPEnable) {

sys/dev/ath/ath_hal/ar5212/ar2425.c

647

totalF = ar2425GetMaxPower(ah, &data[i]) - ar2425GetMaxPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

649

ar2425GetMaxPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2425.c

65

OS_REG_WRITE(ah, AR_PCIE_PMC,

sys/dev/ath/ath_hal/ar5212/ar2425.c

650

totalMin = ar2425GetMinPower(ah, &data[i]) - ar2425GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

652

ar2425GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar2425.c

656

*maxPow = ar2425GetMaxPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

657

*minPow = ar2425GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar2425.c

668

ar2425RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2425.c

670

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

682

ar2425RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar2425.c

684

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

687

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar2425.c

692

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar2425.c

714

ar2425Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar2425.c

716

return IS_2425(ah) || IS_2417(ah);

sys/dev/ath/ath_hal/ar5212/ar2425.c

75

OS_REG_SET_BIT(ah, AR_PCIE_PMC, MAC_WOW_PWR_STATE_MASK_D2);

sys/dev/ath/ath_hal/ar5212/ar2425.c

85

ar2425SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar2425.c

87

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar2425.c

93

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar5111.c

144

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar5111.c

156

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar5111.c

159

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5111.c

162

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5111.c

180

OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));

sys/dev/ath/ath_hal/ar5212/ar5111.c

182

OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));

sys/dev/ath/ath_hal/ar5212/ar5111.c

184

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar5111.c

193

ar5111GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar5111.c

195

struct ar5111State *priv = AR5111(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

206

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar5111.c

218

ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5111.c

221

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5111.c

222

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

223

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5111.c

229

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar5111.c

282

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5111.c

297

HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

300

HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

303

HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

306

HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

320

HAL_INI_WRITE_BANK(ah, ar5212Bank6_5111, rfReg, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

339

HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5111.c

389

ar5111SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5111.c

394

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5111.c

395

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

396

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5111.c

432

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5111.c

46

#define AR5111(ah) ((struct ar5111State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar5111.c

626

ar5111GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5111.c

63

ar5111WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar5111.c

639

ar5111GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar5212/ar5111.c

66

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5111, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5111.c

668

ar5111RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5111.c

67

HAL_INI_WRITE_ARRAY(ah, ar5212Common_5111, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar5111.c

670

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

68

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5111, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5111.c

682

ar5111RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar5111.c

684

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

687

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5111.c

692

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5111.c

714

ar5111Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5111.c

716

return IS_RAD5111(ah);

sys/dev/ath/ath_hal/ar5212/ar5111.c

77

ar5111SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5111.c

80

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5112.c

107

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar5112.c

110

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5112.c

113

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5112.c

134

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar5112.c

141

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar5112.c

144

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar5112.c

146

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar5112.c

154

ar5112GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar5112.c

156

struct ar5112State *priv = AR5112(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

166

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar5112.c

178

ar5112SetRfRegs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5112.c

187

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5112.c

188

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

189

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5112.c

193

struct ar5112State *priv = AR5112(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

199

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar5112.c

237

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5112.c

284

if (IS_RADX112_REV2(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5112.c

293

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {

sys/dev/ath/ath_hal/ar5212/ar5112.c

326

HAL_INI_WRITE_BANK(ah, ar5212Bank1_5112, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5112.c

327

HAL_INI_WRITE_BANK(ah, ar5212Bank2_5112, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5112.c

328

HAL_INI_WRITE_BANK(ah, ar5212Bank3_5112, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5112.c

329

HAL_INI_WRITE_BANK(ah, ar5212Bank6_5112, priv->Bank6Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5112.c

330

HAL_INI_WRITE_BANK(ah, ar5212Bank7_5112, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5112.c

344

ar5112SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5112.c

349

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5112.c

350

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

351

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5112.c

352

uint32_t numXpdGain = IS_RADX112_REV2(ah) ? 2 : 1;

sys/dev/ath/ath_hal/ar5212/ar5112.c

392

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5112.c

398

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5112.c

416

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5112.c

45

#define AR5112(ah) ((struct ar5112State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar5112.c

64

ar5112WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar5112.c

67

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5112, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5112.c

68

HAL_INI_WRITE_ARRAY(ah, ar5212Common_5112, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar5112.c

69

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5112, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5112.c

740

ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_PER_CHANNEL_5112 *data)

sys/dev/ath/ath_hal/ar5212/ar5112.c

766

ar5112GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5112.c

771

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5112.c

78

ar5112SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5112.c

80

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5112.c

804

*minPow = ar5112GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar5112.c

808

*minPow = ar5112GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar5112.c

822

totalMin = ar5112GetMinPower(ah,&data[i]) - ar5112GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar5112.c

823

*minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) + ar5112GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar5112.c

828

*minPow = ar5112GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar5112.c

839

ar5112RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5112.c

841

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

853

ar5112RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar5112.c

855

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

858

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5112.c

86

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar5112.c

863

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5112.c

885

ar5112Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5112.c

887

return IS_RAD5112(ah);

sys/dev/ath/ath_hal/ar5212/ar5112.c

98

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212.h

133

void (*rfDetach)(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

136

uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);

sys/dev/ath/ath_hal/ar5212/ar5212.h

142

HAL_BOOL (*setPowerTable)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

145

HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

361

#define IS_2317(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

362

((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

363

(AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))

sys/dev/ath/ath_hal/ar5212/ar5212.h

364

#define IS_2316(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

365

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)

sys/dev/ath/ath_hal/ar5212/ar5212.h

366

#define IS_2413(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

367

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))

sys/dev/ath/ath_hal/ar5212/ar5212.h

368

#define IS_5424(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

369

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

370

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \

sys/dev/ath/ath_hal/ar5212/ar5212.h

371

AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))

sys/dev/ath/ath_hal/ar5212/ar5212.h

372

#define IS_5413(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

373

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))

sys/dev/ath/ath_hal/ar5212/ar5212.h

374

#define IS_2425(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

375

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)

sys/dev/ath/ath_hal/ar5212/ar5212.h

376

#define IS_2417(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

377

((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)

sys/dev/ath/ath_hal/ar5212/ar5212.h

378

#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)

sys/dev/ath/ath_hal/ar5212/ar5212.h

380

#define AH_RADIO_MAJOR(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

381

(AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)

sys/dev/ath/ath_hal/ar5212/ar5212.h

382

#define AH_RADIO_MINOR(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

383

(AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)

sys/dev/ath/ath_hal/ar5212/ar5212.h

384

#define IS_RAD5111(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

385

(AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

386

AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)

sys/dev/ath/ath_hal/ar5212/ar5212.h

387

#define IS_RAD5112(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

388

(AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

389

AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)

sys/dev/ath/ath_hal/ar5212/ar5212.h

391

#define IS_RAD5112_ANY(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

392

(AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \

sys/dev/ath/ath_hal/ar5212/ar5212.h

393

AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)

sys/dev/ath/ath_hal/ar5212/ar5212.h

394

#define IS_RAD5112_REV1(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

395

(IS_RAD5112(ah) && \

sys/dev/ath/ath_hal/ar5212/ar5212.h

396

AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))

sys/dev/ath/ath_hal/ar5212/ar5212.h

397

#define IS_RADX112_REV2(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

398

(AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

399

AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

400

AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \

sys/dev/ath/ath_hal/ar5212/ar5212.h

401

AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)

sys/dev/ath/ath_hal/ar5212/ar5212.h

403

#define ar5212RfDetach(ah) do { \

sys/dev/ath/ath_hal/ar5212/ar5212.h

404

if (AH5212(ah)->ah_rfHal != AH_NULL) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

405

AH5212(ah)->ah_rfHal->rfDetach(ah); \

sys/dev/ath/ath_hal/ar5212/ar5212.h

407

#define ar5212GetRfBank(ah, b) \

sys/dev/ath/ath_hal/ar5212/ar5212.h

408

AH5212(ah)->ah_rfHal->getRfBank(ah, b)

sys/dev/ath/ath_hal/ar5212/ar5212.h

432

extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

435

extern void ar5212Detach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

436

extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

437

extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

439

extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

441

extern void ar5212SetBeaconTimers(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

443

extern void ar5212BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

445

extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

446

extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

450

extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

451

extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);

sys/dev/ath/ath_hal/ar5212/ar5212.h

452

extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

453

extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);

sys/dev/ath/ath_hal/ar5212/ar5212.h

457

extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);

sys/dev/ath/ath_hal/ar5212/ar5212.h

460

extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5212/ar5212.h

463

extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);

sys/dev/ath/ath_hal/ar5212/ar5212.h

464

extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);

sys/dev/ath/ath_hal/ar5212/ar5212.h

465

extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);

sys/dev/ath/ath_hal/ar5212/ar5212.h

469

extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

471

extern u_int ar5212GetWirelessModes(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

477

extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);

sys/dev/ath/ath_hal/ar5212/ar5212.h

478

extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);

sys/dev/ath/ath_hal/ar5212/ar5212.h

479

extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);

sys/dev/ath/ath_hal/ar5212/ar5212.h

480

extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,

sys/dev/ath/ath_hal/ar5212/ar5212.h

482

extern uint32_t ar5212GetTsf32(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

483

extern uint64_t ar5212GetTsf64(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

484

extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64);

sys/dev/ath/ath_hal/ar5212/ar5212.h

485

extern void ar5212ResetTsf(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

486

extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);

sys/dev/ath/ath_hal/ar5212/ar5212.h

487

extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

488

extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

491

extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);

sys/dev/ath/ath_hal/ar5212/ar5212.h

492

extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

493

extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

494

extern u_int ar5212GetDefAntenna(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

495

extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);

sys/dev/ath/ath_hal/ar5212/ar5212.h

498

extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

512

extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5212/ar5212.h

513

extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5212/ar5212.h

514

extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5212/ar5212.h

517

extern void ar5212SetCompRegs(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

522

extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5212/ar5212.h

525

extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,

sys/dev/ath/ath_hal/ar5212/ar5212.h

533

extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,

sys/dev/ath/ath_hal/ar5212/ar5212.h

535

extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

536

extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

539

extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE);

sys/dev/ath/ath_hal/ar5212/ar5212.h

540

extern void ar5212EnableReceive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

541

extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

542

extern void ar5212StartPcuReceive(struct ath_hal *ah, HAL_BOOL);

sys/dev/ath/ath_hal/ar5212/ar5212.h

543

extern void ar5212StopPcuReceive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

544

extern void ar5212SetMulticastFilter(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

548

extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

549

extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);

sys/dev/ath/ath_hal/ar5212/ar5212.h

552

extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,

sys/dev/ath/ath_hal/ar5212/ar5212.h

556

extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5212/ar5212.h

561

extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);

sys/dev/ath/ath_hal/ar5212/ar5212.h

562

extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

563

extern HAL_BOOL ar5212Disable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

564

extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

566

extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

568

extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

571

extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

573

extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

578

extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

580

extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);

sys/dev/ath/ath_hal/ar5212/ar5212.h

581

extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

584

extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

589

extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5212/ar5212.h

591

extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,

sys/dev/ath/ath_hal/ar5212/ar5212.h

593

extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5212/ar5212.h

595

extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

596

extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

597

extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

598

extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);

sys/dev/ath/ath_hal/ar5212/ar5212.h

599

extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

600

extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

601

extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5212/ar5212.h

602

extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212.h

612

extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212.h

616

extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

618

extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);

sys/dev/ath/ath_hal/ar5212/ar5212.h

619

extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);

sys/dev/ath/ath_hal/ar5212/ar5212.h

620

extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

622

extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5212/ar5212.h

624

extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5212/ar5212.h

626

extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds,

sys/dev/ath/ath_hal/ar5212/ar5212.h

640

extern void ar5212AniPhyErrReport(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

649

extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

650

extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);

sys/dev/ath/ath_hal/ar5212/ar5212.h

651

extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);

sys/dev/ath/ath_hal/ar5212/ar5212.h

652

extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

654

extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);

sys/dev/ath/ath_hal/ar5212/ar5212.h

655

extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212.h

658

extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212.h

659

extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1000

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1008

OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1017

updateMIBStats(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1022

ar5212AniLowerImmunity(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1023

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1026

updateMIBStats(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1030

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1033

ar5212AniOfdmErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1034

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1037

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1040

ar5212AniCckErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

1041

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

105

ar5212AniGetCurrentState(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

107

return AH5212(ah)->ah_curani;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

114

ar5212AniGetCurrentStats(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

116

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

120

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

125

setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

128

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

135

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

150

ar5212AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

153

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

156

AH_PRIVATE(ah)->ah_caps.halHwPhyCounterSupport;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

160

setPhyErrBase(ah, &ahp->ah_aniParams24);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

164

setPhyErrBase(ah, &ahp->ah_aniParams5);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

170

enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

181

ar5212AniSetParams(struct ath_hal *ah, const struct ar5212AniParams *params24,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

184

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

187

ar5212AniControl(ah, HAL_ANI_MODE, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

190

setPhyErrBase(ah, &ahp->ah_aniParams24);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

192

setPhyErrBase(ah, &ahp->ah_aniParams5);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

195

ar5212AniReset(ah, AH_PRIVATE(ah)->ah_curchan,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

196

AH_PRIVATE(ah)->ah_opmode, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

198

ar5212AniControl(ah, HAL_ANI_MODE, ena);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

207

ar5212AniDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

209

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

211

HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

213

disableAniMIBCounters(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

220

ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

223

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

234

OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

241

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

247

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

249

OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

251

OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

253

OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

272

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

274

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

276

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

278

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

280

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

282

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

286

OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

290

OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

301

OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

314

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

319

OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

332

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

337

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

352

ar5212AniDetach(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

353

ah->ah_setRxFilter(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

354

ah->ah_getRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

360

ar5212SetRxFilter(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

361

ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

363

enableAniMIBCounters(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

368

ah->ah_setRxFilter(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

369

ah->ah_getRxFilter(ah) | HAL_RX_FILTER_PHYERR);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

381

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

389

ar5212AniOfdmErrTrigger(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

391

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

392

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

398

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

405

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

407

ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

413

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

415

ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

420

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

428

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

430

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

433

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

442

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

445

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

455

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

457

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

462

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

465

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

477

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

480

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

485

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

489

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

499

ar5212AniCckErrTrigger(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

501

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

502

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

508

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

515

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

517

ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

522

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

530

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

533

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

545

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

549

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

558

ar5212AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

560

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

569

OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

570

OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

571

OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

572

OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

575

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

586

ar5212AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

589

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

59

#define ANI_ENA(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

590

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

60

(AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

606

ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

61

#define ANI_ENA_RSSI(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

610

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

614

OS_MARK(ah, AH_MARK_ANI_RESET, opmode);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

619

rxfilter = ah->ah_getRxFilter(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

62

(AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

620

ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

627

if (! ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

628

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

647

ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

649

ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

651

ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

653

ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

655

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

658

ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

659

ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

660

ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

662

ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

663

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

669

enableAniMIBCounters(ah, ahp->ah_curani->params);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

67

enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

670

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

674

ah->ah_setRxFilter(ah, rxfilter);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

683

ar5212ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

685

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

688

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

69

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

690

__func__, OS_REG_READ(ah, AR_MIBC),

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

691

OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

692

OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

704

phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

705

phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

707

OS_REG_WRITE(ah, AR_FILTOFDM, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

708

OS_REG_WRITE(ah, AR_FILTCCK, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

71

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

711

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

743

ar5212AniOfdmErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

745

ar5212AniCckErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

747

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

75

OS_REG_WRITE(ah, AR_FILTOFDM, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

752

ar5212AniPhyErrReport(struct ath_hal *ah, const struct ath_rx_status *rs)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

754

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

76

OS_REG_WRITE(ah, AR_FILTCCK, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

766

ar5212AniOfdmErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

767

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

773

ar5212AniCckErrTrigger(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

774

ar5212AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

78

OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

780

ar5212AniLowerImmunity(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

782

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

786

HALASSERT(ANI_ENA(ah));

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

79

OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

790

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

80

OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

804

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

806

ar5212AniControl(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

81

OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

812

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

815

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

824

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

827

ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

83

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

835

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower SI %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

837

ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

84

ar5212EnableMibCounters(ah); /* enable everything */

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

846

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower NI %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

848

ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

865

ar5212AniGetListenTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

867

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

876

if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

877

ath_hal_printf(ah, "%s: ah_curchan = NULL?\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

88

disableAniMIBCounters(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

886

good = ar5212GetMibCycleCounts(ah, &hs);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

887

ath_hal_survey_add_sample(ah, &hs);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

889

if (ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

90

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

900

} else if (ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

906

AH5212(ah)->ah_cycleCount - aniState->cycleCount;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

908

AH5212(ah)->ah_rxBusy - aniState->rxFrameCount;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

910

AH5212(ah)->ah_txBusy - aniState->txFrameCount;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

917

if (ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

918

aniState->cycleCount = AH5212(ah)->ah_cycleCount;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

919

aniState->rxFrameCount = AH5212(ah)->ah_rxBusy;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

92

HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

920

aniState->txFrameCount = AH5212(ah)->ah_txBusy;

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

930

updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

932

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

94

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

940

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

943

phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

944

phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

949

HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

95

ar5212DisableMibCounters(ah); /* disable everything */

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

959

HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

969

ar5212RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

97

OS_REG_WRITE(ah, AR_PHYCNTMASK1, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

972

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

98

OS_REG_WRITE(ah, AR_PHYCNTMASK2, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

981

ar5212AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

983

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

989

listenTime = ar5212AniGetListenTime(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_ani.c

994

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

183

ar5212GetRadioRev(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

189

OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

191

OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

192

val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

198

ar5212AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

218

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

222

ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

224

ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

227

AH5212(ah)->ah_aniControl = ar5212AniControl;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

240

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

242

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

245

ah->ah_sc = sc;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

246

ah->ah_st = st;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

247

ah->ah_sh = sh;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

249

ah->ah_devid = devid; /* NB: for alq */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

250

AH_PRIVATE(ah)->ah_devid = devid;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

251

AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

253

AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

254

AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

32

static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

324

#define AH_EEPROM_PROTECT(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

325

(AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

327

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

34

static void ar5212DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

345

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

347

if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

348

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

354

val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

355

AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

356

AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

357

AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

359

if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

360

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

362

__func__, AH_PRIVATE(ah)->ah_macVersion,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

363

AH_PRIVATE(ah)->ah_macRev);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

372

if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

373

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

378

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

380

if (AH_PRIVATE(ah)->ah_ispcie) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

382

ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

385

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

386

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

393

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

394

OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

400

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

403

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

405

rf = ath_hal_rfprobe(ah, &ecode);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

410

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

420

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

429

if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

430

AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

431

AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

432

AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

435

if (IS_2413(ah)) { /* Griffin */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

436

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

440

if (IS_5413(ah)) { /* Eagle */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

441

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

445

if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

446

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

452

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

455

__func__, AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

460

if (IS_RAD5112_REV1(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

461

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

464

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

469

val = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

472

if (!AH_PRIVATE(ah)->ah_ispcie) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

473

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

482

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

488

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

494

ecode = ath_hal_legacyEepromAttach(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

498

ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

503

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

504

(AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

509

OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

511

AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

514

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

516

if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

517

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

520

AH_PRIVATE(ah)->ah_analog2GhzRev);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

526

ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

528

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

533

AH_PRIVATE(ah)->ah_currentRD = eeval;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

539

if (!ar5212FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

540

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

546

if (!rf->attach(ah, &ecode)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

547

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

555

AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

558

ar5212InitializeGainValues(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

560

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

562

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

567

ar5212AniSetup(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

569

ar5212InitNfCalHistBuffer(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

573

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

575

return ah;

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

587

ar5212Detach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

589

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

591

HALASSERT(ah != AH_NULL);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

592

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

594

ar5212AniDetach(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

595

ar5212RfDetach(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

596

ar5212Disable(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

597

ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

599

ath_hal_eepromDetach(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

600

ath_hal_free(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

604

ar5212ChipTest(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

617

regHold[i] = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

620

OS_REG_WRITE(ah, addr, wrData);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

621

rdData = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

623

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

631

OS_REG_WRITE(ah, addr, wrData);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

632

rdData = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

634

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

640

OS_REG_WRITE(ah, regAddr[i], regHold[i]);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

650

ar5212GetChannelEdges(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

659

(ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

660

ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

678

ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

680

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

681

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

684

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

685

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

686

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

689

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

690

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

691

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

692

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

695

OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

699

ar5212DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

710

ar5212FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

713

#define IS_GRIFFIN_LITE(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

714

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

715

AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

716

#define IS_COBRA(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

717

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

718

#define IS_2112(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

719

((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

721

struct ath_hal_private *ahpriv = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

726

if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

727

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

731

if (IS_2112(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

732

ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

733

if (capField == 0 && IS_GRIFFIN_LITE(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

737

ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

738

ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

739

ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

740

ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

741

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

754

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

758

if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

759

AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

760

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

763

ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

764

ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

765

ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

766

ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

767

ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

772

if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

774

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

777

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

779

if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

782

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

788

if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

811

if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

821

(ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

822

((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

823

((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

824

(AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

828

pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

833

if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

840

if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

842

ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

844

pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

846

ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

864

if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

869

if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

883

if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

884

ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

892

(AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

895

if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

896

AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

897

AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

913

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

100

switch (AH_PRIVATE(ah)->ah_opmode) {

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

109

ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

111

ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

123

ar5212SetBeaconTimers(ah, &bt);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

127

ar5212ResetStaBeaconTimers(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

131

OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

132

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

135

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

137

OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

146

ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

148

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

155

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

156

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

159

OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

162

OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

165

OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

168

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

169

OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

175

OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

184

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

185

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

198

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

250

OS_REG_WRITE(ah, AR_SLEEP1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

256

OS_REG_WRITE(ah, AR_SLEEP2,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

260

OS_REG_WRITE(ah, AR_SLEEP3,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

264

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

266

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

268

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

270

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

32

ar5212GetNextTBTT(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

35

return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

45

ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

47

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

57

OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

58

OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

59

OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

61

OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

75

OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

77

OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

88

ar5212BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

36

ar5212EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

38

OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

39

OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

41

if (!ath_hal_wait(ah, AR_EEPROM_STS,

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

44

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c

48

*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

105

ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

110

val = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

120

OS_REG_WRITE(ah, AR_GPIOCR, val);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

123

(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

39

ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

47

OS_REG_WRITE(ah, AR_GPIOCR,

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

48

OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

57

ar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

61

OS_REG_WRITE(ah, AR_GPIOCR,

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

62

(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

72

ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

78

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

82

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

90

ar5212GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

93

uint32_t val = OS_REG_READ(ah, AR_GPIODI);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

102

if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

103

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

113

AH_PRIVATE(ah)->ah_fatalState[0] = isr;

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

114

AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

115

AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

116

AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

117

AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

118

AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

119

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

121

__func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

127

ar5212GetInterrupts(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

129

return AH5212(ah)->ah_maskReg;

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

137

ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

139

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

143

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

147

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

148

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

149

(void) OS_REG_READ(ah, AR_IER); /* flush write to HW */

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

188

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

189

OS_REG_WRITE(ah, AR_IMR, mask);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

190

OS_REG_WRITE(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

191

(OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

196

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

197

OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

35

ar5212IsInterruptPending(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

41

return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

54

ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

58

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

60

isr = OS_REG_READ(ah, AR_ISR);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

63

uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

75

isr = OS_REG_READ(ah, AR_ISR_RAC);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

89

isr0 = OS_REG_READ(ah, AR_ISR_S0_S);

sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c

92

isr1 = OS_REG_READ(ah, AR_ISR_S1_S);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

110

ar5212SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

115

if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

116

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

144

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

145

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

154

ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

158

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

159

const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

166

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

176

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

178

__func__, AH_PRIVATE(ah)->ah_macRev);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

185

if (IS_MIC_ENABLED(ah) && entry+64 >= pCap->halKeyCacheSize) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

186

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

194

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

210

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

229

if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

238

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

239

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

240

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

241

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

242

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

243

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

244

(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

276

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

277

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

278

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

279

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

280

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

281

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

284

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

285

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

288

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

289

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

291

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

292

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

293

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

294

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

295

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

296

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

298

(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

36

#define IS_MIC_ENABLED(ah) \

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

37

(AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

43

ar5212GetKeyCacheSize(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

45

return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

52

ar5212IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

54

if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

55

uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

66

ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

70

if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

71

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

75

keyType = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

78

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

79

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

80

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

81

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

82

OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

83

OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

84

OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

85

OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

86

if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

89

HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

90

OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

91

OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

92

OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c

93

OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1015

OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1030

AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) :

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1043

return ath_hal_setcapability(ah, type, capability,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1050

ar5212GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1054

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1058

if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1066

return ath_hal_eepromDiag(ah, request,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1082

*result = ar5212AniGetCurrentState(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1088

astats = ar5212AniGetCurrentStats(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1101

AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0],

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1112

ar5212AniGetCurrentState(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1121

return ar5212AniSetParams(ah, args, args);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

113

ar5212GetWirelessModes(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1135

ar5212IsNFCalInProgress(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1137

if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1150

ar5212WaitNFCalComplete(struct ath_hal *ah, int i)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1156

if (! ar5212IsNFCalInProgress(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1164

ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1167

val = OS_REG_READ(ah, AR_PHY_RADAR_0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

117

if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

119

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1194

if (IS_5413(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1196

OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1199

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1203

OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1206

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

121

if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1210

OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1213

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1217

OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1220

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1224

OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1227

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

123

if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1231

OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1235

OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1239

OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1243

OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

126

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1268

ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1271

if (IS_5413(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

128

if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

129

AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1305

ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1309

val = OS_REG_READ(ah, AR_PHY_RADAR_0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

131

if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

133

if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1330

if (IS_5413(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1331

val = OS_REG_READ(ah, AR_PHY_RADAR_2);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1349

ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

135

if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1377

HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n",

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1395

ar5212IsFastClockEnabled(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1405

ar5212Get11nExtBusy(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1414

ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1416

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1420

uint32_t rc = OS_REG_READ(ah, AR_RCCNT);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1421

uint32_t rf = OS_REG_READ(ah, AR_RFCNT);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1422

uint32_t tf = OS_REG_READ(ah, AR_TFCNT);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1423

uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1431

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1455

ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1466

ar5212GetNav(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

147

ar5212EnableRfKill(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1470

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1481

ar5212SetNav(struct ath_hal *ah, u_int val)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1484

OS_REG_WRITE(ah, AR_NAV, val);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

149

uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

157

ath_hal_gpioCfgInput(ah, select);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

158

OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

167

ath_hal_gpioSetIntr(ah, select,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

168

(ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

175

ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

189

bits = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

190

if (IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

207

OS_REG_WRITE(ah, AR_PCICFG, bits);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

217

ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

219

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

224

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

225

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

233

ar5212GetTsf64(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

238

low1 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

239

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

240

low2 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

261

ar5212GetTsf32(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

263

return OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

267

ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

269

OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

270

OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

277

ar5212ResetTsf(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

280

uint32_t val = OS_REG_READ(ah, AR_BEACON);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

282

OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

290

OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

299

ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

301

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

319

reg = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

321

OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

323

OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

331

ar5212GetRandomSeed(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

335

nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

338

return (OS_REG_READ(ah, AR_TSF_U32) ^

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

339

OS_REG_READ(ah, AR_TSF_L32) ^ nf);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

346

ar5212DetectCardPresent(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

356

v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

359

return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

36

ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

360

AH_PRIVATE(ah)->ah_macRev == macRev);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

364

ar5212EnableMibCounters(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

367

OS_REG_WRITE(ah, AR_MIBC,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

372

ar5212DisableMibCounters(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

374

OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

38

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

381

ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

383

stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

384

stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

385

stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

386

stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

387

stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

394

ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

403

ar5212GetCurRssi(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

405

return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

409

ar5212GetDefAntenna(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

411

return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

415

ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

417

OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

421

ar5212GetAntennaSwitch(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

423

return AH5212(ah)->ah_antControl;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

427

ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

429

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

430

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

438

return ar5212SetAntennaSwitchInternal(ah, setting, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

44

ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

442

ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

448

ar5212SetSifsTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

450

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

452

if (us > ath_hal_mac_usec(ah, 0xffff)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

453

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

459

OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

46

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

466

ar5212GetSifsTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

468

u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

469

return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

473

ar5212SetSlotTime(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

475

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

477

if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

478

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

484

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

491

ar5212GetSlotTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

493

u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

494

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

498

ar5212SetAckTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

500

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

502

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

503

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

509

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

510

AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

517

ar5212GetAckTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

519

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

520

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

524

ar5212GetAckCTSRate(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

526

return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

53

ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

530

ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

532

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

535

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

538

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

545

ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

547

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

549

if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

55

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

550

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

556

OS_REG_RMW_FIELD(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

557

AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

564

ar5212GetCTSTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

566

u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

567

return ath_hal_mac_usec(ah, clks); /* convert from system clocks */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

572

ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

574

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

578

OS_REG_WRITE(ah, AR_DCM_A, keyidx);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

579

OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

587

ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

592

AH_PRIVATE(ah)->ah_coverageClass = coverageclass;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

595

if (AH_PRIVATE(ah)->ah_coverageClass == 0)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

599

if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

603

clkRate = ath_hal_mac_clks(ah, 1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

608

if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

61

ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

611

} else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

628

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

629

OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

63

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

630

OS_REG_WRITE(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

637

ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

640

OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

642

OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

645

OS_REG_WRITE(ah, AR_QUIET1, nextStart);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

651

ar5212SetPCUConfig(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

653

ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

663

ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

666

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

667

return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

68

OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

681

ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

683

if (ar5212Use32KHzclock(ah, opmode)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

689

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

69

OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

690

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

691

IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

692

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

693

OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

694

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

696

if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

697

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

698

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

699

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

700

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

702

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

704

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

705

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

706

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

707

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

708

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

711

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

712

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

714

OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

716

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

717

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

719

if (IS_2417(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

720

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

721

else if (IS_HB63(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

722

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

724

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

725

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

726

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

727

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

728

IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

729

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

730

IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

738

ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

740

if (ar5212Use32KHzclock(ah, opmode)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

742

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

743

OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

745

OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

746

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

747

IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

752

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

753

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

754

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

755

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

756

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

757

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

758

IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

767

ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

77

ar5212SetRegulatoryDomain(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

793

ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

796

#define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

797

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

798

const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

82

if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

837

return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

838

(MACVERSION(ah) == AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

839

AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

847

*result = OS_REG_READ(ah, AR_PHY_RESTART);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

853

*result = AH_PRIVATE(ah)->ah_diagreg;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

86

if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

866

return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

869

return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

870

ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

91

if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

910

ani = ar5212AniGetCurrentState(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

92

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

924

return ath_hal_getcapability(ah, type, capability, result);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

930

ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

934

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

935

const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

95

AH_PRIVATE(ah)->ah_currentRD = regDomain;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

954

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

963

v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

968

OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

977

v = OS_REG_READ(ah, AR_PHY_RESTART);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

980

OS_REG_WRITE(ah, AR_PHY_RESTART, v);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

991

AH_PRIVATE(ah)->ah_diagreg = setting;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

992

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5212/ar5212_phy.c

162

ar5212GetRateTable(struct ath_hal *ah, u_int mode)

sys/dev/ath/ath_hal/ar5212/ar5212_phy.c

194

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_phy.c

198

ath_hal_setupratetable(ah, rt);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

108

ar5212SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

110

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

112

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

120

ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

132

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

133

modes[ah->ah_powerMode], modes[mode],

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

138

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

139

status = ar5212SetPowerModeAwake(ah, setChip);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

142

ar5212SetPowerModeSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

144

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

147

ar5212SetPowerModeNetworkSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

149

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

152

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

163

ar5212GetPowerMode(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

166

return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

175

ar5212GetPowerStatus(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

177

return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

38

ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

57

scr = OS_REG_READ(ah, AR_SCR);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

59

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

61

__func__, scr, OS_REG_READ(ah, AR_PCICFG));

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

65

OS_REG_WRITE(ah, AR_SCR, scr);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

69

val = OS_REG_READ(ah, AR_PCICFG);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

73

OS_REG_WRITE(ah, AR_SCR, scr);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

77

ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

84

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

95

ar5212SetPowerModeSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

97

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

99

OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

104

ar5212StopPcuReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

106

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

107

OS_REG_WRITE(ah, AR_DIAG_SW,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

108

OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

109

ar5212DisableMibCounters(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

117

ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

119

OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

120

OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

127

ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

134

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

135

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

137

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

138

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

147

ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

154

val = OS_REG_READ(ah, AR_MCAST_FIL1);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

155

OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

157

val = OS_REG_READ(ah, AR_MCAST_FIL0);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

158

OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

167

ar5212GetRxFilter(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

169

uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

170

uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

175

if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

176

(AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

185

ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

187

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

190

OS_REG_WRITE(ah, AR_RX_FILTER,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

198

OS_REG_WRITE(ah, AR_PHY_ERR, phybits);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

200

OS_REG_WRITE(ah, AR_RXCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

201

OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

203

OS_REG_WRITE(ah, AR_RXCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

204

OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

206

if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

211

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

220

ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

246

ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

260

if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

305

if (!AH5212(ah)->ah_hasHwPhyCounters &&

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

307

ar5212AniPhyErrReport(ah, rs);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

44

ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

48

OS_REG_WRITE(ah, AR_RXDP, rxdp);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

49

HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

56

ar5212EnableReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

58

OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

65

ar5212StopDmaReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

67

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

68

OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

69

if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

70

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

72

ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

75

OS_REG_READ(ah, AR_CR),

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

76

OS_REG_READ(ah, AR_DIAG_SW));

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

88

ar5212StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

90

struct ath_hal_private *ahp = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

92

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

93

OS_REG_WRITE(ah, AR_DIAG_SW,

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

94

OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

95

ar5212EnableMibCounters(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_recv.c

97

ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, !is_scanning);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1001

!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1012

powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1013

powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1014

iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1018

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1022

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1024

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1053

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1057

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1059

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1061

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1076

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1079

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1087

ar5212GetNf(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1091

(IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan)))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1092

ar5212RequestRfgain(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1095

RESTORE_CCK(ah, chan, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1102

ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1105

return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1109

ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1113

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1115

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1131

ar5212MacStop(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1142

OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1146

ar5212SetTxdpInvalid(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1148

OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1155

if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1161

if (!OS_REG_IS_BIT_SET(ah, AR_Q_TXE, AR_Q_TXE_M)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1169

pendFrameCount += OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

117

ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1185

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1197

ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1203

if (AH_PRIVATE(ah)->ah_ispcie) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1212

rt = ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1221

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1222

OS_REG_READ(ah, AR_IER);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1224

if (ar5212MacStop(ah) != AH_TRUE) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1231

OS_REG_READ(ah, AR_RXDP);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1235

if (! AH_PRIVATE(ah)->ah_ispcie) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1243

if (AH_PRIVATE(ah)->ah_bustype == HAL_BUS_TYPE_PCI) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1244

if (!IS_5112_REV5_UP(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

125

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1250

ath_hal_read_pci_config_space(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1267

OS_REG_READ(ah, AR_RXDP);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1271

(void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1272

OS_REG_WRITE(ah, AR_RC, resetMask);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1277

rt = ath_hal_wait(ah, AR_RC, mask, resetMask);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1287

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1289

OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1290

if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1291

(void) OS_REG_READ(ah, AR_ISR_RAC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1295

AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1300

ar5212GetNoiseFloor(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1302

int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1309

getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1312

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1314

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1328

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1340

ar5212InitNfCalHistBuffer(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1342

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1390

ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1392

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1394

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1398

if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1399

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1408

nf = ar5212GetNoiseFloor(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1409

if (getNoiseFloorThresh(ah, chan, &nfThresh)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

141

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1411

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

142

ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

144

OS_MARK(ah, AH_MARK_RESET, bChannelChange);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1447

val = OS_REG_READ(ah, AR_PHY(25));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1450

OS_REG_WRITE(ah, AR_PHY(25), val);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1451

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1452

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1453

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1455

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1457

ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1458

__func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1468

OS_REG_WRITE(ah, AR_PHY(25), val);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1469

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

147

if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1470

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1471

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

148

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1480

ar5212SetCompRegs(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1482

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1486

if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1489

OS_REG_WRITE(ah, AR_DCCFG, 1);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1491

OS_REG_WRITE(ah, AR_CCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1494

OS_REG_WRITE(ah, AR_CCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1495

OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1496

OS_REG_WRITE(ah, AR_CCUCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1499

OS_REG_WRITE(ah, AR_CPCOVF, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1503

OS_REG_WRITE(ah, AR_DCM_A, i);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1504

OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1509

ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1514

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1515

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1519

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1531

if (IS_2425(ah) || IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1538

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

156

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1568

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1573

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1575

OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1579

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1581

OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1587

OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1588

OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1596

ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1598

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1600

((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1611

ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1618

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1619

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1622

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1627

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1633

if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1634

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1646

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1652

AR_PHY_BIS(ah, 68, 0xFFFFFC06,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1655

ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1658

OS_REG_WRITE(ah, AR_PHY(90),

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

166

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1676

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1678

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1680

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1682

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1684

OS_REG_WRITE(ah, AR_PHY(13),

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1689

AR_PHY_BIS(ah, 10, 0xFFFF00FF,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1691

AR_PHY_BIS(ah, 25, 0xFFF80FFF,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1702

if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1706

if (ar5212IsSpurChannel(ah, chan))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1709

AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

171

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1720

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1722

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1724

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1729

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

173

SAVE_CCK(ah, chan, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1734

OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1749

ar5212SetSpurMitigation(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1760

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1764

if (IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1765

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1787

spurChan = ath_hal_getSpurChan(ah, i, is2GHz);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1804

if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1806

OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1807

val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1811

OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1812

OS_REG_WRITE(ah, AR_PHY_TIMING11, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1815

OS_REG_WRITE(ah, AR_PHY_TIMING7, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1816

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1817

OS_REG_WRITE(ah, AR_PHY_TIMING9, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1818

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1821

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1822

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1823

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1824

OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1825

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1826

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1827

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1828

OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1867

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1894

OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1895

val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1899

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1900

OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC |

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1905

OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1906

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1907

OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1908

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1911

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1912

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1913

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1914

OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1915

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1916

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1917

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1918

OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1928

ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1932

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

197

saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1971

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1973

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1986

ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1989

struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1993

SAVE_CCK(ah, &dummy, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1994

AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

1995

return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2003

ar5212SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2011

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2012

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2013

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2017

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

202

ath_hal_survey_clear(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2022

powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2024

tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2027

if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2029

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2033

if (!ahp->ah_rfHal->setPowerTable(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2035

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2044

if (!IS_2413(ah) && !IS_5413(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2061

if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2072

ar5212CorrectGainDelta(ah, cckOfdmPwrDelta);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2079

OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i),

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2087

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2093

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2101

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2107

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

211

if (IS_2413(ah) || IS_5413(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2118

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER |

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2132

ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2136

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2137

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2138

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2151

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2158

cfgCtl = ath_hal_getctl(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2206

ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2208

ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2211

ath_hal_getantennareduction(ah, chan, twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2216

ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2219

ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

222

(AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

223

(chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2236

&& AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

225

(AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

226

if (ar5212ChannelChange(ah, chan)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2290

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2301

ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2335

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2344

AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2350

ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2352

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2363

if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2368

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

237

saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2379

powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2381

tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2384

if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2386

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2394

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2415

ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2418

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2419

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

242

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2425

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

246

saveLedState = OS_REG_READ(ah, AR_PCICFG) &

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

249

softLedCfg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

250

softLedState = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

252

ar5212RestoreClock(ah, opmode); /* move to refclk operation */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2566

ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2570

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

258

(void) ar5212GetRfgain(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

260

if (!ar5212ChipReset(ah, chan)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

261

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2715

ar5212SetRateDurationTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2723

rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2725

rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2727

rt = ar5212GetRateTable(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2732

OS_REG_WRITE(ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2734

ath_hal_computetxtime(ah, rt,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2739

rt = ar5212GetRateTable(ah, HAL_MODE_11G);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2746

OS_REG_WRITE(ah, reg,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2747

ath_hal_computetxtime(ah, rt,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

275

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2754

OS_REG_WRITE(ah, reg,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2755

ath_hal_computetxtime(ah, rt,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2769

ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2776

refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2793

OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2794

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2795

OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2796

OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

287

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

294

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

297

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

299

regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

300

regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

308

OS_REG_WRITE(ah, AR_RXCFG, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

310

ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

312

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

315

ar5212SetIFSTiming(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

316

if (IS_5413(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

321

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

327

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

329

OS_REG_WRITE(ah, AR_PHY_ADC_CTL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

346

OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

352

OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

356

OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

358

OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

362

OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

365

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

367

OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

369

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

372

OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

374

OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

379

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

381

if (IS_5413(ah) || IS_2417(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

386

if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

387

OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

391

if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

392

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

398

if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

399

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

406

if (IS_5413(ah) ||

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

407

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

408

ar5212SetSpurMitigation(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

409

ar5212SetDeltaSlope(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

413

if (!ar5212SetBoardValues(ah, chan)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

414

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

421

OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

423

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

425

OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

426

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

431

ar5212SetOperatingMode(ah, opmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

434

OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

435

OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

438

OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

441

OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

442

OS_REG_WRITE(ah, AR_GPIODO, softLedState);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

445

OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

448

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

449

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

453

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

455

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

457

if (!ar5212SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

46

HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

460

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

462

ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

464

ar5212SetRateDurationTable(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

467

if (IS_RAD5112_ANY(ah) &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

473

OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

498

synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

506

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

527

testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

529

OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

532

(OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

533

OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

536

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

537

OS_REG_READ(ah, AR_PHY_AGC_CONTROL)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

543

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

546

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

553

ar5212SetCompRegs(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

557

OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

560

for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

561

ar5212ResetTxQueue(ah, i);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

575

OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

577

OS_REG_WRITE(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

578

OS_REG_READ(ah, AR_IMR_S2)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

581

if (AH_PRIVATE(ah)->ah_rfkillEnabled)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

582

ar5212EnableRfKill(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

584

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

585

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

594

ar5212SetupClock(ah, opmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

602

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

603

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

608

if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

609

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

610

AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

611

OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

612

OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

616

OS_REG_WRITE(ah, AR_NOACK,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

623

ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

625

ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

628

ath_hal_getantennareduction(ah, chan, twiceAntennaGain);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

667

OS_REG_WRITE(ah, AR_TPC, powerVal);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

671

OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

673

ar5212SetSifsTime(ah, ahp->ah_sifstime);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

675

ar5212SetSlotTime(ah, ahp->ah_slottime);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

677

ar5212SetAckTimeout(ah, ahp->ah_acktimeout);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

679

ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

680

if (AH_PRIVATE(ah)->ah_diagreg != 0)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

681

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

683

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

690

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

692

RESTORE_CCK(ah, chan, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

694

OS_MARK(ah, AH_MARK_RESET_DONE, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

698

RESTORE_CCK(ah, chan, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

700

OS_MARK(ah, AH_MARK_RESET_DONE, ecode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

712

ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

714

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

717

if (!ahp->ah_rfHal->setChannel(ah, chan))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

72

write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

729

ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

740

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

743

for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

744

if (ar5212NumTxPending(ah, qnum)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

753

OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

755

if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

763

if (!ar5212SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

770

data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

779

if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

780

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

787

if (IS_5413(ah) ||

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

788

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

789

ar5212SetSpurMitigation(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

790

ar5212SetDeltaSlope(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

794

OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

797

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

802

ar5212SetOperatingMode(struct ath_hal *ah, int opmode)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

806

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

810

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

812

OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

815

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

817

OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

821

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

833

ar5212PhyDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

835

return ar5212SetResetReg(ah, AR_RC_BB);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

842

ar5212Disable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

844

if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

850

return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

861

ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

864

OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

87

OS_REG_WRITE(ah, reg, V(r, 1));

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

870

if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

874

if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

878

if (!ar5212SetResetReg(ah, 0))

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

894

if (IS_5413(ah)) { /* NB: =>'s 5424 also */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

905

} else if (IS_RAD5111(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

938

curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

947

OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

948

OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

950

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

956

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

960

OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

961

OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

972

ar5212PerCalibrationN(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

977

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

984

OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

986

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

988

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

993

SAVE_CCK(ah, chan, isBmode);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

123

ar5212InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

128

if (IS_RAD5112_ANY(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

129

mixOvr = ar5212GetRfField(ar5212GetRfBank(ah, 7), 1, 36, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

140

gStep = ar5212GetRfField(ar5212GetRfBank(ah, 7), 6, 37, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

160

ar5212RequestRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

162

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

167

OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

179

ar5212IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

188

ar5212AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

192

if (IS_RAD5112_ANY(ah))

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

199

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Max gain limit.\n",

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

203

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

212

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

218

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

222

HALDEBUG(ah, HAL_DEBUG_RFPARAM,

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

232

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

243

ar5212GetGainFCorrection(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

245

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

248

HALASSERT(IS_RADX112_REV2(ah));

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

251

if (ar5212GetRfField(ar5212GetRfBank(ah, 7), 1, 36, 0) == 1) {

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

255

ar5212GetRfField(ar5212GetRfBank(ah, 7), 4, 32, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

279

ar5212GetRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

281

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

291

rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

298

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

300

HALASSERT(IS_RAD5112_ANY(ah));

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

301

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

302

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

307

if (IS_RADX112_REV2(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

308

uint32_t correct = ar5212GetGainFCorrection(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

317

if (!ar5212InvalidGainReadback(ah, gv) &&

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

318

ar5212IsGainAdjustNeeded(ah, gv) &&

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

319

ar5212AdjustGain(ah, gv) > 0) {

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

64

ar5212InitializeGainValues(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

66

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c

70

if (IS_RAD5112_ANY(ah)) {

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

103

ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

105

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

106

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

109

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

113

return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

120

ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

123

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

125

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

153

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

163

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

169

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

174

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

178

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

194

(void) ar5212SetTxQueueProps(ah, q, qInfo);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

204

setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

206

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

208

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

214

OS_REG_WRITE(ah, AR_IMR_S0,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

218

OS_REG_WRITE(ah, AR_IMR_S1,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

222

OS_REG_RMW_FIELD(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

230

ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

232

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

233

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

237

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

243

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

248

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

256

setTxQInterrupts(ah, qi);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

268

ar5212ResetTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

270

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

271

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

272

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

277

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

283

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

288

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

306

OS_REG_WRITE(ah, AR_DLCL_IFS(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

312

OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

327

if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

334

OS_REG_WRITE(ah, AR_QCBRCFG(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

342

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

347

OS_REG_WRITE(ah, AR_DCHNTIME(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

414

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

416

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

432

- (ah->ah_config.ah_sw_beacon_response_time -

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

433

+ ah->ah_config.ah_dma_beacon_response_time)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

434

- ah->ah_config.ah_additional_swba_backoff;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

441

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

444

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

455

OS_REG_WRITE(ah, AR_QMISC(q), qmisc);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

456

OS_REG_WRITE(ah, AR_DMISC(q), dmisc);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

46

ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

466

OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

467

OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

468

OS_REG_WRITE(ah, AR_Q_CBC, HAL_COMP_BUF_MAX_SIZE/1024);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

469

OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

470

OS_REG_READ(ah, AR_Q0_MISC + 4*q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

48

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

504

setTxQInterrupts(ah, qi);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

514

ar5212GetTxDP(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

516

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

517

return OS_REG_READ(ah, AR_QTXDP(q));

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

524

ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

526

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

527

HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

533

HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

535

OS_REG_WRITE(ah, AR_QTXDP(q), txdp);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

544

ar5212StartTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

546

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

548

HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

550

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

553

HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

555

OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

564

ar5212NumTxPending(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

568

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

569

HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

571

npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

578

if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

58

omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

588

ar5212StopTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

593

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

595

HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

597

OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

599

if (ar5212NumTxPending(ah, q) == 0)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

60

txcfg = OS_REG_READ(ah, AR_TXCFG);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

605

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

607

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

609

OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

610

OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

611

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

613

__func__, OS_REG_READ(ah, AR_QMISC(q)),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

614

OS_REG_READ(ah, AR_QRDYTIMECFG(q)),

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

615

OS_REG_READ(ah, AR_Q_RDYTIMESHDN));

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

620

if (ar5212NumTxPending(ah, q) &&

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

621

(IS_2413(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))) {

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

624

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

626

__func__, ar5212NumTxPending(ah, q), q);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

631

tsfLow = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

632

OS_REG_WRITE(ah, AR_QUIET2, SM(100, AR_QUIET2_QUIET_PER) |

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

634

OS_REG_WRITE(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE |

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

636

if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) {

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

639

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

645

OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

649

OS_REG_CLR_BIT(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

655

while (ar5212NumTxPending(ah, q)) {

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

657

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

665

OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

668

OS_REG_WRITE(ah, AR_Q_TXD, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

688

ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

70

OS_REG_WRITE(ah, AR_TXCFG,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

705

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

743

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

76

ath_hal_setInterrupts(ah, omask);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

760

ar5212SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

792

ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

804

ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

86

ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

876

ar5212ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

88

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

89

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

92

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

951

ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

953

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

96

return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

962

ar5212GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

980

ar5212SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

988

ar5212GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)

sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c

996

ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)

sys/dev/ath/ath_hal/ar5212/ar5413.c

107

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5212/ar5413.c

110

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5413.c

113

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5212/ar5413.c

134

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",

sys/dev/ath/ath_hal/ar5212/ar5413.c

141

OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);

sys/dev/ath/ath_hal/ar5212/ar5413.c

144

OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);

sys/dev/ath/ath_hal/ar5212/ar5413.c

146

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5212/ar5413.c

157

ar5413SetRfRegs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5413.c

166

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

167

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5413.c

168

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5413.c

171

struct ar5413State *priv = AR5413(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

174

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",

sys/dev/ath/ath_hal/ar5212/ar5413.c

208

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5413.c

235

if (AH_PRIVATE(ah)->ah_ispcie) {

sys/dev/ath/ath_hal/ar5212/ar5413.c

248

HAL_INI_WRITE_BANK(ah, ar5212Bank1_5413, priv->Bank1Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5413.c

249

HAL_INI_WRITE_BANK(ah, ar5212Bank2_5413, priv->Bank2Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5413.c

250

HAL_INI_WRITE_BANK(ah, ar5212Bank3_5413, priv->Bank3Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5413.c

251

HAL_INI_WRITE_BANK(ah, ar5212Bank6_5413, priv->Bank6Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5413.c

252

HAL_INI_WRITE_BANK(ah, ar5212Bank7_5413, priv->Bank7Data, regWrites);

sys/dev/ath/ath_hal/ar5212/ar5413.c

265

ar5413GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5212/ar5413.c

267

struct ar5413State *priv = AR5413(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

277

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5212/ar5413.c

394

ar5413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

sys/dev/ath/ath_hal/ar5212/ar5413.c

400

struct ar5413State *priv = AR5413(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

474

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5413.c

539

ar5413SetPowerTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5413.c

544

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

545

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5413.c

546

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5413.c

558

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",

sys/dev/ath/ath_hal/ar5212/ar5413.c

570

pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar5212/ar5413.c

573

numPdGainsUsed = ar5413getGainBoundariesAndPdadcsForPowers(ah,

sys/dev/ath/ath_hal/ar5212/ar5413.c

58

#define AR5413(ah) ((struct ar5413State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5212/ar5413.c

585

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar5212/ar5413.c

588

tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);

sys/dev/ath/ath_hal/ar5212/ar5413.c

606

if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))

sys/dev/ath/ath_hal/ar5212/ar5413.c

607

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "

sys/dev/ath/ath_hal/ar5212/ar5413.c

609

__func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar5413.c

611

OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);

sys/dev/ath/ath_hal/ar5212/ar5413.c

631

OS_REG_WRITE(ah, regoffset, reg32);

sys/dev/ath/ath_hal/ar5212/ar5413.c

635

OS_REG_WRITE(ah, AR_PHY_TPCRG5,

sys/dev/ath/ath_hal/ar5212/ar5413.c

64

ar5413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5212/ar5413.c

646

ar5413GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar5413.c

664

ar5413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

sys/dev/ath/ath_hal/ar5212/ar5413.c

67

HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5413, modesIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5413.c

68

HAL_INI_WRITE_ARRAY(ah, ar5212Common_5413, 1, writes);

sys/dev/ath/ath_hal/ar5212/ar5413.c

681

ar5413GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5212/ar5413.c

686

const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5212/ar5413.c

69

HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5413, freqIndex, writes);

sys/dev/ath/ath_hal/ar5212/ar5413.c

715

*maxPow = ar5413GetMaxPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

716

*minPow = ar5413GetMinPower(ah, &data[0]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

719

*maxPow = ar5413GetMaxPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

720

*minPow = ar5413GetMinPower(ah, &data[numChannels - 1]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

730

totalF = ar5413GetMaxPower(ah, &data[i]) - ar5413GetMaxPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

732

ar5413GetMaxPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar5413.c

733

totalMin = ar5413GetMinPower(ah, &data[i]) - ar5413GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

735

ar5413GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5212/ar5413.c

739

*maxPow = ar5413GetMaxPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

740

*minPow = ar5413GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5212/ar5413.c

751

ar5413RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5413.c

753

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

765

ar5413RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5212/ar5413.c

767

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

770

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5212/ar5413.c

775

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5212/ar5413.c

78

ar5413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5212/ar5413.c

797

ar5413Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5212/ar5413.c

799

return IS_5413(ah);

sys/dev/ath/ath_hal/ar5212/ar5413.c

80

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5212/ar5413.c

86

OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

sys/dev/ath/ath_hal/ar5212/ar5413.c

98

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312.h

32

#define IS_5312_2_X(ah) \

sys/dev/ath/ath_hal/ar5312/ar5312.h

33

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && \

sys/dev/ath/ath_hal/ar5312/ar5312.h

34

(AH_PRIVATE(ah)->ah_macRev == 2 || AH_PRIVATE(ah)->ah_macRev == 7))

sys/dev/ath/ath_hal/ar5312/ar5312.h

35

#define IS_5315(ah) \

sys/dev/ath/ath_hal/ar5312/ar5312.h

36

(AH_PRIVATE(ah)->ah_devid == AR5212_AR2315_REV6 || \

sys/dev/ath/ath_hal/ar5312/ar5312.h

37

AH_PRIVATE(ah)->ah_devid == AR5212_AR2315_REV7 || \

sys/dev/ath/ath_hal/ar5312/ar5312.h

38

AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1 || \

sys/dev/ath/ath_hal/ar5312/ar5312.h

39

AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)

sys/dev/ath/ath_hal/ar5312/ar5312.h

41

extern HAL_BOOL ar5312IsInterruptPending(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

48

extern uint32_t ar5312GpioGet(struct ath_hal *ah, uint32_t gpio);

sys/dev/ath/ath_hal/ar5312/ar5312.h

49

extern void ar5312GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);

sys/dev/ath/ath_hal/ar5312/ar5312.h

56

extern uint32_t ar5315GpioGet(struct ath_hal *ah, uint32_t gpio);

sys/dev/ath/ath_hal/ar5312/ar5312.h

57

extern void ar5315GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);

sys/dev/ath/ath_hal/ar5312/ar5312.h

59

extern void ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state);

sys/dev/ath/ath_hal/ar5312/ar5312.h

60

extern HAL_BOOL ar5312DetectCardPresent(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

61

extern void ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5312/ar5312.h

62

extern void ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5312/ar5312.h

63

extern void ar5312DumpState(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

64

extern HAL_BOOL ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5312/ar5312.h

69

extern HAL_BOOL ar5312ChipReset(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5312/ar5312.h

71

extern HAL_BOOL ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,

sys/dev/ath/ath_hal/ar5312/ar5312.h

73

extern HAL_BOOL ar5312PhyDisable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

74

extern HAL_BOOL ar5312Disable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

75

extern HAL_BOOL ar5312MacReset(struct ath_hal *ah, unsigned int RCMask);

sys/dev/ath/ath_hal/ar5312/ar5312.h

76

extern uint32_t ar5312GetPowerMode(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312.h

77

extern HAL_BOOL ar5312GetPowerStatus(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

102

if (IS_5315(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

118

ah->ah_gpioCfgInput = ahp->ah_priv.ah_gpioCfgInput;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

119

ah->ah_gpioCfgOutput = ahp->ah_priv.ah_gpioCfgOutput;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

120

ah->ah_gpioGet = ahp->ah_priv.ah_gpioGet;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

121

ah->ah_gpioSet = ahp->ah_priv.ah_gpioSet;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

122

ah->ah_gpioSetIntr = ahp->ah_priv.ah_gpioSetIntr;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

128

if (!ar5312ChipReset(ah, AH_NULL)) { /* reset chip */

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

129

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

139

val = ((OS_REG_READ(ah, (AR5315_RSTIMER_BASE -((uint32_t) sh)) + AR5315_WREV)) >> AR5315_WREV_S)

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

141

AH_PRIVATE(ah)->ah_macVersion = val >> AR5315_WREV_ID_S;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

142

AH_PRIVATE(ah)->ah_macRev = val & AR5315_WREV_REVISION;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

143

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

145

AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

149

val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0020);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

150

val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0080);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

152

val = ((OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + AR5312_WREV)) >> AR5312_WREV_S) & AR5312_WREV_ID;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

153

AH_PRIVATE(ah)->ah_macVersion = val >> AR5312_WREV_ID_S;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

154

AH_PRIVATE(ah)->ah_macRev = val & AR5312_WREV_REVISION;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

157

if (((AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

158

AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_VENICE) ||

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

159

AH_PRIVATE(ah)->ah_macRev < AR_SREV_D2PLUS) &&

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

160

AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_COBRA) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

162

ath_hal_printf(ah, "%s: Mac Chip Rev 0x%02x.%x is not supported by "

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

164

AH_PRIVATE(ah)->ah_macVersion,

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

165

AH_PRIVATE(ah)->ah_macRev);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

171

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

173

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

174

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

184

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

187

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

189

rf = ath_hal_rfprobe(ah, &ecode);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

192

if (IS_RAD5112(ah) && !IS_RADX112_REV2(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

194

ath_hal_printf(ah, "%s: 5112 Rev 1 is not supported by this "

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

196

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

202

ecode = ath_hal_legacyEepromAttach(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

210

if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

211

(AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

216

OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

218

AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

221

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

223

if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

225

ath_hal_printf(ah, "%s: 2G Radio Chip Rev 0x%02X is not "

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

227

AH_PRIVATE(ah)->ah_analog2GhzRev);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

234

ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

236

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

241

AH_PRIVATE(ah)->ah_currentRD = eeval;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

248

if (!ar5212FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

249

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

255

if (!rf->attach(ah, &ecode)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

256

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

261

AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

264

ar5212InitializeGainValues(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

267

if (!ar5312GetMacAddr(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

272

ar5312AniSetup(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

273

ar5212InitNfCalHistBuffer(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

276

return ah;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

287

ar5312GetMacAddr(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

289

const struct ar531x_boarddata *board = AR5312_BOARDCONFIG(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

290

int wlanNum = AR5312_UNIT(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

302

ath_hal_printf(ah, "Invalid WLAN wmac index (%d)\n",

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

307

OS_MEMCPY(AH5212(ah)->ah_macaddr, macAddr, 6);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

33

static HAL_BOOL ar5312GetMacAddr(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

36

ar5312AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

56

ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

68

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

86

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

89

ah->ah_reset = ar5312Reset;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

90

ah->ah_phyDisable = ar5312PhyDisable;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

91

ah->ah_setLedState = ar5312SetLedState;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

92

ah->ah_detectCardPresent = ar5312DetectCardPresent;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

93

ah->ah_setPowerMode = ar5312SetPowerMode;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

94

ah->ah_getPowerMode = ar5312GetPowerMode;

sys/dev/ath/ath_hal/ar5312/ar5312_attach.c

95

ah->ah_isInterruptPending = ar5312IsInterruptPending;

sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c

34

ar5312EepromRead(struct ath_hal *ah, u_int off, uint16_t *dataIn)

sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c

37

const char *eepromAddr = AR5312_RADIOCONFIG(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

108

ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

111

uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

114

val = OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

124

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, val);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

127

(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

38

ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

40

uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

44

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

45

(OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

55

ar5312GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

57

uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

61

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

62

(OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

72

ar5312GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

75

uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5312_GPIODO);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

91

ar5312GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

93

uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

96

uint32_t val = OS_REG_READ(ah, gpioOffset+AR5312_GPIODI);

sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c

37

ar5312IsInterruptPending(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

100

if (ar5212Use32KHzclock(ah, opmode)) {

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

106

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

107

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

108

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

109

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

110

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

111

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

112

IS_RAD5112_ANY(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

114

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

115

OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

118

OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

119

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

120

IS_RAD5112_ANY(ah) ? 39 : 31);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

122

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

123

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

125

if (IS_5312_2_X(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

127

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

129

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

130

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

131

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

132

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

133

IS_RAD5112_ANY(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

142

ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

144

if (ar5212Use32KHzclock(ah, opmode)) {

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

146

OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

147

OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

148

IS_RAD5112_ANY(ah) ? 39 : 31);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

153

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

154

OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

155

if (IS_5312_2_X(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

157

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

159

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

160

OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

161

OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

162

OS_REG_WRITE(ah, AR_PHY_REFCLKPD,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

163

IS_RAD5112_ANY(ah) ? 0x14 : 0x18);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

38

ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

41

uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

42

if(IS_2316(ah)) return; /* not yet */

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

46

OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

47

(OS_REG_READ(ah, AR5312_PCICFG) &~

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

57

ar5312DetectCardPresent(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

68

if(IS_5315(ah))

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

70

v = (OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

71

(AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

75

return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

76

AH_PRIVATE(ah)->ah_macRev == macRev);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

81

v = (OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

82

(AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

86

return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

87

AH_PRIVATE(ah)->ah_macRev == macRev);

sys/dev/ath/ath_hal/ar5312/ar5312_misc.c

98

ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

102

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

110

ar5312GetPowerMode(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

120

ar5312GetPowerStatus(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

40

ar5312SetPowerModeAwake(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

51

ar5312SetPowerModeSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

62

ar5312SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

72

ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

84

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

85

modes[ah->ah_powerMode], modes[mode],

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

89

status = ar5312SetPowerModeAwake(ah, setChip);

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

92

ar5312SetPowerModeSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

95

ar5312SetPowerModeNetworkSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5312/ar5312_power.c

98

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: unknown power mode %u\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

110

HALASSERT(ah->ah_magic == AR5212_MAGIC);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

111

ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

113

OS_MARK(ah, AH_MARK_RESET, bChannelChange);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

117

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

119

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

131

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

160

saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

165

if ((IS_2413(ah) || IS_5413(ah))) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

174

AH_PRIVATE(ah)->ah_curchan != AH_NULL &&

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

175

(chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

177

(AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

178

if (ar5212ChannelChange(ah, chan))

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

187

saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

192

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

196

if (!IS_5315(ah))

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

197

saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

201

ar5312RestoreClock(ah, opmode); /* move to refclk operation */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

207

(void) ar5212GetRfgain(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

209

if (!ar5312ChipReset(ah, chan)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

210

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

224

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

227

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

229

regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

230

regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

232

ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

234

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

237

ar5212SetIFSTiming(ah, chan);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

240

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

242

OS_REG_WRITE(ah, AR_PHY_ADC_CTL,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

256

OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

260

OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

264

OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

266

OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

270

OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

273

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

275

OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

277

if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

280

OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

282

OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

286

if (IS_5312_2_X(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

288

OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

295

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

299

OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

302

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

306

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

309

OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

313

if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

314

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

320

if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

321

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

328

if (IS_5413(ah) ||

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

329

AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

330

ar5212SetSpurMitigation(ah, chan);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

331

ar5212SetDeltaSlope(ah, chan);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

335

if (!ar5212SetBoardValues(ah, chan)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

336

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

343

OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

345

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

347

OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

348

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

353

ar5212SetOperatingMode(ah, opmode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

356

OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

357

OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

360

if (!IS_5315(ah))

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

361

OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

364

OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

367

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

368

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

371

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

373

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

375

if (!ar5212SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

378

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

380

ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

382

ar5212SetRateDurationTable(ah, chan);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

385

if (IS_RAD5112_ANY(ah) &&

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

391

OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

40

extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

413

if (IS_5312_2_X(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

414

(void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

422

synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

430

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

451

testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

453

OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

456

(OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

457

OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

460

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

461

OS_REG_READ(ah, AR_PHY_AGC_CONTROL)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

467

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

470

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

477

ar5212SetCompRegs(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

481

OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

484

for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

485

ar5212ResetTxQueue(ah, i);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

499

OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

501

OS_REG_WRITE(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

502

OS_REG_READ(ah, AR_IMR_S2)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

505

if (AH_PRIVATE(ah)->ah_rfkillEnabled)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

506

ar5212EnableRfKill(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

508

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

509

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

518

ar5312SetupClock(ah, opmode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

526

OS_REG_WRITE(ah, AR_BEACON,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

527

(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

532

if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

533

(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

534

AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

535

OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

536

OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

540

OS_REG_WRITE(ah, AR_NOACK,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

547

OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

549

ar5212SetSlotTime(ah, ahp->ah_slottime);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

551

ar5212SetAckTimeout(ah, ahp->ah_acktimeout);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

553

ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

555

ar5212SetSifsTime(ah, ahp->ah_sifstime);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

556

if (AH_PRIVATE(ah)->ah_diagreg != 0)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

557

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

559

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

56

write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

564

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

566

OS_MARK(ah, AH_MARK_RESET_DONE, 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

570

OS_MARK(ah, AH_MARK_RESET_DONE, ecode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

585

ar5312PhyDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

587

return ar5312SetResetReg(ah, AR_RC_BB);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

594

ar5312Disable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

596

if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

602

return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

613

ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

616

OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

621

if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

622

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

628

if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

629

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

635

if (!ar5312SetResetReg(ah, 0)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

636

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

654

if (IS_RAD5112_ANY(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

656

if (!IS_5315(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

701

curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

71

OS_REG_WRITE(ah, reg, V(i, 1));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

710

OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

711

OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

713

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

719

OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

723

OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

724

OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

734

ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

739

if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

753

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

755

OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

767

ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

769

int wlanNum = AR5312_UNIT(ah);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

776

if (IS_5315(ah)) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

794

reg = OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

795

(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

808

OS_REG_WRITE(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

809

(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

812

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

813

(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

819

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

820

(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

821

OS_REG_WRITE(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

822

(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

825

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

826

(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

849

reg = OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

850

(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

863

OS_REG_WRITE(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

864

(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

867

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

868

(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

874

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

875

(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

876

OS_REG_WRITE(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

877

(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

880

OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

881

(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

89

ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

97

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

108

ar5315GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

111

uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

114

val = OS_REG_READ(ah, gpioOffset+AR5315_GPIOINT);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

123

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIOINT, val);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

126

(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

38

ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

40

uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

44

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

45

(OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

55

ar5315GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

57

uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

61

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

62

(OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

72

ar5315GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

75

uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

91

ar5315GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

93

uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

96

uint32_t val = OS_REG_READ(ah, gpioOffset+AR5315_GPIODI);

sys/dev/ath/ath_hal/ar5416/ar2133.c

109

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Force rf_pwd_icsyndiv to %1d on %4d\n",

sys/dev/ath/ath_hal/ar5416/ar2133.c

116

ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6, priv->Bank6Data, reg_writes);

sys/dev/ath/ath_hal/ar5416/ar2133.c

125

ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar2133.c

134

OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);

sys/dev/ath/ath_hal/ar5416/ar2133.c

136

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar2133.c

149

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar2133.c

157

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar5416/ar2133.c

160

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

163

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

195

if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar2133.c

201

if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar2133.c

209

HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,

sys/dev/ath/ath_hal/ar5416/ar2133.c

216

if (AR_SREV_OWL(ah) && ah->ah_config.ah_ar5416_biasadj)

sys/dev/ath/ath_hal/ar5416/ar2133.c

217

ar2133ForceBias(ah, freq);

sys/dev/ath/ath_hal/ar5416/ar2133.c

222

OS_REG_WRITE(ah, AR_PHY(0x37), reg32);

sys/dev/ath/ath_hal/ar5416/ar2133.c

224

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar5416/ar2133.c

233

ar2133GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar5416/ar2133.c

235

struct ar2133State *priv = AR2133(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

245

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar5416/ar2133.c

257

ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar2133.c

260

struct ar2133State *priv = AR2133(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

266

ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);

sys/dev/ath/ath_hal/ar5416/ar2133.c

269

ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);

sys/dev/ath/ath_hal/ar5416/ar2133.c

272

ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);

sys/dev/ath/ath_hal/ar5416/ar2133.c

275

ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);

sys/dev/ath/ath_hal/ar5416/ar2133.c

278

ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);

sys/dev/ath/ath_hal/ar5416/ar2133.c

282

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 2ghz: OB_2:%d, DB_2:%d\n",

sys/dev/ath/ath_hal/ar5416/ar2133.c

284

ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL),

sys/dev/ath/ath_hal/ar5416/ar2133.c

285

ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL));

sys/dev/ath/ath_hal/ar5416/ar2133.c

287

ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);

sys/dev/ath/ath_hal/ar5416/ar2133.c

289

ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);

sys/dev/ath/ath_hal/ar5416/ar2133.c

291

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 5ghz: OB_5:%d, DB_5:%d\n",

sys/dev/ath/ath_hal/ar5416/ar2133.c

293

ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL),

sys/dev/ath/ath_hal/ar5416/ar2133.c

294

ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL));

sys/dev/ath/ath_hal/ar5416/ar2133.c

296

ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);

sys/dev/ath/ath_hal/ar5416/ar2133.c

298

ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);

sys/dev/ath/ath_hal/ar5416/ar2133.c

301

ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);

sys/dev/ath/ath_hal/ar5416/ar2133.c

304

writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,

sys/dev/ath/ath_hal/ar5416/ar2133.c

306

writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,

sys/dev/ath/ath_hal/ar5416/ar2133.c

308

writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,

sys/dev/ath/ath_hal/ar5416/ar2133.c

310

writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,

sys/dev/ath/ath_hal/ar5416/ar2133.c

312

writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,

sys/dev/ath/ath_hal/ar5416/ar2133.c

314

(void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,

sys/dev/ath/ath_hal/ar5416/ar2133.c

328

ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,

sys/dev/ath/ath_hal/ar5416/ar2133.c

336

ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)

sys/dev/ath/ath_hal/ar5416/ar2133.c

363

ar2133GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar2133.c

368

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

408

totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar5416/ar2133.c

409

*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar5416/ar2133.c

414

*minPow = ar2133GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar5416/ar2133.c

437

ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])

sys/dev/ath/ath_hal/ar5416/ar2133.c

439

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

45

#define AR2133(ah) ((struct ar2133State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar5416/ar2133.c

451

nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

454

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

458

nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

461

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

467

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

470

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

474

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

477

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

482

nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

485

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

489

nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar5416/ar2133.c

492

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar2133.c

505

ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar5416/ar2133.c

514

ar2133RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar2133.c

516

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

528

ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar5416/ar2133.c

53

ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar5416/ar2133.c

530

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar2133.c

534

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR2133 radio\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar2133.c

538

+ AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

539

+ AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

540

+ AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

541

+ AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

542

+ AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

543

+ AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t)

sys/dev/ath/ath_hal/ar5416/ar2133.c

546

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar2133.c

56

(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,

sys/dev/ath/ath_hal/ar5416/ar2133.c

561

priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

562

priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

563

priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

564

priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

565

priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

566

priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows;

sys/dev/ath/ath_hal/ar5416/ar2133.c

575

AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;

sys/dev/ath/ath_hal/ar5416/ar2133.c

576

AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor;

sys/dev/ath/ath_hal/ar5416/ar2133.c

582

ar2133Probe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar2133.c

584

return (AR_SREV_OWL(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah));

sys/dev/ath/ath_hal/ar5416/ar2133.c

88

ar2133ForceBias(struct ath_hal *ah, uint16_t synth_freq)

sys/dev/ath/ath_hal/ar5416/ar2133.c

93

struct ar2133State *priv = AR2133(ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

101

void (*ah_initPLL) (struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

105

void (*ah_btCoexSetDiversity)(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

162

#define IS_5416_PCI(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCI)

sys/dev/ath/ath_hal/ar5416/ar5416.h

163

#define IS_5416_PCIE(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCIE)

sys/dev/ath/ath_hal/ar5416/ar5416.h

165

#define IS_PCIE(ah) (IS_5416_PCIE(ah))

sys/dev/ath/ath_hal/ar5416/ar5416.h

171

extern uint32_t ar5416GetRadioRev(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

175

extern void ar5416Detach(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

176

extern void ar5416AttachPCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

177

extern HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

193

extern void ar5416BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

195

extern void ar5416ResetStaBeaconTimers(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

196

extern void ar5416SetStaBeaconTimers(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

201

extern void ar5416SetBTCoexInfo(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

203

extern void ar5416BTCoexConfig(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

205

extern void ar5416BTCoexAntennaDiversity(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

206

extern void ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum);

sys/dev/ath/ath_hal/ar5416/ar5416.h

207

extern void ar5416BTCoexSetWeights(struct ath_hal *ah, uint32_t stompType);

sys/dev/ath/ath_hal/ar5416/ar5416.h

208

extern void ar5416BTCoexSetupBmissThresh(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

210

extern void ar5416BTCoexSetParameter(struct ath_hal *ah, uint32_t type,

sys/dev/ath/ath_hal/ar5416/ar5416.h

212

extern void ar5416BTCoexDisable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

213

extern int ar5416BTCoexEnable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

214

extern void ar5416InitBTCoex(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

219

extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

221

extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints);

sys/dev/ath/ath_hal/ar5416/ar5416.h

227

extern uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio);

sys/dev/ath/ath_hal/ar5416/ar5416.h

228

extern void ar5416GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);

sys/dev/ath/ath_hal/ar5416/ar5416.h

230

extern u_int ar5416GetWirelessModes(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

231

extern void ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state);

sys/dev/ath/ath_hal/ar5416/ar5416.h

232

extern uint64_t ar5416GetTsf64(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

233

extern void ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64);

sys/dev/ath/ath_hal/ar5416/ar5416.h

234

extern void ar5416ResetTsf(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

235

extern uint32_t ar5416GetCurRssi(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

239

extern HAL_BOOL ar5416GetMibCycleCounts(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

241

extern void ar5416SetChainMasks(struct ath_hal *ah, uint32_t, uint32_t);

sys/dev/ath/ath_hal/ar5416/ar5416.h

242

extern uint32_t ar5416Get11nExtBusy(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

243

extern void ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode);

sys/dev/ath/ath_hal/ar5416/ar5416.h

244

extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

245

extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear);

sys/dev/ath/ath_hal/ar5416/ar5416.h

246

extern HAL_STATUS ar5416SetQuiet(struct ath_hal *ah, uint32_t period,

sys/dev/ath/ath_hal/ar5416/ar5416.h

248

extern HAL_STATUS ar5416GetCapability(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

250

extern HAL_BOOL ar5416SetCapability(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

253

extern HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5416/ar5416.h

256

extern HAL_BOOL ar5416SetRifsDelay(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

259

extern void ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);

sys/dev/ath/ath_hal/ar5416/ar5416.h

260

extern HAL_BOOL ar5416GetDfsDefaultThresh(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

262

extern void ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);

sys/dev/ath/ath_hal/ar5416/ar5416.h

263

extern HAL_BOOL ar5416ProcessRadarEvent(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

266

extern HAL_BOOL ar5416IsFastClockEnabled(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

269

extern void ar5416ConfigureSpectralScan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss);

sys/dev/ath/ath_hal/ar5416/ar5416.h

270

extern void ar5416GetSpectralParams(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss);

sys/dev/ath/ath_hal/ar5416/ar5416.h

271

extern HAL_BOOL ar5416IsSpectralActive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

272

extern HAL_BOOL ar5416IsSpectralEnabled(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

273

extern void ar5416StartSpectralScan(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

274

extern void ar5416StopSpectralScan(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

275

extern uint32_t ar5416GetSpectralConfig(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

276

extern void ar5416RestoreSpectralConfig(struct ath_hal *ah, uint32_t restoreval);

sys/dev/ath/ath_hal/ar5416/ar5416.h

278

extern HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,

sys/dev/ath/ath_hal/ar5416/ar5416.h

280

extern HAL_POWER_MODE ar5416GetPowerMode(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

281

extern HAL_BOOL ar5416GetPowerStatus(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

283

extern HAL_BOOL ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);

sys/dev/ath/ath_hal/ar5416/ar5416.h

284

extern HAL_BOOL ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5416/ar5416.h

287

extern uint32_t ar5416GetRxFilter(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

288

extern void ar5416SetRxFilter(struct ath_hal *ah, uint32_t bits);

sys/dev/ath/ath_hal/ar5416/ar5416.h

289

extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

290

extern void ar5416StartPcuReceive(struct ath_hal *ah, HAL_BOOL);

sys/dev/ath/ath_hal/ar5416/ar5416.h

291

extern void ar5416StopPcuReceive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

294

extern HAL_STATUS ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *,

sys/dev/ath/ath_hal/ar5416/ar5416.h

298

extern HAL_BOOL ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5416/ar5416.h

303

extern HAL_BOOL ar5416PhyDisable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

304

extern HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

305

extern HAL_BOOL ar5416Disable(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

306

extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

309

extern int ar5416GetRegChainOffset(struct ath_hal *ah, int i);

sys/dev/ath/ath_hal/ar5416/ar5416.h

313

extern HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);

sys/dev/ath/ath_hal/ar5416/ar5416.h

316

extern HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

320

extern void ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

329

extern void ar5416GetTargetPowers(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

334

extern void ar5416GetTargetPowersLeg(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

339

extern void ar5416InitChainMasks(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

340

extern void ar5416RestoreChainMask(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

341

extern void ar5416EepromSetAddac(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

345

extern void ar5416InitPLL(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

349

extern void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

355

extern void ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

358

extern uint16_t ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask,

sys/dev/ath/ath_hal/ar5416/ar5416.h

360

extern void ar5416WriteDetectorGainBiases(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

362

extern void ar5416WritePdadcValues(struct ath_hal *ah, int i,

sys/dev/ath/ath_hal/ar5416/ar5416.h

364

extern HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

367

extern void ar5416WriteTxPowerRateRegisters(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

370

extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5416/ar5416.h

371

extern HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

381

extern HAL_BOOL ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

385

extern HAL_STATUS ar5416ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

387

extern HAL_BOOL ar5416GetTxCompletionRates(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

390

extern HAL_BOOL ar5416ResetTxQueue(struct ath_hal *ah, u_int q);

sys/dev/ath/ath_hal/ar5416/ar5416.h

391

extern int ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5416/ar5416.h

394

extern HAL_BOOL ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

399

extern HAL_BOOL ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

402

extern HAL_BOOL ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

404

extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu);

sys/dev/ath/ath_hal/ar5416/ar5416.h

405

extern u_int ar5416GetGlobalTxTimeout(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416.h

406

extern void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

410

extern void ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416.h

412

extern void ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims);

sys/dev/ath/ath_hal/ar5416/ar5416.h

413

extern void ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds);

sys/dev/ath/ath_hal/ar5416/ar5416.h

414

extern void ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds);

sys/dev/ath/ath_hal/ar5416/ar5416.h

415

extern void ar5416Set11nVirtualMoreFrag(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416.h

418

extern void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration);

sys/dev/ath/ath_hal/ar5416/ar5416.h

95

HAL_BOOL (*ah_setPowerCalTable) (struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

101

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

102

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

106

setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

109

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

116

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

131

ar5416AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

134

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

138

setPhyErrBase(ah, &ahp->ah_aniParams24);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

142

setPhyErrBase(ah, &ahp->ah_aniParams5);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

147

enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

163

ar5416AniDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

165

HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

166

disableAniMIBCounters(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

173

ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

176

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

187

OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

197

ar5416AniDetach(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

206

enableAniMIBCounters(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

217

if (((1 << cmd) & AH5416(ah)->ah_ani_function) == 0) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

218

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: command %d disabled\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

220

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: cmd %d; mask %x\n", __func__, cmd, AH5416(ah)->ah_ani_function);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

228

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_NOISE_IMMUNITY_LEVEL: set level = %d\n", __func__, level);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

230

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

236

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

238

OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

240

OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

242

OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

261

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: %s\n", __func__, on ? "enabled" : "disabled");

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

262

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

264

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

266

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

268

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

270

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

272

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

275

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

277

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

279

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

281

OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

285

OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

288

OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

302

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_CCK_WEAK_SIGNAL_THR: %s\n", __func__, high ? "high" : "low");

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

303

OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

315

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_FIRSTEP_LEVEL: level = %d\n", __func__, level);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

317

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

322

OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

334

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_SPUR_IMMUNITY_LEVEL: level = %d\n", __func__, level);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

336

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

341

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

358

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: invalid cmd %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

366

ar5416AniOfdmErrTrigger(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

368

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

369

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

375

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

382

if (ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

388

if (ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

398

if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

400

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

405

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

413

ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

416

ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

425

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

435

ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

439

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

450

ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

454

if (ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

463

ar5416AniCckErrTrigger(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

465

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

466

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

472

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

478

if ((AH5416(ah)->ah_ani_function & (1 << HAL_ANI_NOISE_IMMUNITY_LEVEL) &&

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

480

ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

485

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

493

ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

502

ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

510

ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

512

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

520

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

523

OS_REG_WRITE(ah, AR_PHY_ERR_1, params->ofdmPhyErrBase);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

524

OS_REG_WRITE(ah, AR_PHY_ERR_2, params->cckPhyErrBase);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

525

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

526

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

529

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

542

ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

545

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

546

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

562

ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

566

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

570

OS_MARK(ah, AH_MARK_ANI_RESET, opmode);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

575

rxfilter = ah->ah_getRxFilter(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

576

ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

583

if (! ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

584

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

594

AH5416(ah)->ah_ani_function =

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

597

AH5416(ah)->ah_ani_function = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

614

ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

616

ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

618

ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

620

ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

622

ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

625

ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

626

ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

627

ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

629

ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

63

#define ANI_ENA(ah) \

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

630

ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

637

enableAniMIBCounters(ah, aniState->params);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

638

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

64

(AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

642

ah->ah_setRxFilter(ah, rxfilter);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

65

#define ANI_ENA_RSSI(ah) \

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

651

ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

653

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

656

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

658

__func__, OS_REG_READ(ah, AR_MIBC),

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

659

OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

66

(AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

660

OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

672

phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

673

phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

675

OS_REG_WRITE(ah, AR_FILTOFDM, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

676

OS_REG_WRITE(ah, AR_FILTCCK, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

677

if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

678

OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

681

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

71

enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

713

ar5416AniOfdmErrTrigger(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

715

ar5416AniCckErrTrigger(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

717

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

722

ar5416AniLowerImmunity(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

724

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

728

HALASSERT(ANI_ENA(ah));

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

73

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

738

if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

740

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

745

if (ANI_ENA_RSSI(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

75

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

759

if (ar5416AniControl(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

765

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

774

if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

782

if (ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

79

OS_REG_WRITE(ah, AR_FILTOFDM, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

791

if (ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

80

OS_REG_WRITE(ah, AR_FILTCCK, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

813

ar5416AniGetListenTime(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

815

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

82

OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

824

if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

825

ath_hal_printf(ah, "%s: ah_curchan = NULL?\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

83

OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

834

good = ar5416GetMibCycleCounts(ah, &hs);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

835

ath_hal_survey_add_sample(ah, &hs);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

837

if (ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

84

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

848

} else if (ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

85

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

854

AH5416(ah)->ah_cycleCount - aniState->cycleCount;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

856

AH5416(ah)->ah_rxBusy - aniState->rxFrameCount;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

858

AH5416(ah)->ah_txBusy - aniState->txFrameCount;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

865

if (ANI_ENA(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

866

aniState->cycleCount = AH5416(ah)->ah_cycleCount;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

867

aniState->rxFrameCount = AH5416(ah)->ah_rxBusy;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

868

aniState->txFrameCount = AH5416(ah)->ah_txBusy;

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

87

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

878

updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

88

ar5212EnableMibCounters(ah); /* enable everything */

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

880

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

886

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

889

phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

890

phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

895

HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

905

HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

915

ar5416RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

918

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

92

disableAniMIBCounters(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

927

ar5416AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

929

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

935

listenTime = ar5416AniGetListenTime(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

94

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

941

if (!ANI_ENA(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

947

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: invalid listenTime\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

949

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

957

OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

96

HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

965

updateMIBStats(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

970

ar5416AniLowerImmunity(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

971

HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower immunity\n",

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

973

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

975

updateMIBStats(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

979

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

98

ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

982

ar5416AniOfdmErrTrigger(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

983

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

986

HALDEBUG(ah, HAL_DEBUG_ANI,

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

989

ar5416AniCckErrTrigger(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

99

ar5212DisableMibCounters(ah); /* disable everything */

sys/dev/ath/ath_hal/ar5416/ar5416_ani.c

990

ar5416AniRestart(ah, aniState);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

100

ah->ah_reset = ar5416Reset;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

1000

pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

101

ah->ah_phyDisable = ar5416PhyDisable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

102

ah->ah_disable = ar5416Disable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

1026

if (AR_SREV_OWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

1029

if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

103

ah->ah_configPCIE = ar5416ConfigPCIE;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

1030

ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

104

ah->ah_disablePCIE = ar5416DisablePCIE;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

105

ah->ah_perCalibration = ar5416PerCalibration;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

1051

if (! AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

106

ah->ah_perCalibrationN = ar5416PerCalibrationN;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

107

ah->ah_resetCalValid = ar5416ResetCalValid;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

108

ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

109

ah->ah_setTxPower = ar5416SetTransmitPower;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

110

ah->ah_setBoardValues = ar5416SetBoardValues;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

113

ah->ah_stopTxDma = ar5416StopTxDma;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

114

ah->ah_setupTxDesc = ar5416SetupTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

115

ah->ah_setupXTxDesc = ar5416SetupXTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

116

ah->ah_fillTxDesc = ar5416FillTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

117

ah->ah_procTxDesc = ar5416ProcTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

118

ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

119

ah->ah_setupTxQueue = ar5416SetupTxQueue;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

120

ah->ah_resetTxQueue = ar5416ResetTxQueue;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

123

ah->ah_getRxFilter = ar5416GetRxFilter;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

124

ah->ah_setRxFilter = ar5416SetRxFilter;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

125

ah->ah_stopDmaReceive = ar5416StopDmaReceive;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

126

ah->ah_startPcuReceive = ar5416StartPcuReceive;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

127

ah->ah_stopPcuReceive = ar5416StopPcuReceive;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

128

ah->ah_setupRxDesc = ar5416SetupRxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

129

ah->ah_procRxDesc = ar5416ProcRxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

130

ah->ah_rxMonitor = ar5416RxMonitor;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

131

ah->ah_aniPoll = ar5416AniPoll;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

132

ah->ah_procMibEvent = ar5416ProcessMibIntr;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

135

ah->ah_getCapability = ar5416GetCapability;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

136

ah->ah_setCapability = ar5416SetCapability;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

137

ah->ah_getDiagState = ar5416GetDiagState;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

138

ah->ah_setLedState = ar5416SetLedState;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

139

ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

140

ah->ah_gpioCfgInput = ar5416GpioCfgInput;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

141

ah->ah_gpioGet = ar5416GpioGet;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

142

ah->ah_gpioSet = ar5416GpioSet;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

143

ah->ah_gpioSetIntr = ar5416GpioSetIntr;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

144

ah->ah_getTsf64 = ar5416GetTsf64;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

145

ah->ah_setTsf64 = ar5416SetTsf64;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

146

ah->ah_resetTsf = ar5416ResetTsf;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

147

ah->ah_getRfGain = ar5416GetRfgain;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

148

ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

149

ah->ah_setDecompMask = ar5416SetDecompMask;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

150

ah->ah_setCoverageClass = ar5416SetCoverageClass;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

151

ah->ah_setQuiet = ar5416SetQuiet;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

152

ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

153

ah->ah_setChainMasks = ar5416SetChainMasks;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

155

ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

156

ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

159

ah->ah_enableDfs = ar5416EnableDfs;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

160

ah->ah_getDfsThresh = ar5416GetDfsThresh;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

161

ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

162

ah->ah_procRadarEvent = ar5416ProcessRadarEvent;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

163

ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

166

ah->ah_spectralConfigure = ar5416ConfigureSpectralScan;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

167

ah->ah_spectralGetConfig = ar5416GetSpectralParams;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

168

ah->ah_spectralStart = ar5416StartSpectralScan;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

169

ah->ah_spectralStop = ar5416StopSpectralScan;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

170

ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

171

ah->ah_spectralIsActive = ar5416IsSpectralActive;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

174

ah->ah_setPowerMode = ar5416SetPowerMode;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

177

ah->ah_setBeaconTimers = ar5416SetBeaconTimers;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

178

ah->ah_beaconInit = ar5416BeaconInit;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

179

ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

180

ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

181

ah->ah_getNextTBTT = ar5416GetNextTBTT;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

184

ah->ah_chainTxDesc = ar5416ChainTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

185

ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

186

ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

187

ah->ah_set11nRateScenario = ar5416Set11nRateScenario;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

188

ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

189

ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

190

ah->ah_set11nAggrLast = ar5416Set11nAggrLast;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

191

ah->ah_clr11nAggr = ar5416Clr11nAggr;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

192

ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

193

ah->ah_get11nExtBusy = ar5416Get11nExtBusy;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

194

ah->ah_set11nMac2040 = ar5416Set11nMac2040;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

195

ah->ah_get11nRxClear = ar5416Get11nRxClear;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

196

ah->ah_set11nRxClear = ar5416Set11nRxClear;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

197

ah->ah_set11nVirtMoreFrag = ar5416Set11nVirtualMoreFrag;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

200

ah->ah_isInterruptPending = ar5416IsInterruptPending;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

201

ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

202

ah->ah_setInterrupts = ar5416SetInterrupts;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

205

ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

206

ah->ah_btCoexSetConfig = ar5416BTCoexConfig;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

207

ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

208

ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

209

ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

210

ah->ah_btCoexSetParameter = ar5416BTCoexSetParameter;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

211

ah->ah_btCoexDisable = ar5416BTCoexDisable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

212

ah->ah_btCoexEnable = ar5416BTCoexEnable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

213

AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

223

AH5416(ah)->ah_writeIni = ar5416WriteIni;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

224

AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

227

AH5416(ah)->ah_initPLL = ar5416InitPLL;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

230

AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

233

AH5416(ah)->ah_olcInit = ar5416olcInit;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

234

AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

235

AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

240

AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

241

AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

244

AH5416(ah)->ah_ani_function = 0xffffffff;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

247

AH5212(ah)->ah_aniControl = ar5416AniControl;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

266

if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

267

AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

268

AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

270

AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

271

AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

276

AH5212(ah)->ah_maxTxTrigLev -= 4;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

280

ar5416GetRadioRev(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

286

OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

288

OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

289

val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

304

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

325

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

327

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

329

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

33

static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

334

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

335

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

340

val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

341

AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

342

AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

343

AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

349

HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

35

static void ar5416DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

350

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

351

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

352

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

353

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

354

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

355

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

356

HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

358

if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

359

ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n");

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

36

static void ar5416WriteIni(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

365

OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

366

AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

367

HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

370

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

371

ar5416AttachPCIE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

373

ecode = ath_hal_v14EepromAttach(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

377

if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

378

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

38

static void ar5416SpurMitigate(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

384

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

386

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

387

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

397

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

400

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

401

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

408

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

415

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

42

ar5416AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

421

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

424

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

433

if (!ar5416FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

438

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

440

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

446

AH_PRIVATE(ah)->ah_currentRD =

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

447

ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

448

AH_PRIVATE(ah)->ah_currentRDext =

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

449

ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

458

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

460

rfStatus = ar2133RfAttach(ah, &ecode);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

462

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

467

ar5416AniSetup(ah); /* Anti Noise Immunity */

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

469

AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

470

AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

471

AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

472

AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

473

AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

474

AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

476

ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

478

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

480

return ah;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

490

ar5416Detach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

492

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

494

HALASSERT(ah != AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

495

HALASSERT(ah->ah_magic == AR5416_MAGIC);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

498

if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

499

HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

503

ar5416AniDetach(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

504

ar5212RfDetach(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

505

ah->ah_disable(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

506

ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

507

ath_hal_eepromDetach(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

508

ath_hal_free(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

512

ar5416AttachPCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

514

if (AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

515

ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

517

ath_hal_disablePCIE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

521

ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

525

if (! AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

529

ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

535

OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

538

OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

541

OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

549

ar5416DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

553

if (AH_PRIVATE(ah)->ah_ispcie)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

557

if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah)))

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

560

OS_REG_WRITE_BUFFER_ENABLE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

565

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

566

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

567

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

568

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

569

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

570

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

571

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

572

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

573

OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

576

OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

578

OS_REG_WRITE_BUFFER_FLUSH(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

579

OS_REG_WRITE_BUFFER_DISABLE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

583

ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

608

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

613

OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

616

if (AR_SREV_SOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

617

ar5416EepromSetAddac(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

619

regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

621

OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

623

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

625

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

629

AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

63

AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

638

ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

64

ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

640

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

672

cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

686

tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

692

OS_REG_WRITE_BUFFER_ENABLE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

694

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

701

OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

71

ar5416olcInit(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

720

OS_REG_WRITE(ah, AR_PHY_TIMING11, new);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

747

OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

748

OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

76

ar5416olcTempCompensation(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

798

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

799

OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

809

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

810

OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

820

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

821

OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

831

OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

832

OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

842

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

843

OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

853

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

854

OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

864

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

865

OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

875

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

876

OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

878

OS_REG_WRITE_BUFFER_FLUSH(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

879

OS_REG_WRITE_BUFFER_DISABLE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

88

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

888

ar5416FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

890

struct ath_hal_private *ahpriv = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

896

if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

903

if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

92

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

924

pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

928

pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

95

ah->ah_magic = AR5416_MAGIC;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

955

if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

96

ah->ah_getRateTable = ar5416GetRateTable;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

960

if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

97

ah->ah_detach = ar5416Detach;

sys/dev/ath/ath_hal/ar5416/ar5416_attach.c

998

pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

103

OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

108

ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

110

ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

125

ar5416SetBeaconTimers(ah, &bt);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

131

ar5416ResetStaBeaconTimers(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

135

OS_REG_WRITE(ah, AR_NEXT_TBTT, 0); /* no beacons */

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

136

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

139

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

141

OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

142

OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

151

ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

159

OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bs->bs_nexttbtt));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

166

OS_REG_WRITE(ah, AR5416_BEACON_PERIOD,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

168

OS_REG_WRITE(ah, AR_DBA_PERIOD,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

178

OS_REG_RMW_FIELD(ah, AR_RSSI_THR,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

250

OS_REG_WRITE(ah, AR_NEXT_DTIM,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

252

OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

255

OS_REG_WRITE(ah, AR5416_SLEEP1,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

261

OS_REG_WRITE(ah, AR5416_SLEEP2,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

265

OS_REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

266

OS_REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

268

OS_REG_SET_BIT(ah, AR_TIMER_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

275

OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, HAL_TSFOOR_THRESHOLD);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

277

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

279

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

281

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

283

HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

35

ar5416GetNextTBTT(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

37

return OS_REG_READ(ah, AR_NEXT_TBTT);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

46

ar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

49

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

51

OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

52

OS_REG_WRITE(ah, AR_NEXT_DBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextdba));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

53

OS_REG_WRITE(ah, AR_NEXT_SWBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextswba));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

54

OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

58

OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

59

OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

60

OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

61

OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

67

ar5416ResetTsf(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

71

OS_REG_SET_BIT(ah, AR_TIMER_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

82

ar5416BeaconInit(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

95

switch (AH_PRIVATE(ah)->ah_opmode) {

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

168

ar5416BTCoexSetupBmissThresh(struct ath_hal *ah, u_int32_t thresh)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

170

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

181

ar5416BTCoexAntennaDiversity(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

186

ar5416BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

188

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

194

OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

197

OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

208

AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1;

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

209

ar5416SetTxPowerLimit(ah, AH_PRIVATE(ah)->ah_power_limit, AH_PRIVATE(ah)->ah_extra_txpow, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

215

AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

216

ar5416SetTxPowerLimit(ah, AH_PRIVATE(ah)->ah_power_limit, AH_PRIVATE(ah)->ah_extra_txpow, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

227

ar5416BTCoexDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

229

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

232

ar5416GpioSet(ah, ahp->ah_wlanActiveGpioSelect, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

233

ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

236

if (AR_SREV_9271(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

241

ar5416GpioCfgInput(ah, ahp->ah_wlanActiveGpioSelect);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

245

OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

247

OS_REG_RMW_FIELD(ah, AR_MISC_MODE, AR_PCU_BT_ANT_PREVENT_RX,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

251

OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

252

OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

253

if (AR_SREV_KIWI_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

254

OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT2, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

255

OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

261

ar5416BTCoexEnable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

263

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

266

OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_btCoexMode);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

267

OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

270

if (AR_SREV_KIWI_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

271

OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT2,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

274

OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

277

if (AR_SREV_9271(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

280

val = OS_REG_READ(ah, AR9271_CLOCK_CONTROL);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

282

OS_REG_WRITE(ah, AR9271_CLOCK_CONTROL, val);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

286

OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

288

OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

291

OS_REG_RMW_FIELD(ah, AR_QUIET1,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

294

OS_REG_RMW_FIELD(ah, AR_MISC_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

297

OS_REG_RMW_FIELD(ah, AR_QUIET1,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

300

OS_REG_RMW_FIELD(ah, AR_MISC_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

306

ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

313

ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

321

OS_REG_RMW(ah, AR_GPIO_PDPU,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

331

ar5416InitBTCoex(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

333

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

335

HALDEBUG(ah, HAL_DEBUG_BT_COEX,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

341

OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

349

OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

352

OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

359

ar5416GpioCfgInput(ah, ahp->ah_btActiveGpioSelect);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

360

ar5416GpioCfgInput(ah, ahp->ah_btPriorityGpioSelect);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

367

AH5416(ah)->ah_btCoexSetDiversity(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

37

ar5416SetBTCoexInfo(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

370

ar5416BTCoexEnable(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

372

ar5416BTCoexDisable(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

377

OS_REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

380

OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

387

OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

39

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

392

ar5416GpioCfgInput(ah, ahp->ah_btActiveGpioSelect);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

395

ar5416BTCoexEnable(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

52

ar5416BTCoexConfig(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

54

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

61

if (AR_SREV_KIWI(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

85

ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

87

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

93

ar5416BTCoexSetWeights(struct ath_hal *ah, u_int32_t stompType)

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

95

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c

97

if (AR_SREV_KIWI_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

100

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

107

OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

108

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

112

OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

113

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

117

OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

118

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

122

OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

123

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

128

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

135

ar5416ResetMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

137

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

144

ar5416SetupMeasurement(ah, currCal);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

155

ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

157

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

158

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

170

ar5416ResetMeasurement(ah, curCal);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

172

if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

173

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

181

ar5416DoCalibration(ah, &ichan, ahp->ah_rxchainmask,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

184

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

201

ar5416InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

204

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

206

OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

210

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

215

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

218

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

219

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

225

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

227

OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

231

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

243

ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

245

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

248

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

252

if (! AH5416(ah)->ah_cal_initcal(ah, chan)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

253

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

260

if (AH5416(ah)->ah_cal_pacal)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

261

AH5416(ah)->ah_cal_pacal(ah, AH_TRUE);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

269

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

284

if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

288

if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

295

if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

301

if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

304

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

307

if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

310

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

313

if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

316

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

324

ar5416ResetMeasurement(ah, cal->cal_curr);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

338

ar5416ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

340

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

341

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

344

if (!AR_SREV_SOWL_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

349

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

359

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

36

static void ar5416StartNFCal(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

366

if (!ar5416IsCalSupp(ah, chan, currCal->calData->calType))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

369

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

37

static HAL_BOOL ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

386

ar5416DoCalibration(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

389

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

394

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

40

static uint16_t ar5416GetDefaultNF(struct ath_hal *ah, const struct ieee80211_channel *chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

402

if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

403

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

41

static void ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

410

currCal->calData->calCollect(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

420

currCal->calData->calPostProc(ah, numChains);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

430

ar5416SetupMeasurement(ah, currCal);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

435

ar5416ResetMeasurement(ah, currCal);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

443

ar5416PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

446

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

451

OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

460

rxchainmask = AH5416(ah)->ah_rx_chainmask;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

463

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

465

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

483

ar5416DoCalibration(ah, ichan, rxchainmask, currCal, isCalDone);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

488

ar5416ResetMeasurement(ah, currCal);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

496

if (AH5416(ah)->ah_cal_pacal)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

497

AH5416(ah)->ah_cal_pacal(ah, AH_FALSE);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

500

if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

501

AH5416(ah)->ah_olcTempCompensation(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

507

r = ar5416GetNf(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

510

HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: NF calibration"

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

521

ret = ar5416LoadNF(ah, AH_PRIVATE(ah)->ah_curchan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

524

ar5416StartNFCal(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

542

ar5416PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

545

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

546

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

550

return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

556

return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

562

ar5416GetEepromNoiseFloorThresh(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

566

ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_5, nft);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

570

ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_2, nft);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

573

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

579

ar5416StartNFCal(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

581

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

582

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

583

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

587

ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

601

int16_t default_nf = ar5416GetDefaultNF(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

606

if (AR_SREV_KITE(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

609

} else if (AR_SREV_MERLIN(ah) || AR_SREV_KIWI(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

620

h = AH5416(ah)->ah_cal.nfCalHist;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

621

HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

636

val = OS_REG_READ(ah, ar5416_cca_regs[i]);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

639

HALDEBUG(ah, HAL_DEBUG_NFCAL, "[%d: %d]", i, nf_val);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

64

ar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

640

OS_REG_WRITE(ah, ar5416_cca_regs[i], val);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

643

HALDEBUG(ah, HAL_DEBUG_NFCAL, "\n");

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

646

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

647

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

648

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

651

if (! ar5212WaitNFCalComplete(ah, 1000)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

661

HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "Timeout while waiting for "

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

663

OS_REG_READ(ah, AR_PHY_AGC_CONTROL));

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

67

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

679

val = OS_REG_READ(ah, ar5416_cca_regs[i]);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

682

OS_REG_WRITE(ah, ar5416_cca_regs[i], val);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

711

ar5416UpdateNFHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

737

ar5416GetDefaultNF(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

742

limit = &AH5416(ah)->nf_2g;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

744

limit = &AH5416(ah)->nf_5g;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

750

ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

756

if (IEEE80211_IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

757

limit = &AH5416(ah)->nf_2g;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

759

limit = &AH5416(ah)->nf_5g;

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

766

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

771

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

786

ar5416GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

792

if (ar5212IsNFCalInProgress(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

793

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

800

HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

803

ath_hal_getNoiseFloor(ah, nfarray);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

805

ar5416SanitizeNF(ah, nfarray);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

806

if (ar5416GetEepromNoiseFloorThresh(ah, chan, &nfThresh)) {

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

808

HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

82

(IS_5GHZ_FAST_CLOCK_EN(ah, chan)))

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

832

ar5416UpdateNFHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist, nfarray);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.c

97

ar5416SetupMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

105

HAL_BOOL ar5416InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

114

void ar5416IQCalCollect(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

115

void ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

116

void ar5416AdcGainCalCollect(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

117

void ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

118

void ar5416AdcDcCalCollect(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_cal.h

119

void ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains);

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

101

val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

104

OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

106

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

109

OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

36

ar5416AdcDcCalCollect(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

38

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

43

OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

45

OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

47

OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

49

OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

51

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

62

ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

64

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

78

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

81

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

83

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

85

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

87

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

96

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

98

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

101

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

105

val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

108

OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

110

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

114

OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

39

ar5416AdcGainCalCollect(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

41

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

49

OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

51

OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

53

OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

55

OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

57

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

69

ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

71

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

80

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

82

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

84

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

86

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

88

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c

98

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

103

HALDEBUG(ah, HAL_DEBUG_PERCAL, " iCoff = 0x%08x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

105

HALDEBUG(ah, HAL_DEBUG_PERCAL, " qCoff = 0x%08x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

110

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

119

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

122

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

124

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

126

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

130

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

38

ar5416IQCalCollect(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

40

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

48

OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

50

OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

52

OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

53

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

64

ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains)

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

66

struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

76

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

78

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

88

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_i = 0x%08x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

90

HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_q = 0x%08x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c

92

HALDEBUG(ah, HAL_DEBUG_PERCAL, " iqCorrNeg is 0x%08x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_eeprom.c

35

ar5416EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)

sys/dev/ath/ath_hal/ar5416/ar5416_eeprom.c

37

OS_REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

sys/dev/ath/ath_hal/ar5416/ar5416_eeprom.c

38

if (!ath_hal_wait(ah, AR_EEPROM_STATUS_DATA,

sys/dev/ath/ath_hal/ar5416/ar5416_eeprom.c

41

*data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

106

HALDEBUG(ah, HAL_DEBUG_GPIO,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

113

ath_hal_printf(ah, "%s: mux %d is invalid!\n",

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

118

cfgOutputMux(ah, gpio, MuxSignalConversionTable[type]);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

124

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

127

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

137

ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

141

HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

143

HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d\n", __func__, gpio);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

149

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

152

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

161

ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

165

HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

166

HALDEBUG(ah, HAL_DEBUG_GPIO,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

169

reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

174

OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

182

ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

186

if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

192

if (AR_SREV_KIWI_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

193

bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9287_GPIO_IN_VAL);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

194

if (AR_SREV_KITE_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

195

bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

196

else if (AR_SREV_MERLIN_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

197

bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

199

bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

208

ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

212

HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

213

HALDEBUG(ah, HAL_DEBUG_GPIO,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

217

val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

219

OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

222

mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

224

OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

228

val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

230

OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

233

mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

235

OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

238

val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

240

OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

243

val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

252

OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

256

val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

258

OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

261

mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

263

OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

267

val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

269

OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

272

mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

274

OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

277

AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

35

cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

40

HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, type=%d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

67

if (AR_SREV_MERLIN_20_OR_LATER(ah) ||

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

69

OS_REG_RMW(ah, addr, (type << gpio_shift),

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

72

tmp = OS_REG_READ(ah, addr);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

76

OS_REG_WRITE(ah, addr, tmp);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

84

ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

90

HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

105

ah->ah_intrstate[0] = isr;

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

106

ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

107

ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

108

ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

109

ah->ah_intrstate[4] = OS_REG_READ(ah, AR_ISR_S3);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

110

ah->ah_intrstate[5] = OS_REG_READ(ah, AR_ISR_S4);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

111

ah->ah_intrstate[6] = OS_REG_READ(ah, AR_ISR_S5);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

115

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

120

uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

140

OS_REG_WRITE(ah, AR_ISR_S2, isr2);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

180

isr0 = OS_REG_READ(ah, AR_ISR_S0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

181

OS_REG_WRITE(ah, AR_ISR_S0, isr0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

182

isr1 = OS_REG_READ(ah, AR_ISR_S1);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

183

OS_REG_WRITE(ah, AR_ISR_S1, isr1);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

200

isr5 = OS_REG_READ(ah, AR_ISR_S5);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

201

OS_REG_WRITE(ah, AR_ISR_S5, isr5);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

220

OS_REG_WRITE(ah, AR_ISR, isr);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

222

OS_REG_READ(ah, AR_ISR);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

224

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

228

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: sync_cause=0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

235

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

237

OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

238

OS_REG_WRITE(ah, AR_RC, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

245

AH_PRIVATE(ah)->ah_fatalState[0] = isr;

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

246

AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

247

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

252

OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

254

(void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

264

ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

266

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

270

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

274

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

275

OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

276

(void) OS_REG_READ(ah, AR_IER);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

278

if (! AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

279

OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

280

(void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

282

OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

283

(void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

338

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

339

OS_REG_WRITE(ah, AR_IMR, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

34

ar5416IsInterruptPending(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

341

(void) OS_REG_READ(ah, AR_IMR);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

343

mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

351

OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

357

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

358

OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

360

if (! AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

363

mask |= SM(AH5416(ah)->ah_gpioMask,

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

365

OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

366

OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

370

mask |= SM(AH5416(ah)->ah_gpioMask,

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

372

OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

373

OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

38

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

45

isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

49

isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

68

ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

71

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

77

bzero(&ah->ah_intrstate, sizeof(ah->ah_intrstate));

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

78

ah->ah_syncstate = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

84

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

86

isr = OS_REG_READ(ah, AR_ISR);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

88

if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

89

(OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

90

isr = OS_REG_READ(ah, AR_ISR);

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

94

ah->ah_syncstate =

sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

96

o_sync_cause = sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

39

ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

41

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

43

if (ar5212ResetKeyCacheEntry(ah, entry)) {

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

55

ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

59

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_keycache.c

61

if (ar5212SetKeyCacheEntry(ah, entry, k, mac, xorKey)) {

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

107

ar5416GetTsf64(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

112

low1 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

113

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

114

low2 = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

144

ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

152

v = OS_REG_READ(ah, AR_SLP32_MODE);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

158

ath_hal_printf(ah, "%s: couldn't slew things right!\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

161

OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

162

OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

169

ar5416ResetTsf(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

175

v = OS_REG_READ(ah, AR_SLP32_MODE);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

180

OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

184

ar5416GetCurRssi(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

186

if (AR_SREV_OWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

187

return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

188

return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

192

ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

199

ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

206

ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

209

ar5212SetCoverageClass(ah, coverageclass, now);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

216

ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

218

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

222

uint32_t rc = OS_REG_READ(ah, AR_RCCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

223

uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

224

uint32_t rf = OS_REG_READ(ah, AR_RFCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

225

uint32_t tf = OS_REG_READ(ah, AR_TFCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

226

uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

234

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

263

ar5416SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

266

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

268

AH5416(ah)->ah_tx_chainmask = tx_chainmask & pCap->halTxChainMask;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

269

AH5416(ah)->ah_rx_chainmask = rx_chainmask & pCap->halRxChainMask;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

280

ar5416Get11nExtBusy(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

282

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

286

ctlBusy = OS_REG_READ(ah, AR_RCCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

287

extBusy = OS_REG_READ(ah, AR_EXTRCCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

288

cycleCount = OS_REG_READ(ah, AR_CCCNT);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

297

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n",

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

331

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, "

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

355

ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

365

OS_REG_WRITE(ah, AR_2040_MODE, macmode);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

375

ar5416Get11nRxClear(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

380

val = OS_REG_READ(ah, AR_DIAG_SW);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

40

ar5416GetWirelessModes(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

401

ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

405

OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

407

OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

411

OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

413

OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

421

ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

429

nextStart_us += OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

43

struct ath_hal_private *ahpriv = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

432

nextStart_us += ah->ah_config.ah_sw_beacon_response_time;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

434

OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

435

OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

436

OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

437

OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

438

OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

440

OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

447

ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

454

return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

456

return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

458

return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

46

mode = ar5212GetWirelessModes(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

462

return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) ||

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

463

(ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) ||

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

464

AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ?

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

474

!! (AH5212(ah)->ah_miscMode & AR_PCU_TXOP_TBTT_LIMIT_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

479

return ar5212GetCapability(ah, type, capability, result);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

483

ar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

486

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

490

setting &= ath_hal_eepromGet(ah, AR_EEP_RXMASK, NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

498

setting &= ath_hal_eepromGet(ah, AR_EEP_TXMASK, NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

509

AH5212(ah)->ah_miscMode

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

511

OS_REG_SET_BIT(ah, AR_MISC_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

514

AH5212(ah)->ah_miscMode

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

516

OS_REG_CLR_BIT(ah, AR_MISC_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

523

return ar5212SetCapability(ah, type, capability, setting, status);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

526

static int ar5416DetectMacHang(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

527

static int ar5416DetectBBHang(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

530

ar5416GetDiagState(struct ath_hal *ah, int request,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

534

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

537

if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

541

return ath_hal_eepromDiag(ah, request,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

549

ahp->ah_hangs |= ar5416DetectBBHang(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

552

ahp->ah_hangs |= ar5416DetectMacHang(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

557

return ar5212GetDiagState(ah, request,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

562

ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

582

val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

584

OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

596

if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah)))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

602

OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

604

OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

607

OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

609

OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

615

ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

657

ar5416DetectMacHang(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

66

ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

676

mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

677

mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

678

mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

679

mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

681

if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) ||

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

682

mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) ||

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

683

mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) ||

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

684

mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

688

if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

690

if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

693

HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature "

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

705

ar5416DetectBBHang(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

735

hang_sig = OS_REG_READ(ah, AR_OBSERV_1);

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

737

if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

742

HALDEBUG(ah, HAL_DEBUG_HANG,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

748

HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! "

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

79

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

85

OS_REG_RMW_FIELD(ah, AR_MAC_LED,

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c

99

OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE,

sys/dev/ath/ath_hal/ar5416/ar5416_phy.c

107

ar5416GetRateTable(struct ath_hal *ah, u_int mode)

sys/dev/ath/ath_hal/ar5416/ar5416_phy.c

122

return ar5212GetRateTable(ah, mode);

sys/dev/ath/ath_hal/ar5416/ar5416_phy.c

124

ath_hal_setupratetable(ah, rt);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

101

if (! AR_SREV_OWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

102

OS_REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

112

ar5416SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

114

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

117

OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

125

ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

142

HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

143

modes[ah->ah_powerMode], modes[mode], setChip ? "set chip " : "");

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

147

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

148

status = ar5416SetPowerModeAwake(ah, setChip);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

151

ar5416SetPowerModeSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

153

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

156

ar5416SetPowerModeNetworkSleep(ah, setChip);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

158

ah->ah_powerMode = mode;

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

161

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode 0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

172

ar5416GetPowerMode(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

174

int mode = OS_REG_READ(ah, AR_RTC_STATUS);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

184

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

37

ar5416SetPowerModeAwake(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

49

if ((OS_REG_READ(ah, AR_RTC_STATUS)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

51

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

53

AH5416(ah)->ah_initPLL(ah, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

56

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

57

OS_REG_SET_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

59

OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

60

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

66

val = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

70

OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

75

ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

82

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

92

ar5416SetPowerModeSleep(struct ath_hal *ah, int setChip)

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

94

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

97

OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

98

if (! AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

99

OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

101

pe->pe_extchannel = !! (OS_REG_READ(ah, AR_PHY_RADAR_EXT) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

104

pe->pe_usefir128 = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

106

pe->pe_blockradar = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

108

pe->pe_enmaxrssi = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

111

(OS_REG_READ(ah, AR_PHY_RADAR_0) & AR_PHY_RADAR_0_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

112

pe->pe_enrelpwr = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

114

pe->pe_en_relstep_check = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) &

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

123

ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

127

val = OS_REG_READ(ah, AR_PHY_RADAR_0);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

152

OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

156

OS_REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

158

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

161

OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

163

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

166

OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

168

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

171

OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

173

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

176

val = OS_REG_READ(ah, AR_PHY_RADAR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

179

OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

182

val = OS_REG_READ(ah, AR_PHY_RADAR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

185

OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

189

OS_REG_SET_BIT(ah, AR_PHY_RADAR_1,

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

192

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1,

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

196

OS_REG_SET_BIT(ah, AR_PHY_RADAR_1,

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

199

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1,

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

203

val = OS_REG_READ(ah, AR_PHY_RADAR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

206

OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

215

OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

217

OS_REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

233

ar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

255

doDfsExtCh = AH_PRIVATE(ah)->ah_caps.halExtChanDfsSupport;

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

256

doDfsEnhanced = AH_PRIVATE(ah)->ah_caps.halEnhancedDfsSupport;

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

257

doDfsCombinedRssi = AH_PRIVATE(ah)->ah_caps.halUseCombinedRadarRssi;

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

288

HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, ext_rssi=%d, pulse_length_pri=%d,"

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

300

HALDEBUG(ah, HAL_DEBUG_DFS, "%s: dur and rssi are 0\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

304

HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n", __func__, rssi, dur);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

427

ar5416IsFastClockEnabled(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

429

struct ath_hal_private *ahp = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

431

return IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

54

ar5416GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

81

ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

85

val = OS_REG_READ(ah, AR_PHY_RADAR_0);

sys/dev/ath/ath_hal/ar5416/ar5416_radar.c

96

val = OS_REG_READ(ah, AR_PHY_RADAR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

107

ar5416StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

109

struct ath_hal_private *ahp = AH_PRIVATE(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

111

HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

112

ar5212EnableMibCounters(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

114

ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, ! is_scanning);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

119

OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

127

ar5416StopPcuReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

129

OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

131

HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

132

ar5212DisableMibCounters(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

140

ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

169

ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

198

rs->rs_rate = RXSTATUS_RATE(ah, ads);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

214

if (AR_SREV_MERLIN_10_OR_LATER(ah)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

259

ath_hal_printf(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

33

ar5416GetRxFilter(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

35

uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

36

uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

49

ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

53

OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

59

OS_REG_WRITE(ah, AR_PHY_ERR, phybits);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

61

OS_REG_WRITE(ah, AR_RXCFG,

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

62

OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

64

OS_REG_WRITE(ah, AR_RXCFG,

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

65

OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

73

ar5416StopDmaReceive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

77

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

78

OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

79

if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

80

OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

82

ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

85

OS_REG_READ(ah, AR_CR),

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

86

OS_REG_READ(ah, AR_DIAG_SW));

sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

97

if (AR_SREV_9100(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1000

OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1004

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1010

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1019

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1025

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1032

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1044

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER |

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1045

(AH5212(ah)->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1056

ar5416SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1063

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

107

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1072

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1075

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1080

AH5416(ah)->ah_ht40PowerIncForPdadc = 2;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1083

OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1084

cfgCtl = ath_hal_getctl(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1087

twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1089

HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1092

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1093

AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1096

if (!ar5416SetPowerPerRateTable(ah, pEepData, chan,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1097

&AH5416(ah)->ah_ratesArray[0],

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1101

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1106

if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1107

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1112

maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb],

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1113

AH5416(ah)->ah_ratesArray[rateHt20_0]);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1116

maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1120

maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1124

AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1131

for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1132

AH5416(ah)->ah_ratesArray[i] =

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1133

(int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1134

if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1135

AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1146

ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1155

if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1158

(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1162

for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1167

AH5416(ah)->ah_ratesArray[i] -= (pwr_table_offset * 2);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1168

if (AH5416(ah)->ah_ratesArray[i] < 0)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1169

AH5416(ah)->ah_ratesArray[i] = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

117

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1170

else if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1171

AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1189

if (AR_SREV_MERLIN_20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1190

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1198

AH5416(ah)->ah_ratesArray[adj[i]] -= cck_ofdm_delta;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1199

if (AH5416(ah)->ah_ratesArray[adj[i]] < 0)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1200

AH5416(ah)->ah_ratesArray[adj[i]] = 0;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1212

AH5416(ah)->ah_ratesArray[rateHt40_0] +=

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1213

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1214

AH5416(ah)->ah_ratesArray[rateHt40_1] +=

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1215

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1216

AH5416(ah)->ah_ratesArray[rateHt40_2] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1217

AH5416(ah)->ah_ratesArray[rateHt40_3] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1218

AH5416(ah)->ah_ratesArray[rateHt40_4] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1219

AH5416(ah)->ah_ratesArray[rateHt40_5] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

122

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1220

AH5416(ah)->ah_ratesArray[rateHt40_6] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1221

AH5416(ah)->ah_ratesArray[rateHt40_7] += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1225

ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1228

OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1242

ar5416GetRfgain(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

125

ath_hal_survey_clear(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1252

ar5416Disable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1255

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1257

if (! ar5416SetResetReg(ah, HAL_RESET_COLD))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1260

AH5416(ah)->ah_initPLL(ah, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1271

ar5416PhyDisable(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1274

if (! ar5416SetResetReg(ah, HAL_RESET_WARM))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1277

AH5416(ah)->ah_initPLL(ah, AH_NULL);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1285

ar5416SetResetReg(struct ath_hal *ah, uint32_t type)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1290

OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1295

return ar5416SetResetPowerOn(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1298

return ar5416SetReset(ah, type);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1306

ar5416SetResetPowerOn(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1319

OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1327

if (! AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1328

OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

133

rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1332

OS_REG_WRITE(ah, AR_RTC_RESET, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1335

if (! AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1336

OS_REG_WRITE(ah, AR_RC, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1338

OS_REG_WRITE(ah, AR_RTC_RESET, 1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1343

if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1344

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1348

return ar5416SetReset(ah, HAL_RESET_COLD);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1352

ar5416SetReset(struct ath_hal *ah, int type)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1358

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1359

HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n");

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1360

uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1363

OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1364

(void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1371

OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1375

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1388

tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1390

OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1391

OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1393

OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1402

OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1404

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

141

saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1412

OS_REG_WRITE(ah, AR_RTC_RC, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1413

if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1414

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1419

if (! AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1420

OS_REG_WRITE(ah, AR_RC, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1422

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1425

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1427

mask = OS_REG_READ(ah, AR_CFG);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1429

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1434

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1435

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1436

"Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1448

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1450

OS_REG_WRITE(ah, AR_CFG, mask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1452

OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1460

ar5416InitChainMasks(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1462

int rx_chainmask = AH5416(ah)->ah_rx_chainmask;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1466

OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1472

if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1473

OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1474

OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1476

OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1477

OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1479

OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1481

if (AH5416(ah)->ah_tx_chainmask == 0x5)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1482

OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1484

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1485

OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1486

OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1498

ar5416RestoreChainMask(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1500

int rx_chainmask = AH5416(ah)->ah_rx_chainmask;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1502

if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1503

OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1504

OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1509

ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1525

OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1533

OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1537

ar5416SetDefGainValues(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1543

if (IS_EEP_MINOR_V3(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1546

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1547

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

155

if ((! AR_SREV_KITE(ah)) && saveDefAntenna == 0) /* XXX magic constants */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1550

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1553

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1556

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1560

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1563

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1569

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1570

OS_REG_RMW_FIELD(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1573

OS_REG_RMW_FIELD(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1577

OS_REG_RMW_FIELD(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1580

OS_REG_RMW_FIELD(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

159

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1595

ar5416GetRegChainOffset(struct ath_hal *ah, int i)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1599

if (AR_SREV_5416_V20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1600

(AH5416(ah)->ah_rx_chainmask == 0x5 ||

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1601

AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1618

ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1620

const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1626

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

163

saveLedState = OS_REG_READ(ah, AR_MAC_LED) &

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1632

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1634

if (AR_SREV_MERLIN(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1637

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1639

OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1641

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1642

(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1654

if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1655

ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1658

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1660

OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1661

OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1662

OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1663

OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1665

OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1666

OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1667

OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1668

OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1670

OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1671

OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1673

OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1677

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1678

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

168

if (AR_SREV_HOWL(ah) ||

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1680

if (! AR_SREV_MERLIN_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1681

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1683

OS_REG_WRITE(ah, AR_PHY_RF_CTL4,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1689

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

169

(AR_SREV_MERLIN(ah) &&

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1692

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1693

OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1695

OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1698

OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

170

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) ||

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1700

OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1705

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1706

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1708

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1712

if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1714

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1717

if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1718

OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1720

if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1722

OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1725

OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1727

OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

173

(ah->ah_config.ah_force_full_reset))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1732

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1734

OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

174

tsf = ar5416GetTsf64(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1753

ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

177

ar5416MarkPhyInactive(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

179

if (!ar5416ChipReset(ah, chan, resetType)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

180

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1810

ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1845

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

186

ar5416SetTsf64(ah, tsf);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1871

ath_hal_eepromSet(ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

188

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1883

switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

189

if (AR_SREV_MERLIN_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

190

OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1904

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1906

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1908

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1914

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1917

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1919

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

192

AH5416(ah)->ah_writeIni(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1927

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1929

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1935

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1937

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

194

if(AR_SREV_KIWI_13_OR_LATER(ah) ) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

196

OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

1972

rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

198

OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

199

OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

201

OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2024

ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

206

ar5416OverrideIni(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

209

ar5416Set11nRegs(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2100

ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

211

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2111

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2159

ar5416GetTargetPowersLeg(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2171

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

219

if (AR_SREV_HOWL(ah) && (ar5416GetTsf64(ah) < tsf)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

221

ar5416SetTsf64(ah, tsf);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2227

ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2232

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2234

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d,"

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2238

OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

224

HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

225

__func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2255

ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

226

HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

227

__func__, OS_REG_READ(ah,AR_PHY_ADC_CTL));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2286

ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2289

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d,"

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2293

OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2310

ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[])

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2316

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2324

OS_REG_WRITE(ah, regOffset, reg32);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2325

HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |"

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

233

ar5416InitChainMasks(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2345

ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

236

if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2363

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2366

pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

237

AH5416(ah)->ah_olcInit(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2378

numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

238

AH5416(ah)->ah_olcTempCompensation(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2381

ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2384

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2394

ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2400

if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2401

ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2406

ar5416WritePdadcValues(ah, i, pdadcValues);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

242

if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2421

ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

243

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2452

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

249

if (!ahp->ah_rfHal->setRfRegs(ah, chan,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

251

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2512

if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2527

if (AR_SREV_MERLIN_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

258

ar5416SetDeltaSlope(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2589

ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2595

if (AR_SREV_KITE_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2596

enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

260

AH5416(ah)->ah_spurMitigate(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2617

OS_REG_WRITE(ah, AR_PHY_TURBO, phymode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2620

ar5416Set11nMac2040(ah, macmode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2624

OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2627

OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2628

OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

263

if (!ah->ah_setBoardValues(ah, chan)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2632

ar5416GetChannelCenters(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2635

uint16_t freq = ath_hal_gethwchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

264

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2660

ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2669

OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2671

if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2672

val = OS_REG_READ(ah, AR_PCU_MISC_MODE2);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2674

if (!AR_SREV_9271(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2677

if (AR_SREV_KIWI_10_OR_LATER(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2680

OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2687

if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2688

(void) ar5416SetRifsDelay(ah, chan, AH_FALSE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

269

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2690

if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2697

OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

271

OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2710

ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2714

HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2718

if (! AR_SREV_SOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

272

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2721

if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2732

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2753

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2764

HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) =

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2765

(HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2767

HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) =

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2768

(HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

277

ar5212SetOperatingMode(ah, opmode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2773

ar5416MarkPhyInactive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2775

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

280

OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

281

OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2826

ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2838

IS_5GHZ_FAST_CLOCK_EN(ah, chan))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

284

if (AR_SREV_HOWL(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2845

refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

285

OS_REG_WRITE(ah, AR_MAC_LED,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

288

OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) |

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2894

OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2895

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2896

OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2897

OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

293

if (AR_SREV_KIWI(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

294

ar5416StartTsf2(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

300

if (AH5416(ah)->ah_btCoexConfigType != HAL_BT_COEX_CFG_NONE)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

301

ar5416InitBTCoex(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

304

OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

307

OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

308

OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

312

OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

314

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

317

OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

319

if (!ar5212SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

322

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

326

OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

329

for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

330

ah->ah_resetTxQueue(ah, i);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

332

ar5416InitIMR(ah, opmode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

333

ar5416SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

334

ar5416InitQoS(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

336

ar5416InitUserSettings(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

340

ar5416SetIFSTiming(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

347

OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

353

if (AR_SREV_KIWI_13_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

364

OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

366

OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

368

OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

371

OS_REG_WRITE(ah, AR_TIME_OUT,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

373

OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

375

OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

377

OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

381

if (AR_SREV_KIWI_13_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

383

OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

390

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

391

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

393

ar5416InitDMA(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

398

OS_REG_WRITE(ah, AR_OBS, 8);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

403

OS_REG_WRITE(ah, AR_MIRT, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

42

static void ar5416InitDMA(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

425

OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

426

OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

428

ar5416InitBB(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

43

static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

431

ar5212SetCompRegs(ah); /* XXX not needed? */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

44

static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

443

OS_REG_WRITE(ah, AR_TPC, powerVal);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

445

if (!ar5416InitCal(ah, chan))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

448

ar5416RestoreChainMask(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

45

static void ar5416InitQoS(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

450

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

455

if (AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

46

static void ar5416InitUserSettings(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

463

reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

464

OS_REG_WRITE(ah,AR_STA_ID1, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

465

ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

468

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

47

static void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

470

OS_MARK(ah, AH_MARK_RESET_DONE, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

474

OS_MARK(ah, AH_MARK_RESET_DONE, ecode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

490

ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

495

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

501

ichan = ath_hal_checkchannel(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

504

for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

505

if (ar5212NumTxPending(ah, qnum)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

506

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

515

OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

516

if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

517

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

522

ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

525

if (!ar5212SetChannel(ah, chan))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

529

if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

530

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

54

static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

540

data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

55

static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

550

OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

554

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

555

ar5212SetSpurMitigation(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

556

ar5416SetDeltaSlope(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

56

static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

565

ichan->tsf_last = ar5416GetTsf64(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

566

ar5212TxEnable(ah, AH_TRUE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

572

ar5416InitDMA(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

574

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

579

OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

584

OS_REG_WRITE(ah, AR_TXCFG,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

585

(OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

594

OS_REG_WRITE(ah, AR_RXCFG,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

595

(OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

598

OS_REG_WRITE(ah, AR_TXCFG,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

599

(OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) |

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

605

OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

611

if (AR_SREV_KITE(ah))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

617

OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

619

OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

62

static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

623

ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

63

static void ar5416MarkPhyInactive(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

632

synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

64

static void ar5416SetIFSTiming(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

640

HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

644

OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

662

ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

664

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

685

OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

689

if (! AR_SREV_HOWL(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

690

OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

691

OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

692

OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

698

OS_REG_WRITE(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

699

OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

704

ar5416InitQoS(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

707

OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

708

OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

711

OS_REG_WRITE(ah, AR_NOACK,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

719

OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

720

OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

721

OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

722

OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

723

OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

727

ar5416InitUserSettings(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

729

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

733

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

736

ar5212SetSifsTime(ah, ahp->ah_sifstime);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

738

ar5212SetSlotTime(ah, ahp->ah_slottime);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

740

ar5212SetAckTimeout(ah, ahp->ah_acktimeout);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

742

ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

743

if (AH_PRIVATE(ah)->ah_diagreg != 0)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

744

OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

745

if (AH5416(ah)->ah_globaltxtimeout != (u_int) -1)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

746

ar5416SetGlobalTxTimeout(ah, AH5416(ah)->ah_globaltxtimeout);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

750

ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

76

ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

761

if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

765

} else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

770

OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

777

ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

780

OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

784

if (AR_SREV_MERLIN(ah) &&

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

785

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

786

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

788

} else if (ah->ah_config.ah_force_full_reset) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

789

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

793

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

796

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

799

if (!ar5416SetResetReg(ah, HAL_RESET_WARM))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

804

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

811

AH5416(ah)->ah_initPLL(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

819

ar5416SetRfMode(ah, chan);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

829

ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

84

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

858

ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

880

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

883

ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

885

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

887

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

896

ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

899

OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

901

OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

913

ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

917

AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

918

return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

923

ar5416GetChipPowerLimits(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

926

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

932

if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

937

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

943

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

95

OS_MARK(ah, AH_MARK_RESET, bChannelChange);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

964

ar5416WriteTxPowerRateRegisters(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

970

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

976

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

98

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

985

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

99

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

991

OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

997

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

999

__func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

108

if (AR_SREV_MERLIN(ah) ) {

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

141

OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val | AR_PHY_SPECTRAL_SCAN_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

143

ar5416GetSpectralParams(ah, ss);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

151

ar5416GetSpectralParams(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

155

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

159

if (AR_SREV_MERLIN(ah) ) {

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

166

val = OS_REG_READ(ah, AR_PHY_RADAR_1);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

171

ar5416IsSpectralActive(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

175

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

180

ar5416IsSpectralEnabled(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

184

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

189

ar5416StartSpectralScan(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

193

ar5416PrepSpectralScan(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

196

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

199

OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

200

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

201

val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

202

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val | AR_PHY_ERR_RADAR);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

206

ar5416StopSpectralScan(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

209

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

214

OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

215

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

216

val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

217

OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

221

ar5416GetSpectralConfig(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

225

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

230

ar5416RestoreSpectralConfig(struct ath_hal *ah, uint32_t restoreval)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

234

ar5416PrepSpectralScan(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

236

curval = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

240

OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, restoreval);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

44

static void ar5416DisableRadar(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

45

static void ar5416PrepSpectralScan(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

48

ar5416DisableRadar(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

53

val = OS_REG_READ(ah, AR_PHY_RADAR_0);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

64

OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

67

val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

68

OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

70

val = OS_REG_READ(ah, AR_RX_FILTER);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

72

OS_REG_WRITE(ah, AR_RX_FILTER, val);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

76

ar5416PrepSpectralScan(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

79

ar5416DisableRadar(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

80

OS_REG_WRITE(ah, AR_PHY_ERR, ENABLE_ALL_PHYERR);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

84

ar5416ConfigureSpectralScan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

88

ar5416PrepSpectralScan(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c

90

val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

101

if (ar5212NumTxPending(ah, q) == 0)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1012

ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1015

uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1031

ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1041

ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1051

ar5416Set11nVirtualMoreFrag(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

106

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1066

ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1073

if (! AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1097

ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

110

OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1122

ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1125

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1127

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

113

OS_REG_WRITE(ah, AR_Q_TXD, 0);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1163

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1173

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1179

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1184

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1188

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1204

(void) ar5212SetTxQueueProps(ah, q, qInfo);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1214

setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1216

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1218

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1224

OS_REG_WRITE(ah, AR_IMR_S0,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1228

OS_REG_WRITE(ah, AR_IMR_S1,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1232

OS_REG_RMW_FIELD(ah, AR_IMR_S2,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1243

ar5416ResetTxQueue(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1245

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1246

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1247

const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1252

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1258

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1263

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1281

OS_REG_WRITE(ah, AR_DLCL_IFS(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1287

OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1312

OS_REG_WRITE(ah, AR_QCBRCFG(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1321

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1326

OS_REG_WRITE(ah, AR_DCHNTIME(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1391

HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: CAB: tqi_readyTime = %d\n",

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1394

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1396

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1416

- ah->ah_config.ah_additional_swba_backoff

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1417

- ah->ah_config.ah_sw_beacon_response_time

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1418

+ ah->ah_config.ah_dma_beacon_response_time;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1425

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1428

OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1445

OS_REG_WRITE(ah, AR_QMISC(q), qmisc);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1446

OS_REG_WRITE(ah, AR_DMISC(q), dmisc);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1456

OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1457

OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1458

OS_REG_WRITE(ah, AR_Q_CBC, HAL_COMP_BUF_MAX_SIZE/1024);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1459

OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1460

OS_REG_READ(ah, AR_Q0_MISC + 4*q)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

1494

setTxQInterrupts(ah, qi);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

159

ar5416RateToRateTable(struct ath_hal *ah, uint8_t rate, HAL_BOOL is_ht40)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

168

return (AH5416(ah)->ah_ratesArray[rate1l]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

170

return (AH5416(ah)->ah_ratesArray[rate2l]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

172

return (AH5416(ah)->ah_ratesArray[rate2s]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

174

return (AH5416(ah)->ah_ratesArray[rate5_5l]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

176

return (AH5416(ah)->ah_ratesArray[rate5_5s]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

178

return (AH5416(ah)->ah_ratesArray[rate11l]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

180

return (AH5416(ah)->ah_ratesArray[rate11s]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

186

return (AH5416(ah)->ah_ratesArray[rate6mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

188

return (AH5416(ah)->ah_ratesArray[rate9mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

190

return (AH5416(ah)->ah_ratesArray[rate12mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

192

return (AH5416(ah)->ah_ratesArray[rate18mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

194

return (AH5416(ah)->ah_ratesArray[rate24mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

196

return (AH5416(ah)->ah_ratesArray[rate36mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

198

return (AH5416(ah)->ah_ratesArray[rate48mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

200

return (AH5416(ah)->ah_ratesArray[rate54mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

208

return (AH5416(ah)->ah_ratesArray[rateHt40_0 + (rate & 0x7)]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

210

return (AH5416(ah)->ah_ratesArray[rateHt20_0 + (rate & 0x7)]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

214

return (AH5416(ah)->ah_ratesArray[rate6mb]);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

224

ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

238

n_txpower += AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

246

if (AR_SREV_KIWI_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

248

} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

251

(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

265

if (AR_SREV_MERLIN_20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

266

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

278

max_txpower = ar5416RateToRateTable(ah, rate, is_ht40);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

280

ath_hal_printf(ah, "%s: n_txpower = %d, max_txpower = %d, "

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

312

if ((! AR_SREV_MERLIN_10_OR_LATER(ah)) && (n_txpower == 0))

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

321

ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

338

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

34

ar5416StopTxDma(struct ath_hal *ah, u_int q)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

348

txPower = (txPower + AH5212(ah)->ah_txPowerIndexOffset);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

356

if (AH5212(ah)->ah_tpcEnabled) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

357

txPower = ar5416GetTxRatePower(ah, txRate0,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

399

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

40

HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

418

if (AR_SREV_KITE(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

42

HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

429

ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

44

OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

459

ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

46

if (ar5212NumTxPending(ah, q) == 0)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

52

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

523

ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

537

uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

538

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

54

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

545

(void) ah;

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

56

OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

57

OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

58

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

60

__func__, OS_REG_READ(ah, AR_QMISC(q)),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

61

OS_REG_READ(ah, AR_QRDYTIMECFG(q)),

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

618

ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

62

OS_REG_READ(ah, AR_Q_RDYTIMESHDN));

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

625

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

642

ads->ds_ctl7 = SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel0)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

643

| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

644

| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

645

| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

667

if (AR_SREV_KITE(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

67

if (ar5212NumTxPending(ah, q)) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

679

ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

70

HALDEBUG(ah, HAL_DEBUG_TXQUEUE,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

717

ar5416ProcTxDesc(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

72

__func__, ar5212NumTxPending(ah, q), q);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

721

uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

77

uint32_t tsfLow = OS_REG_READ(ah, AR_TSF_L32);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

78

OS_REG_WRITE(ah, AR_QUIET2,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

80

OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

81

OS_REG_WRITE(ah, AR_NEXT_QUIET, tsfLow >> 10);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

82

OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

824

ar5212UpdateTxTrigLevel(ah, AH_TRUE);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

830

ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

832

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

835

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n",

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

84

if ((OS_REG_READ(ah, AR_TSF_L32)>>10) == (tsfLow>>10))

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

841

OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

847

ar5416GetGlobalTxTimeout(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

849

return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

87

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

873

ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

93

OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

932

if (AH5212(ah)->ah_tpcEnabled) {

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

937

txPower = ar5416GetTxRatePower(ah, series[0].Rate,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

951

txPower = ar5416GetTxRatePower(ah, series[1].Rate,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

957

txPower = ar5416GetTxRatePower(ah, series[2].Rate,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

963

txPower = ar5416GetTxRatePower(ah, series[3].Rate,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

97

OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

977

ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen,

sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c

991

if (! AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

404

#define TXCTL_OFFSET(ah) 2

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

405

#define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8)

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

406

#define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10)

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

407

#define TXSTATUS_NUMWORDS(ah) 10

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

409

#define RXCTL_OFFSET(ah) 3

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

410

#define RXCTL_NUMWORDS(ah) 1

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

411

#define RXSTATUS_OFFSET(ah) 4

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

412

#define RXSTATUS_NUMWORDS(ah) 9

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

413

#define RXSTATUS_RATE(ah, ads) \

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

414

(AR_SREV_5416_V20_OR_LATER(ah) ? \

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

417

#define RXSTATUS_DUPLICATE(ah, ads) \

sys/dev/ath/ath_hal/ar5416/ar5416desc.h

418

(AR_SREV_5416_V20_OR_LATER(ah) ? \

sys/dev/ath/ath_hal/ar5416/ar5416reg.h

760

(AR_SREV_KITE(ah) && \

sys/dev/ath/ath_hal/ar5416/ar5416reg.h

769

(AR_SREV_KITE(ah) && \

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

106

OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

108

OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

122

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

140

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

144

AH5416(ah)->ah_initPLL = ar9160InitPLL;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

146

AH5416(ah)->ah_cal.iqCalData.calData = &ar9160_iq_cal;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

147

AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9160_adc_gain_cal;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

148

AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9160_adc_dc_cal;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

149

AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9160_adc_init_dc_cal;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

150

AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

152

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

154

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

160

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

161

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

167

val = OS_REG_READ(ah, AR_SREV);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

168

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

173

AH_PRIVATE(ah)->ah_macVersion =

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

175

AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

176

AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

182

HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar9160BB_RfGain, 3);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

183

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar9160Bank0, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

184

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar9160Bank1, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

185

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar9160Bank2, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

186

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar9160Bank3, 3);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

187

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar9160Bank6TPC, 3);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

188

HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar9160Bank7, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

189

if (AR_SREV_SOWL_11(ah))

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

190

HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac_1_1, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

192

HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

194

ecode = ath_hal_v14EepromAttach(ah);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

198

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar9160PciePhy, 2);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

199

ar5416AttachPCIE(ah);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

201

if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

202

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

207

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

209

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

210

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

220

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

223

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

224

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

229

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

230

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

235

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

238

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

243

rfStatus = ar2133RfAttach(ah, &ecode);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

245

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

253

if (!ar9160FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

258

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

260

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

266

AH_PRIVATE(ah)->ah_currentRD =

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

267

ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

268

AH_PRIVATE(ah)->ah_currentRDext =

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

269

ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

278

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

280

ar9160AniSetup(ah); /* Anti Noise Immunity */

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

283

AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

284

AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

285

AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

286

AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

287

AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

288

AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

290

ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

292

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

294

return ah;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

309

ar9160FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

311

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

313

if (!ar5416FillCapabilityInfo(ah))

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

60

static HAL_BOOL ar9160FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

63

ar9160AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

85

AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

86

ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar9001/ar9160_attach.c

90

ar9160InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9280.c

100

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar9002/ar9280.c

103

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

106

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

194

OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,

sys/dev/ath/ath_hal/ar9002/ar9280.c

209

OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);

sys/dev/ath/ath_hal/ar9002/ar9280.c

211

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar9002/ar9280.c

220

ar9280GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar9002/ar9280.c

222

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar9002/ar9280.c

232

ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar9002/ar9280.c

245

ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,

sys/dev/ath/ath_hal/ar9002/ar9280.c

253

ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)

sys/dev/ath/ath_hal/ar9002/ar9280.c

280

ar9280GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280.c

285

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9280.c

325

totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar9002/ar9280.c

326

*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar9002/ar9280.c

331

*minPow = ar9280GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar9002/ar9280.c

353

ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])

sys/dev/ath/ath_hal/ar9002/ar9280.c

357

nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9280.c

360

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

364

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9280.c

367

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

371

nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9280.c

374

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

378

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9280.c

381

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9280.c

39

#define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar9002/ar9280.c

396

ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar9002/ar9280.c

405

ar9280RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280.c

407

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9280.c

415

ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar9002/ar9280.c

417

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9280.c

420

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9280.c

425

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9280.c

43

int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);

sys/dev/ath/ath_hal/ar9002/ar9280.c

446

AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;

sys/dev/ath/ath_hal/ar9002/ar9280.c

447

AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor;

sys/dev/ath/ath_hal/ar9002/ar9280.c

453

ar9280RfProbe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280.c

455

return (AR_SREV_MERLIN(ah));

sys/dev/ath/ath_hal/ar9002/ar9280.c

46

ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar9002/ar9280.c

49

(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,

sys/dev/ath/ath_hal/ar9002/ar9280.c

73

ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9280.c

81

OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);

sys/dev/ath/ath_hal/ar9002/ar9280.c

83

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9280.c

86

reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);

sys/dev/ath/ath_hal/ar9002/ar9280.c

89

if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK)

sys/dev/ath/ath_hal/ar9002/ar9280.h

62

void ar9280InitPLL(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

101

ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

105

ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

109

if (AR_SREV_MERLIN_20(ah) &&

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

116

pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

121

} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

136

OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

138

OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

156

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

175

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

177

ar5416InitState(AH5416(ah), devid, sc, st, sh, status);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

186

AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

187

AH_PRIVATE((ah))->ah_eepromWrite = NULL;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

188

ah->ah_eepromdata = eepromdata;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

193

AH5416(ah)->ah_initPLL = ar9280InitPLL;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

195

ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

196

ah->ah_configPCIE = ar9280ConfigPCIE;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

197

ah->ah_disablePCIE = ar9280DisablePCIE;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

199

AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

200

AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

201

AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

202

AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

203

AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

205

AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

206

AH5416(ah)->ah_writeIni = ar9280WriteIni;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

207

AH5416(ah)->ah_olcInit = ar9280olcInit;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

208

AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

209

AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

211

AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

212

AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

214

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

216

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

222

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

223

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

229

val = OS_REG_READ(ah, AR_SREV);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

230

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

235

AH_PRIVATE(ah)->ah_macVersion =

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

237

AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

238

AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

241

if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

244

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

251

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

254

ar5416AttachPCIE(ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

256

ecode = ath_hal_v14EepromAttach(ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

260

if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

261

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

266

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

268

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

269

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

279

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

282

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

283

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

288

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

289

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

294

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

297

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

302

rfStatus = ar9280RfAttach(ah, &ecode);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

304

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

317

ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

318

if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

320

AH5416(ah)->ah_need_an_top2_fixup = 1;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

327

(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

329

ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

333

if (AR_SREV_MERLIN_20(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

335

switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

355

if (AR_SREV_MERLIN_20(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

357

switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

375

if (!ar9280FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

380

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

382

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

388

AH_PRIVATE(ah)->ah_currentRD =

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

389

ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

390

AH_PRIVATE(ah)->ah_currentRDext =

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

391

ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

400

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

402

ar9280AniSetup(ah); /* Anti Noise Immunity */

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

405

AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

406

AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

407

AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

408

AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

409

AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

410

AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

412

ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

414

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

416

return ah;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

418

if (ah != AH_NULL)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

419

ah->ah_detach(ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

426

ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

430

if (AH_PRIVATE(ah)->ah_ispcie && !restore) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

431

ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

445

OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

447

val = OS_REG_READ(ah, AR_WA);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

471

OS_REG_WRITE(ah, AR_WA, val);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

479

OS_REG_WRITE(ah, AR_WA, val);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

482

OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

487

ar9280DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

492

ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

519

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

520

OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

527

ia = &AH5212(ah)->ah_ini_modes;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

529

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

537

if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

540

OS_REG_WRITE(ah, reg, val);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

549

if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

550

regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

552

regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

556

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

559

if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

561

regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

572

ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

602

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

610

cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

64

static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

641

OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

644

OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

652

OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

657

tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

66

static void ar9280DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

663

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

67

static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

670

OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

68

static void ar9280WriteIni(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

705

OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

709

OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

72

ar9280AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

737

OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

738

OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

788

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

789

OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

799

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

800

OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

810

OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

811

OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

821

OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

822

OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

832

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

833

OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

843

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

844

OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

854

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

855

OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

865

OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

866

OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

875

ar9280FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

877

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

879

if (!ar5416FillCapabilityInfo(ah))

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

905

if (AR_SREV_MERLIN_20(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

927

ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

932

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

943

if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

955

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n",

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

98

AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

100

ar9280olcGetPDADCs(struct ath_hal *ah, uint32_t initTxGain, int txPower,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

106

OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

107

OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

109

OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

129

ar9280olcTemperatureCompensation(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

135

if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

138

rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

141

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

143

__func__, AH5416(ah)->initPDADC, currPDADC);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

145

if (AH5416(ah)->initPDADC == 0 || currPDADC == 0)

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

148

(void) (ath_hal_eepromGet(ah, AR_EEP_DAC_HPWR_5G, &hpwr_5g));

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

151

delta = (currPDADC - AH5416(ah)->initPDADC + 4) / 8;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

153

delta = (currPDADC - AH5416(ah)->initPDADC + 5) / 10;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

155

HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d, PDADCdelta=%d\n",

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

156

__func__, delta, AH9280(ah)->PDADCdelta);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

158

if (delta != AH9280(ah)->PDADCdelta) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

159

AH9280(ah)->PDADCdelta = delta;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

161

regval = AH9280(ah)->originalGain[i] - delta;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

165

OS_REG_RMW_FIELD(ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

173

ar9280ChangeGainBoundarySettings(struct ath_hal *ah, uint16_t *gb,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

184

if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

211

ar9280AdjustPDADCValues(struct ath_hal *ah, int8_t pwr_table_offset,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

222

if (AR_SREV_MERLIN_20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

242

ar9280SetGainBoundariesOpenLoop(struct ath_hal *ah, int i,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

247

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

253

HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: writing closed loop values\n",

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

256

OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

281

ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

300

(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

302

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

305

pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

317

if (IEEE80211_IS_CHAN_2GHZ(chan) && AR_SREV_MERLIN_20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

318

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

320

AH5416(ah)->initPDADC = ((struct calDataPerFreqOpLoop *) pRawDataset)->vpdPdg[0][0];

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

331

AH5416(ah)->initPDADC = 0;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

335

numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

338

ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

341

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

352

if (AR_SREV_MERLIN_20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

353

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

357

ar9280olcGetTxGainIndex(ah, chan,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

360

ar9280olcGetPDADCs(ah, pcdacIdx, txPower / 2, pdadcValues);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

362

ar5416GetGainBoundariesAndPdadcs(ah, chan,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

374

diff = ar9280ChangeGainBoundarySettings(ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

378

if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

380

if (AR_SREV_MERLIN_20_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

381

ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

382

ar9280SetGainBoundariesOpenLoop(ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

386

ar5416SetGainBoundariesClosedLoop(ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

397

ar9280AdjustPDADCValues(ah, pwr_table_offset, diff, pdadcValues);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

400

ar5416WritePdadcValues(ah, i, pdadcValues);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

42

ar9280olcInit(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

47

if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

50

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Setting up TX gain tables.\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

53

AH9280(ah)->originalGain[i] = MS(OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

56

AH9280(ah)->PDADCdelta = 0;

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

60

ar9280olcGetTxGainIndex(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

70

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.c

87

while (pcdac > AH9280(ah)->originalGain[i] &&

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

31

extern void ar9280olcInit(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

34

extern void ar9280olcGetPDADCs(struct ath_hal *ah, uint32_t initTxGain,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

36

extern void ar9280olcGetTxGainIndex(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

40

extern void ar9280GetGainBoundariesAndPdadcs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

46

extern HAL_BOOL ar9280SetPowerCalTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9280_olc.h

51

extern void ar9280olcTemperatureCompensation(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9285.c

42

ar9285GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])

sys/dev/ath/ath_hal/ar9002/ar9285.c

46

nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9285.c

49

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9285.c

53

nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9285.c

56

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9285.c

70

ar9285RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar9002/ar9285.c

72

if (ar9280RfAttach(ah, status) == AH_FALSE)

sys/dev/ath/ath_hal/ar9002/ar9285.c

75

AH_PRIVATE(ah)->ah_getNoiseFloor = ar9285GetNoiseFloor;

sys/dev/ath/ath_hal/ar9002/ar9285.c

81

ar9285RfProbe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285.c

83

return (AR_SREV_KITE(ah));

sys/dev/ath/ath_hal/ar9002/ar9285.h

52

extern void ar9285BTCoexAntennaDiversity(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9285.h

53

extern void ar9285BTCoexSetParameter(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

103

AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

105

ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

116

ar9285_eeprom_print_diversity_settings(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

118

const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

121

ath_hal_printf(ah, "[ath] AR9285 Main LNA config: %s\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

123

ath_hal_printf(ah, "[ath] AR9285 Alt LNA config: %s\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

125

ath_hal_printf(ah, "[ath] LNA diversity %s, Diversity %s\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

141

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

158

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

160

ar5416InitState(AH5416(ah), devid, sc, st, sh, status);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

169

AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

170

AH_PRIVATE(ah)->ah_eepromWrite = NULL;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

171

ah->ah_eepromdata = eepromdata;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

175

AH5416(ah)->ah_initPLL = ar9280InitPLL;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

176

AH5416(ah)->ah_btCoexSetDiversity = ar9285BTCoexAntennaDiversity;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

178

ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

179

ah->ah_configPCIE = ar9285ConfigPCIE;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

180

ah->ah_disablePCIE = ar9285DisablePCIE;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

181

ah->ah_setTxPower = ar9285SetTransmitPower;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

182

ah->ah_setBoardValues = ar9285SetBoardValues;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

183

ah->ah_btCoexSetParameter = ar9285BTCoexSetParameter;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

184

ah->ah_divLnaConfGet = ar9285_antdiv_comb_conf_get;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

185

ah->ah_divLnaConfSet = ar9285_antdiv_comb_conf_set;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

187

AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

188

AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

189

AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

190

AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

191

AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

193

AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

194

AH5416(ah)->ah_writeIni = ar9285WriteIni;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

195

AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

196

AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

200

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

202

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

208

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

209

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

215

val = OS_REG_READ(ah, AR_SREV);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

216

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

221

AH_PRIVATE(ah)->ah_macVersion =

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

223

AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

224

AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

227

if (AR_SREV_KITE_12_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

230

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

235

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

238

ar5416AttachPCIE(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

241

if (AR_SREV_KITE_12_OR_LATER(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

242

AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

243

if (AR_SREV_KITE_11_OR_LATER(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

244

AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

246

ecode = ath_hal_v4kEepromAttach(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

250

if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

251

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

257

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

259

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

260

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

270

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

273

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

274

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

279

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

280

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

285

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

288

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

293

rfStatus = ar9285RfAttach(ah, &ecode);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

295

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

303

if (AR_SREV_9285E_20(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

304

ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

307

switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

309

if (AR_SREV_9285E_20(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

317

if (AR_SREV_9285E_20(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

332

if (!ar9285FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

342

ar9285_eeprom_print_diversity_settings(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

345

if (ar9285_check_div_comb(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

346

ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

351

AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

353

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

355

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

361

AH_PRIVATE(ah)->ah_currentRD =

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

362

ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

367

AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

376

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

378

ar9285AniSetup(ah); /* Anti Noise Immunity */

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

381

AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

382

AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

383

AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

386

ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

388

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

390

return ah;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

392

if (ah != AH_NULL)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

393

ah->ah_detach(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

400

ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

413

if (AR_SREV_9285E_20(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

414

val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

418

OS_REG_WRITE(ah, 0x570c, val);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

423

if (AH_PRIVATE(ah)->ah_ispcie && !restore) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

424

ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

438

OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

440

val = OS_REG_READ(ah, AR_WA);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

459

if (AR_SREV_9285E_20(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

462

OS_REG_WRITE(ah, AR_WA, val);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

473

if (AR_SREV_9285E_20(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

476

OS_REG_WRITE(ah, AR_WA, val);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

479

OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

484

ar9285DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

489

ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

505

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

506

OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

507

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

509

if (AR_SREV_KITE_12_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

510

regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

513

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

523

ar9285FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

525

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

527

if (!ar5416FillCapabilityInfo(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

539

if (ar9285_check_div_comb(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

561

if (AR_SREV_KITE_12_OR_LATER(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

69

static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

71

static void ar9285DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

72

static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

73

static void ar9285WriteIni(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_attach.c

77

ar9285AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

101

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

102

OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

105

regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

118

OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

120

regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

124

OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

129

ar9285BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value)

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

131

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

135

if (AR_SREV_KITE(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

143

ar9285BTCoexAntennaDiversity(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

147

ar5416BTCoexSetParameter(ah, type, value);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

44

ar9285BTCoexAntennaDiversity(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

46

struct ath_hal_5416 *ahp = AH5416(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

50

HALDEBUG(ah, HAL_DEBUG_BT_COEX,

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

57

(AH5212(ah)->ah_diversity == AH_TRUE)) {

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

59

(AH5212(ah)->ah_antControl == HAL_ANT_VARIABLE)) {

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

66

OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

69

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM,

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

71

OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

72

} else if (AH5212(ah)->ah_antControl == HAL_ANT_FIXED_B) {

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

79

OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

85

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM,

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

87

OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0x60000000, 0xf0000000);

sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c

95

OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

102

regVal = OS_REG_READ(ah, 0x7834);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

104

OS_REG_WRITE(ah, 0x7834, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

106

regVal = OS_REG_READ(ah, 0x7834);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

108

reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

110

OS_REG_WRITE(ah, 0x7834, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

113

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

115

reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

116

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

117

offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

118

offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

125

if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) {

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

126

if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

127

AH9285(ah)->pacal_info.max_skipcount =

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

128

2 * AH9285(ah)->pacal_info.max_skipcount;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

129

AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

131

AH9285(ah)->pacal_info.max_skipcount = 1;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

132

AH9285(ah)->pacal_info.skipcount = 0;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

133

AH9285(ah)->pacal_info.prev_offset = offset;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

136

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

137

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

139

regVal = OS_REG_READ(ah, 0x7834);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

141

OS_REG_WRITE(ah, 0x7834, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

142

regVal = OS_REG_READ(ah, 0x9808);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

144

OS_REG_WRITE(ah, 0x9808, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

147

OS_REG_WRITE(ah, regList[i][0], regList[i][1]);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

149

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

153

ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

155

if (AR_SREV_KITE_11_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

156

if (is_reset || !AH9285(ah)->pacal_info.skipcount)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

157

ar9285_hw_pa_cal(ah, is_reset);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

159

AH9285(ah)->pacal_info.skipcount--;

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

165

ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

167

OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

169

OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

170

OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

171

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

173

OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

174

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

175

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

177

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

181

OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

182

OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

183

OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

185

OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

186

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

187

OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

188

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

189

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

191

HALDEBUG(ah, HAL_DEBUG_PERCAL,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

196

OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

197

OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

198

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

204

ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

216

if (!(ar9285_hw_cl_cal(ah, chan)))

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

219

txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7),

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

223

clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

232

reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

234

reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

244

reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

245

if (AR_SREV_9285E_20(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

246

OS_REG_WRITE(ah, AR9285_RF2G5,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

250

OS_REG_WRITE(ah, AR9285_RF2G5,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

254

retv = ar9285_hw_cl_cal(ah, chan);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

255

OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

261

ar9285InitCalHardware(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

264

if (AR_SREV_KITE(ah) && AR_SREV_KITE_10_OR_LATER(ah) &&

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

265

(! ar9285_hw_clc(ah, chan)))

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

49

ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

65

if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) ==

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

69

HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n");

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

72

regList[i][1] = OS_REG_READ(ah, regList[i][0]);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

74

regVal = OS_REG_READ(ah, 0x7834);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

76

OS_REG_WRITE(ah, 0x7834, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

77

regVal = OS_REG_READ(ah, 0x9808);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

79

OS_REG_WRITE(ah, 0x9808, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

81

OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

82

OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

83

OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

84

OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

85

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

86

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

87

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

88

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

89

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

90

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

91

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

92

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

93

ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

94

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

96

OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

98

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.c

99

OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.h

31

extern void ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset);

sys/dev/ath/ath_hal/ar9002/ar9285_cal.h

32

extern HAL_BOOL ar9285InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

103

HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_A\n",

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

112

HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_B\n",

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

121

OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

122

regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

123

regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

128

OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

129

regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

141

if (ar9285_check_div_comb(ah) && AH5212(ah)->ah_diversity == AH_TRUE) {

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

143

HALDEBUG(ah, HAL_DEBUG_DIVERSITY,

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

146

regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

152

OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

62

ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

65

const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

70

HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: not supported\n",

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

76

AH5212(ah)->ah_antControl = settings;

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

77

AH5212(ah)->ah_diversity = (settings == HAL_ANT_VARIABLE);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

86

regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c

94

HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_VARIABLE\n",

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

43

ar9285_antdiv_comb_conf_get(struct ath_hal *ah, HAL_ANT_COMB_CONFIG *antconf)

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

47

regval = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

58

ar9285_antdiv_comb_conf_set(struct ath_hal *ah, HAL_ANT_COMB_CONFIG *antconf)

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

62

regval = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

73

OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

83

ar9285_check_div_comb(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

86

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9285_phy.c

94

if (! AR_SREV_KITE(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_phy.h

35

extern void ar9285_antdiv_comb_conf_set(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_phy.h

37

extern void ar9285_antdiv_comb_conf_get(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_phy.h

39

extern HAL_BOOL ar9285_check_div_comb(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

100

twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

102

HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

105

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

106

AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

109

if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

110

&AH5416(ah)->ah_ratesArray[0],cfgCtl,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

113

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

118

if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

119

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

124

maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb],

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

125

AH5416(ah)->ah_ratesArray[rateHt20_0]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

126

maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

129

maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

133

AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

140

for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

141

AH5416(ah)->ah_ratesArray[i] = (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

143

AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

144

if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

145

AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

146

if (AH5416(ah)->ah_ratesArray[i] < 0)

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

147

AH5416(ah)->ah_ratesArray[i] = 0;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

151

ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

162

AH5416(ah)->ah_ratesArray[rateHt40_0] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

163

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

164

AH5416(ah)->ah_ratesArray[rateHt40_1] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

165

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

166

AH5416(ah)->ah_ratesArray[rateHt40_2] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

167

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

168

AH5416(ah)->ah_ratesArray[rateHt40_3] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

169

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

170

AH5416(ah)->ah_ratesArray[rateHt40_4] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

171

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

172

AH5416(ah)->ah_ratesArray[rateHt40_5] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

173

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

174

AH5416(ah)->ah_ratesArray[rateHt40_6] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

175

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

176

AH5416(ah)->ah_ratesArray[rateHt40_7] +=

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

177

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

181

ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

189

ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

192

OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

195

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0),

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

196

(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) &

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

206

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

208

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

210

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

212

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

216

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

219

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

221

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

224

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

228

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

230

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

233

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

235

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

244

ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

246

const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

255

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

258

ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

261

(void) ar9285SetAntennaSwitch(ah, AH5212(ah)->ah_antControl);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

299

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

300

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

301

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

302

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

303

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

305

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

306

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

307

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

308

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

309

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

311

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

312

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

313

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

314

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

315

OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

317

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

319

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

322

OS_REG_WRITE(ah, AR_PHY_RF_CTL4,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

328

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

331

OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

333

OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

338

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

340

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

347

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

362

if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

365

ath_hal_printf(ah, "[ath]: adjusting cck tx gain factor\n");

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

371

OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

372

OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

373

OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

378

OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

383

OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

384

OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

396

ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

426

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

434

ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

447

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

449

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

451

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

457

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

460

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

462

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

497

owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

54

static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

547

ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

564

ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

582

if (IS_EEP_MINOR_V2(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

585

pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

60

static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

605

ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

608

regChainOffset = ar5416GetRegChainOffset(ah, i);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

612

ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

618

if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

624

ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

628

ar5416WritePdadcValues(ah, i, pdadcValues);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

637

ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

64

static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

668

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

72

ar9285SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

732

if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) {

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

747

if (AR_SREV_MERLIN_20_OR_LATER(ah))

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

79

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

88

HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

91

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

93

AH5416(ah)->ah_ht40PowerIncForPdadc = 2;

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

96

OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray));

sys/dev/ath/ath_hal/ar9002/ar9285_reset.c

97

cfgCtl = ath_hal_getctl(ah, chan);

sys/dev/ath/ath_hal/ar9002/ar9287.c

100

&AH9287(ah)->ah_ini_cckFirJapan2484, 1,

sys/dev/ath/ath_hal/ar9002/ar9287.c

103

ath_hal_ini_write(ah,

sys/dev/ath/ath_hal/ar9002/ar9287.c

104

&AH9287(ah)->ah_ini_cckFirNormal, 1,

sys/dev/ath/ath_hal/ar9002/ar9287.c

109

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);

sys/dev/ath/ath_hal/ar9002/ar9287.c

112

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

115

OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

137

OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,

sys/dev/ath/ath_hal/ar9002/ar9287.c

151

OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);

sys/dev/ath/ath_hal/ar9002/ar9287.c

153

AH_PRIVATE(ah)->ah_curchan = chan;

sys/dev/ath/ath_hal/ar9002/ar9287.c

162

ar9287GetRfBank(struct ath_hal *ah, int bank)

sys/dev/ath/ath_hal/ar9002/ar9287.c

164

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",

sys/dev/ath/ath_hal/ar9002/ar9287.c

174

ar9287SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,

sys/dev/ath/ath_hal/ar9002/ar9287.c

187

ar9287SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,

sys/dev/ath/ath_hal/ar9002/ar9287.c

195

ar9287GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)

sys/dev/ath/ath_hal/ar9002/ar9287.c

222

ar9287GetChannelMaxMinPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287.c

227

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9287.c

267

totalMin = ar9287GetMinPower(ah,&data[i]) - ar9287GetMinPower(ah, &data[last]);

sys/dev/ath/ath_hal/ar9002/ar9287.c

268

*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9287GetMinPower(ah, &data[last])*totalD)/totalD);

sys/dev/ath/ath_hal/ar9002/ar9287.c

273

*minPow = ar9287GetMinPower(ah, &data[i]);

sys/dev/ath/ath_hal/ar9002/ar9287.c

295

ar9287GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])

sys/dev/ath/ath_hal/ar9002/ar9287.c

299

nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9287.c

302

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

306

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9287.c

309

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

313

nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9287.c

316

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

320

nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);

sys/dev/ath/ath_hal/ar9002/ar9287.c

323

HALDEBUG(ah, HAL_DEBUG_NFCAL,

sys/dev/ath/ath_hal/ar9002/ar9287.c

338

ar9287GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)

sys/dev/ath/ath_hal/ar9002/ar9287.c

347

ar9287RfDetach(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287.c

349

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9287.c

357

ar9287RfAttach(struct ath_hal *ah, HAL_STATUS *status)

sys/dev/ath/ath_hal/ar9002/ar9287.c

359

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9287.c

362

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9287.c

367

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9287.c

388

AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;

sys/dev/ath/ath_hal/ar9002/ar9287.c

389

AH_PRIVATE(ah)->ah_getNoiseFloor = ar9287GetNoiseFloor;

sys/dev/ath/ath_hal/ar9002/ar9287.c

39

#define AR9287(ah) ((struct ar9287State *) AH5212(ah)->ah_rfHal)

sys/dev/ath/ath_hal/ar9002/ar9287.c

395

ar9287RfProbe(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287.c

397

return (AR_SREV_KIWI(ah));

sys/dev/ath/ath_hal/ar9002/ar9287.c

43

int16_t ar9287GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);

sys/dev/ath/ath_hal/ar9002/ar9287.c

46

ar9287WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,

sys/dev/ath/ath_hal/ar9002/ar9287.c

49

(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,

sys/dev/ath/ath_hal/ar9002/ar9287.c

73

ar9287SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9287.c

80

OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);

sys/dev/ath/ath_hal/ar9002/ar9287.c

82

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9287.c

85

reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);

sys/dev/ath/ath_hal/ar9002/ar9287.c

97

if (AR_SREV_KIWI_11_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9287.c

99

ath_hal_ini_write(ah,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

102

AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

105

ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

119

struct ath_hal *ah;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

137

ah = &ahp->ah_priv.h;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

139

ar5416InitState(AH5416(ah), devid, sc, st, sh, status);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

142

AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

143

AH_PRIVATE(ah)->ah_eepromWrite = NULL;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

144

ah->ah_eepromdata = eepromdata;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

149

AH5416(ah)->ah_initPLL = ar9280InitPLL;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

151

ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

152

ah->ah_configPCIE = ar9287ConfigPCIE;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

153

ah->ah_disablePCIE = ar9287DisablePCIE;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

155

AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

156

AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

157

AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

158

AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

160

AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

162

AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

163

AH5416(ah)->ah_writeIni = ar9287WriteIni;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

165

ah->ah_setTxPower = ar9287SetTransmitPower;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

166

ah->ah_setBoardValues = ar9287SetBoardValues;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

168

AH5416(ah)->ah_olcInit = ar9287olcInit;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

169

AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

171

AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

172

AH5416(ah)->ah_cal_pacal = ar9287PACal;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

178

AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

179

AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

181

if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

183

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

189

if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

190

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

196

val = OS_REG_READ(ah, AR_SREV);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

197

HALDEBUG(ah, HAL_DEBUG_ATTACH,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

202

AH_PRIVATE(ah)->ah_macVersion =

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

204

AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

205

AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

208

if (! AR_SREV_KIWI_12_OR_LATER(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

209

ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

219

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

226

HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

236

ar5416AttachPCIE(ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

238

ecode = ath_hal_9287EepromAttach(ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

242

if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

243

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

248

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

250

if (!ar5212ChipTest(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

251

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

261

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

264

AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

265

switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

270

if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

271

AH_PRIVATE(ah)->ah_analog5GhzRev =

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

276

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

279

AH_PRIVATE(ah)->ah_analog5GhzRev);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

284

rfStatus = ar9287RfAttach(ah, &ecode);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

286

HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

295

if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

296

ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

306

(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

308

ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

320

if (!ar9287FillCapabilityInfo(ah)) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

325

ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

327

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

333

AH_PRIVATE(ah)->ah_currentRD =

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

334

ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

335

AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

344

OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

346

ar9287AniSetup(ah); /* Anti Noise Immunity */

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

349

AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

350

AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

351

AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

352

AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

353

AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

354

AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

356

ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

358

HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

360

return ah;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

362

if (ah != AH_NULL)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

363

ah->ah_detach(ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

370

ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

372

if (AH_PRIVATE(ah)->ah_ispcie && !restore) {

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

373

ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

375

OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

377

OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

382

ar9287DisablePCIE(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

388

ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

413

OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

414

OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

416

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

417

regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

418

regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

419

regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

428

ar9287FillCapabilityInfo(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

430

HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

432

if (!ar5416FillCapabilityInfo(ah))

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

477

ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

68

static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

70

static void ar9287DisablePCIE(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

71

static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

72

static void ar9287WriteIni(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_attach.c

76

ar9287AniSetup(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

43

ar9287PACal(struct ath_hal *ah, HAL_BOOL is_reset)

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

52

ar9287InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

54

OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

57

OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

58

OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

61

if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

63

HALDEBUG(ah, HAL_DEBUG_RESET,

sys/dev/ath/ath_hal/ar9002/ar9287_cal.c

69

OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

sys/dev/ath/ath_hal/ar9002/ar9287_cal.h

30

extern void ar9287PACal(struct ath_hal *ah, HAL_BOOL is_reset);

sys/dev/ath/ath_hal/ar9002/ar9287_cal.h

31

extern HAL_BOOL ar9287InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

103

ar9287olcGetTxGainIndex(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

112

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

132

ar9287olcSetPDADCs(struct ath_hal *ah, int32_t txPower,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

140

tmpVal = OS_REG_READ(ah, 0xa270);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

143

OS_REG_WRITE(ah, 0xa270, tmpVal);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

147

tmpVal = OS_REG_READ(ah, 0xb270);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

150

OS_REG_WRITE(ah, 0xb270, tmpVal);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

155

tmpVal = OS_REG_READ(ah, 0xa398);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

159

OS_REG_WRITE(ah, 0xa398, tmpVal);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

165

tmpVal = OS_REG_READ(ah, 0xb398);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

169

OS_REG_WRITE(ah, 0xb398, tmpVal);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

45

ar9287olcInit(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

47

OS_REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

49

OS_A_REG_RMW_FIELD(ah, AR9287_AN_TXPC0,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

65

ar9287olcTemperatureCompensation(struct ath_hal *ah)

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

70

rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

73

HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: initPDADC=%d, currPDADC=%d\n",

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

74

__func__, AH5416(ah)->initPDADC, currPDADC);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

76

if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) {

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

85

(void) (ath_hal_eepromGet(ah, AR_EEP_TEMPSENSE_SLOPE, &val));

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

91

delta = ((currPDADC - AH5416(ah)->initPDADC)*4) / slope;

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

93

OS_REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

95

OS_REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.c

98

HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d\n", __func__, delta);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.h

22

extern void ar9287olcInit(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.h

23

extern void ar9287olcTemperatureCompensation(struct ath_hal *ah);

sys/dev/ath/ath_hal/ar9002/ar9287_olc.h

24

extern void ar9287olcGetTxGainIndex(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_olc.h

28

extern void ar9287olcSetPDADCs(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

103

ar9287olcGetTxGainIndex(ah, chan,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

107

ar9287olcSetPDADCs(ah, txPower, i);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

126

ar9287SetPowerPerRateTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

161

ar5416GetChannelCenters(ah, chan, &centers);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

172

ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

182

switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

201

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

203

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

205

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

211

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

214

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

216

ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

251

rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

303

ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

327

ar9287SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

334

struct ath_hal_5212 *ahp = AH5212(ah);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

343

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

346

AH5416(ah)->ah_ht40PowerIncForPdadc = 2;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

349

OS_MEMZERO(AH5416(ah)->ah_ratesArray,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

350

sizeof(AH5416(ah)->ah_ratesArray));

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

351

cfgCtl = ath_hal_getctl(ah, chan);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

355

AH_PRIVATE(ah)->ah_powerLimit);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

357

HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

361

AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

364

if (! ar9287SetPowerPerRateTable(ah, pEepData, chan,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

365

&AH5416(ah)->ah_ratesArray[0],

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

369

HALDEBUG(ah, HAL_DEBUG_ANY,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

375

ar9287SetPowerCalTable(ah, chan, &txPowerIndexOffset);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

378

maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb],

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

379

AH5416(ah)->ah_ratesArray[rateHt20_0]);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

381

AH5416(ah)->ah_ratesArray[rate1l]);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

385

AH5416(ah)->ah_ratesArray[rateHt40_0]);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

388

AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

396

for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

397

AH5416(ah)->ah_ratesArray[i] =

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

399

AH5416(ah)->ah_ratesArray[i]);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

401

AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

402

if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

403

AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

404

if (AH5416(ah)->ah_ratesArray[i] < 0)

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

405

AH5416(ah)->ah_ratesArray[i] = 0;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

409

ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

420

AH5416(ah)->ah_ratesArray[rateHt40_0] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

421

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

422

AH5416(ah)->ah_ratesArray[rateHt40_1] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

423

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

424

AH5416(ah)->ah_ratesArray[rateHt40_2] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

425

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

426

AH5416(ah)->ah_ratesArray[rateHt40_3] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

427

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

428

AH5416(ah)->ah_ratesArray[rateHt40_4] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

429

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

430

AH5416(ah)->ah_ratesArray[rateHt40_5] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

431

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

432

AH5416(ah)->ah_ratesArray[rateHt40_6] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

433

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

434

AH5416(ah)->ah_ratesArray[rateHt40_7] +=

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

435

AH5416(ah)->ah_ht40PowerIncForPdadc;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

439

ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

45

ar9287SetPowerCalTable(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

451

ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

453

const HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

485

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

490

OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

493

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

494

(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

505

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

508

OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

511

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

514

OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

520

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

523

OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

526

OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

529

OS_REG_WRITE(ah, AR_PHY_RF_CTL4,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

535

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

538

OS_REG_RMW_FIELD(ah, AR_PHY_CCA,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

540

OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

543

regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH0);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

55

HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

558

OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

560

regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

574

OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

576

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

578

OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

581

OS_A_REG_RMW_FIELD(ah, AR9287_AN_TOP2,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

64

pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

72

AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

87

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

89

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

91

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.c

93

OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.h

22

extern HAL_BOOL ar9287SetTransmitPower(struct ath_hal *ah,

sys/dev/ath/ath_hal/ar9002/ar9287_reset.h

24

extern HAL_BOOL ar9287SetBoardValues(struct ath_hal *ah,

sys/dev/ath/if_ath.c

1005

if (ath_hal_hasbursting(ah))

sys/dev/ath/if_ath.c

1007

sc->sc_hasbmask = ath_hal_hasbssidmask(ah);

sys/dev/ath/if_ath.c

1008

sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);

sys/dev/ath/if_ath.c

1009

sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);

sys/dev/ath/if_ath.c

1010

sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);

sys/dev/ath/if_ath.c

1013

if (ath_hal_get_rx_tsf_prec(ah, &i)) {

sys/dev/ath/if_ath.c

1020

if (ath_hal_get_tx_tsf_prec(ah, &i)) {

sys/dev/ath/if_ath.c

1025

sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);

sys/dev/ath/if_ath.c

1026

sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);

sys/dev/ath/if_ath.c

1027

sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);

sys/dev/ath/if_ath.c

1051

if (ath_hal_hasfastframes(ah))

sys/dev/ath/if_ath.c

1053

wmodes = ath_hal_getwirelessmodes(ah);

sys/dev/ath/if_ath.c

1057

if (ath_hal_macversion(ah) > 0x78) {

sys/dev/ath/if_ath.c

1129

ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);

sys/dev/ath/if_ath.c

1130

ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);

sys/dev/ath/if_ath.c

1141

if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,

sys/dev/ath/if_ath.c

1149

if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&

sys/dev/ath/if_ath.c

1170

if ((ath_hal_getcapability(ah,

sys/dev/ath/if_ath.c

1187

(void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);

sys/dev/ath/if_ath.c

1188

(void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);

sys/dev/ath/if_ath.c

1199

if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,

sys/dev/ath/if_ath.c

1206

if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,

sys/dev/ath/if_ath.c

1214

(void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,

sys/dev/ath/if_ath.c

1224

if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc))

sys/dev/ath/if_ath.c

1253

ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,

sys/dev/ath/if_ath.c

1275

sc->sc_defant = ath_hal_getdefantenna(ah);

sys/dev/ath/if_ath.c

1281

sc->sc_hasveol = ath_hal_hasveol(ah);

sys/dev/ath/if_ath.c

1286

ath_hal_setmac(ah, ic->ic_macaddr);

sys/dev/ath/if_ath.c

1288

ath_hal_getmac(ah, ic->ic_macaddr);

sys/dev/ath/if_ath.c

1292

ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);

sys/dev/ath/if_ath.c

1401

if (ah)

sys/dev/ath/if_ath.c

1402

ath_hal_detach(ah);

sys/dev/ath/if_ath.c

1795

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

1809

ath_hal_intrset(ah, 0); /* disable interrupts */

sys/dev/ath/if_ath.c

1873

ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);

sys/dev/ath/if_ath.c

1904

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

1959

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

1965

ath_hal_keyreset(ah, i);

sys/dev/ath/if_ath.c

2001

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

2004

ath_hal_enablepcie(ah, 0, 0);

sys/dev/ath/if_ath.c

2022

ath_hal_reset(ah, sc->sc_opmode,

sys/dev/ath/if_ath.c

2054

ath_hal_setledstate(ah, HAL_LED_INIT);

sys/dev/ath/if_ath.c

2083

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

2094

ath_hal_getisr(ah, &status); /* clear ISR */

sys/dev/ath/if_ath.c

2095

ath_hal_intrset(ah, 0); /* disable further intr's */

sys/dev/ath/if_ath.c

2112

if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */

sys/dev/ath/if_ath.c

2126

ath_hal_getisr(ah, &status); /* clear ISR */

sys/dev/ath/if_ath.c

2127

ath_hal_intrset(ah, 0); /* disable further intr's */

sys/dev/ath/if_ath.c

2142

ath_hal_getisr(ah, &status); /* NB: clears ISR too */

sys/dev/ath/if_ath.c

2146

if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,

sys/dev/ath/if_ath.c

2147

ah->ah_syncstate);

sys/dev/ath/if_ath.c

2152

ah->ah_intrstate[0],

sys/dev/ath/if_ath.c

2153

ah->ah_intrstate[1],

sys/dev/ath/if_ath.c

2154

ah->ah_intrstate[2],

sys/dev/ath/if_ath.c

2155

ah->ah_intrstate[3],

sys/dev/ath/if_ath.c

2156

ah->ah_intrstate[6]);

sys/dev/ath/if_ath.c

2160

if (ah->ah_syncstate != 0) {

sys/dev/ath/if_ath.c

2163

if (ah->ah_syncstate & (1 << i))

sys/dev/ath/if_ath.c

2194

ath_hal_intrset(ah, 0); /* disable intr's until reset */

sys/dev/ath/if_ath.c

2251

ath_hal_intrset(ah, imask);

sys/dev/ath/if_ath.c

2278

ath_hal_updatetxtriglevel(ah, AH_TRUE);

sys/dev/ath/if_ath.c

2324

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath.c

2329

ath_hal_mibevent(ah, &sc->sc_halstats);

sys/dev/ath/if_ath.c

2337

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

2476

ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)

sys/dev/ath/if_ath.c

2481

if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))

sys/dev/ath/if_ath.c

2598

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

2628

if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,

sys/dev/ath/if_ath.c

2669

sc->sc_diversity = ath_hal_getdiversity(ah);

sys/dev/ath/if_ath.c

2741

if (ath_hal_gtxto_supported(ah))

sys/dev/ath/if_ath.c

2749

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

2759

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

2794

ath_hal_gpioset(ah, sc->sc_ledpin,

sys/dev/ath/if_ath.c

2798

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath.c

2803

ath_hal_phydisable(ah);

sys/dev/ath/if_ath.c

2949

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

2983

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath.c

3013

if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE,

sys/dev/ath/if_ath.c

3018

sc->sc_diversity = ath_hal_getdiversity(ah);

sys/dev/ath/if_ath.c

3082

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

3136

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

3145

if (!ath_hal_gettpc(ah))

sys/dev/ath/if_ath.c

3146

ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);

sys/dev/ath/if_ath.c

3709

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

3716

ath_hal_setrxfilter(ah, rfilt);

sys/dev/ath/if_ath.c

3719

ath_hal_setopmode(ah);

sys/dev/ath/if_ath.c

3722

ath_hal_setmac(ah, ic->ic_macaddr);

sys/dev/ath/if_ath.c

3735

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

3760

ath_hal_setslottime(ah, usec);

sys/dev/ath/if_ath.c

3964

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

3968

*noise = ath_hal_getchannoise(ah, ni->ni_chan);

sys/dev/ath/if_ath.c

3979

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

3982

ath_hal_setdefantenna(ah, antenna);

sys/dev/ath/if_ath.c

4011

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

4039

qnum = ath_hal_setuptxqueue(ah, qtype, &qi);

sys/dev/ath/if_ath.c

4051

ath_hal_releasetxqueue(ah, qnum);

sys/dev/ath/if_ath.c

4100

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

4106

ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);

sys/dev/ath/if_ath.c

4155

if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {

sys/dev/ath/if_ath.c

4160

ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */

sys/dev/ath/if_ath.c

4436

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

4471

status = ath_hal_txprocdesc(ah, ds, ts);

sys/dev/ath/if_ath.c

5013

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5043

status = (ath_hal_txprocdesc(ah,

sys/dev/ath/if_ath.c

5086

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5095

(caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),

sys/dev/ath/if_ath.c

5096

(int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),

sys/dev/ath/if_ath.c

5097

(int) ath_hal_numtxpending(ah, txq->axq_qnum),

sys/dev/ath/if_ath.c

5102

(void) ath_hal_stoptxdma(ah, txq->axq_qnum);

sys/dev/ath/if_ath.c

5117

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5128

(caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),

sys/dev/ath/if_ath.c

5132

(void) ath_hal_stoptxdma(ah, sc->sc_bhalq);

sys/dev/ath/if_ath.c

5151

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5162

ath_hal_txprocdesc(ah, bf->bf_lastds,

sys/dev/ath/if_ath.c

5177

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5213

ath_hal_gettxdesclinkptr(ah,

sys/dev/ath/if_ath.c

5229

ath_hal_txprocdesc(ah, bf->bf_lastds,

sys/dev/ath/if_ath.c

5268

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5281

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath.c

5306

ath_hal_intrset(ah, 0); /* disable interrupts */

sys/dev/ath/if_ath.c

5322

if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE,

sys/dev/ath/if_ath.c

533

ah->config.no_pll_pwrsave = true;

sys/dev/ath/if_ath.c

5331

sc->sc_diversity = ath_hal_getdiversity(ah);

sys/dev/ath/if_ath.c

5395

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

5403

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

5420

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5448

ath_hal_ani_poll(ah, sc->sc_curchan);

sys/dev/ath/if_ath.c

5454

if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {

sys/dev/ath/if_ath.c

5474

(void) ath_hal_calreset(ah, sc->sc_curchan);

sys/dev/ath/if_ath.c

5485

if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {

sys/dev/ath/if_ath.c

5490

ath_hal_process_noisefloor(ah);

sys/dev/ath/if_ath.c

5562

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5575

ath_hal_setrxfilter(ah, rfilt);

sys/dev/ath/if_ath.c

5576

ath_hal_setassocid(ah, ieee80211broadcastaddr, 0);

sys/dev/ath/if_ath.c

5587

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5596

ath_hal_setrxfilter(ah, rfilt);

sys/dev/ath/if_ath.c

5597

ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);

sys/dev/ath/if_ath.c

5599

ath_hal_process_noisefloor(ah);

sys/dev/ath/if_ath.c

5823

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

5882

ath_hal_setledstate(ah, leds[nstate]); /* set LED */

sys/dev/ath/if_ath.c

5898

ath_hal_intrset(ah,

sys/dev/ath/if_ath.c

5918

ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);

sys/dev/ath/if_ath.c

5922

ath_hal_setrxfilter(ah, rfilt);

sys/dev/ath/if_ath.c

5928

if (ath_hal_keyisvalid(ah, i))

sys/dev/ath/if_ath.c

5929

ath_hal_keysetmac(ah, i, ni->ni_bssid);

sys/dev/ath/if_ath.c

602

struct ath_hal *ah = NULL;

sys/dev/ath/if_ath.c

6033

ath_hal_stoptxdma(ah, sc->sc_bhalq);

sys/dev/ath/if_ath.c

6116

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath.c

6127

ath_hal_process_noisefloor(ah);

sys/dev/ath/if_ath.c

6170

ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);

sys/dev/ath/if_ath.c

6186

ath_hal_setcca(ah, AH_TRUE);

sys/dev/ath/if_ath.c

623

ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,

sys/dev/ath/if_ath.c

625

if (ah == NULL) {

sys/dev/ath/if_ath.c

631

sc->sc_ah = ah;

sys/dev/ath/if_ath.c

6359

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

6367

status = ath_hal_set_channels(ah, chans, nchans,

sys/dev/ath/if_ath.c

6383

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

6389

(void) ath_hal_getchannels(ah, chans, maxchans, nchans,

sys/dev/ath/if_ath.c

6398

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

6404

status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,

sys/dev/ath/if_ath.c

6412

(void) ath_hal_getregdomain(ah, &sc->sc_eerd);

sys/dev/ath/if_ath.c

6413

ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */

sys/dev/ath/if_ath.c

6435

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

6440

rt = ath_hal_getratetable(ah, HAL_MODE_11A);

sys/dev/ath/if_ath.c

6443

rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);

sys/dev/ath/if_ath.c

6446

rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);

sys/dev/ath/if_ath.c

6449

rt = ath_hal_getratetable(ah, HAL_MODE_11B);

sys/dev/ath/if_ath.c

6452

rt = ath_hal_getratetable(ah, HAL_MODE_11G);

sys/dev/ath/if_ath.c

6455

rt = ath_hal_getratetable(ah, HAL_MODE_108A);

sys/dev/ath/if_ath.c

6458

rt = ath_hal_getratetable(ah, HAL_MODE_108G);

sys/dev/ath/if_ath.c

6461

rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);

sys/dev/ath/if_ath.c

6464

rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);

sys/dev/ath/if_ath.c

6467

rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);

sys/dev/ath/if_ath.c

6645

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath.c

6648

ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,

sys/dev/ath/if_ath.c

6649

ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);

sys/dev/ath/if_ath.c

6651

ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);

sys/dev/ath/if_ath.c

674

sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);

sys/dev/ath/if_ath.c

681

if (ath_hal_hwphycounters(ah))

sys/dev/ath/if_ath.c

687

sc->sc_keymax = ath_hal_keycachesize(ah);

sys/dev/ath/if_ath.c

699

ath_hal_keyreset(ah, i);

sys/dev/ath/if_ath.c

901

ath_hal_setledstate(ah, HAL_LED_INIT);

sys/dev/ath/if_ath.c

933

if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))

sys/dev/ath/if_ath.c

935

if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))

sys/dev/ath/if_ath.c

937

if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))

sys/dev/ath/if_ath.c

939

if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))

sys/dev/ath/if_ath.c

941

if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {

sys/dev/ath/if_ath.c

948

if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))

sys/dev/ath/if_ath.c

954

if (ath_hal_hastkipsplit(ah) ||

sys/dev/ath/if_ath.c

955

!ath_hal_settkipsplit(ah, AH_FALSE))

sys/dev/ath/if_ath.c

962

if (ath_hal_haswmetkipmic(ah))

sys/dev/ath/if_ath.c

965

sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);

sys/dev/ath/if_ath.c

973

sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);

sys/dev/ath/if_ath.c

993

if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))

sys/dev/ath/if_ath_beacon.c

1047

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_beacon.c

114

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

1169

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath_beacon.c

1170

ath_hal_beacontimers(ah, &bs);

sys/dev/ath/if_ath_beacon.c

1172

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath_beacon.c

1174

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath_beacon.c

1193

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_beacon.c

1222

ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8);

sys/dev/ath/if_ath_beacon.c

1224

ath_hal_beaconinit(ah, nexttbtt, intval);

sys/dev/ath/if_ath_beacon.c

1226

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath_beacon.c

1236

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_beacon.c

127

return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);

sys/dev/ath/if_ath_beacon.c

138

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

141

ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);

sys/dev/ath/if_ath_beacon.c

165

if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {

sys/dev/ath/if_ath_beacon.c

170

ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */

sys/dev/ath/if_ath_beacon.c

274

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

326

ath_hal_setuptxdesc(ah, ds

sys/dev/ath/if_ath_beacon.c

353

ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4),

sys/dev/ath/if_ath_beacon.c

355

ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags);

sys/dev/ath/if_ath_beacon.c

363

ath_hal_filltxdesc(ah, ds

sys/dev/ath/if_ath_beacon.c

433

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

448

if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {

sys/dev/ath/if_ath_beacon.c

476

tsftu = ath_hal_gettsf32(ah) >> 10;

sys/dev/ath/if_ath_beacon.c

552

if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {

sys/dev/ath/if_ath_beacon.c

560

ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);

sys/dev/ath/if_ath_beacon.c

561

ath_hal_txstart(ah, sc->sc_bhalq);

sys/dev/ath/if_ath_beacon.c

828

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

860

ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);

sys/dev/ath/if_ath_beacon.c

861

ath_hal_txstart(ah, sc->sc_bhalq);

sys/dev/ath/if_ath_beacon.c

930

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_beacon.c

978

ath_hal_set_quiet(ah, 0, 0, 0, HAL_QUIET_DISABLE);

sys/dev/ath/if_ath_btcoex.c

113

ath_hal_btcoex_set_info(ah, &btinfo);

sys/dev/ath/if_ath_btcoex.c

125

ath_hal_btcoex_set_config(ah, &btconfig);

sys/dev/ath/if_ath_btcoex.c

130

ath_hal_btcoex_set_parameter(ah, HAL_BT_COEX_ANTENNA_DIVERSITY, 1);

sys/dev/ath/if_ath_btcoex.c

146

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_btcoex.c

148

if (! ath_hal_btcoex_supported(ah))

sys/dev/ath/if_ath_btcoex.c

170

ath_hal_btcoex_set_info(ah, &btinfo);

sys/dev/ath/if_ath_btcoex.c

182

ath_hal_btcoex_set_config(ah, &btconfig);

sys/dev/ath/if_ath_btcoex.c

187

ath_hal_btcoex_set_parameter(ah, HAL_BT_COEX_ANTENNA_DIVERSITY, 1);

sys/dev/ath/if_ath_btcoex.c

197

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_btcoex.c

199

if (! ath_hal_btcoex_supported(ah))

sys/dev/ath/if_ath_btcoex.c

233

ath_hal_btcoex_set_info(ah, &btinfo);

sys/dev/ath/if_ath_btcoex.c

245

ath_hal_btcoex_set_config(ah, &btconfig);

sys/dev/ath/if_ath_btcoex.c

251

ath_hal_btcoex_set_weights(ah, HAL_BT_COEX_STOMP_NONE);

sys/dev/ath/if_ath_btcoex.c

256

ath_hal_btcoex_set_parameter(ah, HAL_BT_COEX_ANTENNA_DIVERSITY,

sys/dev/ath/if_ath_btcoex.c

344

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_btcoex.c

350

if (! ath_hal_btcoex_supported(ah))

sys/dev/ath/if_ath_btcoex.c

90

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_btcoex.c

92

if (! ath_hal_btcoex_supported(ah))

sys/dev/ath/if_ath_debug.c

103

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_debug.c

115

if (ah->ah_magic == 0x20065416) {

sys/dev/ath/if_ath_debug.c

120

} else if (ah->ah_magic == 0x19741014) {

sys/dev/ath/if_ath_debug.c

203

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_debug.c

224

if (ah->ah_magic == 0x20065416) {

sys/dev/ath/if_ath_ioctl.c

169

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_ioctl.c

210

if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {

sys/dev/ath/if_ath_keycache.c

127

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_keycache.c

141

if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))

sys/dev/ath/if_ath_keycache.c

149

return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);

sys/dev/ath/if_ath_keycache.c

163

return ath_hal_keyset(ah, k->wk_keyix, hk, mac);

sys/dev/ath/if_ath_keycache.c

179

return ath_hal_keyset(ah, k->wk_keyix, hk, mac);

sys/dev/ath/if_ath_keycache.c

185

return ath_hal_keyset(ah, k->wk_keyix, hk, mac);

sys/dev/ath/if_ath_keycache.c

210

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_keycache.c

278

ret = ath_hal_keyset(ah, k->wk_keyix, &hk, mac);

sys/dev/ath/if_ath_keycache.c

505

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_keycache.c

513

ath_hal_keyreset(ah, keyix);

sys/dev/ath/if_ath_keycache.c

519

ath_hal_keyreset(ah, keyix+32); /* RX key */

sys/dev/ath/if_ath_misc.h

68

extern int ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask,

sys/dev/ath/if_ath_rx.c

1076

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx.c

1106

nf = ath_hal_getchannoise(ah, sc->sc_curchan);

sys/dev/ath/if_ath_rx.c

1108

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_rx.c

1161

status = ath_hal_rxprocdesc(ah, ds,

sys/dev/ath/if_ath_rx.c

1211

ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);

sys/dev/ath/if_ath_rx.c

1262

ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);

sys/dev/ath/if_ath_rx.c

1263

ath_hal_rxena(ah); /* enable recv descriptors */

sys/dev/ath/if_ath_rx.c

1265

ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */

sys/dev/ath/if_ath_rx.c

1268

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath_rx.c

1393

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx.c

1397

ath_hal_stoppcurecv(ah); /* disable PCU */

sys/dev/ath/if_ath_rx.c

1398

ath_hal_setrxfilter(ah, 0); /* clear recv filter */

sys/dev/ath/if_ath_rx.c

1399

ath_hal_stopdmarecv(ah); /* disable DMA engine */

sys/dev/ath/if_ath_rx.c

1416

(caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),

sys/dev/ath/if_ath_rx.c

1422

HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,

sys/dev/ath/if_ath_rx.c

1452

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx.c

1478

ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);

sys/dev/ath/if_ath_rx.c

1479

ath_hal_rxena(ah); /* enable recv descriptors */

sys/dev/ath/if_ath_rx.c

1481

ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */

sys/dev/ath/if_ath_rx.c

248

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx.c

318

ath_hal_setuprxdesc(ah, ds

sys/dev/ath/if_ath_rx_edma.c

161

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx_edma.c

168

ath_hal_stoppcurecv(ah);

sys/dev/ath/if_ath_rx_edma.c

169

ath_hal_setrxfilter(ah, 0);

sys/dev/ath/if_ath_rx_edma.c

174

if (ath_hal_stopdmarecv(ah) == AH_TRUE)

sys/dev/ath/if_ath_rx_edma.c

244

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx_edma.c

260

ath_hal_rxena(ah);

sys/dev/ath/if_ath_rx_edma.c

298

ath_hal_startpcurecv(ah, (!! sc->sc_scanning));

sys/dev/ath/if_ath_rx_edma.c

417

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_rx_edma.c

422

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_rx_edma.c

423

nf = ath_hal_getchannoise(ah, sc->sc_curchan);

sys/dev/ath/if_ath_rx_edma.c

464

bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,

sys/dev/ath/if_ath_rx_edma.c

510

ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);

sys/dev/ath/if_ath_sysctl.c

424

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_sysctl.c

432

rfkill = ath_hal_getrfkill(ah);

sys/dev/ath/if_ath_sysctl.c

437

if (rfkill == ath_hal_getrfkill(ah)) { /* unchanged */

sys/dev/ath/if_ath_sysctl.c

441

if (!ath_hal_setrfkill(ah, rfkill)) {

sys/dev/ath/if_ath_sysctl.c

728

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_sysctl.c

741

if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS,

sys/dev/ath/if_ath_sysctl.c

816

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_sysctl.c

874

if (ath_hal_hasdiversity(ah))

sys/dev/ath/if_ath_sysctl.c

888

if (ath_hal_hastpc(ah)) {

sys/dev/ath/if_ath_sysctl.c

899

if (ath_hal_hasrfsilent(ah)) {

sys/dev/ath/if_ath_sysctl.c

920

if (ath_hal_hasintmit(ah)) {

sys/dev/ath/if_ath_sysctl.c

977

if (ath_hal_macversion(ah) > 0x78) {

sys/dev/ath/if_ath_tdma.c

136

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tdma.c

185

ath_hal_beaconsettimers(ah, &bt);

sys/dev/ath/if_ath_tdma.c

252

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tdma.c

290

sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,

sys/dev/ath/if_ath_tdma.c

295

ath_hal_intrset(ah, 0);

sys/dev/ath/if_ath_tdma.c

299

ath_hal_setcca(ah, AH_FALSE); /* disable CCA */

sys/dev/ath/if_ath_tdma.c

308

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath_tdma.c

363

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tdma.c

390

ath_hal_intrset(ah, sc->sc_imask);

sys/dev/ath/if_ath_tdma.c

396

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_tdma.c

430

txtime = ath_hal_pkt_txtime(ah, rt, rs->rs_datalen,

sys/dev/ath/if_ath_tdma.c

474

nexttbtt_full = ath_hal_getnexttbtt(ah);

sys/dev/ath/if_ath_tdma.c

582

tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_tdma.c

583

ath_hal_settsf64(ah, tsf + tsfdelta);

sys/dev/ath/if_ath_tdma.c

616

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tdma.c

627

if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {

sys/dev/ath/if_ath_tdma.c

669

(! ath_hal_stoptxdma(ah, sc->sc_bhalq))) {

sys/dev/ath/if_ath_tdma.c

675

ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);

sys/dev/ath/if_ath_tdma.c

676

ath_hal_txstart(ah, sc->sc_bhalq);

sys/dev/ath/if_ath_tdma.c

685

vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);

sys/dev/ath/if_ath_tx.c

1129

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx.c

1159

dur += ath_hal_computetxtime(ah,

sys/dev/ath/if_ath_tx.c

1182

ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,

sys/dev/ath/if_ath_tx.c

1207

ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,

sys/dev/ath/if_ath_tx.c

1232

ctsduration += ath_hal_computetxtime(ah,

sys/dev/ath/if_ath_tx.c

1239

ctsduration += ath_hal_computetxtime(ah,

sys/dev/ath/if_ath_tx.c

1337

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx.c

1343

ath_hal_setuptxdesc(ah, ds

sys/dev/ath/if_ath_tx.c

367

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx.c

418

ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0);

sys/dev/ath/if_ath_tx.c

420

ath_hal_settxdesclink(ah, (struct ath_desc *) ds,

sys/dev/ath/if_ath_tx.c

429

ath_hal_filltxdesc(ah, (struct ath_desc *) ds

sys/dev/ath/if_ath_tx.c

743

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx.c

845

ath_hal_puttxbuf(ah, txq->axq_qnum, bf_first->bf_daddr);

sys/dev/ath/if_ath_tx.c

880

ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link);

sys/dev/ath/if_ath_tx.c

897

ath_hal_txstart(ah, txq->axq_qnum);

sys/dev/ath/if_ath_tx_edma.c

796

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx_edma.c

818

ath_hal_gettxrawtxdesc(ah, txstatus);

sys/dev/ath/if_ath_tx_edma.c

820

status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);

sys/dev/ath/if_ath_tx_ht.c

594

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx_ht.c

684

series[i].PktDuration = ath_hal_computetxtime(ah,

sys/dev/ath/if_ath_tx_ht.c

722

struct ath_hal *ah = sc->sc_ah;

sys/dev/ath/if_ath_tx_ht.c

742

ath_hal_set11nratescenario(ah, ds,

sys/dev/bce/if_bce.c

9542

struct arphdr *ah;

sys/dev/bce/if_bce.c

9601

ah = (struct arphdr *) (m->m_data + ehlen);

sys/dev/bce/if_bce.c

9602

switch (ntohs(ah->ar_op)) {

sys/dev/bnxt/bnxt_re/ib_verbs.c

1002

struct bnxt_re_ah *ah)

sys/dev/bnxt/bnxt_re/ib_verbs.c

1041

memcpy(ah->qplib_ah.dmac, dmac, ETH_ALEN);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1051

struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ibah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1065

ah->rdev = rdev;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1066

ah->qplib_ah.pd = &pd->qplib_pd;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1070

memcpy(ah->qplib_ah.dgid.data, ah_attr->grh.dgid.raw,

sys/dev/bnxt/bnxt_re/ib_verbs.c

1072

ah->qplib_ah.sgid_index = _get_sgid_index(rdev, ah_attr->grh.sgid_index);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1073

if (ah->qplib_ah.sgid_index == 0xFF) {

sys/dev/bnxt/bnxt_re/ib_verbs.c

1078

ah->qplib_ah.host_sgid_index = ah_attr->grh.sgid_index;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1079

ah->qplib_ah.traffic_class = ah_attr->grh.traffic_class;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1080

ah->qplib_ah.flow_label = ah_attr->grh.flow_label;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1081

ah->qplib_ah.hop_limit = ah_attr->grh.hop_limit;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1082

ah->qplib_ah.sl = ah_attr->sl;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1086

ah->qplib_ah.nw_type = ah_info.nw_type;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1088

rc = bnxt_re_init_dmac(rdev, ah_attr, &ah_info, is_user, ah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1092

rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, block);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1109

*wrptr = ah->qplib_ah.id;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1130

struct bnxt_re_ah *ah = to_bnxt_re(ib_ah, struct bnxt_re_ah, ibah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1132

memcpy(ah_attr->grh.dgid.raw, ah->qplib_ah.dgid.data,

sys/dev/bnxt/bnxt_re/ib_verbs.c

1134

ah_attr->grh.sgid_index = ah->qplib_ah.host_sgid_index;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1135

ah_attr->grh.traffic_class = ah->qplib_ah.traffic_class;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1136

ah_attr->sl = ah->qplib_ah.sl;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1137

memcpy(ROCE_DMAC(ah_attr), ah->qplib_ah.dmac, ETH_ALEN);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1799

struct bnxt_re_ah *ah;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1803

ah = kzalloc(sizeof(*ah), GFP_KERNEL);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1804

if (!ah) {

sys/dev/bnxt/bnxt_re/ib_verbs.c

1808

memset(ah, 0, sizeof(*ah));

sys/dev/bnxt/bnxt_re/ib_verbs.c

1809

ah->rdev = rdev;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1810

ah->qplib_ah.pd = &pd->qplib_pd;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1817

memcpy(ah->qplib_ah.dgid.data, &sgid.raw,

sys/dev/bnxt/bnxt_re/ib_verbs.c

1819

ah->qplib_ah.sgid_index = 0;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1821

ah->qplib_ah.traffic_class = 0;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1822

ah->qplib_ah.flow_label = 0;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1823

ah->qplib_ah.hop_limit = 1;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1824

ah->qplib_ah.sl = 0;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1826

ether_addr_copy(ah->qplib_ah.dmac, rdev->dev_addr);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1828

ah->qplib_ah.dmac[0], ah->qplib_ah.dmac[1], ah->qplib_ah.dmac[2],

sys/dev/bnxt/bnxt_re/ib_verbs.c

1829

ah->qplib_ah.dmac[3], ah->qplib_ah.dmac[4], ah->qplib_ah.dmac[5]);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1831

rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, true);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1837

dev_dbg(rdev_to_dev(rdev), "AH ID = %d\n", ah->qplib_ah.id);

sys/dev/bnxt/bnxt_re/ib_verbs.c

1840

return ah;

sys/dev/bnxt/bnxt_re/ib_verbs.c

1842

kfree(ah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

2553

memcpy(data, qp->qplib_qp.ah.dmac, ETH_ALEN);

sys/dev/bnxt/bnxt_re/ib_verbs.c

2559

memcpy(data + buf_len, qp->qplib_qp.ah.dgid.data + ip_off, addr_len);

sys/dev/bnxt/bnxt_re/ib_verbs.c

2582

if (ipv6_addr_v4mapped((struct in6_addr *)&qp->qplib_qp.ah.dgid)) {

sys/dev/bnxt/bnxt_re/ib_verbs.c

2584

qp->qp_info_entry.d_ip.ipv4_addr = ipv4_from_gid(qp->qplib_qp.ah.dgid.data);

sys/dev/bnxt/bnxt_re/ib_verbs.c

2588

memcpy(&qp->qp_info_entry.d_ip.ipv6_addr, qp->qplib_qp.ah.dgid.data,

sys/dev/bnxt/bnxt_re/ib_verbs.c

2728

memcpy(qp->qplib_qp.ah.dgid.data, qp_attr->ah_attr.grh.dgid.raw,

sys/dev/bnxt/bnxt_re/ib_verbs.c

2729

sizeof(qp->qplib_qp.ah.dgid.data));

sys/dev/bnxt/bnxt_re/ib_verbs.c

2730

qp->qplib_qp.ah.flow_label = qp_attr->ah_attr.grh.flow_label;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2731

qp->qplib_qp.ah.sgid_index = _get_sgid_index(rdev,

sys/dev/bnxt/bnxt_re/ib_verbs.c

2733

qp->qplib_qp.ah.host_sgid_index = qp_attr->ah_attr.grh.sgid_index;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2734

qp->qplib_qp.ah.hop_limit = qp_attr->ah_attr.grh.hop_limit;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2735

qp->qplib_qp.ah.traffic_class =

sys/dev/bnxt/bnxt_re/ib_verbs.c

2737

qp->qplib_qp.ah.sl = qp_attr->ah_attr.sl;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2738

ether_addr_copy(qp->qplib_qp.ah.dmac, ROCE_DMAC(&qp_attr->ah_attr));

sys/dev/bnxt/bnxt_re/ib_verbs.c

2937

qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2951

memcpy(qp_attr->ah_attr.grh.dgid.raw, qplib_qp->ah.dgid.data,

sys/dev/bnxt/bnxt_re/ib_verbs.c

2952

sizeof(qplib_qp->ah.dgid.data));

sys/dev/bnxt/bnxt_re/ib_verbs.c

2953

qp_attr->ah_attr.grh.flow_label = qplib_qp->ah.flow_label;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2954

qp_attr->ah_attr.grh.sgid_index = qplib_qp->ah.host_sgid_index;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2955

qp_attr->ah_attr.grh.hop_limit = qplib_qp->ah.hop_limit;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2956

qp_attr->ah_attr.grh.traffic_class = qplib_qp->ah.traffic_class;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2957

qp_attr->ah_attr.sl = qplib_qp->ah.sl;

sys/dev/bnxt/bnxt_re/ib_verbs.c

2958

ether_addr_copy(ROCE_DMAC(&qp_attr->ah_attr), qplib_qp->ah.dmac);

sys/dev/bnxt/bnxt_re/ib_verbs.c

3007

struct bnxt_re_ah *ah = to_bnxt_re(ud_wr(wr)->ah, struct bnxt_re_ah,

sys/dev/bnxt/bnxt_re/ib_verbs.c

3009

struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;

sys/dev/bnxt/bnxt_re/ib_verbs.c

3026

ptmac = ah->qplib_ah.dmac;

sys/dev/bnxt/bnxt_re/ib_verbs.c

3287

struct bnxt_re_ah *ah = NULL;

sys/dev/bnxt/bnxt_re/ib_verbs.c

3290

ah = to_bnxt_re(ud_wr(wr)->ah, struct bnxt_re_ah, ibah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

3293

wqe->send.avid = ah->qplib_ah.id;

sys/dev/bnxt/bnxt_re/ib_verbs.c

4504

udwr.ah = &gsi_sah->ibah;

sys/dev/bnxt/bnxt_re/ib_verbs.c

908

struct bnxt_re_ah *ah = to_bnxt_re(ib_ah, struct bnxt_re_ah, ibah);

sys/dev/bnxt/bnxt_re/ib_verbs.c

909

struct bnxt_re_dev *rdev = ah->rdev;

sys/dev/bnxt/bnxt_re/ib_verbs.c

915

rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);

sys/dev/bnxt/bnxt_re/ib_verbs.c

919

__func__, ah->qplib_ah.id, block, rc);

sys/dev/bnxt/bnxt_re/ib_verbs.c

945

struct ib_global_route *grh, struct ib_ah *ah)

sys/dev/bnxt/bnxt_re/ib_verbs.h

313

int bnxt_re_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);

sys/dev/bnxt/bnxt_re/ib_verbs.h

314

int bnxt_re_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);

sys/dev/bnxt/bnxt_re/ib_verbs.h

383

struct ib_global_route *grh, struct ib_ah *ah);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1333

qp->ah.sgid_index = 0;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1420

memcpy(temp32, qp->ah.dgid.data, sizeof(struct bnxt_qplib_gid));

sys/dev/bnxt/bnxt_re/qplib_fp.c

1427

req.flow_label = cpu_to_le32(qp->ah.flow_label);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1430

req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[qp->ah.sgid_index]);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1433

req.hop_limit = qp->ah.hop_limit;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1436

req.traffic_class = qp->ah.traffic_class;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1439

memcpy(req.dest_mac, qp->ah.dmac, 6);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1552

memcpy(qp->ah.dgid.data, temp32, sizeof(qp->ah.dgid.data));

sys/dev/bnxt/bnxt_re/qplib_fp.c

1554

qp->ah.flow_label = le32_to_cpu(sb->flow_label);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1556

qp->ah.sgid_index = 0;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1559

qp->ah.sgid_index = i;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1568

qp->ah.hop_limit = sb->hop_limit;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1569

qp->ah.traffic_class = sb->traffic_class;

sys/dev/bnxt/bnxt_re/qplib_fp.c

1570

memcpy(qp->ah.dmac, sb->dest_mac, ETH_ALEN);

sys/dev/bnxt/bnxt_re/qplib_fp.c

1571

qp->ah.vlan_id = le16_to_cpu(sb->path_mtu_dest_vlan_id) &

sys/dev/bnxt/bnxt_re/qplib_fp.h

362

struct bnxt_qplib_ah ah;

sys/dev/bnxt/bnxt_re/qplib_sp.c

461

int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,

sys/dev/bnxt/bnxt_re/qplib_sp.c

475

memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid));

sys/dev/bnxt/bnxt_re/qplib_sp.c

481

req.type = ah->nw_type;

sys/dev/bnxt/bnxt_re/qplib_sp.c

482

req.hop_limit = ah->hop_limit;

sys/dev/bnxt/bnxt_re/qplib_sp.c

483

req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]);

sys/dev/bnxt/bnxt_re/qplib_sp.c

484

req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label &

sys/dev/bnxt/bnxt_re/qplib_sp.c

487

req.pd_id = cpu_to_le32(ah->pd->id);

sys/dev/bnxt/bnxt_re/qplib_sp.c

488

req.traffic_class = ah->traffic_class;

sys/dev/bnxt/bnxt_re/qplib_sp.c

491

memcpy(temp16, ah->dmac, ETH_ALEN);

sys/dev/bnxt/bnxt_re/qplib_sp.c

502

ah->id = le32_to_cpu(resp.xid);

sys/dev/bnxt/bnxt_re/qplib_sp.c

504

if (!_is_chip_gen_p5_p7(res->cctx) && !ah->id)

sys/dev/bnxt/bnxt_re/qplib_sp.c

510

int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,

sys/dev/bnxt/bnxt_re/qplib_sp.c

522

req.ah_cid = cpu_to_le32(ah->id);

sys/dev/bnxt/bnxt_re/qplib_sp.h

360

int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,

sys/dev/bnxt/bnxt_re/qplib_sp.h

362

int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,

sys/dev/cxgbe/iw_cxgbe/provider.c

59

static int c4iw_ah_create(struct ib_ah *ah,

sys/dev/cxgbe/iw_cxgbe/provider.c

66

static void c4iw_ah_destroy(struct ib_ah *ah, u32 flags)

sys/dev/irdma/irdma_cm.c

1323

if (sqbuf->ah)

sys/dev/irdma/irdma_cm.c

1324

atomic_inc(&sqbuf->ah->ah_info.ah_refcnt);

sys/dev/irdma/irdma_cm.c

1494

if (send_entry->sqbuf->ah)

sys/dev/irdma/irdma_cm.c

1495

atomic_inc(&send_entry->sqbuf->ah->ah_info.ah_refcnt);

sys/dev/irdma/irdma_cm.c

1602

if (sqbuf->ah)

sys/dev/irdma/irdma_cm.c

1603

atomic_inc(&sqbuf->ah->ah_info.ah_refcnt);

sys/dev/irdma/irdma_cm.c

2192

&cm_node->ah))

sys/dev/irdma/irdma_cm.c

2195

atomic_set(&cm_node->ah->ah_info.ah_refcnt, 1);

sys/dev/irdma/irdma_cm.c

2207

struct irdma_sc_ah *ah = container_of(work, struct irdma_sc_ah, ah_free_work);

sys/dev/irdma/irdma_cm.c

2209

irdma_puda_free_ah(ah->dev, ah);

sys/dev/irdma/irdma_cm.c

2221

if (cm_node->ah) {

sys/dev/irdma/irdma_cm.c

2222

if (!atomic_dec_and_test(&cm_node->ah->ah_info.ah_refcnt))

sys/dev/irdma/irdma_cm.c

2225

INIT_WORK(&cm_node->ah->ah_free_work, irdma_cm_free_ah_worker);

sys/dev/irdma/irdma_cm.c

2226

queue_work(iwdev->cleanup_wq, &cm_node->ah->ah_free_work);

sys/dev/irdma/irdma_cm.c

2227

cm_node->ah = NULL;

sys/dev/irdma/irdma_cm.c

449

if (!cm_node->ah || !cm_node->ah->ah_info.ah_valid) {

sys/dev/irdma/irdma_cm.c

460

sqbuf->ah_id = cm_node->ah->ah_info.ah_idx;

sys/dev/irdma/irdma_cm.c

461

sqbuf->ah = cm_node->ah;

sys/dev/irdma/irdma_cm.h

322

struct irdma_sc_ah *ah;

sys/dev/irdma/irdma_kcompat.c

1214

struct irdma_ah *ah = to_iwah(ibah);

sys/dev/irdma/irdma_kcompat.c

1216

irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,

sys/dev/irdma/irdma_kcompat.c

1217

false, NULL, ah);

sys/dev/irdma/irdma_kcompat.c

1220

ah->sc_ah.ah_info.ah_idx);

sys/dev/irdma/irdma_kcompat.c

534

struct irdma_ah *ah = container_of(ib_ah, struct irdma_ah, ibah);

sys/dev/irdma/irdma_kcompat.c

557

ah->pd = pd;

sys/dev/irdma/irdma_kcompat.c

558

sc_ah = &ah->sc_ah;

sys/dev/irdma/irdma_kcompat.c

562

ah->sgid_index = attr->grh.sgid_index;

sys/dev/irdma/irdma_kcompat.c

563

memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid));

sys/dev/irdma/irdma_kcompat.c

577

ah->av.attrs = *attr;

sys/dev/irdma/irdma_kcompat.c

578

ah->av.net_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);

sys/dev/irdma/irdma_kcompat.c

597

dmac, ah->av.net_type);

sys/dev/irdma/irdma_kcompat.c

615

uresp.ah_id = ah->sc_ah.ah_info.ah_idx;

sys/dev/irdma/irdma_kcompat.c

618

irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah,

sys/dev/irdma/irdma_kcompat.c

619

IRDMA_OP_AH_DESTROY, false, NULL, ah);

sys/dev/irdma/irdma_puda.c

1531

txbuf->ah_id = pfpdu->ah->ah_info.ah_idx;

sys/dev/irdma/irdma_puda.c

1622

txbuf->ah_id = pfpdu->ah->ah_info.ah_idx;

sys/dev/irdma/irdma_puda.c

1708

&qp->pfpdu.ah);

sys/dev/irdma/irdma_puda.c

1790

if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) {

sys/dev/irdma/irdma_puda.c

1792

if (!pfpdu->ah)

sys/dev/irdma/irdma_puda.c

1798

else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid)

sys/dev/irdma/irdma_puda.c

1864

if (qp->pfpdu.ah) {

sys/dev/irdma/irdma_puda.c

1865

irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah);

sys/dev/irdma/irdma_puda.c

1866

qp->pfpdu.ah = NULL;

sys/dev/irdma/irdma_puda.h

112

struct irdma_sc_ah *ah;

sys/dev/irdma/irdma_puda.h

217

struct irdma_sc_ah **ah);

sys/dev/irdma/irdma_puda.h

218

void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah);

sys/dev/irdma/irdma_type.h

375

struct irdma_sc_ah *ah;

sys/dev/irdma/irdma_uda.h

80

static inline void irdma_sc_init_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)

sys/dev/irdma/irdma_uda.h

82

ah->dev = dev;

sys/dev/irdma/irdma_utils.c

1910

struct irdma_sc_ah *sc_ah = qp->pfpdu.ah;

sys/dev/irdma/irdma_utils.c

1935

struct irdma_sc_ah *sc_ah = cm_node->ah;

sys/dev/irdma/irdma_utils.c

1960

struct irdma_sc_ah *ah;

sys/dev/irdma/irdma_utils.c

1964

ah = kzalloc(sizeof(*ah), GFP_ATOMIC);

sys/dev/irdma/irdma_utils.c

1965

*ah_ret = ah;

sys/dev/irdma/irdma_utils.c

1966

if (!ah)

sys/dev/irdma/irdma_utils.c

1974

ah->dev = dev;

sys/dev/irdma/irdma_utils.c

1975

ah->ah_info = *ah_info;

sys/dev/irdma/irdma_utils.c

1978

err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,

sys/dev/irdma/irdma_utils.c

1981

err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,

sys/dev/irdma/irdma_utils.c

1989

irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);

sys/dev/irdma/irdma_utils.c

1991

kfree(ah);

sys/dev/irdma/irdma_utils.c

2002

irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)

sys/dev/irdma/irdma_utils.c

2006

if (!ah)

sys/dev/irdma/irdma_utils.c

2009

if (ah->ah_info.ah_valid) {

sys/dev/irdma/irdma_utils.c

2010

irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_DESTROY, false, NULL, NULL);

sys/dev/irdma/irdma_utils.c

2011

irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);

sys/dev/irdma/irdma_utils.c

2014

kfree(ah);

sys/dev/irdma/irdma_verbs.c

2447

struct irdma_ah *ah;

sys/dev/irdma/irdma_verbs.c

2492

ah = to_iwah(ud_wr(ib_wr)->ah);

sys/dev/irdma/irdma_verbs.c

2493

info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx;

sys/dev/irdma/irdma_verbs.c

3237

struct irdma_ah *ah = to_iwah(ibah);

sys/dev/irdma/irdma_verbs.c

3240

if (ah->av.attrs.ah_flags & IB_AH_GRH) {

sys/dev/irdma/irdma_verbs.c

3242

ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label;

sys/dev/irdma/irdma_verbs.c

3243

ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos;

sys/dev/irdma/irdma_verbs.c

3244

ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl;

sys/dev/irdma/irdma_verbs.c

3245

ah_attr->grh.sgid_index = ah->sgid_index;

sys/dev/irdma/irdma_verbs.c

3246

ah_attr->grh.sgid_index = ah->sgid_index;

sys/dev/irdma/irdma_verbs.c

3247

memcpy(&ah_attr->grh.dgid, &ah->dgid,

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

412

struct ib_ah *ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

742

int mlx4_ib_create_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr, u32 flags,

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

744

int mlx4_ib_create_ah_slave(struct ib_ah *ah, struct ib_ah_attr *ah_attr,

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

747

void mlx4_ib_destroy_ah(struct ib_ah *ah, u32 flags);

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

797

static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah)

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

799

u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3;

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

801

if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET)

sys/dev/mlx4/mlx4_ib/mlx4_ib.h

804

return !!(ah->av.ib.g_slid & 0x80);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

101

memcpy(ah->av.eth.s_mac, if_getlladdr(gid_attr.ndev), ETH_ALEN);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

106

ah->av.eth.port_pd = cpu_to_be32(to_mpd(pd)->pdn | (ah_attr->port_num << 24));

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

110

ah->av.eth.gid_index = ret;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

111

ah->av.eth.vlan = cpu_to_be16(vlan_tag);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

112

ah->av.eth.hop_limit = ah_attr->grh.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

114

ah->av.eth.stat_rate = ah_attr->static_rate + MLX4_STAT_RATE_OFFSET;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

115

while (ah->av.eth.stat_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

116

!(1 << ah->av.eth.stat_rate & dev->caps.stat_rate_support))

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

117

--ah->av.eth.stat_rate;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

124

ah->av.ib.dlid = cpu_to_be16(0xc000);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

126

memcpy(ah->av.eth.dgid, ah_attr->grh.dgid.raw, 16);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

127

ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 29);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

153

int mlx4_ib_create_ah_slave(struct ib_ah *ah, struct ib_ah_attr *ah_attr,

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

157

struct mlx4_ib_ah *mah = to_mah(ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

161

ret = mlx4_ib_create_ah(ah, &slave_attr, 0, NULL);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

168

if (rdma_port_get_link_layer(ah->pd->device, ah_attr->port_num) == IB_LINK_LAYER_ETHERNET)

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

180

struct mlx4_ib_ah *ah = to_mah(ibah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

184

ah_attr->port_num = be32_to_cpu(ah->av.ib.port_pd) >> 24;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

187

ah_attr->sl = be32_to_cpu(ah->av.eth.sl_tclass_flowlabel) >> 29;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

189

ah_attr->sl = be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

191

ah_attr->dlid = ll == IB_LINK_LAYER_INFINIBAND ? be16_to_cpu(ah->av.ib.dlid) : 0;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

192

if (ah->av.ib.stat_rate)

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

193

ah_attr->static_rate = ah->av.ib.stat_rate - MLX4_STAT_RATE_OFFSET;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

194

ah_attr->src_path_bits = ah->av.ib.g_slid & 0x7F;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

196

if (mlx4_ib_ah_grh_present(ah)) {

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

200

be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

202

be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) & 0xfffff;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

203

ah_attr->grh.hop_limit = ah->av.ib.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

204

ah_attr->grh.sgid_index = ah->av.ib.gid_index;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

205

memcpy(ah_attr->grh.dgid.raw, ah->av.ib.dgid, 16);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

211

void mlx4_ib_destroy_ah(struct ib_ah *ah, u32 flags)

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

48

struct mlx4_ib_ah *ah = to_mah(ib_ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

51

ah->av.ib.port_pd = cpu_to_be32(to_mpd(pd)->pdn | (ah_attr->port_num << 24));

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

52

ah->av.ib.g_slid = ah_attr->src_path_bits;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

53

ah->av.ib.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

55

ah->av.ib.g_slid |= 0x80;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

56

ah->av.ib.gid_index = ah_attr->grh.sgid_index;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

57

ah->av.ib.hop_limit = ah_attr->grh.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

58

ah->av.ib.sl_tclass_flowlabel |=

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

61

memcpy(ah->av.ib.dgid, ah_attr->grh.dgid.raw, 16);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

64

ah->av.ib.dlid = cpu_to_be16(ah_attr->dlid);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

66

ah->av.ib.stat_rate = ah_attr->static_rate + MLX4_STAT_RATE_OFFSET;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

67

while (ah->av.ib.stat_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

68

!(1 << ah->av.ib.stat_rate & dev->caps.stat_rate_support))

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

69

--ah->av.ib.stat_rate;

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

78

struct mlx4_ib_ah *ah = to_mah(ib_ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

90

rdma_get_mcast_mac(&in6, ah->av.eth.mac);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

92

memcpy(ah->av.eth.mac, ah_attr->dmac, ETH_ALEN);

sys/dev/mlx4/mlx4_ib/mlx4_ib_ah.c

98

eth_zero_addr(ah->av.eth.s_mac);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1334

struct ib_ah *ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1359

ah = rdma_zalloc_drv_obj(sqp_ctx->pd->device, ib_ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1360

if (!ah)

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1363

ah->device = sqp_ctx->pd->device;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1364

ah->pd = sqp_ctx->pd;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1367

ret = mlx4_ib_create_ah_slave(ah, attr,

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1384

kfree(sqp->tx_ring[wire_tx_ix].ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1385

sqp->tx_ring[wire_tx_ix].ah = ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1402

wr.ah = ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1421

sqp->tx_ring[wire_tx_ix].ah = NULL;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1423

kfree(ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1449

struct mlx4_ib_ah ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1529

memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1530

ah.ibah.device = ctx->ib_dev;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1532

port = be32_to_cpu(ah.av.ib.port_pd) >> 24;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1536

ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1538

mlx4_ib_query_ah(&ah.ibah, &ah_attr);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1620

tun_qp->tx_ring[i].ah = NULL;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1681

if (tun_qp->tx_ring[i].ah)

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1682

ib_destroy_ah(tun_qp->tx_ring[i].ah, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1715

(MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1716

tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1732

(MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1733

tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1871

(MLX4_NUM_TUNNEL_BUFS - 1)].ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1872

sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1901

(MLX4_NUM_TUNNEL_BUFS - 1)].ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

1902

sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

401

if ((send_buf->ah = dev->sm_ah[port_num - 1]))

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

493

struct ib_ah *ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

543

ah = ib_create_ah(tun_ctx->pd, &attr, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

544

if (IS_ERR(ah))

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

559

if (tun_qp->tx_ring[tun_tx_ix].ah)

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

560

ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

561

tun_qp->tx_ring[tun_tx_ix].ah = ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

615

wr.ah = ah;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

633

tun_qp->tx_ring[tun_tx_ix].ah = NULL;

sys/dev/mlx4/mlx4_ib/mlx4_ib_mad.c

635

ib_destroy_ah(ah, 0);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1394

static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1405

path->grh_mylmc = ah->src_path_bits & 0x7f;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1406

path->rlid = cpu_to_be16(ah->dlid);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1407

if (ah->static_rate) {

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1408

path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1415

if (ah->ah_flags & IB_AH_GRH) {

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1418

ah->grh.sgid_index);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1428

path->hop_limit = ah->grh.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1430

cpu_to_be32((ah->grh.traffic_class << 20) |

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1431

(ah->grh.flow_label));

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1432

memcpy(path->rgid, ah->grh.dgid.raw, 16);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1436

if (!(ah->ah_flags & IB_AH_GRH))

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1440

((port - 1) << 6) | ((ah->sl & 7) << 3);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1500

memcpy(path->dmac, ah->dmac, 6);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1506

((port - 1) << 6) | ((ah->sl & 0xf) << 2);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2305

struct mlx4_ib_ah *ah = to_mah(wr->ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2330

be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2332

cpu_to_be16(ah->av.ib.g_slid & 0x7f);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2334

cpu_to_be16(ah->av.ib.g_slid & 0x7f);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2434

struct mlx4_ib_ah *ah = to_mah(wr->ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2454

is_grh = mlx4_ib_ah_grh_present(ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2463

be32_to_cpu(ah->av.ib.port_pd) >> 24,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2464

ah->av.ib.gid_index, &sgid.raw[0]);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2469

be32_to_cpu(ah->av.ib.port_pd) >> 24,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2470

ah->av.ib.gid_index, &sgid,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2491

if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2492

vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2503

be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2504

sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2505

sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2510

(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2512

ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2513

sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2528

guid_cache[ah->av.ib.gid_index];

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2531

be32_to_cpu(ah->av.ib.port_pd) >> 24,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2532

ah->av.ib.gid_index,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2537

ah->av.ib.dgid, 16);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2542

(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2545

sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2549

memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2566

if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2588

u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2595

ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2596

memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2597

memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2598

memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2775

memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2778

dseg->vlan = to_mah(wr->ah)->av.eth.vlan;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2779

memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2787

union mlx4_ext_av *av = &to_mah(wr->ah)->av;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2810

struct mlx4_ib_ah *ah = to_mah(wr->ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2814

memcpy(&hdr.av, &ah->av, sizeof hdr.av);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2818

memcpy(hdr.mac, ah->av.eth.mac, 6);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2819

hdr.vlan = ah->av.eth.vlan;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2956

struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2961

be32_to_cpu(ah->av.ib.port_pd) >> 24,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2962

ah->av.ib.gid_index, &gid,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2970

ah->av.ib.gid_index);

sys/dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h

397

u8 ah[0x1];

sys/dev/mlx5/mlx5_ib/mlx5_ib.h

904

int mlx5_ib_create_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr, u32 flags,

sys/dev/mlx5/mlx5_ib/mlx5_ib.h

907

void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

101

struct mlx5_ib_ah *ah = to_mah(ibah);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

106

tmp = be32_to_cpu(ah->av.grh_gid_fl);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

111

memcpy(&ah_attr->grh.dgid, ah->av.rgid, 16);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

112

ah_attr->grh.hop_limit = ah->av.hop_limit;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

113

ah_attr->grh.traffic_class = ah->av.tclass;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

115

ah_attr->dlid = be16_to_cpu(ah->av.rlid);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

116

ah_attr->static_rate = ah->av.stat_rate_sl >> 4;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

117

ah_attr->sl = ah->av.stat_rate_sl & 0xf;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

122

void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

32

struct mlx5_ib_ah *ah,

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

37

memcpy(ah->av.rgid, &ah_attr->grh.dgid, 16);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

38

ah->av.grh_gid_fl = cpu_to_be32(ah_attr->grh.flow_label |

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

41

ah->av.hop_limit = ah_attr->grh.hop_limit;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

42

ah->av.tclass = ah_attr->grh.traffic_class;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

45

ah->av.stat_rate_sl = (ah_attr->static_rate << 4);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

48

memcpy(ah->av.rmac, ah_attr->dmac, sizeof(ah_attr->dmac));

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

49

ah->av.udp_sport =

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

53

ah->av.stat_rate_sl |= (ah_attr->sl & 0x7) << 1;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

55

ah->av.rlid = cpu_to_be16(ah_attr->dlid);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

56

ah->av.fl_mlid = ah_attr->src_path_bits & 0x7f;

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

57

ah->av.stat_rate_sl |= (ah_attr->sl & 0xf);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

65

struct mlx5_ib_ah *ah = to_mah(ibah);

sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c

95

create_ib_ah(dev, ah, ah_attr, ll);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2325

const struct ib_ah_attr *ah,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2338

if (ah->ah_flags & IB_AH_GRH) {

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2339

if (ah->grh.sgid_index >=

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2342

ah->grh.sgid_index,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2349

if (!(ah->ah_flags & IB_AH_GRH))

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2351

err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2355

memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2357

ah->grh.sgid_index);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2358

path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2360

path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2365

path->rlid = cpu_to_be16(ah->dlid);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2366

path->grh_mlid = ah->src_path_bits & 0x7f;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2367

if (ah->ah_flags & IB_AH_GRH)

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2369

path->dci_cfi_prio_sl = ah->sl & 0xf;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2372

if (ah->ah_flags & IB_AH_GRH) {

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2373

path->mgid_index = ah->grh.sgid_index;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2374

path->hop_limit = ah->grh.hop_limit;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2376

cpu_to_be32((ah->grh.traffic_class << 20) |

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2377

(ah->grh.flow_label));

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2378

memcpy(path->rgid, ah->grh.dgid.raw, 16);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2381

err = ib_rate_to_mlx5(dev, ah->static_rate);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

2393

ah->sl & 0xf, qp->ibqp.pd);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3115

memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));

sys/dev/mthca/mthca_av.c

156

struct mthca_ah *ah)

sys/dev/mthca/mthca_av.c

161

ah->type = MTHCA_AH_PCI_POOL;

sys/dev/mthca/mthca_av.c

164

ah->av = kmalloc(sizeof *ah->av, GFP_ATOMIC);

sys/dev/mthca/mthca_av.c

165

if (!ah->av)

sys/dev/mthca/mthca_av.c

168

ah->type = MTHCA_AH_KMALLOC;

sys/dev/mthca/mthca_av.c

169

av = ah->av;

sys/dev/mthca/mthca_av.c

182

ah->type = MTHCA_AH_ON_HCA;

sys/dev/mthca/mthca_av.c

183

ah->avdma = dev->av_table.ddr_av_base +

sys/dev/mthca/mthca_av.c

188

if (ah->type == MTHCA_AH_PCI_POOL) {

sys/dev/mthca/mthca_av.c

189

ah->av = pci_pool_alloc(dev->av_table.pool,

sys/dev/mthca/mthca_av.c

190

GFP_ATOMIC, &ah->avdma);

sys/dev/mthca/mthca_av.c

191

if (!ah->av)

sys/dev/mthca/mthca_av.c

194

av = ah->av;

sys/dev/mthca/mthca_av.c

197

ah->key = pd->ntmr.ibmr.lkey;

sys/dev/mthca/mthca_av.c

225

av, (unsigned long) ah->avdma);

sys/dev/mthca/mthca_av.c

231

if (ah->type == MTHCA_AH_ON_HCA) {

sys/dev/mthca/mthca_av.c

240

int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah)

sys/dev/mthca/mthca_av.c

242

switch (ah->type) {

sys/dev/mthca/mthca_av.c

245

(ah->avdma - dev->av_table.ddr_av_base) /

sys/dev/mthca/mthca_av.c

250

pci_pool_free(dev->av_table.pool, ah->av, ah->avdma);

sys/dev/mthca/mthca_av.c

254

kfree(ah->av);

sys/dev/mthca/mthca_av.c

261

int mthca_ah_grh_present(struct mthca_ah *ah)

sys/dev/mthca/mthca_av.c

263

return !!(ah->av->g_slid & 0x80);

sys/dev/mthca/mthca_av.c

266

int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,

sys/dev/mthca/mthca_av.c

269

if (ah->type == MTHCA_AH_ON_HCA)

sys/dev/mthca/mthca_av.c

272

header->lrh.service_level = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;

sys/dev/mthca/mthca_av.c

273

header->lrh.destination_lid = ah->av->dlid;

sys/dev/mthca/mthca_av.c

274

header->lrh.source_lid = cpu_to_be16(ah->av->g_slid & 0x7f);

sys/dev/mthca/mthca_av.c

275

if (mthca_ah_grh_present(ah)) {

sys/dev/mthca/mthca_av.c

277

(be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20) & 0xff;

sys/dev/mthca/mthca_av.c

279

ah->av->sl_tclass_flowlabel & cpu_to_be32(0xfffff);

sys/dev/mthca/mthca_av.c

280

header->grh.hop_limit = ah->av->hop_limit;

sys/dev/mthca/mthca_av.c

282

be32_to_cpu(ah->av->port_pd) >> 24,

sys/dev/mthca/mthca_av.c

283

ah->av->gid_index % dev->limits.gid_table_len,

sys/dev/mthca/mthca_av.c

286

ah->av->dgid, 16);

sys/dev/mthca/mthca_av.c

294

struct mthca_ah *ah = to_mah(ibah);

sys/dev/mthca/mthca_av.c

298

if (ah->type == MTHCA_AH_ON_HCA)

sys/dev/mthca/mthca_av.c

302

attr->dlid = be16_to_cpu(ah->av->dlid);

sys/dev/mthca/mthca_av.c

303

attr->sl = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;

sys/dev/mthca/mthca_av.c

304

attr->port_num = be32_to_cpu(ah->av->port_pd) >> 24;

sys/dev/mthca/mthca_av.c

305

attr->static_rate = mthca_rate_to_ib(dev, ah->av->msg_sr & 0x7,

sys/dev/mthca/mthca_av.c

307

attr->src_path_bits = ah->av->g_slid & 0x7F;

sys/dev/mthca/mthca_av.c

308

attr->ah_flags = mthca_ah_grh_present(ah) ? IB_AH_GRH : 0;

sys/dev/mthca/mthca_av.c

312

be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20;

sys/dev/mthca/mthca_av.c

314

be32_to_cpu(ah->av->sl_tclass_flowlabel) & 0xfffff;

sys/dev/mthca/mthca_av.c

315

attr->grh.hop_limit = ah->av->hop_limit;

sys/dev/mthca/mthca_av.c

316

attr->grh.sgid_index = ah->av->gid_index &

sys/dev/mthca/mthca_av.c

318

memcpy(attr->grh.dgid.raw, ah->av->dgid, 16);

sys/dev/mthca/mthca_dev.h

569

struct mthca_ah *ah);

sys/dev/mthca/mthca_dev.h

570

int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);

sys/dev/mthca/mthca_dev.h

571

int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,

sys/dev/mthca/mthca_dev.h

574

int mthca_ah_grh_present(struct mthca_ah *ah);

sys/dev/mthca/mthca_mad.c

186

if ((send_buf->ah = dev->sm_ah[port_num - 1]))

sys/dev/mthca/mthca_provider.c

394

struct mthca_ah *ah = to_mah(ibah);

sys/dev/mthca/mthca_provider.c

397

init_attr, ah);

sys/dev/mthca/mthca_provider.c

400

static void mthca_ah_destroy(struct ib_ah *ah, u32 flags)

sys/dev/mthca/mthca_provider.c

402

mthca_destroy_ah(to_mdev(ah->device), to_mah(ah));

sys/dev/mthca/mthca_qp.c

1494

mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,

sys/dev/mthca/mthca_qp.c

1497

err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);

sys/dev/mthca/mthca_qp.c

1593

useg->lkey = cpu_to_be32(to_mah(wr->ah)->key);

sys/dev/mthca/mthca_qp.c

1594

useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);

sys/dev/mthca/mthca_qp.c

1603

memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);

sys/dev/mthca/mthca_qp.c

516

static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,

sys/dev/mthca/mthca_qp.c

519

path->g_mylmc = ah->src_path_bits & 0x7f;

sys/dev/mthca/mthca_qp.c

520

path->rlid = cpu_to_be16(ah->dlid);

sys/dev/mthca/mthca_qp.c

521

path->static_rate = mthca_get_rate(dev, ah->static_rate, port);

sys/dev/mthca/mthca_qp.c

523

if (ah->ah_flags & IB_AH_GRH) {

sys/dev/mthca/mthca_qp.c

524

if (ah->grh.sgid_index >= dev->limits.gid_table_len) {

sys/dev/mthca/mthca_qp.c

526

ah->grh.sgid_index, dev->limits.gid_table_len-1);

sys/dev/mthca/mthca_qp.c

531

path->mgid_index = ah->grh.sgid_index;

sys/dev/mthca/mthca_qp.c

532

path->hop_limit = ah->grh.hop_limit;

sys/dev/mthca/mthca_qp.c

534

cpu_to_be32((ah->sl << 28) |

sys/dev/mthca/mthca_qp.c

535

(ah->grh.traffic_class << 20) |

sys/dev/mthca/mthca_qp.c

536

(ah->grh.flow_label));

sys/dev/mthca/mthca_qp.c

537

memcpy(path->rgid, ah->grh.dgid.raw, 16);

sys/dev/mthca/mthca_qp.c

539

path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);

sys/dev/qlnx/qlnxe/ecore_dev_api.h

451

struct ecore_eth_stats_ah ah;

sys/dev/qlnx/qlnxe/ecore_l2.c

2002

struct ecore_eth_stats_ah *p_ah = &p_stats->ah;

sys/dev/qlnx/qlnxr/qlnxr_cm.c

488

struct ib_ah_attr *ah_attr = &get_qlnxr_ah((ud_wr(swr)->ah))->attr;

sys/dev/qlnx/qlnxr/qlnxr_cm.c

545

0, has_vlan, get_qlnxr_ah((ud_wr(swr)->ah)));

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

5533

struct qlnxr_ah *ah = get_qlnxr_ah(ibah);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

5540

ah->attr = *attr;

sys/dev/usb/usb_hub_acpi.c

100

acpi_uhub_find_rh_cb(ACPI_HANDLE ah, UINT32 nl, void *ctx, void **status)

sys/dev/usb/usb_hub_acpi.c

108

ret = AcpiGetObjectInfo(ah, &devinfo);

sys/dev/usb/usb_hub_acpi.c

113

*status = ah;

sys/dev/usb/usb_hub_acpi.c

138

acpi_uhub_parse_upc(device_t dev, unsigned p, ACPI_HANDLE ah, struct sysctl_oid_list *poid)

sys/dev/usb/usb_hub_acpi.c

147

if (AcpiEvaluateObject(ah, "_UPC", NULL, &buf) == AE_OK) {

sys/dev/usb/usb_hub_acpi.c

264

acpi_uhub_parse_pld(device_t dev, unsigned p, ACPI_HANDLE ah, struct sysctl_oid_list *tree)

sys/dev/usb/usb_hub_acpi.c

273

if (AcpiEvaluateObject(ah, "_PLD", NULL, &buf) == AE_OK) {

sys/dev/usb/usb_hub_acpi.c

348

acpi_uhub_find_rh(device_t dev, ACPI_HANDLE *ah)

sys/dev/usb/usb_hub_acpi.c

353

*ah = NULL;

sys/dev/usb/usb_hub_acpi.c

360

acpi_uhub_find_rh_cb, NULL, dev, ah));

sys/dev/usb/usb_hub_acpi.c

364

acpi_usb_hub_port_probe_cb(ACPI_HANDLE ah, UINT32 lv, void *ctx, void **rv)

sys/dev/usb/usb_hub_acpi.c

371

ret = AcpiGetObjectInfo(ah, &devinfo);

sys/dev/usb/usb_hub_acpi.c

388

sc->port[devinfo->Address - 1].handle = ah;

sys/dev/usb/usb_hub_acpi.c

390

acpi_uhub_parse_upc(dev, devinfo->Address, ah, tree);

sys/dev/usb/usb_hub_acpi.c

391

acpi_uhub_parse_pld(dev, devinfo->Address, ah, tree);

sys/dev/usb/usb_hub_acpi.c

404

acpi_usb_hub_port_probe(device_t dev, ACPI_HANDLE ah)

sys/dev/usb/usb_hub_acpi.c

407

ah, 1,

sys/dev/usb/usb_hub_acpi.c

416

ACPI_HANDLE ah;

sys/dev/usb/usb_hub_acpi.c

421

status = acpi_uhub_find_rh(dev, &ah);

sys/dev/usb/usb_hub_acpi.c

422

if (ACPI_SUCCESS(status) && ah != NULL &&

sys/dev/usb/usb_hub_acpi.c

433

ACPI_HANDLE ah;

sys/dev/usb/usb_hub_acpi.c

438

ah = acpi_get_handle(dev);

sys/dev/usb/usb_hub_acpi.c

439

if (ah == NULL)

sys/dev/usb/usb_hub_acpi.c

460

status = acpi_usb_hub_port_probe(dev, sc->ah);

sys/dev/usb/usb_hub_acpi.c

485

if (ACPI_FAILURE(acpi_uhub_find_rh(dev, &sc->ah)) ||

sys/dev/usb/usb_hub_acpi.c

486

(sc->ah == NULL)) {

sys/dev/usb/usb_hub_acpi.c

505

sc->ah = acpi_get_handle(dev);

sys/dev/usb/usb_hub_acpi.c

507

if (sc->ah == NULL) {

sys/dev/usb/usb_hub_acpi.c

526

ACPI_HANDLE ah;

sys/dev/usb/usb_hub_acpi.c

535

(ah = sc->port[hres.portno - 1].handle)) {

sys/dev/usb/usb_hub_acpi.c

536

*res = (uintptr_t)ah;

sys/dev/usb/usb_hub_acpi.c

545

ACPI_HANDLE ah;

sys/dev/usb/usb_hub_acpi.c

549

ah = acpi_get_handle(child);

sys/dev/usb/usb_hub_acpi.c

550

if (ah != NULL)

sys/dev/usb/usb_hub_acpi.c

551

sbuf_printf(sb, " handle=%s", acpi_name(ah));

sys/dev/usb/usb_hub_acpi.c

95

ACPI_HANDLE ah;

sys/net/debugnet_inet.c

231

struct arphdr *ah;

sys/net/debugnet_inet.c

249

ah = mtod(m, struct arphdr *);

sys/net/debugnet_inet.c

250

ah->ar_hrd = htons(ARPHRD_ETHER);

sys/net/debugnet_inet.c

251

ah->ar_pro = htons(ETHERTYPE_IP);

sys/net/debugnet_inet.c

252

ah->ar_hln = ETHER_ADDR_LEN;

sys/net/debugnet_inet.c

253

ah->ar_pln = sizeof(struct in_addr);

sys/net/debugnet_inet.c

254

ah->ar_op = htons(ARPOP_REQUEST);

sys/net/debugnet_inet.c

255

memcpy(ar_sha(ah), IF_LLADDR(ifp), ETHER_ADDR_LEN);

sys/net/debugnet_inet.c

256

((struct in_addr *)ar_spa(ah))->s_addr = pcb->dp_client;

sys/net/debugnet_inet.c

257

bzero(ar_tha(ah), ETHER_ADDR_LEN);

sys/net/debugnet_inet.c

258

((struct in_addr *)ar_tpa(ah))->s_addr = dst;

sys/net/debugnet_inet.c

283

struct arphdr *ah;

sys/net/debugnet_inet.c

299

ah = mtod(m, struct arphdr *);

sys/net/debugnet_inet.c

300

if (ntohs(ah->ar_hrd) != ARPHRD_ETHER) {

sys/net/debugnet_inet.c

302

(unsigned char *)&ah->ar_hrd, "");

sys/net/debugnet_inet.c

305

if (ntohs(ah->ar_pro) != ETHERTYPE_IP) {

sys/net/debugnet_inet.c

307

ntohs(ah->ar_pro));

sys/net/debugnet_inet.c

319

ah = mtod(m, struct arphdr *);

sys/net/debugnet_inet.c

321

op = ntohs(ah->ar_op);

sys/net/debugnet_inet.c

322

memcpy(&isaddr, ar_spa(ah), sizeof(isaddr));

sys/net/debugnet_inet.c

323

memcpy(&itaddr, ar_tpa(ah), sizeof(itaddr));

sys/net/debugnet_inet.c

326

if (memcmp(ar_sha(ah), enaddr, ifp->if_addrlen) == 0) {

sys/net/debugnet_inet.c

333

ifp->if_addrlen, (u_char *)ar_sha(ah), ":",

sys/net/debugnet_inet.c

338

if (memcmp(ar_sha(ah), ifp->if_broadcastaddr, ifp->if_addrlen) == 0) {

sys/net/debugnet_inet.c

358

memcpy(pcb->dp_gw_mac.octet, ar_sha(ah),

sys/net/debugnet_inet.c

359

min(ah->ar_hln, ETHER_ADDR_LEN));

sys/net/debugnet_inet.c

378

memcpy(ar_tha(ah), ar_sha(ah), ah->ar_hln);

sys/net/debugnet_inet.c

379

memcpy(ar_sha(ah), enaddr, ah->ar_hln);

sys/net/debugnet_inet.c

380

memcpy(ar_tpa(ah), ar_spa(ah), ah->ar_pln);

sys/net/debugnet_inet.c

381

memcpy(ar_spa(ah), &itaddr, ah->ar_pln);

sys/net/debugnet_inet.c

382

ah->ar_op = htons(ARPOP_REPLY);

sys/net/debugnet_inet.c

383

ah->ar_pro = htons(ETHERTYPE_IP);

sys/net/debugnet_inet.c

385

m->m_len = arphdr_len(ah);

sys/net/debugnet_inet.c

388

memcpy(dst.octet, ar_tha(ah), ETHER_ADDR_LEN);

sys/net/if_ethersubr.c

145

struct arphdr *ah;

sys/net/if_ethersubr.c

167

ah = (struct arphdr *)req->hdata;

sys/net/if_ethersubr.c

168

ah->ar_hrd = htons(ARPHRD_ETHER);

sys/net/if_ethersubr.c

170

switch(ntohs(ah->ar_op)) {

sys/net/if_fwsubr.c

178

struct arphdr *ah;

sys/net/if_fwsubr.c

179

ah = mtod(m, struct arphdr *);

sys/net/if_fwsubr.c

180

ah->ar_hrd = htons(ARPHRD_IEEE1394);

sys/net/if_fwsubr.c

182

*destfw = *(struct fw_hwaddr *) ar_tha(ah);

sys/net/if_fwsubr.c

188

bcopy(ar_tpa(ah), ar_tha(ah), ah->ar_pln);

sys/net/if_fwsubr.c

189

m_adj(m, -ah->ar_hln);

sys/net/if_fwsubr.c

628

struct arphdr *ah;

sys/net/if_fwsubr.c

629

ah = mtod(m, struct arphdr *);

sys/net/if_fwsubr.c

634

m->m_len += ah->ar_hln;

sys/net/if_fwsubr.c

635

m->m_pkthdr.len += ah->ar_hln;

sys/net/if_fwsubr.c

636

bcopy(ar_tha(ah), ar_tpa(ah), ah->ar_pln);

sys/net/if_infiniband.c

212

struct arphdr *ah;

sys/net/if_infiniband.c

234

ah = (struct arphdr *)req->hdata;

sys/net/if_infiniband.c

235

ah->ar_hrd = htons(ARPHRD_INFINIBAND);

sys/net/if_infiniband.c

237

switch (ntohs(ah->ar_op)) {

sys/netinet/if_ether.c

1008

(void)memcpy(ar_tha(ah), ar_sha(ah), ah->ar_hln);

sys/netinet/if_ether.c

1009

(void)memcpy(ar_sha(ah), enaddr, ah->ar_hln);

sys/netinet/if_ether.c

1021

(void)memcpy(ar_tha(ah), ar_sha(ah), ah->ar_hln);

sys/netinet/if_ether.c

1022

(void)memcpy(ar_sha(ah), lle->ll_addr, ah->ar_hln);

sys/netinet/if_ether.c

1044

(void)memcpy(ar_tha(ah), ar_sha(ah), ah->ar_hln);

sys/netinet/if_ether.c

1045

(void)memcpy(ar_sha(ah), enaddr, ah->ar_hln);

sys/netinet/if_ether.c

1085

(void)memcpy(ar_tpa(ah), ar_spa(ah), ah->ar_pln);

sys/netinet/if_ether.c

1086

(void)memcpy(ar_spa(ah), &itaddr, ah->ar_pln);

sys/netinet/if_ether.c

1087

ah->ar_op = htons(ARPOP_REPLY);

sys/netinet/if_ether.c

1088

ah->ar_pro = htons(ETHERTYPE_IP); /* let's be sure! */

sys/netinet/if_ether.c

1089

m->m_len = sizeof(*ah) + (2 * ah->ar_pln) + (2 * ah->ar_hln);

sys/netinet/if_ether.c

1098

error = arp_fillheader(ifp, ah, 0, linkhdr, &linkhdrsize);

sys/netinet/if_ether.c

1168

arp_check_update_lle(struct arphdr *ah, struct in_addr isaddr, struct ifnet *ifp,

sys/netinet/if_ether.c

1185

ifp->if_addrlen, (u_char *)ar_sha(ah), ":",

sys/netinet/if_ether.c

1191

bcmp(ar_sha(ah), la->ll_addr, ifp->if_addrlen)) {

sys/netinet/if_ether.c

1199

(u_char *)ar_sha(ah), ":",

sys/netinet/if_ether.c

1210

ifp->if_addrlen, (u_char *)ar_sha(ah), ":",

sys/netinet/if_ether.c

1217

if (lltable_calc_llheader(ifp, AF_INET, ar_sha(ah), linkhdr,

sys/netinet/if_ether.c

185

static void arp_check_update_lle(struct arphdr *ah, struct in_addr isaddr,

sys/netinet/if_ether.c

316

arp_fillheader(struct ifnet *ifp, struct arphdr *ah, int bcast, u_char *buf,

sys/netinet/if_ether.c

328

ereq.lladdr = ar_tha(ah);

sys/netinet/if_ether.c

329

ereq.hdata = (u_char *)ah;

sys/netinet/if_ether.c

350

struct arphdr *ah;

sys/netinet/if_ether.c

394

m->m_len = sizeof(*ah) + 2 * sizeof(struct in_addr) +

sys/netinet/if_ether.c

398

ah = mtod(m, struct arphdr *);

sys/netinet/if_ether.c

399

bzero((caddr_t)ah, m->m_len);

sys/netinet/if_ether.c

403

ah->ar_pro = htons(ETHERTYPE_IP);

sys/netinet/if_ether.c

404

ah->ar_hln = ifp->if_addrlen; /* hardware address length */

sys/netinet/if_ether.c

405

ah->ar_pln = sizeof(struct in_addr); /* protocol address length */

sys/netinet/if_ether.c

406

ah->ar_op = htons(ARPOP_REQUEST);

sys/netinet/if_ether.c

407

bcopy(enaddr, ar_sha(ah), ah->ar_hln);

sys/netinet/if_ether.c

408

bcopy(sip, ar_spa(ah), ah->ar_pln);

sys/netinet/if_ether.c

409

bcopy(tip, ar_tpa(ah), ah->ar_pln);

sys/netinet/if_ether.c

416

error = arp_fillheader(ifp, ah, 1, linkhdr, &linkhdrsize);

sys/netinet/if_ether.c

768

struct arphdr *ah;

sys/netinet/if_ether.c

804

ah = mtod(m, struct arphdr *);

sys/netinet/if_ether.c

810

if (ah->ar_pln != sizeof(struct in_addr)) {

sys/netinet/if_ether.c

816

if (allow_multicast == 0 && ETHER_IS_MULTICAST(ar_sha(ah))) {

sys/netinet/if_ether.c

818

ifp->if_addrlen, (u_char *)ar_sha(ah), ":");

sys/netinet/if_ether.c

822

op = ntohs(ah->ar_op);

sys/netinet/if_ether.c

823

(void)memcpy(&isaddr, ar_spa(ah), sizeof (isaddr));

sys/netinet/if_ether.c

824

(void)memcpy(&itaddr, ar_tpa(ah), sizeof (itaddr));

sys/netinet/if_ether.c

898

if (!bcmp(ar_sha(ah), enaddr, ifp->if_addrlen))

sys/netinet/if_ether.c

900

if (!bcmp(ar_sha(ah), ifp->if_broadcastaddr, ifp->if_addrlen)) {

sys/netinet/if_ether.c

906

if (ifp->if_addrlen != ah->ar_hln) {

sys/netinet/if_ether.c

909

(u_char *) ar_sha(ah), ":", ah->ar_hln,

sys/netinet/if_ether.c

923

ifp->if_addrlen, (u_char *)ar_sha(ah), ":",

sys/netinet/if_ether.c

939

arp_check_update_lle(ah, isaddr, ifp, bridged, la);

sys/netinet/if_ether.c

946

if (lltable_calc_llheader(ifp, AF_INET, ar_sha(ah), linkhdr,

sys/netinet/if_ether.c

996

arp_check_update_lle(ah, isaddr, ifp, bridged, la);

sys/netinet/in_kdtrace.c

393

#define MIB_PROBE_AH(name) SDT_PROBE_DEFINE1(mib, ah, count, name, "int")

sys/netinet/in_kdtrace.c

394

#define MIB_PROBE_AH2(name) SDT_PROBE_DEFINE2(mib, ah, count, name, "int", "int")

sys/netinet/in_kdtrace.h

380

SDT_PROBE_DECLARE(mib, ah, count, ahs_hdrops);

sys/netinet/in_kdtrace.h

381

SDT_PROBE_DECLARE(mib, ah, count, ahs_nopf);

sys/netinet/in_kdtrace.h

382

SDT_PROBE_DECLARE(mib, ah, count, ahs_notdb);

sys/netinet/in_kdtrace.h

383

SDT_PROBE_DECLARE(mib, ah, count, ahs_badkcr);

sys/netinet/in_kdtrace.h

384

SDT_PROBE_DECLARE(mib, ah, count, ahs_badauth);

sys/netinet/in_kdtrace.h

385

SDT_PROBE_DECLARE(mib, ah, count, ahs_noxform);

sys/netinet/in_kdtrace.h

386

SDT_PROBE_DECLARE(mib, ah, count, ahs_qfull);

sys/netinet/in_kdtrace.h

387

SDT_PROBE_DECLARE(mib, ah, count, ahs_wrap);

sys/netinet/in_kdtrace.h

388

SDT_PROBE_DECLARE(mib, ah, count, ahs_replay);

sys/netinet/in_kdtrace.h

389

SDT_PROBE_DECLARE(mib, ah, count, ahs_badauthl);

sys/netinet/in_kdtrace.h

390

SDT_PROBE_DECLARE(mib, ah, count, ahs_input);

sys/netinet/in_kdtrace.h

391

SDT_PROBE_DECLARE(mib, ah, count, ahs_output);

sys/netinet/in_kdtrace.h

392

SDT_PROBE_DECLARE(mib, ah, count, ahs_invalid);

sys/netinet/in_kdtrace.h

393

SDT_PROBE_DECLARE(mib, ah, count, ahs_ibytes);

sys/netinet/in_kdtrace.h

394

SDT_PROBE_DECLARE(mib, ah, count, ahs_obytes);

sys/netinet/in_kdtrace.h

395

SDT_PROBE_DECLARE(mib, ah, count, ahs_toobig);

sys/netinet/in_kdtrace.h

396

SDT_PROBE_DECLARE(mib, ah, count, ahs_pdrops);

sys/netinet/in_kdtrace.h

397

SDT_PROBE_DECLARE(mib, ah, count, ahs_crypto);

sys/netinet/in_kdtrace.h

398

SDT_PROBE_DECLARE(mib, ah, count, ahs_tunnel);

sys/netinet/in_kdtrace.h

399

SDT_PROBE_DECLARE(mib, ah, count, ahs_hist);

sys/netinet/in_proto.c

122

SYSCTL_NODE(_net_inet, IPPROTO_AH, ah, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,

sys/netinet/libalias/alias_dummy.c

146

AliasHandleDummy(struct libalias *la, struct ip *ip, struct alias_data *ah)

sys/netinet/libalias/alias_dummy.c

60

AliasHandleDummy(struct libalias *la, struct ip *ip, struct alias_data *ah);

sys/netinet/libalias/alias_dummy.c

63

fingerprint(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_dummy.c

69

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL ||

sys/netinet/libalias/alias_dummy.c

70

ah->maxpktsize == 0)

sys/netinet/libalias/alias_dummy.c

76

if (ntohs(*ah->dport) == 123 || ntohs(*ah->sport) == 456)

sys/netinet/libalias/alias_dummy.c

87

protohandler(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_dummy.c

89

AliasHandleDummy(la, pip, ah);

sys/netinet/libalias/alias_ftp.c

108

fingerprint_out(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_ftp.c

110

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL ||

sys/netinet/libalias/alias_ftp.c

111

ah->maxpktsize == 0)

sys/netinet/libalias/alias_ftp.c

113

if (ntohs(*ah->dport) == FTP_CONTROL_PORT_NUMBER ||

sys/netinet/libalias/alias_ftp.c

114

ntohs(*ah->sport) == FTP_CONTROL_PORT_NUMBER)

sys/netinet/libalias/alias_ftp.c

120

fingerprint_in(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_ftp.c

122

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL)

sys/netinet/libalias/alias_ftp.c

124

if (ntohs(*ah->dport) == FTP_CONTROL_PORT_NUMBER ||

sys/netinet/libalias/alias_ftp.c

125

ntohs(*ah->sport) == FTP_CONTROL_PORT_NUMBER)

sys/netinet/libalias/alias_ftp.c

131

protohandler_out(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_ftp.c

133

AliasHandleFtpOut(la, pip, ah->lnk, ah->maxpktsize);

sys/netinet/libalias/alias_ftp.c

138

protohandler_in(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_ftp.c

140

AliasHandleFtpIn(la, pip, ah->lnk);

sys/netinet/libalias/alias_irc.c

100

if (ntohs(*ah->dport) == IRC_CONTROL_PORT_NUMBER_1

sys/netinet/libalias/alias_irc.c

101

|| ntohs(*ah->dport) == IRC_CONTROL_PORT_NUMBER_2)

sys/netinet/libalias/alias_irc.c

107

protohandler(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_irc.c

111

AliasHandleIrcOut(la, pip, ah->lnk, ah->maxpktsize);

sys/netinet/libalias/alias_irc.c

96

fingerprint(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_irc.c

98

if (ah->dport == NULL || ah->lnk == NULL || ah->maxpktsize == 0)

sys/netinet/libalias/alias_nbt.c

100

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL ||

sys/netinet/libalias/alias_nbt.c

101

ah->aaddr == NULL || ah->aport == NULL)

sys/netinet/libalias/alias_nbt.c

103

if (ntohs(*ah->dport) == NETBIOS_NS_PORT_NUMBER

sys/netinet/libalias/alias_nbt.c

104

|| ntohs(*ah->sport) == NETBIOS_NS_PORT_NUMBER)

sys/netinet/libalias/alias_nbt.c

110

protohandler2in(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_nbt.c

112

AliasHandleUdpNbtNS(la, pip, ah->lnk, ah->aaddr, ah->aport,

sys/netinet/libalias/alias_nbt.c

113

ah->oaddr, ah->dport);

sys/netinet/libalias/alias_nbt.c

118

protohandler2out(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_nbt.c

120

return (AliasHandleUdpNbtNS(la, pip, ah->lnk, &pip->ip_src, ah->sport,

sys/netinet/libalias/alias_nbt.c

121

ah->aaddr, ah->aport));

sys/netinet/libalias/alias_nbt.c

80

fingerprint1(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_nbt.c

82

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL ||

sys/netinet/libalias/alias_nbt.c

83

ah->aaddr == NULL || ah->aport == NULL)

sys/netinet/libalias/alias_nbt.c

85

if (ntohs(*ah->dport) == NETBIOS_DGM_PORT_NUMBER

sys/netinet/libalias/alias_nbt.c

86

|| ntohs(*ah->sport) == NETBIOS_DGM_PORT_NUMBER)

sys/netinet/libalias/alias_nbt.c

92

protohandler1(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_nbt.c

94

return (AliasHandleUdpNbt(la, pip, ah->lnk, ah->aaddr, *ah->aport));

sys/netinet/libalias/alias_nbt.c

98

fingerprint2(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

104

protohandlerout(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

106

AliasHandlePptpOut(la, pip, ah->lnk);

sys/netinet/libalias/alias_pptp.c

111

protohandlergrein(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

120

protohandlergreout(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

80

fingerprint(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

82

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL)

sys/netinet/libalias/alias_pptp.c

84

if (ntohs(*ah->dport) == PPTP_CONTROL_PORT_NUMBER

sys/netinet/libalias/alias_pptp.c

85

|| ntohs(*ah->sport) == PPTP_CONTROL_PORT_NUMBER)

sys/netinet/libalias/alias_pptp.c

91

fingerprintgre(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

97

protohandlerin(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_pptp.c

99

AliasHandlePptpIn(la, pip, ah->lnk);

sys/netinet/libalias/alias_skinny.c

60

fingerprint(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_skinny.c

62

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL)

sys/netinet/libalias/alias_skinny.c

64

if (la->skinnyPort != 0 && (ntohs(*ah->sport) == la->skinnyPort ||

sys/netinet/libalias/alias_skinny.c

65

ntohs(*ah->dport) == la->skinnyPort))

sys/netinet/libalias/alias_skinny.c

71

protohandler(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_skinny.c

73

AliasHandleSkinny(la, pip, ah->lnk);

sys/netinet/libalias/alias_smedia.c

135

fingerprint(struct libalias *la, struct alias_data *ah)

sys/netinet/libalias/alias_smedia.c

137

if (ah->dport != NULL && ah->aport != NULL && ah->sport != NULL &&

sys/netinet/libalias/alias_smedia.c

138

ntohs(*ah->dport) == TFTP_PORT_NUMBER)

sys/netinet/libalias/alias_smedia.c

140

if (ah->dport == NULL || ah->sport == NULL || ah->lnk == NULL ||

sys/netinet/libalias/alias_smedia.c

141

ah->maxpktsize == 0)

sys/netinet/libalias/alias_smedia.c

143

if (ntohs(*ah->dport) == RTSP_CONTROL_PORT_NUMBER_1

sys/netinet/libalias/alias_smedia.c

144

|| ntohs(*ah->sport) == RTSP_CONTROL_PORT_NUMBER_1

sys/netinet/libalias/alias_smedia.c

145

|| ntohs(*ah->dport) == RTSP_CONTROL_PORT_NUMBER_2

sys/netinet/libalias/alias_smedia.c

146

|| ntohs(*ah->sport) == RTSP_CONTROL_PORT_NUMBER_2)

sys/netinet/libalias/alias_smedia.c

152

protohandler(struct libalias *la, struct ip *pip, struct alias_data *ah)

sys/netinet/libalias/alias_smedia.c

154

if (ntohs(*ah->dport) == TFTP_PORT_NUMBER)

sys/netinet/libalias/alias_smedia.c

156

*ah->sport, *ah->aport, IPPROTO_UDP);

sys/netinet/libalias/alias_smedia.c

157

else AliasHandleRtspOut(la, pip, ah->lnk, ah->maxpktsize);

sys/netipsec/ah_var.h

82

MIB_SDT_PROBE1(ah, count, name, (val)); \

sys/netipsec/ah_var.h

87

MIB_SDT_PROBE2(ah, count, name, 1, (type)); \

sys/netipsec/key.c

6697

key_getsizes_ah(const struct auth_hash *ah, int alg, u_int16_t* min,

sys/netipsec/key.c

6701

*min = *max = ah->hashsize;

sys/netipsec/key.c

6702

if (ah->keysize == 0) {

sys/netipsec/xform_ah.c

169

size = sizeof (struct ah) + sizeof (u_int32_t) + 16;

sys/netipsec/xform_ah.c

541

struct newah *ah;

sys/netipsec/xform_ah.c

565

ah = (struct newah *)(mtod(m, caddr_t) + skip);

sys/netipsec/xform_ah.c

570

ipsec_chkreplay(ntohl(ah->ah_seq), &seqh, sav) == 0) {

sys/netipsec/xform_ah.c

582

hl = sizeof(struct ah) + (ah->ah_len * sizeof (u_int32_t));

sys/netipsec/xform_ah.c

643

hl = ah->ah_nxt;

sys/netipsec/xform_ah.c

84

sizeof (struct ah) : sizeof (struct ah) + sizeof (u_int32_t))

sys/netipsec/xform_ah.c

862

struct newah *ah;

sys/netipsec/xform_ah.c

944

ah = (struct newah *)(mtod(mi, caddr_t) + roff);

sys/netipsec/xform_ah.c

947

m_copydata(m, protoff, sizeof(u_int8_t), (caddr_t) &ah->ah_nxt);

sys/netipsec/xform_ah.c

948

ah->ah_len = (ahsize - sizeof(struct ah)) / sizeof(u_int32_t);

sys/netipsec/xform_ah.c

949

ah->ah_reserve = 0;

sys/netipsec/xform_ah.c

950

ah->ah_spi = sav->spi;

sys/netipsec/xform_ah.c

981

ah->ah_seq = htonl((uint32_t)sav->replay->count);

sys/netpfil/ipfilter/netinet/fil.c

1038

authhdr_t *ah;

sys/netpfil/ipfilter/netinet/fil.c

1042

ah = (authhdr_t *)ipf_pr_ipv6exthdr(fin, 0, IPPROTO_HOPOPTS);

sys/netpfil/ipfilter/netinet/fil.c

1043

if (ah == NULL) {

sys/netpfil/ipfilter/netinet/fil.c

1050

ipf_pr_short6(fin, sizeof(*ah));

sys/netpfil/ipfilter/netinet/fil.c

1056

return (ah->ah_next);

sys/netpfil/ipfilter/netinet/fil.c

1578

authhdr_t *ah;

sys/netpfil/ipfilter/netinet/fil.c

1582

ipf_pr_short(fin, sizeof(*ah));

sys/netpfil/ipfilter/netinet/fil.c

1589

if (ipf_pr_pullup(fin, sizeof(*ah)) == -1) {

sys/netpfil/ipfilter/netinet/fil.c

1595

ah = (authhdr_t *)fin->fin_dp;

sys/netpfil/ipfilter/netinet/fil.c

1597

len = (ah->ah_plen + 2) << 2;

sys/netpfil/ipfilter/netinet/fil.c

1611

return (ah->ah_next);

sys/netpfil/pf/pf.c

10793

struct ah ext;

sys/netpfil/pf/pf.c

8496

struct sctp_asconf_paramhdr ah;

sys/netpfil/pf/pf.c

8498

if (!pf_pull_hdr(pd->m, start + off, &ah, sizeof(ah),

sys/netpfil/pf/pf.c

8502

ret = pf_multihome_scan(start + off + sizeof(ah),

sys/netpfil/pf/pf.c

8503

ntohs(ah.ph.param_length) - sizeof(ah), pd,

sys/netpfil/pf/pf.c

8511

struct sctp_asconf_paramhdr ah;

sys/netpfil/pf/pf.c

8513

if (!pf_pull_hdr(pd->m, start + off, &ah, sizeof(ah),

sys/netpfil/pf/pf.c

8516

ret = pf_multihome_scan(start + off + sizeof(ah),

sys/netpfil/pf/pf.c

8517

ntohs(ah.ph.param_length) - sizeof(ah), pd,

sys/ofed/drivers/infiniband/core/ib_agent.c

104

ah = ib_create_ah_from_wc(agent->qp->pd, wc, grh, port_num);

sys/ofed/drivers/infiniband/core/ib_agent.c

105

if (IS_ERR(ah)) {

sys/ofed/drivers/infiniband/core/ib_agent.c

107

PTR_ERR(ah));

sys/ofed/drivers/infiniband/core/ib_agent.c

125

send_buf->ah = ah;

sys/ofed/drivers/infiniband/core/ib_agent.c

142

ib_destroy_ah(ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_agent.c

148

ib_destroy_ah(mad_send_wc->send_buf->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_agent.c

90

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_cm.c

325

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_cm.c

352

ah = ib_create_ah(mad_agent->qp->pd, &av->ah_attr, 0);

sys/ofed/drivers/infiniband/core/ib_cm.c

353

if (IS_ERR(ah)) {

sys/ofed/drivers/infiniband/core/ib_cm.c

354

ret = PTR_ERR(ah);

sys/ofed/drivers/infiniband/core/ib_cm.c

364

ib_destroy_ah(ah, 0);

sys/ofed/drivers/infiniband/core/ib_cm.c

370

m->ah = ah;

sys/ofed/drivers/infiniband/core/ib_cm.c

395

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_cm.c

397

ah = ib_create_ah_from_wc(port->mad_agent->qp->pd, mad_recv_wc->wc,

sys/ofed/drivers/infiniband/core/ib_cm.c

399

if (IS_ERR(ah))

sys/ofed/drivers/infiniband/core/ib_cm.c

400

return PTR_ERR(ah);

sys/ofed/drivers/infiniband/core/ib_cm.c

402

msg->ah = ah;

sys/ofed/drivers/infiniband/core/ib_cm.c

408

if (msg->ah)

sys/ofed/drivers/infiniband/core/ib_cm.c

409

ib_destroy_ah(msg->ah, 0);

sys/ofed/drivers/infiniband/core/ib_mad.c

1252

mad_send_wr->send_wr.ah = send_buf->ah;

sys/ofed/drivers/infiniband/core/ib_mad.c

1861

if (ib_query_ah(wr->send_buf.ah, &attr))

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

153

msg->ah = rmpp_recv->ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

163

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

166

ah = ib_create_ah_from_wc(agent->qp->pd, recv_wc->wc,

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

168

if (IS_ERR(ah))

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

169

return (void *) ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

177

ib_destroy_ah(ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

179

msg->ah = ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

180

msg->context[0] = ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

207

ib_destroy_ah(msg->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

214

if (mad_send_wc->send_buf->context[0] == mad_send_wc->send_buf->ah)

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

215

ib_destroy_ah(mad_send_wc->send_buf->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

243

ib_destroy_ah(msg->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

297

rmpp_recv->ah = ib_create_ah_from_wc(agent->agent.qp->pd,

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

301

if (IS_ERR(rmpp_recv->ah))

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

60

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

87

ib_destroy_ah(rmpp_recv->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_mad_rmpp.c

873

if (ib_query_ah(mad_send_wr->send_buf.ah, &ah_attr))

sys/ofed/drivers/infiniband/core/ib_sa_query.c

496

ib_destroy_ah(sm_ah->ah, 0);

sys/ofed/drivers/infiniband/core/ib_sa_query.c

536

new_ah->ah = ib_create_ah(port->agent->qp->pd, &ah_attr, RDMA_CREATE_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_sa_query.c

537

if (IS_ERR(new_ah->ah)) {

sys/ofed/drivers/infiniband/core/ib_sa_query.c

61

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_sa_query.c

765

query->mad_buf->ah = query->sm_ah->ah;

sys/ofed/drivers/infiniband/core/ib_user_mad.c

202

ib_destroy_ah(packet->msg->ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_user_mad.c

458

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_user_mad.c

510

ah = ib_create_user_ah(agent->qp->pd, &ah_attr, NULL);

sys/ofed/drivers/infiniband/core/ib_user_mad.c

511

if (IS_ERR(ah)) {

sys/ofed/drivers/infiniband/core/ib_user_mad.c

512

ret = PTR_ERR(ah);

sys/ofed/drivers/infiniband/core/ib_user_mad.c

541

packet->msg->ah = ah;

sys/ofed/drivers/infiniband/core/ib_user_mad.c

604

ib_destroy_ah(ah, RDMA_DESTROY_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2071

ud->ah = uobj_get_obj_read(ah, UVERBS_OBJECT_AH,

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2072

user_wr->wr.ud.ah, attrs);

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2073

if (!ud->ah) {

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2181

if (is_ud && ud_wr(wr)->ah)

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2182

uobj_put_obj_read(ud_wr(wr)->ah);

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2401

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2444

ah = ib_create_user_ah(pd, &attr, &attrs->driver_udata);

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2445

if (IS_ERR(ah)) {

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2446

ret = PTR_ERR(ah);

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2450

ah->uobject = uobj;

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2452

uobj->object = ah;

sys/ofed/drivers/infiniband/core/ib_uverbs_cmd.c

2465

ib_destroy_ah_user(ah, RDMA_DESTROY_AH_SLEEPABLE,

sys/ofed/drivers/infiniband/core/ib_verbs.c

361

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_verbs.c

369

ah = rdma_zalloc_drv_obj_gfp(

sys/ofed/drivers/infiniband/core/ib_verbs.c

372

if (!ah)

sys/ofed/drivers/infiniband/core/ib_verbs.c

375

ah->device = device;

sys/ofed/drivers/infiniband/core/ib_verbs.c

376

ah->pd = pd;

sys/ofed/drivers/infiniband/core/ib_verbs.c

378

ret = device->create_ah(ah, ah_attr, flags, udata);

sys/ofed/drivers/infiniband/core/ib_verbs.c

380

kfree(ah);

sys/ofed/drivers/infiniband/core/ib_verbs.c

385

return ah;

sys/ofed/drivers/infiniband/core/ib_verbs.c

402

struct ib_ah *ah;

sys/ofed/drivers/infiniband/core/ib_verbs.c

404

ah = _ib_create_ah(pd, ah_attr, flags, NULL);

sys/ofed/drivers/infiniband/core/ib_verbs.c

406

return ah;

sys/ofed/drivers/infiniband/core/ib_verbs.c

670

int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr)

sys/ofed/drivers/infiniband/core/ib_verbs.c

672

return ah->device->modify_ah ?

sys/ofed/drivers/infiniband/core/ib_verbs.c

673

ah->device->modify_ah(ah, ah_attr) :

sys/ofed/drivers/infiniband/core/ib_verbs.c

678

int ib_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr)

sys/ofed/drivers/infiniband/core/ib_verbs.c

680

return ah->device->query_ah ?

sys/ofed/drivers/infiniband/core/ib_verbs.c

681

ah->device->query_ah(ah, ah_attr) :

sys/ofed/drivers/infiniband/core/ib_verbs.c

686

int ib_destroy_ah_user(struct ib_ah *ah, u32 flags, struct ib_udata *udata)

sys/ofed/drivers/infiniband/core/ib_verbs.c

692

pd = ah->pd;

sys/ofed/drivers/infiniband/core/ib_verbs.c

693

ah->device->destroy_ah(ah, flags);

sys/ofed/drivers/infiniband/core/ib_verbs.c

696

kfree(ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib.h

184

struct ipoib_ah *ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib.h

405

struct ib_ah *ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib.h

419

struct ipoib_ah *ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib.h

445

static inline void ipoib_put_ah(struct ipoib_ah *ah)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib.h

447

kref_put(&ah->ref, ipoib_free_ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

466

priv->tx_wr.ah = address;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

547

priv->tx_head & (ipoib_sendq_size - 1), address->ah, qpn,

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

564

struct ipoib_ah *ah, *tah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

570

list_for_each_entry_safe(ah, tah, &priv->dead_ahs, list)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

571

if ((int) priv->tx_tail - (int) ah->last_send >= 0) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

572

list_del(&ah->list);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

573

ib_destroy_ah(ah->ah, 0);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

574

kfree(ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

61

struct ipoib_ah *ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

63

ah = kmalloc(sizeof *ah, GFP_KERNEL);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

64

if (!ah)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

67

ah->priv = priv;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

68

ah->last_send = 0;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

69

kref_init(&ah->ref);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

71

ah->ah = ib_create_ah(pd, attr, RDMA_CREATE_AH_SLEEPABLE);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

72

if (IS_ERR(ah->ah)) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

73

kfree(ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

74

ah = NULL;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

76

ipoib_dbg(priv, "Created ah %p\n", ah->ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

78

return ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

83

struct ipoib_ah *ah = container_of(kref, struct ipoib_ah, ref);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

84

struct ipoib_dev_priv *priv = ah->priv;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c

89

list_add_tail(&ah->list, &priv->dead_ahs);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

396

if (path->ah)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

397

ipoib_put_ah(path->ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

513

struct ipoib_ah *ah = NULL;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

533

ah = ipoib_create_ah(priv, priv->pd, &av);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

538

if (ah) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

541

old_ah = path->ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

542

path->ah = ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

545

ah, be16_to_cpu(pathrec->dlid), pathrec->sl);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

706

} else if (path->ah) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c

707

ipoib_send(priv, mb, path->ah, IPOIB_QPN(eh->hwaddr));

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

157

struct ipoib_ah *ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

213

ah = ipoib_create_ah(priv, priv->pd, &av);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

214

if (!ah) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

218

mcast->ah = ah;

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

223

mcast->ah->ah,

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

662

if (!mcast->ah) {

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

684

if (mcast && mcast->ah)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

685

ipoib_send(priv, mb, mcast->ah, IB_MULTICAST_QPN);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

70

if (mcast->ah)

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

71

ipoib_put_ah(mcast->ah);

sys/ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c

902

iter->complete = !!mcast->ah;

sys/ofed/include/rdma/ib_mad.h

414

struct ib_ah *ah;

sys/ofed/include/rdma/ib_verbs.h

1283

struct ib_ah *ah;

sys/ofed/include/rdma/ib_verbs.h

2231

int (*create_ah)(struct ib_ah *ah, struct ib_ah_attr *ah_attr,

sys/ofed/include/rdma/ib_verbs.h

2233

int (*modify_ah)(struct ib_ah *ah,

sys/ofed/include/rdma/ib_verbs.h

2235

int (*query_ah)(struct ib_ah *ah,

sys/ofed/include/rdma/ib_verbs.h

2237

void (*destroy_ah)(struct ib_ah *ah, u32 flags);

sys/ofed/include/rdma/ib_verbs.h

3059

int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);

sys/ofed/include/rdma/ib_verbs.h

3068

int ib_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);

sys/ofed/include/rdma/ib_verbs.h

3081

int ib_destroy_ah_user(struct ib_ah *ah, u32 flags, struct ib_udata *udata);

sys/ofed/include/rdma/ib_verbs.h

3090

static inline int ib_destroy_ah(struct ib_ah *ah, u32 flags)

sys/ofed/include/rdma/ib_verbs.h

3092

return ib_destroy_ah_user(ah, flags, NULL);

sys/ofed/include/uapi/rdma/ib_user_verbs.h

821

__u32 ah;

tools/tools/ath/athpow/athpow.c

42

#define IS_5112(ah) \

tools/tools/ath/athpow/athpow.c

43

(((ah)->ah_analog5GhzRev&0xf0) >= AR_RAD5112_SREV_MAJOR \

tools/tools/ath/athpow/athpow.c

44

&& ((ah)->ah_analog5GhzRev&0xf0) < AR_RAD2316_SREV_MAJOR )

tools/tools/ath/athpow/athpow.c

45

#define IS_2316(ah) \

tools/tools/ath/athpow/athpow.c

46

((ah)->ah_macVersion == AR_SREV_2415)

tools/tools/ath/athpow/athpow.c

47

#define IS_2413(ah) \

tools/tools/ath/athpow/athpow.c

48

((ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))

tools/tools/ath/athpow/athpow.c

49

#define IS_5424(ah) \

tools/tools/ath/athpow/athpow.c

50

((ah)->ah_macVersion == AR_SREV_5424 || \

tools/tools/ath/athpow/athpow.c

51

((ah)->ah_macVersion == AR_SREV_5413 && \

tools/tools/ath/athpow/athpow.c

52

(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))

tools/tools/ath/athpow/athpow.c

53

#define IS_5413(ah) \

tools/tools/ath/athpow/athpow.c

54

((ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))

tools/tools/ath/athrd/athrd.c

1400

ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,

tools/tools/ath/athrd/athrd.c

1443

findEdgePower(struct ath_hal *ah, u_int ctl)

tools/tools/ath/athrd/athrd.c

1458

setRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan,

tools/tools/ath/athrd/athrd.c

1476

cfgCtl = ath_hal_getctl(ah, chan);

tools/tools/ath/athrd/athrd.c

1477

rep = findEdgePower(ah, cfgCtl);

tools/tools/ath/athrd/athrd.c

1486

rep = findEdgePower(ah, cfgCtl);

tools/tools/ath/athrd/athrd.c

1503

ath_hal_getantennareduction(ah, chan, twiceAntennaGain);

tools/tools/ath/athrd/athrd.c

1509

ar5212GetTargetPowers(ah, chan, trgtPwr_11g,

tools/tools/ath/athrd/athrd.c

1512

ar5212GetTargetPowers(ah, chan, trgtPwr_11a,

tools/tools/ath/athrd/athrd.c

1529

&& AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP

tools/tools/ath/athrd/athrd.c

1581

HALDEBUG(ah, HAL_DEBUG_ANY,

tools/tools/ath/athrd/athrd.c

1590

ar5212GetTargetPowers(ah, chan, trgtPwr_11b,

tools/tools/ath/athrd/athrd.c

1638

ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)

tools/tools/ath/athrd/athrd.c

1644

ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)

tools/tools/ath/athrd/athrd.c

1648

ath_hal_vprintf(ah, fmt, ap);

tools/tools/ath/athrd/athrd.c

1653

DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)

tools/tools/ath/athrd/athrd.c

1657

ath_hal_vprintf(ah, fmt, ap);

tools/tools/ath/athrd/athrd.c

168

getChannelEdges(struct ath_hal *ah, u_int16_t flags, u_int16_t *low, u_int16_t *high)

tools/tools/ath/athrd/athrd.c

170

struct ath_hal_private *ahp = AH_PRIVATE(ah);

tools/tools/ath/athrd/athrd.c

187

getWirelessModes(struct ath_hal *ah)

tools/tools/ath/athrd/athrd.c

774

setRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan,

tools/tools/ath/athrd/athrd.c

779

calctxpower(struct ath_hal *ah,

tools/tools/ath/athrd/athrd.c

787

if (!setRateTable(ah, &chans[i],

tools/tools/ath/athrd/athrd.c

835

ath_hal_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)

tools/tools/ath/athrd/athrd.c

872

dumpchannels(struct ath_hal *ah, int nc,

tools/tools/ath/athrd/athrd.c

883

ath_hal_mhz2ieee(ah, c->ic_freq, c->ic_flags));

tools/tools/ath/athrd/athrd.c

951

getChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)

tools/tools/ath/athrd/athrd.c

956

eepromRead(struct ath_hal *ah, u_int off, u_int16_t *data)

tools/tools/ath/athrd/athrd.c

974

getCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,

tools/tools/ath/athrd/athrd.c

977

const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;

tools/tools/ath/athrd/athrd.c

981

*result = AH_PRIVATE(ah)->ah_currentRD;

tools/tools/ath/athregs/dumpregs.c

468

fprintf(fd, " %08x", OS_REG_READ(ah, dr->addr));

tools/tools/ath/athregs/dumpregs.c

486

, r, OS_REG_READ(ah, r)

tools/tools/ath/athregs/dumpregs.c

487

, r+4, OS_REG_READ(ah, r+4)

tools/tools/ath/athregs/dumpregs.c

488

, r+8, OS_REG_READ(ah, r+8)

tools/tools/ath/athregs/dumpregs.c

489

, r+12, OS_REG_READ(ah, r+12)

tools/tools/ath/athregs/dumpregs.c

490

, r+16, OS_REG_READ(ah, r+16)

tools/tools/ath/athregs/dumpregs.c

496

, r, OS_REG_READ(ah, r)

tools/tools/ath/athregs/dumpregs.c

497

, r+4, OS_REG_READ(ah, r+4)

tools/tools/ath/athregs/dumpregs.c

498

, r+8, OS_REG_READ(ah, r+8)

tools/tools/ath/athregs/dumpregs.c

499

, r+12, OS_REG_READ(ah, r+12)

tools/tools/ath/athregs/dumpregs.c

504

, r, OS_REG_READ(ah, r)

tools/tools/ath/athregs/dumpregs.c

505

, r+4, OS_REG_READ(ah, r+4)

tools/tools/ath/athregs/dumpregs.c

506

, r+8, OS_REG_READ(ah, r+8)

tools/tools/ath/athregs/dumpregs.c

511

, r, OS_REG_READ(ah, r)

tools/tools/ath/athregs/dumpregs.c

512

, r+4, OS_REG_READ(ah, r+4)

tools/tools/ath/athregs/dumpregs.c

517

, r, OS_REG_READ(ah, r)

tools/tools/ath/athregs/dumpregs.c

530

, OS_REG_READ(ah, AR_IMR)

tools/tools/ath/athregs/dumpregs.c

531

, OS_REG_READ(ah, AR_IMR_S0)

tools/tools/ath/athregs/dumpregs.c

532

, OS_REG_READ(ah, AR_IMR_S1)

tools/tools/ath/athregs/dumpregs.c

533

, OS_REG_READ(ah, AR_IMR_S2)

tools/tools/ath/athregs/dumpregs.c

534

, OS_REG_READ(ah, AR_IMR_S3)

tools/tools/ath/athregs/dumpregs.c

535

, OS_REG_READ(ah, AR_IMR_S4)

tools/tools/ath/athregs/dumpregs.c

538

, OS_REG_READ(ah, AR_ISR)

tools/tools/ath/athregs/dumpregs.c

539

, OS_REG_READ(ah, AR_ISR_S0)

tools/tools/ath/athregs/dumpregs.c

540

, OS_REG_READ(ah, AR_ISR_S1)

tools/tools/ath/athregs/dumpregs.c

541

, OS_REG_READ(ah, AR_ISR_S2)

tools/tools/ath/athregs/dumpregs.c

542

, OS_REG_READ(ah, AR_ISR_S3)

tools/tools/ath/athregs/dumpregs.c

543

, OS_REG_READ(ah, AR_ISR_S4)

tools/tools/ath/athregs/dumpregs.c

554

, "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)

tools/tools/ath/athregs/dumpregs.c

555

, "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)

tools/tools/ath/athregs/dumpregs.c

556

, "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)

tools/tools/ath/athregs/dumpregs.c

559

, OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)

tools/tools/ath/athregs/dumpregs.c

560

, OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)

tools/tools/ath/athregs/dumpregs.c

565

, OS_REG_READ(ah, AR_QTXDP(i))

tools/tools/ath/athregs/dumpregs.c

566

, OS_REG_READ(ah, AR_QCBRCFG(i))

tools/tools/ath/athregs/dumpregs.c

567

, OS_REG_READ(ah, AR_QRDYTIMECFG(i))

tools/tools/ath/athregs/dumpregs.c

568

, OS_REG_READ(ah, AR_QMISC(i))

tools/tools/ath/athregs/dumpregs.c

569

, OS_REG_READ(ah, AR_QSTS(i))

tools/tools/ath/athregs/dumpregs.c

58

#define OS_REG_READ(ah, off) state.regdata[(off) >> 2]

tools/tools/ath/athregs/dumpregs.c

582

, OS_REG_READ(ah, AR_DQCUMASK(i))

tools/tools/ath/athregs/dumpregs.c

583

, OS_REG_READ(ah, AR_DLCL_IFS(i))

tools/tools/ath/athregs/dumpregs.c

584

, OS_REG_READ(ah, AR_DRETRY_LIMIT(i))

tools/tools/ath/athregs/dumpregs.c

585

, OS_REG_READ(ah, AR_DCHNTIME(i))

tools/tools/ath/athregs/dumpregs.c

586

, OS_REG_READ(ah, AR_DMISC(i))

tools/tools/ath/athregs/dumpregs.c

676

OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE;

tools/tools/ath/athregs/dumpregs.c

687

macHi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));

tools/tools/ath/athregs/dumpregs.c

690

macLo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));

tools/tools/ath/athregs/dumpregs.c

701

type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));

tools/tools/ath/athregs/dumpregs.c

704

key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));

tools/tools/ath/athregs/dumpregs.c

705

key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));

tools/tools/ath/athregs/dumpregs.c

706

key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));

tools/tools/ath/athregs/dumpregs.c

707

key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));

tools/tools/ath/athregs/dumpregs.c

708

key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));