sys/arm/nvidia/tegra124/tegra124_car.c
226
MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
sys/arm/nvidia/tegra124/tegra124_car.c
227
MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
sys/arm/nvidia/tegra124/tegra124_car.c
228
MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
sys/arm/nvidia/tegra124/tegra124_car.c
229
MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
sys/arm/nvidia/tegra124/tegra124_car.c
230
MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
sys/arm/nvidia/tegra124/tegra124_car.c
233
MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
sys/arm/nvidia/tegra124/tegra124_car.c
234
MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
sys/arm/nvidia/tegra124/tegra124_car.c
237
MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
sys/arm/nvidia/tegra124/tegra124_car.c
238
MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
359
MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
360
MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
361
MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
362
MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
363
MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
364
MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
365
MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
366
MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
367
MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
368
MUX(IMX8MP_SYS_PLL3_REF_SEL, "sys_pll3_ref_sel", pll_ref_p, 0, 0x114, 0, 2),
sys/arm64/freescale/imx/imx8mp_ccm.c
381
MUX(IMX8MP_AUDIO_PLL1_BYPASS, "audio_pll1_bypass", audio_pll1_bypass_p, 1, 0x00, 16, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
382
MUX(IMX8MP_AUDIO_PLL2_BYPASS, "audio_pll2_bypass", audio_pll2_bypass_p, 1, 0x14, 16, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
383
MUX(IMX8MP_VIDEO_PLL1_BYPASS, "video_pll1_bypass", video_pll1_bypass_p, 1, 0x28, 16, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
384
MUX(IMX8MP_DRAM_PLL_BYPASS, "dram_pll_bypass", dram_pll_bypass_p, 1, 0x50, 16, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
385
MUX(IMX8MP_GPU_PLL_BYPASS, "gpu_pll_bypass", gpu_pll_bypass_p, 1, 0x64, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
386
MUX(IMX8MP_VPU_PLL_BYPASS, "vpu_pll_bypass", vpu_pll_bypass_p, 1, 0x74, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
387
MUX(IMX8MP_ARM_PLL_BYPASS, "arm_pll_bypass", arm_pll_bypass_p, 1, 0x84, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
388
MUX(IMX8MP_SYS_PLL1_BYPASS, "sys_pll1_bypass", sys_pll1_bypass_p, 1, 0x94, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
389
MUX(IMX8MP_SYS_PLL2_BYPASS, "sys_pll2_bypass", sys_pll2_bypass_p, 1, 0x104, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
390
MUX(IMX8MP_SYS_PLL3_BYPASS, "sys_pll3_bypass", sys_pll3_bypass_p, 1, 0x114, 28, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
423
MUX(IMX8MP_CLK_CLKOUT1_SEL, "clkout1_sel", clkout_p, 0x128, 4, 4, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
427
MUX(IMX8MP_CLK_CLKOUT2_SEL, "clkout2_sel", clkout_p, 0x128, 20, 4, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
442
MUX(IMX8MP_CLK_A53_CORE, "arm_a53_core", a53_core_p, 0x9880, 24, 1, 1),
sys/arm64/freescale/imx/imx8mp_ccm.c
552
MUX(IMX8MP_CLK_DRAM_CORE, "dram_core_clk", dram_core_p, 0x9800, 24, 1, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
136
MUX(IMX8MQ_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x28, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
137
MUX(IMX8MQ_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x18, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
138
MUX(IMX8MQ_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x20, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
139
MUX(IMX8MQ_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x0, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
140
MUX(IMX8MQ_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x8, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
141
MUX(IMX8MQ_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x10, 16, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
142
MUX(IMX8MQ_SYS3_PLL1_REF_SEL, "sys3_pll1_ref_sel", pll_ref_p, 0, 0x48, 0, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
143
MUX(IMX8MQ_DRAM_PLL1_REF_SEL, "dram_pll1_ref_sel", pll_ref_p, 0, 0x60, 0, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
144
MUX(IMX8MQ_VIDEO2_PLL1_REF_SEL, "video2_pll1_ref_sel", pll_ref_p, 0, 0x54, 0, 2),
sys/arm64/freescale/imx/imx8mq_ccm.c
161
MUX(IMX8MQ_ARM_PLL_BYPASS, "arm_pll_bypass", arm_pll_bypass_p, 0, 0x28, 14, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
162
MUX(IMX8MQ_GPU_PLL_BYPASS, "gpu_pll_bypass", gpu_pll_bypass_p, 0, 0x18, 14, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
163
MUX(IMX8MQ_VPU_PLL_BYPASS, "vpu_pll_bypass", vpu_pll_bypass_p, 0, 0x20, 14, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
164
MUX(IMX8MQ_AUDIO_PLL1_BYPASS, "audio_pll1_bypass", audio_pll1_bypass_p, 0, 0x0, 14, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
165
MUX(IMX8MQ_AUDIO_PLL2_BYPASS, "audio_pll2_bypass", audio_pll2_bypass_p, 0, 0x8, 14, 1),
sys/arm64/freescale/imx/imx8mq_ccm.c
166
MUX(IMX8MQ_VIDEO_PLL1_BYPASS, "video_pll1_bypass", video_pll1_bypass_p, 0, 0x10, 14, 1),
sys/arm64/nvidia/tegra210/tegra210_car.c
237
MUX(TEGRA210_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 2),
sys/arm64/nvidia/tegra210/tegra210_car.c
238
MUX(0, "xusb_ssp", mux_xusb_ssp, CLK_SOURCE_XUSB_SS, 24, 1),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
491
MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
492
MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
493
MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
494
MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
495
MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
sys/arm64/qoriq/clk/lx2160a_clkgen.c
130
MUX(QORIQ_TYPE_CMUX, 0, "cg-cmux0", cmuxa_plist, 0x70000);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
132
MUX(QORIQ_TYPE_CMUX, 1, "cg-cmux1", cmuxa_plist, 0x70020);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
134
MUX(QORIQ_TYPE_CMUX, 2, "cg-cmux2", cmuxa_plist, 0x70040);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
136
MUX(QORIQ_TYPE_CMUX, 3, "cg-cmux3", cmuxa_plist, 0x70060);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
138
MUX(QORIQ_TYPE_CMUX, 4, "cg-cmux4", cmuxb_plist, 0x70080);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
140
MUX(QORIQ_TYPE_CMUX, 5, "cg-cmux5", cmuxb_plist, 0x700A0);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
142
MUX(QORIQ_TYPE_CMUX, 6, "cg-cmux6", cmuxb_plist, 0x700C0);
sys/arm64/qoriq/clk/lx2160a_clkgen.c
144
MUX(QORIQ_TYPE_CMUX, 7, "cg-cmux7", cmuxb_plist, 0x700E0);
sys/dev/clk/rockchip/rk3288_cru.c
611
MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
617
MUX(0, "i2s_pre", i2s_pre_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
619
MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
625
MUX(0, "spdif_src", cpll_gpll_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
627
MUX(0, "spdif_mux", spdif_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
669
MUX(0, "uart_src", cpll_gpll_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
671
MUX(0, "usbphy480m_src_s", usbphy480m_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
673
MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
679
MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
686
MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
692
MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
716
MUX(SCLK_MAC, "mac_clk", mac_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
720
MUX(0, "sclk_hsadc_out", hsadcout_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
724
MUX(0, "wifi_src", wifi_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
745
MUX(0, "vip_src_s", cpll_gpll_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
756
MUX(0, "sclk_edp_24m_s", edp_24m_p, 0,
sys/dev/clk/rockchip/rk3288_cru.c
838
MUX(0, "spdif_8ch_mux", spdif_8ch_p, 0,
sys/dev/clk/rockchip/rk3328_cru.c
1010
MUX(DCLK_LCDC, "vop_dclk", mux_dclk_lcdc_p, 0, 40, 1, 1),
sys/dev/clk/rockchip/rk3328_cru.c
1016
MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1),
sys/dev/clk/rockchip/rk3328_cru.c
1026
MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_p, 0, 45, 8, 1),
sys/dev/clk/rockchip/rk3328_cru.c
882
MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
889
MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
897
MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
905
MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1),
sys/dev/clk/rockchip/rk3328_cru.c
906
MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
913
MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2),
sys/dev/clk/rockchip/rk3328_cru.c
914
MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
921
MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2),
sys/dev/clk/rockchip/rk3328_cru.c
922
MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2),
sys/dev/clk/rockchip/rk3328_cru.c
929
MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2),
sys/dev/clk/rockchip/rk3328_cru.c
930
MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, 0, 18, 8, 2),
sys/dev/clk/rockchip/rk3399_cru.c
1003
MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1009
MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1015
MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1024
MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1028
MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1084
MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1090
MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1124
MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
1138
MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
875
MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
881
MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
901
MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
903
MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
911
MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
913
MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
961
MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
sys/dev/clk/rockchip/rk3399_cru.c
967
MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
sys/dev/clk/rockchip/rk3399_cru.c
973
MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
sys/dev/clk/rockchip/rk3399_cru.c
979
MUX(0, "clk_i2sout_c", i2sout_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
981
MUX(0, "clk_i2sout_src", i2sch_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
987
MUX(0, "clk_spdif_mux", spdif_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
993
MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
995
MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,
sys/dev/clk/rockchip/rk3399_cru.c
997
MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
sys/dev/clk/rockchip/rk3399_pmucru.c
795
MUX(0, "clk_wifi_sel", wifi_p, 0, 1, 14, 1),
sys/dev/clk/rockchip/rk3399_pmucru.c
796
MUX(0, "clk_timer_sel", xin24m_xin32k_p, 0, 1, 15, 1),
sys/dev/clk/rockchip/rk3399_pmucru.c
816
MUX(0, "clk_uart4_sel", uart4_p, 0, 5, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
303
MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2),
sys/dev/clk/rockchip/rk3568_cru.c
326
MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
351
MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1),
sys/dev/clk/rockchip/rk3568_cru.c
357
MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7,
sys/dev/clk/rockchip/rk3568_cru.c
360
MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
371
MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9,
sys/dev/clk/rockchip/rk3568_cru.c
376
MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
377
MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2),
sys/dev/clk/rockchip/rk3568_cru.c
378
MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
379
MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2),
sys/dev/clk/rockchip/rk3568_cru.c
380
MUX(0, "dclk_sdmmc_buffer_sel", gpll100_gpll75_gpll50_p, 0, 10, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
386
MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 0, 11, 10,
sys/dev/clk/rockchip/rk3568_cru.c
389
MUX(0, "i2s0_mclkout_tx_sel", i2s0_mclkout_tx_p, 0, 11, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
397
MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 0, 13, 10,
sys/dev/clk/rockchip/rk3568_cru.c
400
MUX(0, "i2s0_mclkout_rx_sel", i2s0_mclkout_rx_p, 0, 13, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
408
MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 0, 15, 10,
sys/dev/clk/rockchip/rk3568_cru.c
411
MUX(0, "i2s1_mclkout_tx_sel", i2s1_mclkout_tx_p, 0, 11, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
419
MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 0, 17, 10,
sys/dev/clk/rockchip/rk3568_cru.c
422
MUX(0, "i2s1_mclkout_rx_sel", i2s1_mclkout_rx_p, 0, 17, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
430
MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 0, 19, 10,
sys/dev/clk/rockchip/rk3568_cru.c
433
MUX(0, "i2s2_mclkout_sel", i2s2_mclkout_p, 0, 19, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
441
MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 0, 21, 10,
sys/dev/clk/rockchip/rk3568_cru.c
444
MUX(0, "i2s3_mclkout_tx_sel", i2s3_mclkout_tx_p, 0, 21, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
452
MUX(0, "mclk_pdm_sel", mclk_pdm_p, 0, 23, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
453
MUX(0, "clk_acdcdig_i2c_sel", clk_i2c_p, 0, 23, 10, 2),
sys/dev/clk/rockchip/rk3568_cru.c
455
MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 0, 23, 15,
sys/dev/clk/rockchip/rk3568_cru.c
464
MUX(SCLK_AUDPWM, "sck_audpwm_sel", sclk_audpwm_p, 0, 25, 15, 1),
sys/dev/clk/rockchip/rk3568_cru.c
470
MUX(0, "aclk_secure_flash_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 27, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
471
MUX(0, "hclk_secure_flash_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 27, 2, 2),
sys/dev/clk/rockchip/rk3568_cru.c
472
MUX(0, "clk_crypto_ns_core_sel", gpll200_gpll150_gpll100_p, 0, 27, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
473
MUX(0, "clk_crypto_ns_pka_sel", gpll300_gpll200_gpll100_p, 0, 27, 6, 2),
sys/dev/clk/rockchip/rk3568_cru.c
477
MUX(0, "nclk_nandc_sel", clk_nandc_p, 0, 28, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
479
MUX(0, "sclk_sfc_sel", sclk_sfc_p, 0, 28, 4, 3),
sys/dev/clk/rockchip/rk3568_cru.c
481
MUX(0, "bclk_emmc_sel", gpll200_gpll150_cpll125_p, 0, 28, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
483
MUX(0, "cclk_emmc_sel", cclk_emmc_p, 0, 28, 12, 3),
sys/dev/clk/rockchip/rk3568_cru.c
487
MUX(0, "aclk_pipe_sel", aclk_pipe_p, 0, 29, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
490
MUX(0, "clk_usb3otg0_suspend_sel", xin24m_32k_p, 0, 29, 8, 1),
sys/dev/clk/rockchip/rk3568_cru.c
491
MUX(0, "clk_usb3otg1_suspend_sel", xin24m_32k_p, 0, 29, 9, 1),
sys/dev/clk/rockchip/rk3568_cru.c
493
MUX(0, "clk_xpcs_eee_sel", gpll200_cpll125_p, 0, 29, 13, 1),
sys/dev/clk/rockchip/rk3568_cru.c
497
MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
498
MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2),
sys/dev/clk/rockchip/rk3568_cru.c
500
MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, 0, 30, 8, 3),
sys/dev/clk/rockchip/rk3568_cru.c
502
MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3),
sys/dev/clk/rockchip/rk3568_cru.c
506
MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 0, 31,
sys/dev/clk/rockchip/rk3568_cru.c
508
MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 0, 31, 2, 1),
sys/dev/clk/rockchip/rk3568_cru.c
509
MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed",
sys/dev/clk/rockchip/rk3568_cru.c
511
MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed",
sys/dev/clk/rockchip/rk3568_cru.c
513
MUX(0, "clk_mac0_2top_sel", clk_mac_2top_p, 0, 31, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
514
MUX(0, "clk_gmac0_ptp_ref_sel", clk_gmac_ptp_p, 0, 31, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
515
MUX(0, "clk_mac0_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 31, 14, 2),
sys/dev/clk/rockchip/rk3568_cru.c
523
MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
524
MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
526
MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3),
sys/dev/clk/rockchip/rk3568_cru.c
530
MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 0, 33,
sys/dev/clk/rockchip/rk3568_cru.c
532
MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 0, 33, 2, 1),
sys/dev/clk/rockchip/rk3568_cru.c
533
MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed",
sys/dev/clk/rockchip/rk3568_cru.c
535
MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed",
sys/dev/clk/rockchip/rk3568_cru.c
538
MUX(0, "clk_mac1_2top_sel", clk_mac_2top_p, 0, 33, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
539
MUX(0, "clk_gmac1_ptp_ref_sel", clk_gmac_ptp_p, 0, 33, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
540
MUX(0, "clk_mac1_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 33, 14, 2),
sys/dev/clk/rockchip/rk3568_cru.c
548
MUX(0, "aclk_vi_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 34, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
553
MUX(0, "dclk_vicap1_sel", cpll333_gpll300_gpll200_p, 0, 34, 14, 2),
sys/dev/clk/rockchip/rk3568_cru.c
565
MUX(0, "aclk_vo_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 37, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
573
MUX(0, "clk_edp_200m_sel", gpll200_gpll150_cpll125_p, 0, 38, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
595
MUX(0, "aclk_rga_pre_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 43, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
596
MUX(0, "clk_rga_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 2, 2),
sys/dev/clk/rockchip/rk3568_cru.c
597
MUX(0, "clk_iep_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
598
MUX(0, "dclk_ebc_sel", gpll400_cpll333_gpll200_p, 0, 43, 6, 2),
sys/dev/clk/rockchip/rk3568_cru.c
632
MUX(0, "aclk_bus_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 50, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
634
MUX(0, "pclk_bus_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 50, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
647
MUX(0, "sclk_uart1_sel", sclk_uart1_p, 0, 52, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
656
MUX(0, "sclk_uart2_sel", sclk_uart2_p, 0, 52, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
665
MUX(0, "sclk_uart3_sel", sclk_uart3_p, 0, 56, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
674
MUX(0, "sclk_uart4_sel", sclk_uart4_p, 0, 58, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
683
MUX(0, "sclk_uart5_sel", sclk_uart5_p, 0, 60, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
692
MUX(0, "sclk_uart6_sel", sclk_uart6_p, 0, 62, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
701
MUX(0, "sclk_uart7_sel", sclk_uart7_p, 0, 64, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
710
MUX(0, "sclk_uart8_sel", sclk_uart8_p, 0, 66, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
719
MUX(0, "sclk_uart9_sel", sclk_uart9_p, 0, 68, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
733
MUX(0, "clk_i2c_sel", clk_i2c_p, 0, 71, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
737
MUX(0, "clk_spi0_sel", gpll200_xin24m_cpll100_p, 0, 72, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
738
MUX(0, "clk_spi1_sel", gpll200_xin24m_cpll100_p, 0, 72, 2, 2),
sys/dev/clk/rockchip/rk3568_cru.c
739
MUX(0, "clk_spi2_sel", gpll200_xin24m_cpll100_p, 0, 72, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
740
MUX(0, "clk_spi3_sel", gpll200_xin24m_cpll100_p, 0, 72, 6, 2),
sys/dev/clk/rockchip/rk3568_cru.c
741
MUX(0, "clk_pwm1_sel", gpll100_xin24m_cpll100_p, 0, 72, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
742
MUX(0, "clk_pwm2_sel", gpll100_xin24m_cpll100_p, 0, 72, 10, 2),
sys/dev/clk/rockchip/rk3568_cru.c
743
MUX(0, "clk_pwm3_sel", gpll100_xin24m_cpll100_p, 0, 72, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
744
MUX(0, "dbclk_gpio_sel", xin24m_32k_p, 0, 72, 14, 1),
sys/dev/clk/rockchip/rk3568_cru.c
748
MUX(0, "aclk_top_high_sel", cpll500_gpll400_gpll300_xin24m_p, 0, 73, 0, 2),
sys/dev/clk/rockchip/rk3568_cru.c
750
MUX(0, "aclk_top_low_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 73, 4, 2),
sys/dev/clk/rockchip/rk3568_cru.c
752
MUX(0, "hclk_top_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 73, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
754
MUX(0, "pclk_top_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 73, 12, 2),
sys/dev/clk/rockchip/rk3568_cru.c
756
MUX(0, "clk_optc_arb_sel", xin24m_cpll100_p, 0, 73, 15 , 1),
sys/dev/clk/rockchip/rk3568_cru.c
797
MUX(0, "clk_i2s3_2ch_rx_src_sel", gpll_cpll_npll_p, 0, 83, 8, 2),
sys/dev/clk/rockchip/rk3568_cru.c
798
MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 0, 83, 10,
sys/dev/clk/rockchip/rk3568_cru.c
801
MUX(0, "i2s3_mclkout_rx_sel", i2s3_mclkout_rx_p, 0, 83, 15, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
111
MUX(0, "clk_rtc_32k_mux", clk_rtc32k_pmu_p, 0, 0, 6, 2),
sys/dev/clk/rockchip/rk3568_pmucru.c
118
MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 2, 15, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
125
MUX(0, "sclk_uart0_div_sel", sclk_uart0_div_p, 0, 4, 8, 2),
sys/dev/clk/rockchip/rk3568_pmucru.c
126
MUX(0, "sclk_uart0_mux", sclk_uart0_p, 0, 4, 10, 2),
sys/dev/clk/rockchip/rk3568_pmucru.c
133
MUX(0, "clk_pwm0_sel", clk_pwm0_p, 0, 6, 7, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
134
MUX(0, "dbclk_gpio0_sel", xin24m_32k_p, 0, 6, 15, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
140
MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 8, 0, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
141
MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 8, 1, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
142
MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 8, 2, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
143
MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 8, 3, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
144
MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, 8, 7, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
146
MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, 0, 8, 15, 1),
sys/dev/clk/rockchip/rk3568_pmucru.c
150
MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref",
sys/dev/clk/rockchip/rk3568_pmucru.c
153
MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref",
sys/dev/clk/rockchip/rk3568_pmucru.c
156
MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref",
