crypto/libressl/apps/openssl/passwd.c

121

.opt.flag = &passwd_config.table,

crypto/libressl/apps/openssl/passwd.c

240

passwd_config.table, passwd_config.reverse,

crypto/libressl/apps/openssl/passwd.c

265

passwd_config.quiet, passwd_config.table,

crypto/libressl/apps/openssl/passwd.c

40

char *passwd, BIO * out, int quiet, int table, int reverse,

crypto/libressl/apps/openssl/passwd.c

440

char *passwd, BIO * out, int quiet, int table, int reverse,

crypto/libressl/apps/openssl/passwd.c

50

int table;

crypto/libressl/apps/openssl/passwd.c

505

if (table && !reverse)

crypto/libressl/apps/openssl/passwd.c

507

else if (table && reverse)

crypto/libressl/crypto/bn/bn_exp.c

573

BN_ULONG *table = (BN_ULONG *)buf;

crypto/libressl/crypto/bn/bn_exp.c

579

table[j] = b->d[i];

crypto/libressl/crypto/bn/bn_exp.c

591

volatile BN_ULONG *table = (volatile BN_ULONG *)buf;

crypto/libressl/crypto/bn/bn_exp.c

597

for (i = 0; i < top; i++, table += width) {

crypto/libressl/crypto/bn/bn_exp.c

601

acc |= table[j] &

crypto/libressl/crypto/bn/bn_exp.c

619

for (i = 0; i < top; i++, table += width) {

crypto/libressl/crypto/bn/bn_exp.c

623

acc |= ( (table[j + 0 * xstride] & y0) |

crypto/libressl/crypto/bn/bn_exp.c

624

(table[j + 1 * xstride] & y1) |

crypto/libressl/crypto/bn/bn_exp.c

625

(table[j + 2 * xstride] & y2) |

crypto/libressl/crypto/bn/bn_exp.c

626

(table[j + 3 * xstride] & y3) )

crypto/libressl/crypto/bn/bn_exp.c

752

const void *table, const BN_ULONG *np,

crypto/libressl/crypto/bn/bn_exp.c

755

void *table, size_t power);

crypto/libressl/crypto/bn/bn_exp.c

757

void *table, size_t power);

crypto/libressl/crypto/engine/eng_int.h

116

int engine_table_register(ENGINE_TABLE **table, ENGINE_CLEANUP_CB *cleanup,

crypto/libressl/crypto/engine/eng_int.h

118

void engine_table_unregister(ENGINE_TABLE **table, ENGINE *e);

crypto/libressl/crypto/engine/eng_int.h

119

void engine_table_cleanup(ENGINE_TABLE **table);

crypto/libressl/crypto/engine/eng_int.h

121

ENGINE *engine_table_select(ENGINE_TABLE **table, int nid);

crypto/libressl/crypto/engine/eng_int.h

123

ENGINE *engine_table_select_tmp(ENGINE_TABLE **table, int nid, const char *f,

crypto/libressl/crypto/engine/eng_int.h

129

void engine_table_doall(ENGINE_TABLE *table, engine_table_doall_cb *cb,

crypto/libressl/crypto/engine/eng_table.c

135

engine_table_register(ENGINE_TABLE **table, ENGINE_CLEANUP_CB *cleanup,

crypto/libressl/crypto/engine/eng_table.c

142

if (!(*table))

crypto/libressl/crypto/engine/eng_table.c

144

if (!int_table_check(table, 1))

crypto/libressl/crypto/engine/eng_table.c

151

fnd = lh_ENGINE_PILE_retrieve(&(*table)->piles, &tmplate);

crypto/libressl/crypto/engine/eng_table.c

164

(void)lh_ENGINE_PILE_insert(&(*table)->piles, fnd);

crypto/libressl/crypto/engine/eng_table.c

209

engine_table_unregister(ENGINE_TABLE **table, ENGINE *e)

crypto/libressl/crypto/engine/eng_table.c

212

if (int_table_check(table, 0))

crypto/libressl/crypto/engine/eng_table.c

213

lh_ENGINE_PILE_doall_arg(&(*table)->piles,

crypto/libressl/crypto/engine/eng_table.c

229

engine_table_cleanup(ENGINE_TABLE **table)

crypto/libressl/crypto/engine/eng_table.c

232

if (*table) {

crypto/libressl/crypto/engine/eng_table.c

233

lh_ENGINE_PILE_doall(&(*table)->piles,

crypto/libressl/crypto/engine/eng_table.c

235

lh_ENGINE_PILE_free(&(*table)->piles);

crypto/libressl/crypto/engine/eng_table.c

236

*table = NULL;

crypto/libressl/crypto/engine/eng_table.c

244

engine_table_select(ENGINE_TABLE **table, int nid)

crypto/libressl/crypto/engine/eng_table.c

247

engine_table_select_tmp(ENGINE_TABLE **table, int nid, const char *f, int l)

crypto/libressl/crypto/engine/eng_table.c

254

if (!(*table)) {

crypto/libressl/crypto/engine/eng_table.c

265

if (!int_table_check(table, 0))

crypto/libressl/crypto/engine/eng_table.c

268

fnd = lh_ENGINE_PILE_retrieve(&(*table)->piles, &tmplate);

crypto/libressl/crypto/engine/eng_table.c

346

engine_table_doall(ENGINE_TABLE *table, engine_table_doall_cb *cb, void *arg)

crypto/libressl/crypto/engine/eng_table.c

352

lh_ENGINE_PILE_doall_arg(&table->piles, LHASH_DOALL_ARG_FN(int_cb),

crypto/libressl/include/openssl/x509v3.h

395

#define EXT_BITSTRING(nid, table) { nid, 0, &ASN1_BIT_STRING_it, \

crypto/libressl/include/openssl/x509v3.h

401

table}

crypto/openssh/channels.c

2596

channel_handler(struct ssh *ssh, int table, struct timespec *timeout)

crypto/openssh/channels.c

2599

chan_fn **ftab = table == CHAN_PRE ? sc->channel_pre : sc->channel_post;

crypto/openssh/channels.c

2613

if (table == CHAN_PRE)

crypto/openssh/channels.c

2619

if (table == CHAN_PRE && c->type == SSH_CHANNEL_OPEN &&

games/backgammon/common_source/back.h

102

extern int table[6][6]; /* odds table for possible rolls */

games/backgammon/common_source/init.c

85

int table[6][6];

games/backgammon/common_source/odds.c

43

table[i][j] = 0;

games/backgammon/common_source/odds.c

49

table[i][r1] += val;

games/backgammon/common_source/odds.c

50

table[r1][i] += val;

games/backgammon/common_source/odds.c

53

table[r2][r1] += val;

games/backgammon/common_source/odds.c

54

table[r1][r2] += val;

games/backgammon/common_source/odds.c

69

total += table[i][j];

games/ching/castching/castching.c

101

string[i] = table[getrnum()&01][getrnum()&01][getrnum()&01] + '0';

games/ching/castching/castching.c

62

static int table[2][2][2] = {

games/ching/printching/printching.c

133

if (table[i].lines == lower)

games/ching/printching/printching.c

134

lnum = table[i].trinum;

games/ching/printching/printching.c

135

if (table[i].lines == upper)

games/ching/printching/printching.c

136

unum = table[i].trinum;

games/ching/printching/printching.c

58

} table[] = {

games/primes/primes.c

255

memcpy(table, &pattern[factor], pattern_size-factor);

games/primes/primes.c

259

memcpy(&table[fact_lim], pattern, pattern_size);

games/primes/primes.c

262

memcpy(&table[fact_lim], pattern, TABSIZE-fact_lim);

games/primes/primes.c

269

tab_lim = &table[TABSIZE]; /* sieve it all */

games/primes/primes.c

272

tab_lim = &table[(stop-start)/2]; /* partial sieve */

games/primes/primes.c

282

q = &table[(factor-mod)/2];

games/primes/primes.c

284

q = &table[mod ? factor-(mod/2) : 0];

games/primes/primes.c

296

for (q = table; q < tab_lim; ++q, start+=2) {

games/primes/primes.c

76

static char table[TABSIZE]; /* Eratosthenes sieve of odd numbers */

games/sail/dr_1.c

395

table(sp, closest, shootat, load, hit,

games/sail/dr_2.c

122

table(sp, sq, RIGGING, L_EXPLODE,

games/sail/extern.h

259

void table(struct ship *, struct ship *, int, int, int, int);

games/sail/pl_3.c

199

table(ms, closest, shootat, load, hit, roll);

lib/libc/gen/fnmatch.c

218

struct xlocale_collate *table =

lib/libc/gen/fnmatch.c

274

if (table->__collate_load_error ?

lib/libc/gen/glob.c

806

struct xlocale_collate *table =

lib/libc/gen/glob.c

832

if (table->__collate_load_error ?

lib/libc/locale/collate.c

105

__collate_load_tables_l(const char *encoding, struct xlocale_collate *table)

lib/libc/locale/collate.c

115

table->__collate_load_error = 1;

lib/libc/locale/collate.c

172

if (table->map && (table->maplen > 0)) {

lib/libc/locale/collate.c

173

(void) munmap(table->map, table->maplen);

lib/libc/locale/collate.c

175

table->map = map;

lib/libc/locale/collate.c

176

table->maplen = sbuf.st_size;

lib/libc/locale/collate.c

177

table->info = info;

lib/libc/locale/collate.c

178

table->char_pri_table = (void *)TMP;

lib/libc/locale/collate.c

183

table->subst_table[z] = (void *)TMP;

lib/libc/locale/collate.c

186

table->subst_table[z] = NULL;

lib/libc/locale/collate.c

191

table->chain_pri_table = (void *)TMP;

lib/libc/locale/collate.c

194

table->chain_pri_table = NULL;

lib/libc/locale/collate.c

196

table->large_pri_table = (void *)TMP;

lib/libc/locale/collate.c

198

table->large_pri_table = NULL;

lib/libc/locale/collate.c

200

table->__collate_load_error = 0;

lib/libc/locale/collate.c

205

substsearch(struct xlocale_collate *table, const wchar_t key, int pass)

lib/libc/locale/collate.c

208

int n = table->info->subst_count[pass];

lib/libc/locale/collate.c

213

if (pass >= table->info->directive_count)

lib/libc/locale/collate.c

219

p = table->subst_table[pass] + (key & ~COLLATE_SUBST_PRIORITY);

lib/libc/locale/collate.c

225

chainsearch(struct xlocale_collate *table, const wchar_t *key, int *len)

lib/libc/locale/collate.c

228

int high = table->info->chain_count - 1;;

lib/libc/locale/collate.c

231

collate_chain_t *tab = table->chain_pri_table;

lib/libc/locale/collate.c

257

largesearch(struct xlocale_collate *table, const wchar_t key)

lib/libc/locale/collate.c

260

int high = table->info->large_count - 1;

lib/libc/locale/collate.c

263

collate_large_t *tab = table->large_pri_table;

lib/libc/locale/collate.c

283

_collate_lookup(struct xlocale_collate *table, const wchar_t *t, int *len,

lib/libc/locale/collate.c

295

if (which >= table->info->directive_count) {

lib/libc/locale/collate.c

324

if (((p2 = chainsearch(table, t, &l)) != NULL) &&

lib/libc/locale/collate.c

336

*pri = table->char_pri_table[*t].pri[which];

lib/libc/locale/collate.c

338

} else if ((table->info->large_count > 0) &&

lib/libc/locale/collate.c

339

((match = largesearch(table, *t)) != NULL)) {

lib/libc/locale/collate.c

350

if (table->info->directive[which] & DIRECTIVE_UNDEFINED) {

lib/libc/locale/collate.c

354

*pri = table->info->undef_pri[which];

lib/libc/locale/collate.c

372

if ((sptr = substsearch(table, *pri, which)) != NULL) {

lib/libc/locale/collate.c

386

_collate_wxfrm(struct xlocale_collate *table, const wchar_t *src, wchar_t *xf,

lib/libc/locale/collate.c

398

int ndir = table->info->directive_count;

lib/libc/locale/collate.c

419

direc = table->info->directive[pass];

lib/libc/locale/collate.c

444

_collate_lookup(table, t, &len, &pri, pass, &state);

lib/libc/locale/collate.c

463

_collate_lookup(table, t, &len, &pri, pass, &state);

lib/libc/locale/collate.c

515

xfrm(struct xlocale_collate *table, unsigned char *p, int pri, int pass)

lib/libc/locale/collate.c

518

uint32_t val = (uint32_t)table->info->pri_count[pass];

lib/libc/locale/collate.c

532

_collate_sxfrm(struct xlocale_collate *table, const wchar_t *src, char *xf,

lib/libc/locale/collate.c

546

int ndir = table->info->directive_count;

lib/libc/locale/collate.c

567

direc = table->info->directive[pass];

lib/libc/locale/collate.c

593

_collate_lookup(table, t, &len, &pri, pass, &state);

lib/libc/locale/collate.c

604

b = xfrm(table, buf, pri, pass);

lib/libc/locale/collate.c

619

_collate_lookup(table, t, &len, &pri, pass, &state);

lib/libc/locale/collate.c

630

b = xfrm(table, buf, pri, pass);

lib/libc/locale/collate.c

66

__collate_load_tables_l(const char *encoding, struct xlocale_collate *table);

lib/libc/locale/collate.c

669

struct xlocale_collate *table =

lib/libc/locale/collate.c

672

if (table->__collate_load_error)

lib/libc/locale/collate.c

678

e = table->char_pri_table[*str].pri[0];

lib/libc/locale/collate.c

679

else if (table->info->large_count > 0) {

lib/libc/locale/collate.c

681

match_large = largesearch(table, *str);

lib/libc/locale/collate.c

689

if (table->info->chain_count > 0) {

lib/libc/locale/collate.c

696

match_chain = chainsearch(table, name, &clen);

lib/libc/locale/collate.c

71

struct xlocale_collate *table = t;

lib/libc/locale/collate.c

72

if (table->map && (table->maplen > 0)) {

lib/libc/locale/collate.c

73

(void) munmap(table->map, table->maplen);

lib/libc/locale/collate.c

84

struct xlocale_collate *table = calloc(sizeof(struct xlocale_collate), 1);

lib/libc/locale/collate.c

85

table->header.header.destructor = destruct_collate;

lib/libc/locale/collate.c

88

if (__collate_load_tables_l(encoding, table) != _LDP_LOADED) {

lib/libc/locale/collate.c

89

xlocale_release(table);

lib/libc/locale/collate.c

92

return table;

lib/libc/stdio/printf-pos.c

101

if (types->table != types->stattable)

lib/libc/stdio/printf-pos.c

102

free(types->table);

lib/libc/stdio/printf-pos.c

132

types->table[types->nextarg++] = type;

lib/libc/stdio/printf-pos.c

143

types->table[types->nextarg++] = T_INTMAXT;

lib/libc/stdio/printf-pos.c

145

types->table[types->nextarg++] = T_SSIZET;

lib/libc/stdio/printf-pos.c

147

types->table[types->nextarg++] = T_PTRDIFFT;

lib/libc/stdio/printf-pos.c

149

types->table[types->nextarg++] = T_LLONG;

lib/libc/stdio/printf-pos.c

151

types->table[types->nextarg++] = T_LONG;

lib/libc/stdio/printf-pos.c

153

types->table[types->nextarg++] = T_INT;

lib/libc/stdio/printf-pos.c

164

types->table[types->nextarg++] = T_UINTMAXT;

lib/libc/stdio/printf-pos.c

166

types->table[types->nextarg++] = T_SIZET;

lib/libc/stdio/printf-pos.c

168

types->table[types->nextarg++] = T_SIZET;

lib/libc/stdio/printf-pos.c

170

types->table[types->nextarg++] = T_U_LLONG;

lib/libc/stdio/printf-pos.c

172

types->table[types->nextarg++] = T_U_LONG;

lib/libc/stdio/printf-pos.c

174

types->table[types->nextarg++] = T_U_INT;

lib/libc/stdio/printf-pos.c

621

enum typeid *const oldtable = types->table;

lib/libc/stdio/printf-pos.c

640

types->table = newtable;

lib/libc/stdio/printf-pos.c

664

switch (types->table[n]) {

lib/libc/stdio/printf-pos.c

68

enum typeid *table; /* table of types */

lib/libc/stdio/printf-pos.c

86

types->table = types->stattable;

lib/libc/stdio/printf-pos.c

91

types->table[n] = T_UNUSED;

lib/libc/stdio/vfscanf.c

824

struct xlocale_collate *table =

lib/libc/stdio/vfscanf.c

879

|| (table->__collate_load_error ? n < c :

lib/libc/stdio/vfscanf.c

888

if (table->__collate_load_error) {

lib/libc/string/strcoll.c

71

struct xlocale_collate *table =

lib/libc/string/strcoll.c

74

if (table->__collate_load_error)

lib/libc/string/strxfrm.c

55

struct xlocale_collate *table =

lib/libc/string/strxfrm.c

71

if (table->__collate_load_error)

lib/libc/string/strxfrm.c

80

if ((xlen = _collate_sxfrm(table, wcs, dest, len)) == (size_t)-1)

lib/libc/string/wcscoll.c

116

_collate_lookup(table, w1, &len1,

lib/libc/string/wcscoll.c

129

_collate_lookup(table, w2, &len2,

lib/libc/string/wcscoll.c

155

_collate_lookup(table, w1,

lib/libc/string/wcscoll.c

168

_collate_lookup(table, w2,

lib/libc/string/wcscoll.c

47

struct xlocale_collate *table =

lib/libc/string/wcscoll.c

50

if (table->__collate_load_error)

lib/libc/string/wcscoll.c

71

for (pass = 0; pass <= table->info->directive_count; pass++) {

lib/libc/string/wcscoll.c

80

if (pass == table->info->directive_count) {

lib/libc/string/wcscoll.c

83

direc = table->info->directive[pass];

lib/libc/string/wcsxfrm.c

44

struct xlocale_collate *table =

lib/libc/string/wcsxfrm.c

53

if ((table->__collate_load_error) ||

lib/libc/string/wcsxfrm.c

54

((slen = _collate_wxfrm(table, src, dest, len)) == (size_t)-1)) {

lib/libipfw3/basic/ipfw3_basic.c

101

match_token(struct char_int_map *table, char *string)

lib/libipfw3/basic/ipfw3_basic.c

103

while (table->key) {

lib/libipfw3/basic/ipfw3_basic.c

104

if (strcmp(table->key, string) == 0) {

lib/libipfw3/basic/ipfw3_basic.c

105

return table->val;

lib/libipfw3/basic/ipfw3_basic.c

107

table++;

lib/libipfw3/basic/ipfw3_basic.c

113

match_token2(struct char_int_map *table, int val)

lib/libipfw3/basic/ipfw3_basic.c

115

while (table->val) {

lib/libipfw3/basic/ipfw3_basic.c

116

if (table->val == val)

lib/libipfw3/basic/ipfw3_basic.c

117

return table->key;

lib/libipfw3/basic/ipfw3_basic.c

119

table++;

lib/libkiconv/xlat16_iconv.c

149

uint32_t table[0x80];

lib/libkiconv/xlat16_iconv.c

195

table[us] = c | XLAT16_HAS_LOWER_CASE;

lib/libkiconv/xlat16_iconv.c

200

table[us] = c | XLAT16_HAS_UPPER_CASE;

lib/libkiconv/xlat16_iconv.c

202

table[us] = 0;

lib/libkiconv/xlat16_iconv.c

206

if (table[us])

lib/libkiconv/xlat16_iconv.c

207

xt.idx[ls] = table;

lib/libkiconv/xlat16_iconv.c

219

table[us] = 0;

lib/libkiconv/xlat16_iconv.c

229

table[us] = (ud << 8) | ld;

lib/libkiconv/xlat16_iconv.c

230

table[us] |= (u_char)dst[2] << 16;

lib/libkiconv/xlat16_iconv.c

231

table[us] |= XLAT16_IS_3BYTE_CHR;

lib/libkiconv/xlat16_iconv.c

233

table[us] = 0;

lib/libkiconv/xlat16_iconv.c

238

table[us] = quirk_unix2vendor((ud << 8) | ld,

lib/libkiconv/xlat16_iconv.c

240

if ((table[us] >> 8) == 0)

lib/libkiconv/xlat16_iconv.c

241

table[us] |= XLAT16_ACCEPT_NULL_OUT;

lib/libkiconv/xlat16_iconv.c

244

table[us] = ud;

lib/libkiconv/xlat16_iconv.c

246

table[us] |= (u_char)tolower(ud) << 16;

lib/libkiconv/xlat16_iconv.c

247

table[us] |= XLAT16_HAS_LOWER_CASE;

lib/libkiconv/xlat16_iconv.c

250

table[us] |= (u_char)toupper(ud) << 16;

lib/libkiconv/xlat16_iconv.c

251

table[us] |= XLAT16_HAS_UPPER_CASE;

lib/libkiconv/xlat16_iconv.c

259

table[us] |= XLAT16_ACCEPT_NULL_IN;

lib/libkiconv/xlat16_iconv.c

264

table[us] |= (u_char)tolower(c) << 16;

lib/libkiconv/xlat16_iconv.c

265

table[us] |= XLAT16_HAS_FROM_LOWER_CASE;

lib/libkiconv/xlat16_iconv.c

268

table[us] |= (u_char)toupper(c) << 16;

lib/libkiconv/xlat16_iconv.c

269

table[us] |= XLAT16_HAS_FROM_UPPER_CASE;

lib/libkiconv/xlat16_iconv.c

274

if (table[us] == 0)

lib/libkiconv/xlat16_iconv.c

280

xt.idx[ls] = table;

lib/libkiconv/xlat16_iconv.c

283

memcpy(p, table, sizeof(table));

lib/libkiconv/xlat16_iconv.c

284

p += sizeof(table);

lib/libldns/ldns/util.h

168

ldns_lookup_table *ldns_lookup_by_name(ldns_lookup_table table[],

lib/libldns/ldns/util.h

177

ldns_lookup_table *ldns_lookup_by_id(ldns_lookup_table table[], int id);

lib/libtelnet/genget.c

68

genget(char *name, char **table, int stlen)

lib/libtelnet/genget.c

77

for (c = table; *c != NULL; c = (char **)((char *)c + stlen)) {

libexec/bootpd/hash.c

129

bucketptr = hashtable->table;

libexec/bootpd/hash.c

135

hashtable->member = (hashtable->table)[0];

libexec/bootpd/hash.c

186

memberptr = (hashtable->table)[hashcode % (hashtable->size)];

libexec/bootpd/hash.c

223

temp->next = (hashtable->table)[hashcode];

libexec/bootpd/hash.c

224

(hashtable->table)[hashcode] = temp;

libexec/bootpd/hash.c

252

memberptr = (hashtable->table)[hashcode];

libexec/bootpd/hash.c

254

(hashtable->table)[hashcode] = memberptr->next;

libexec/bootpd/hash.c

260

memberptr = (hashtable->table)[hashcode];

libexec/bootpd/hash.c

304

memberptr = (hashtable->table)[hashcode % (hashtable->size)];

libexec/bootpd/hash.c

340

!(memberptr = (hashtable->table)[bucket])) {

libexec/bootpd/hash.c

352

hashtable->member = (hashtable->table)[0];

libexec/bootpd/hash.c

376

hashtable->member = (hashtable->table)[0];

libexec/bootpd/hash.c

88

hashtblptr->member = (hashtblptr->table)[0];

libexec/bootpd/hash.h

115

hash_member *table[1]; /* Dynamically extended */

libexec/mknetid/hash.c

111

lookup(struct member_entry *table[], char *key)

libexec/mknetid/hash.c

115

cur = table[hashkey(key)];

libexec/mknetid/hash.c

132

mstore(struct member_entry *table[], char *key, int gid, int dup)

libexec/mknetid/hash.c

139

cur = table[i];

libexec/mknetid/hash.c

164

new->next = table[i];

libexec/mknetid/hash.c

165

table[i] = new;

libexec/revnetgroup/hash.c

111

lookup(struct group_entry *table[], char *key)

libexec/revnetgroup/hash.c

115

cur = table[hashkey(key)];

libexec/revnetgroup/hash.c

144

store(struct group_entry *table[], char *key, char *data)

libexec/revnetgroup/hash.c

154

new->next = table[i];

libexec/revnetgroup/hash.c

155

table[i] = new;

libexec/revnetgroup/hash.c

173

mstore(struct member_entry *table[], char *key, char *data, char *domain)

libexec/revnetgroup/hash.c

180

cur = table[i];

libexec/revnetgroup/hash.c

201

new->next = table[i];

libexec/revnetgroup/hash.c

202

table[i] = new;

libexec/talkd/table.c

122

for (ptr = table; ptr != NULL; ptr = ptr->next) {

libexec/talkd/table.c

163

ptr->next = table;

libexec/talkd/table.c

167

table = ptr;

libexec/talkd/table.c

193

ptr = table;

libexec/talkd/table.c

196

for (ptr = table; ptr != NULL; ptr = ptr->next) {

libexec/talkd/table.c

218

if (table == ptr)

libexec/talkd/table.c

219

table = ptr->next;

libexec/talkd/table.c

69

TABLE_ENTRY *table = NULL;

libexec/talkd/table.c

85

for (ptr = table; ptr != NULL; ptr = ptr->next) {

sbin/dump/optr.c

285

static SLIST_HEAD(, pfstab) table;

sbin/dump/optr.c

307

SLIST_INSERT_HEAD(&table, pf, pf_list);

sbin/dump/optr.c

325

SLIST_FOREACH(pf, &table, pf_list) {

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

119

*(*table)++ = here; /* make a table to force an error */

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

120

*(*table)++ = here;

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

201

next = *table; /* current table to fill in */

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

284

(*table)[low].op = (unsigned char)curr;

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

285

(*table)[low].bits = (unsigned char)root;

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

286

(*table)[low].val = (unsigned short)(next - *table);

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

301

*table += used;

sbin/hammer2/zlib/hammer2_zlib_inftrees.c

35

code FAR * FAR *table, unsigned FAR *bits,

sbin/hammer2/zlib/hammer2_zlib_inftrees.h

61

unsigned codes, code FAR * FAR *table,

sbin/ipfw/ipfw2.c

362

match_token(struct _s_x *table, char *string)

sbin/ipfw/ipfw2.c

367

for (pt = table ; i && pt->s != NULL ; pt++)

sbin/ipfw3/ipfw3.c

102

match_token(struct char_int_map *table, char *string)

sbin/ipfw3/ipfw3.c

104

while (table->key) {

sbin/ipfw3/ipfw3.c

105

if (strcmp(table->key, string) == 0) {

sbin/ipfw3/ipfw3.c

106

return table->val;

sbin/ipfw3/ipfw3.c

108

table++;

sbin/ipfw3/ipfw3.h

151

int match_token(struct char_int_map *table, char *string);

sys/bus/cam/scsi/scsi_all.c

614

struct op_table_entry *table[2];

sys/bus/cam/scsi/scsi_all.c

626

table[0] = ((struct scsi_op_quirk_entry *)match)->op_table;

sys/bus/cam/scsi/scsi_all.c

628

table[1] = scsi_op_codes;

sys/bus/cam/scsi/scsi_all.c

639

table[0] = scsi_op_codes;

sys/bus/cam/scsi/scsi_all.c

651

for (i = 0;i < num_ops[j] && table[j][i].opcode <= opcode; i++){

sys/bus/cam/scsi/scsi_all.c

652

if ((table[j][i].opcode == opcode)

sys/bus/cam/scsi/scsi_all.c

653

&& ((table[j][i].opmask & opmask) != 0))

sys/bus/cam/scsi/scsi_all.c

654

return(table[j][i].desc);

sys/bus/ppbus/ppb_msq.c

104

return (&table[index]);

sys/bus/ppbus/ppb_msq.c

58

struct ppb_xfer *table;

sys/bus/ppbus/ppb_msq.c

62

table = ppbdev->get_xfer;

sys/bus/ppbus/ppb_msq.c

66

table = ppbdev->put_xfer;

sys/ddb/db_command.c

163

static void db_cmd_list (struct command *table,

sys/ddb/db_command.c

166

static int db_cmd_search (char *name, struct command *table,

sys/ddb/db_command.c

182

db_cmd_search(char *name, struct command *table, struct command **aux_tablep,

sys/ddb/db_command.c

189

for (cmd = table; cmd->name != 0; cmd++) {

sys/ddb/db_command.c

261

db_cmd_list(struct command *table, struct command **aux_tablep,

sys/ddb/db_command.c

267

for (cmd = table; cmd->name != 0; cmd++) {

sys/dev/apple/fw/apple_fw.c

221

ACPI_TABLE_HEADER *table;

sys/dev/apple/fw/apple_fw.c

229

status = AcpiGetTable(ACPI_SIG_SSDT, instance, &table);

sys/dev/apple/fw/apple_fw.c

234

if (strncmp(table->OemId, "APPLE ", ACPI_OEM_ID_SIZE) != 0)

sys/dev/apple/fw/apple_fw.c

241

memcpy(sc->sc_ssdts[n].oem_table_id, table->OemTableId,

sys/dev/disk/ahci/ahci.c

245

struct ahci_cmd_table *table;

sys/dev/disk/ahci/ahci.c

398

table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table);

sys/dev/disk/ahci/ahci.c

417

ccb->ccb_cmd_table = &table[i];

sys/dev/disk/dm/crypt/dm_target_crypt.c

1083

dmt->table = &dm_target_crypt_table;

sys/dev/disk/dm/delay/dm_target_delay.c

431

dmt->table = &dm_target_delay_table;

sys/dev/disk/dm/dm.h

165

char *(*table)(void *); /* DM_STATUS_TABLE_FLAG */

sys/dev/disk/dm/dm_ioctl.c

978

if (is_table && table_en->target->table) {

sys/dev/disk/dm/dm_ioctl.c

979

params = table_en->target->table(cfg);

sys/dev/disk/dm/dm_table.c

172

_dm_table_size(dm_table_head_t *head, int table)

sys/dev/disk/dm/dm_table.c

181

tbl = dm_table_get_entry(head, table);

sys/dev/disk/dm/flakey/dm_target_flakey.c

419

dmt->table = &dm_target_flakey_table;

sys/dev/disk/dm/linear/dm_target_linear.c

183

dmt->table = &dm_target_linear_table;

sys/dev/disk/dm/striped/dm_target_striped.c

494

dmt->table = &dm_target_stripe_table;

sys/dev/disk/mpt/mpt_debug.c

657

mpt_decode_value(mpt_decode_entry_t *table, u_int num_entries,

sys/dev/disk/mpt/mpt_debug.c

675

if (table == NULL) {

sys/dev/disk/mpt/mpt_debug.c

685

if (((value & table[entry].mask)

sys/dev/disk/mpt/mpt_debug.c

686

!= table[entry].value)

sys/dev/disk/mpt/mpt_debug.c

687

|| ((printed_mask & table[entry].mask)

sys/dev/disk/mpt/mpt_debug.c

688

== table[entry].mask))

sys/dev/disk/mpt/mpt_debug.c

693

table[entry].name);

sys/dev/disk/mpt/mpt_debug.c

694

printed_mask |= table[entry].mask;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

299

#define amdgpu_dpm_get_pp_table(adev, table) \

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

300

((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

447

char *table = NULL;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

451

size = amdgpu_dpm_get_pp_table(adev, &table);

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

458

memcpy(buf, table, size);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1457

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1463

table->FpsHighT = cpu_to_be16(tmp);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1466

table->FpsLowT = cpu_to_be16(tmp);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2358

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2363

table->VddcLevelCount = pi->vddc_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2364

for (count = 0; count < table->VddcLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2367

&table->VddcLevel[count]);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2370

table->VddcLevel[count].Smio |=

sys/dev/drm/amd/amdgpu/ci_dpm.c

2373

table->VddcLevel[count].Smio = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2375

table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2381

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2386

table->VddciLevelCount = pi->vddci_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2387

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2390

&table->VddciLevel[count]);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2393

table->VddciLevel[count].Smio |=

sys/dev/drm/amd/amdgpu/ci_dpm.c

2396

table->VddciLevel[count].Smio = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2398

table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2404

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2409

table->MvddLevelCount = pi->mvdd_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2410

for (count = 0; count < table->MvddLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2413

&table->MvddLevel[count]);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2416

table->MvddLevel[count].Smio |=

sys/dev/drm/amd/amdgpu/ci_dpm.c

2419

table->MvddLevel[count].Smio = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2421

table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2427

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2431

ret = ci_populate_smc_vddc_table(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2435

ret = ci_populate_smc_vddci_table(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2439

ret = ci_populate_smc_mvdd_table(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2763

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2770

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2772

table->LinkLevel[i].PcieLaneCount =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2774

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2775

table->LinkLevel[i].DownT = cpu_to_be32(5);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2776

table->LinkLevel[i].UpT = cpu_to_be32(30);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2785

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2791

table->UvdLevelCount =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2794

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2795

table->UvdLevel[count].VclkFrequency =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2797

table->UvdLevel[count].DclkFrequency =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2799

table->UvdLevel[count].MinVddc =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2801

table->UvdLevel[count].MinVddcPhases = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2805

table->UvdLevel[count].VclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2809

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2813

table->UvdLevel[count].DclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2817

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2819

table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2820

table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2821

table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2828

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2834

table->VceLevelCount =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2837

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2838

table->VceLevel[count].Frequency =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2840

table->VceLevel[count].MinVoltage =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2842

table->VceLevel[count].MinPhases = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2846

table->VceLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2850

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2852

table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2853

table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2861

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2867

table->AcpLevelCount = (u8)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2870

for (count = 0; count < table->AcpLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2871

table->AcpLevel[count].Frequency =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2873

table->AcpLevel[count].MinVoltage =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2875

table->AcpLevel[count].MinPhases = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2879

table->AcpLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2883

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2885

table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2886

table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2893

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2899

table->SamuLevelCount =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2902

for (count = 0; count < table->SamuLevelCount; count++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2903

table->SamuLevel[count].Frequency =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2905

table->SamuLevel[count].MinVoltage =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2907

table->SamuLevel[count].MinPhases = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2911

table->SamuLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2915

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2917

table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2918

table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3132

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3143

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3146

table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3148

table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3150

table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3152

table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3156

table->ACPILevel.SclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3160

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3161

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3162

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3170

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3171

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3172

table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3173

table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3174

table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3175

table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3176

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3177

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3179

table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3180

table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3181

table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3182

table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3183

table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3184

table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3185

table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3186

table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3187

table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3188

table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3189

table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3191

table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3192

table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3196

table->MemoryACPILevel.MinVddci =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3199

table->MemoryACPILevel.MinVddci =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3204

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3206

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3216

table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3217

table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3218

table->MemoryACPILevel.MpllAdFuncCntl =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3220

table->MemoryACPILevel.MpllDqFuncCntl =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3222

table->MemoryACPILevel.MpllFuncCntl =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3224

table->MemoryACPILevel.MpllFuncCntl_1 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3226

table->MemoryACPILevel.MpllFuncCntl_2 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3228

table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3229

table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3231

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3232

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3233

table->MemoryACPILevel.UpH = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3234

table->MemoryACPILevel.DownH = 100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3235

table->MemoryACPILevel.VoltageDownH = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3236

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3239

table->MemoryACPILevel.StutterEnable = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3240

table->MemoryACPILevel.StrobeEnable = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3241

table->MemoryACPILevel.EdcReadEnable = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3242

table->MemoryACPILevel.EdcWriteEnable = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3243

table->MemoryACPILevel.RttEnable = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3684

static int ci_find_boot_level(struct ci_single_dpm_table *table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3690

for(i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3691

if (value == table->dpm_levels[i].value) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3705

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3713

ci_populate_smc_voltage_tables(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3718

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3721

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3724

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3741

ci_populate_smc_link_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3743

ret = ci_populate_smc_acpi_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3747

ret = ci_populate_smc_vce_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3751

ret = ci_populate_smc_acp_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3755

ret = ci_populate_smc_samu_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3763

ret = ci_populate_smc_uvd_level(adev, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3767

table->UvdBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3768

table->VceBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3769

table->AcpBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3770

table->SamuBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3771

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3772

table->MemoryBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3782

table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3783

table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3784

table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3792

table->UVDInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3793

table->VCEInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3794

table->ACPInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3795

table->SAMUInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3796

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3797

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3798

table->GraphicsInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3799

table->VoltageInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3800

table->ThermalInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3801

table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3803

table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3805

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3806

table->MemoryInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3807

table->VoltageResponseTime = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3808

table->VddcVddciDelta = 4000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3809

table->PhaseResponseTime = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3810

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3811

table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3812

table->PCIeGenInterval = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3814

table->SVI2Enable = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3816

table->SVI2Enable = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3818

table->ThermGpio = 17;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3819

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3821

table->SystemFlags = cpu_to_be32(table->SystemFlags);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3822

table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3823

table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3824

table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3825

table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3826

table->SclkStepSize = cpu_to_be32(table->SclkStepSize);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3827

table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3828

table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3829

table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3830

table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3831

table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3832

table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3833

table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3834

table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3839

(u8 *)&table->SystemFlags,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4254

struct amdgpu_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4257

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4258

if (table->entries[i].evclk >= min_evclk)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4262

return table->count - 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4491

struct ci_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4496

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4499

switch(table->mc_reg_address[i].s1) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4502

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4503

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4504

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4505

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4506

((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4513

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4514

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4515

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4516

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4517

(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4519

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4526

table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4527

table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4528

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4529

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4530

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4537

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4538

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4539

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4540

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4541

(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4551

table->last = j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4629

static void ci_set_valid_flag(struct ci_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4633

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4634

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4635

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/amd/amdgpu/ci_dpm.c

4636

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4637

table->valid_flag |= 1 << i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4644

static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4649

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4650

table->mc_reg_address[i].s0 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4651

ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/amd/amdgpu/ci_dpm.c

4652

address : table->mc_reg_address[i].s1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4656

static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4661

if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4663

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4666

for (i = 0; i < table->last; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4667

ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4669

ci_table->last = table->last;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4671

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4673

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4674

for (j = 0; j < table->last; j++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4676

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/amd/amdgpu/ci_dpm.c

4678

ci_table->num_entries = table->num_entries;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4684

struct ci_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4696

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4697

if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4699

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4701

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4702

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

4703

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4704

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4705

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4710

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4711

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

4712

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4713

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4714

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4719

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4720

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

4721

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4722

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4723

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4728

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4729

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

4730

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4731

table->mc_reg_table_entry[k].mc_data[i] = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4735

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4736

if (table->mc_reg_table_entry[k].mclk_max == 125000)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4737

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4738

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4740

else if (table->mc_reg_table_entry[k].mclk_max == 137500)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4741

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4742

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4747

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4748

if (table->mc_reg_table_entry[k].mclk_max == 125000)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4749

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4750

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4752

else if (table->mc_reg_table_entry[k].mclk_max == 137500)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4753

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4754

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |

sys/dev/drm/amd/amdgpu/ci_dpm.c

4776

struct atom_mc_reg_table *table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4781

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4782

if (!table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4806

ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4810

ret = ci_copy_vbios_mc_reg_table(table, ci_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4827

kfree(table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5135

struct amdgpu_clock_voltage_dependency_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5139

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5140

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5141

ci_patch_with_vddc_leakage(adev, &table->entries[i].v);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5146

struct amdgpu_clock_voltage_dependency_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5150

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5151

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5152

ci_patch_with_vddci_leakage(adev, &table->entries[i].v);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5157

struct amdgpu_vce_clock_voltage_dependency_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5161

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5162

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5163

ci_patch_with_vddc_leakage(adev, &table->entries[i].v);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5168

struct amdgpu_uvd_clock_voltage_dependency_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5172

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5173

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5174

ci_patch_with_vddc_leakage(adev, &table->entries[i].v);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5179

struct amdgpu_phase_shedding_limits_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5183

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5184

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5185

ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5190

struct amdgpu_clock_and_voltage_limits *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5192

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5193

ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5194

ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5199

struct amdgpu_cac_leakage_table *table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5203

if (table) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5204

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5205

ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1039

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1045

if (table == NULL || table->count == 0)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1049

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1051

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1054

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1055

pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1058

(u8)kv_get_clk_bypass(adev, table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1061

table->entries[i].clk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1105

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1111

if (table == NULL || table->count == 0)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1115

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1116

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1117

pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1120

table->entries[i].clk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1164

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1167

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1170

if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1172

else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1174

else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1176

else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1178

else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1187

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1191

if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1193

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1195

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1197

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1199

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)

sys/dev/drm/amd/amdgpu/kv_dpm.c

139

ATOM_AVAILABLE_SCLK_LIST *table)

sys/dev/drm/amd/amdgpu/kv_dpm.c

146

if (table[i].ulSupportedSCLK > prev_sclk) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

148

table[i].ulSupportedSCLK;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1497

struct amdgpu_uvd_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

150

table[i].usVoltageIndex;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1503

if (table->count)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1504

pi->uvd_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

151

prev_sclk = table[i].ulSupportedSCLK;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1533

struct amdgpu_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1536

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1537

if (table->entries[i].evclk >= evclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1549

struct amdgpu_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1555

pi->vce_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1583

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1589

pi->samu_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

161

ATOM_AVAILABLE_SCLK_LIST *table)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1614

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1617

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1618

if (table->entries[i].clk >= 0) /* XXX */

sys/dev/drm/amd/amdgpu/kv_dpm.c

1622

if (i >= table->count)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1623

i = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1647

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1653

pi->acp_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

166

if (table[i].ulSupportedSCLK != 0) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

167

vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =

sys/dev/drm/amd/amdgpu/kv_dpm.c

168

table[i].usVoltageID;

sys/dev/drm/amd/amdgpu/kv_dpm.c

169

vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =

sys/dev/drm/amd/amdgpu/kv_dpm.c

170

table[i].usVoltageIndex;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1778

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1781

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1783

if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

1791

if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1797

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/drm/amd/amdgpu/kv_dpm.c

1798

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/drm/amd/amdgpu/kv_dpm.c

1804

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1808

if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

1816

if (table->entries[i].sclk_frequency <=

sys/dev/drm/amd/amdgpu/kv_dpm.c

1824

table->entries[pi->highest_valid].sclk_frequency) >

sys/dev/drm/amd/amdgpu/kv_dpm.c

1825

(table->entries[pi->lowest_valid].sclk_frequency -

sys/dev/drm/amd/amdgpu/kv_dpm.c

2036

struct amdgpu_clock_and_voltage_limits *table)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2042

table->sclk =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2044

table->vddc =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2049

table->mclk = pi->sys_info.nbp_memory_clock[0];

sys/dev/drm/amd/amdgpu/kv_dpm.c

2174

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2178

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2179

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2181

(kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=

sys/dev/drm/amd/amdgpu/kv_dpm.c

2188

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2191

for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2193

(kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=

sys/dev/drm/amd/amdgpu/kv_dpm.c

2215

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2235

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2236

if (stable_p_state_sclk >= table->entries[i].clk) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2237

stable_p_state_sclk = table->entries[i].clk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2243

stable_p_state_sclk = table->entries[0].clk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2260

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2266

ps->levels[i].sclk = table->entries[limit].clk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2270

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2278

ps->levels[i].sclk = table->entries[limit].sclk_frequency;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2419

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2422

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2426

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2429

kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))

sys/dev/drm/amd/amdgpu/kv_dpm.c

2432

kv_set_divider_value(adev, i, table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2435

table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2442

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2446

for (i = 0; i < table->num_max_dpm_entries; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2449

kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))

sys/dev/drm/amd/amdgpu/kv_dpm.c

2452

kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2453

kv_set_vid(adev, i, table->entries[i].vid_2bit);

sys/dev/drm/amd/amdgpu/kv_dpm.c

803

struct amdgpu_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

806

if (table && table->count) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

808

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

815

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

818

if (table->num_max_dpm_entries == 0)

sys/dev/drm/amd/amdgpu/kv_dpm.c

822

if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

905

struct amdgpu_uvd_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

911

if (table == NULL || table->count == 0)

sys/dev/drm/amd/amdgpu/kv_dpm.c

915

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

917

(pi->high_voltage_t < table->entries[i].v))

sys/dev/drm/amd/amdgpu/kv_dpm.c

920

pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

921

pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

922

pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

925

(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

927

(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

930

table->entries[i].vclk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

936

table->entries[i].dclk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

978

struct amdgpu_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/kv_dpm.c

982

if (table == NULL || table->count == 0)

sys/dev/drm/amd/amdgpu/kv_dpm.c

986

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

988

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/amd/amdgpu/kv_dpm.c

991

pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

992

pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

995

(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

998

table->entries[i].evclk, false, &dividers);

sys/dev/drm/amd/amdgpu/si_dpm.c

1837

const struct atom_voltage_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

2634

struct amdgpu_cac_leakage_table *table =

sys/dev/drm/amd/amdgpu/si_dpm.c

2639

if (table == NULL)

sys/dev/drm/amd/amdgpu/si_dpm.c

2645

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

2646

if (table->entries[i].vddc > *max)

sys/dev/drm/amd/amdgpu/si_dpm.c

2647

*max = table->entries[i].vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

2648

if (table->entries[i].vddc < *min)

sys/dev/drm/amd/amdgpu/si_dpm.c

2649

*min = table->entries[i].vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

3038

struct amdgpu_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/amdgpu/si_dpm.c

3042

(table && (table->count == 0))) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3047

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3048

if ((evclk <= table->entries[i].evclk) &&

sys/dev/drm/amd/amdgpu/si_dpm.c

3049

(ecclk <= table->entries[i].ecclk)) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3050

*voltage = table->entries[i].v;

sys/dev/drm/amd/amdgpu/si_dpm.c

3058

*voltage = table->entries[table->count - 1].v;

sys/dev/drm/amd/amdgpu/si_dpm.c

3206

static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)

sys/dev/drm/amd/amdgpu/si_dpm.c

3210

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/amdgpu/si_dpm.c

3211

if (voltage <= table->entries[i].value)

sys/dev/drm/amd/amdgpu/si_dpm.c

3212

return table->entries[i].value;

sys/dev/drm/amd/amdgpu/si_dpm.c

3214

return table->entries[table->count - 1].value;

sys/dev/drm/amd/amdgpu/si_dpm.c

3248

static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

3253

if ((table == NULL) || (table->count == 0)) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3258

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3259

if (clock < table->entries[i].clk)

sys/dev/drm/amd/amdgpu/si_dpm.c

3260

clock = table->entries[i].clk;

sys/dev/drm/amd/amdgpu/si_dpm.c

3265

static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

3270

if ((table == NULL) || (table->count == 0))

sys/dev/drm/amd/amdgpu/si_dpm.c

3273

for (i= 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3274

if (clock <= table->entries[i].clk) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3275

if (*voltage < table->entries[i].v)

sys/dev/drm/amd/amdgpu/si_dpm.c

3276

*voltage = (u16)((table->entries[i].v < max_voltage) ?

sys/dev/drm/amd/amdgpu/si_dpm.c

3277

table->entries[i].v : max_voltage);

sys/dev/drm/amd/amdgpu/si_dpm.c

4355

const struct atom_voltage_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

4360

if ((table == NULL) || (limits == NULL))

sys/dev/drm/amd/amdgpu/si_dpm.c

4363

data = table->mask_low;

sys/dev/drm/amd/amdgpu/si_dpm.c

4372

if (table->count != num_levels)

sys/dev/drm/amd/amdgpu/si_dpm.c

4501

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

4506

table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);

sys/dev/drm/amd/amdgpu/si_dpm.c

4510

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

4526

si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

4527

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =

sys/dev/drm/amd/amdgpu/si_dpm.c

4532

table->maxVDDCIndexInPPTable = i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4539

si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

4541

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =

sys/dev/drm/amd/amdgpu/si_dpm.c

4547

si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

4549

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =

sys/dev/drm/amd/amdgpu/si_dpm.c

4556

si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

4558

table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =

sys/dev/drm/amd/amdgpu/si_dpm.c

4573

const struct atom_voltage_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

4578

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4579

if (value <= table->entries[i].value) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4581

voltage->value = cpu_to_be16(table->entries[i].value);

sys/dev/drm/amd/amdgpu/si_dpm.c

4586

if (i >= table->count)

sys/dev/drm/amd/amdgpu/si_dpm.c

4831

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

4840

table->initialState.levels[0].mclk.vDLL_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4842

table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4844

table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4846

table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4848

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4850

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4852

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4854

table->initialState.levels[0].mclk.vMPLL_SS =

sys/dev/drm/amd/amdgpu/si_dpm.c

4856

table->initialState.levels[0].mclk.vMPLL_SS2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4859

table->initialState.levels[0].mclk.mclk_value =

sys/dev/drm/amd/amdgpu/si_dpm.c

4862

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

4864

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4866

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4868

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4870

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/amd/amdgpu/si_dpm.c

4872

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

4875

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/amd/amdgpu/si_dpm.c

4878

table->initialState.levels[0].arbRefreshState =

sys/dev/drm/amd/amdgpu/si_dpm.c

4881

table->initialState.levels[0].ACIndex = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4885

&table->initialState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4891

&table->initialState.levels[0].vddc,

sys/dev/drm/amd/amdgpu/si_dpm.c

4895

table->initialState.levels[0].vddc.index,

sys/dev/drm/amd/amdgpu/si_dpm.c

4896

&table->initialState.levels[0].std_vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4903

&table->initialState.levels[0].vddci);

sys/dev/drm/amd/amdgpu/si_dpm.c

4911

&table->initialState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4913

si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);

sys/dev/drm/amd/amdgpu/si_dpm.c

4916

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4917

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4918

table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/drm/amd/amdgpu/si_dpm.c

4921

table->initialState.levels[0].strobeMode =

sys/dev/drm/amd/amdgpu/si_dpm.c

4926

table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;

sys/dev/drm/amd/amdgpu/si_dpm.c

4928

table->initialState.levels[0].mcFlags = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4931

table->initialState.levelCount = 1;

sys/dev/drm/amd/amdgpu/si_dpm.c

4933

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/amdgpu/si_dpm.c

4935

table->initialState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4936

table->initialState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4937

table->initialState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4938

table->initialState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4939

table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4942

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4945

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4951

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

4970

table->ACPIState = table->initialState;

sys/dev/drm/amd/amdgpu/si_dpm.c

4972

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/amdgpu/si_dpm.c

4976

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4981

&table->ACPIState.levels[0].vddc, &std_vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4984

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/amd/amdgpu/si_dpm.c

4985

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4987

table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;

sys/dev/drm/amd/amdgpu/si_dpm.c

4995

&table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4999

pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

5004

&table->ACPIState.levels[0].vddc, &std_vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

5008

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/amd/amdgpu/si_dpm.c

5009

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

5011

table->ACPIState.levels[0].gen2PCIE =

sys/dev/drm/amd/amdgpu/si_dpm.c

5023

&table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

5030

&table->ACPIState.levels[0].vddci);

sys/dev/drm/amd/amdgpu/si_dpm.c

5041

table->ACPIState.levels[0].mclk.vDLL_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5043

table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5045

table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5047

table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5049

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5051

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5053

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5055

table->ACPIState.levels[0].mclk.vMPLL_SS =

sys/dev/drm/amd/amdgpu/si_dpm.c

5057

table->ACPIState.levels[0].mclk.vMPLL_SS2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5060

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/amd/amdgpu/si_dpm.c

5062

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5064

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5066

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =

sys/dev/drm/amd/amdgpu/si_dpm.c

5069

table->ACPIState.levels[0].mclk.mclk_value = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5070

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5072

si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/amd/amdgpu/si_dpm.c

5075

table->ACPIState.levels[0].ACIndex = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5077

table->ACPIState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5078

table->ACPIState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5079

table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5080

table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5081

table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

5084

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

5087

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

5161

SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;

sys/dev/drm/amd/amdgpu/si_dpm.c

5166

si_populate_smc_voltage_tables(adev, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

5171

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/amd/amdgpu/si_dpm.c

5174

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/amd/amdgpu/si_dpm.c

5177

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/amd/amdgpu/si_dpm.c

5182

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/amdgpu/si_dpm.c

5186

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

sys/dev/drm/amd/amdgpu/si_dpm.c

5190

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/amdgpu/si_dpm.c

5193

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/amdgpu/si_dpm.c

5196

table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;

sys/dev/drm/amd/amdgpu/si_dpm.c

5199

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;

sys/dev/drm/amd/amdgpu/si_dpm.c

5205

ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

5209

ret = si_populate_smc_acpi_state(adev, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

5213

table->driverState = table->initialState;

sys/dev/drm/amd/amdgpu/si_dpm.c

5221

ret = si_populate_ulv_state(adev, &table->ULVState);

sys/dev/drm/amd/amdgpu/si_dpm.c

5235

table->ULVState = table->initialState;

sys/dev/drm/amd/amdgpu/si_dpm.c

5239

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/drm/amd/amdgpu/si_dpm.c

5816

struct si_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

5821

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5824

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5827

table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;

sys/dev/drm/amd/amdgpu/si_dpm.c

5828

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;

sys/dev/drm/amd/amdgpu/si_dpm.c

5829

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/amd/amdgpu/si_dpm.c

5830

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/si_dpm.c

5832

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/amd/amdgpu/si_dpm.c

5838

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;

sys/dev/drm/amd/amdgpu/si_dpm.c

5839

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;

sys/dev/drm/amd/amdgpu/si_dpm.c

5840

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5841

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/si_dpm.c

5843

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/amdgpu/si_dpm.c

5845

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/amd/amdgpu/si_dpm.c

5852

table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;

sys/dev/drm/amd/amdgpu/si_dpm.c

5853

table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;

sys/dev/drm/amd/amdgpu/si_dpm.c

5854

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/amd/amdgpu/si_dpm.c

5855

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/si_dpm.c

5856

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/amd/amdgpu/si_dpm.c

5862

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;

sys/dev/drm/amd/amdgpu/si_dpm.c

5863

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;

sys/dev/drm/amd/amdgpu/si_dpm.c

5864

for(k = 0; k < table->num_entries; k++)

sys/dev/drm/amd/amdgpu/si_dpm.c

5865

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/amdgpu/si_dpm.c

5867

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/amdgpu/si_dpm.c

5875

table->last = j;

sys/dev/drm/amd/amdgpu/si_dpm.c

5934

static void si_set_valid_flag(struct si_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

5938

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5939

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5940

if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5941

table->valid_flag |= 1 << i;

sys/dev/drm/amd/amdgpu/si_dpm.c

5948

static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

5953

for (i = 0; i < table->last; i++)

sys/dev/drm/amd/amdgpu/si_dpm.c

5954

table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/amd/amdgpu/si_dpm.c

5955

address : table->mc_reg_address[i].s1;

sys/dev/drm/amd/amdgpu/si_dpm.c

5959

static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,

sys/dev/drm/amd/amdgpu/si_dpm.c

5964

if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/si_dpm.c

5966

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/amd/amdgpu/si_dpm.c

5969

for (i = 0; i < table->last; i++)

sys/dev/drm/amd/amdgpu/si_dpm.c

5970

si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/amd/amdgpu/si_dpm.c

5971

si_table->last = table->last;

sys/dev/drm/amd/amdgpu/si_dpm.c

5973

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5975

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/amd/amdgpu/si_dpm.c

5976

for (j = 0; j < table->last; j++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5978

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/amd/amdgpu/si_dpm.c

5981

si_table->num_entries = table->num_entries;

sys/dev/drm/amd/amdgpu/si_dpm.c

5989

struct atom_mc_reg_table *table;

sys/dev/drm/amd/amdgpu/si_dpm.c

5994

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/amd/amdgpu/si_dpm.c

5995

if (!table)

sys/dev/drm/amd/amdgpu/si_dpm.c

6013

ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);

sys/dev/drm/amd/amdgpu/si_dpm.c

6017

ret = si_copy_vbios_mc_reg_table(table, si_table);

sys/dev/drm/amd/amdgpu/si_dpm.c

6030

kfree(table);

sys/dev/drm/amd/amdgpu/si_dpm.c

6320

struct amdgpu_clock_voltage_dependency_table *table)

sys/dev/drm/amd/amdgpu/si_dpm.c

6326

if (table) {

sys/dev/drm/amd/amdgpu/si_dpm.c

6327

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

6329

table->entries[i].v,

sys/dev/drm/amd/amdgpu/si_dpm.c

6332

table->entries[i].v = leakage_voltage;

sys/dev/drm/amd/amdgpu/si_dpm.c

6342

for (j = (table->count - 2); j >= 0; j--) {

sys/dev/drm/amd/amdgpu/si_dpm.c

6343

table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?

sys/dev/drm/amd/amdgpu/si_dpm.c

6344

table->entries[j].v : table->entries[j + 1].v;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

718

struct amdgpu_mm_table *table)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

721

uint64_t addr = table->gpu_addr;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

722

struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

153

struct amdgpu_mm_table *table)

sys/dev/drm/amd/amdgpu/vce_v4_0.c

156

uint64_t addr = table->gpu_addr;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

157

struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;

sys/dev/drm/amd/display/dc/bios/bios_parser.c

135

ATOM_OBJECT_TABLE *table;

sys/dev/drm/amd/display/dc/bios/bios_parser.c

139

table = GET_IMAGE(ATOM_OBJECT_TABLE, object_table_offset);

sys/dev/drm/amd/display/dc/bios/bios_parser.c

141

if (!table)

sys/dev/drm/amd/display/dc/bios/bios_parser.c

144

return table->ucNumberOfObjects;

sys/dev/drm/amd/display/dc/bios/bios_parser.c

55

#define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)

sys/dev/drm/amd/display/dc/bios/bios_parser2.c

110

#define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1226

const struct link_mst_stream_allocation_table *table)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1245

if (table->stream_count >= 1) {

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1247

&table->stream_allocations[0],

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1259

if (table->stream_count >= 2) {

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1261

&table->stream_allocations[1],

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1273

if (table->stream_count >= 3) {

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1275

&table->stream_allocations[2],

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1287

if (table->stream_count >= 4) {

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1289

&table->stream_allocations[3],

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

251

const struct link_mst_stream_allocation_table *table);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1144

const struct link_mst_stream_allocation_table *table)

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1164

if (table->stream_count >= 1) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1166

&table->stream_allocations[0],

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1178

if (table->stream_count >= 2) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1180

&table->stream_allocations[1],

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1192

if (table->stream_count >= 3) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1194

&table->stream_allocations[2],

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1206

if (table->stream_count >= 4) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1208

&table->stream_allocations[3],

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

316

const struct link_mst_stream_allocation_table *table);

sys/dev/drm/amd/display/dc/inc/hw/link_encoder.h

144

const struct link_mst_stream_allocation_table *table);

sys/dev/drm/amd/display/dc/virtual/virtual_link_encoder.c

72

const struct link_mst_stream_allocation_table *table) {}

sys/dev/drm/amd/include/kgd_pp_interface.h

235

int (*get_pp_table)(void *handle, char **table);

sys/dev/drm/amd/include/linux/chash.h

110

#define DECLARE_CHASH_TABLE(table, bts, key_sz, val_sz) \

sys/dev/drm/amd/include/linux/chash.h

111

STRUCT_CHASH_TABLE(bts, key_sz, val_sz) table

sys/dev/drm/amd/include/linux/chash.h

153

.table = { \

sys/dev/drm/amd/include/linux/chash.h

167

__CHASH_TABLE_INIT(((tbl).table), (tbl).data, bts, key_sz, val_sz)

sys/dev/drm/amd/include/linux/chash.h

169

int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,

sys/dev/drm/amd/include/linux/chash.h

171

void chash_table_free(struct chash_table *table);

sys/dev/drm/amd/include/linux/chash.h

182

#define chash_table_dump_stats(tbl) __chash_table_dump_stats(&(*tbl).table)

sys/dev/drm/amd/include/linux/chash.h

184

void __chash_table_dump_stats(struct __chash_table *table);

sys/dev/drm/amd/include/linux/chash.h

194

#define chash_table_reset_stats(tbl) __chash_table_reset_stats(&(*tbl).table)

sys/dev/drm/amd/include/linux/chash.h

196

static inline void __chash_table_reset_stats(struct __chash_table *table)

sys/dev/drm/amd/include/linux/chash.h

198

(void)table __CHASH_STATS_INIT((*table));

sys/dev/drm/amd/include/linux/chash.h

217

__chash_table_copy_in(&(*tbl).table, key, value)

sys/dev/drm/amd/include/linux/chash.h

219

int __chash_table_copy_in(struct __chash_table *table, u64 key,

sys/dev/drm/amd/include/linux/chash.h

233

__chash_table_copy_out(&(*tbl).table, key, value, false)

sys/dev/drm/amd/include/linux/chash.h

235

int __chash_table_copy_out(struct __chash_table *table, u64 key,

sys/dev/drm/amd/include/linux/chash.h

250

__chash_table_copy_out(&(*tbl).table, key, value, true)

sys/dev/drm/amd/include/linux/chash.h

256

struct __chash_table *table;

sys/dev/drm/amd/include/linux/chash.h

266

#define CHASH_ITER_INIT(table, s) { \

sys/dev/drm/amd/include/linux/chash.h

267

table, \

sys/dev/drm/amd/include/linux/chash.h

288

(iter).slot = ((iter).slot + 1) & (iter).table->size_mask; \

sys/dev/drm/amd/include/linux/chash.h

293

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

294

return !!(iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &

sys/dev/drm/amd/include/linux/chash.h

299

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

300

return !(iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &

sys/dev/drm/amd/include/linux/chash.h

306

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

307

iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;

sys/dev/drm/amd/include/linux/chash.h

308

iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;

sys/dev/drm/amd/include/linux/chash.h

312

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

313

iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;

sys/dev/drm/amd/include/linux/chash.h

317

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

318

iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;

sys/dev/drm/amd/include/linux/chash.h

323

BUG_ON(iter.table->key_size != 4);

sys/dev/drm/amd/include/linux/chash.h

324

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

325

return iter.table->keys32[iter.slot];

sys/dev/drm/amd/include/linux/chash.h

329

BUG_ON(iter.table->key_size != 8);

sys/dev/drm/amd/include/linux/chash.h

330

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

331

return iter.table->keys64[iter.slot];

sys/dev/drm/amd/include/linux/chash.h

335

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

336

return (iter.table->key_size == 4) ?

sys/dev/drm/amd/include/linux/chash.h

337

iter.table->keys32[iter.slot] : iter.table->keys64[iter.slot];

sys/dev/drm/amd/include/linux/chash.h

342

BUG_ON(iter.table->key_size != 4);

sys/dev/drm/amd/include/linux/chash.h

343

return hash_32(chash_iter_key32(iter), iter.table->bits);

sys/dev/drm/amd/include/linux/chash.h

348

BUG_ON(iter.table->key_size != 8);

sys/dev/drm/amd/include/linux/chash.h

349

return hash_64(chash_iter_key64(iter), iter.table->bits);

sys/dev/drm/amd/include/linux/chash.h

354

return (iter.table->key_size == 4) ?

sys/dev/drm/amd/include/linux/chash.h

355

hash_32(chash_iter_key32(iter), iter.table->bits) :

sys/dev/drm/amd/include/linux/chash.h

356

hash_64(chash_iter_key64(iter), iter.table->bits);

sys/dev/drm/amd/include/linux/chash.h

361

BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));

sys/dev/drm/amd/include/linux/chash.h

362

return iter.table->values +

sys/dev/drm/amd/include/linux/chash.h

363

((unsigned long)iter.slot * iter.table->value_size);

sys/dev/drm/amd/include/linux/chash.h

71

struct __chash_table table; \

sys/dev/drm/amd/include/linux/chash.h

84

struct __chash_table table;

sys/dev/drm/amd/lib/chash.c

109

table->key_size, table->value_size);

sys/dev/drm/amd/lib/chash.c

111

1 << table->bits, filled, empty, tombstones);

sys/dev/drm/amd/lib/chash.c

112

if (table->hits > 0) {

sys/dev/drm/amd/lib/chash.c

113

DIV_FRAC(table->hits_steps, table->hits, quot1, frac1, 1000);

sys/dev/drm/amd/lib/chash.c

114

DIV_FRAC(table->hits * 1000, table->hits_time_ns,

sys/dev/drm/amd/lib/chash.c

121

table->hits, quot1, frac1, quot2, frac2);

sys/dev/drm/amd/lib/chash.c

122

if (table->miss > 0) {

sys/dev/drm/amd/lib/chash.c

123

DIV_FRAC(table->miss_steps, table->miss, quot1, frac1, 1000);

sys/dev/drm/amd/lib/chash.c

124

DIV_FRAC(table->miss * 1000, table->miss_time_ns,

sys/dev/drm/amd/lib/chash.c

131

table->miss, quot1, frac1, quot2, frac2);

sys/dev/drm/amd/lib/chash.c

132

if (table->hits + table->miss > 0) {

sys/dev/drm/amd/lib/chash.c

133

DIV_FRAC(table->hits_steps + table->miss_steps,

sys/dev/drm/amd/lib/chash.c

134

table->hits + table->miss, quot1, frac1, 1000);

sys/dev/drm/amd/lib/chash.c

135

DIV_FRAC((table->hits + table->miss) * 1000,

sys/dev/drm/amd/lib/chash.c

136

(table->hits_time_ns + table->miss_time_ns),

sys/dev/drm/amd/lib/chash.c

143

table->hits + table->miss, quot1, frac1, quot2, frac2);

sys/dev/drm/amd/lib/chash.c

144

if (table->relocs > 0) {

sys/dev/drm/amd/lib/chash.c

145

DIV_FRAC(table->hits + table->miss, table->relocs,

sys/dev/drm/amd/lib/chash.c

147

DIV_FRAC(table->reloc_dist, table->relocs, quot2, frac2, 1000);

sys/dev/drm/amd/lib/chash.c

149

table->relocs, quot1, frac1, quot2, frac2);

sys/dev/drm/amd/lib/chash.c

159

#define CHASH_INC(table, a) ((a) = ((a) + 1) & (table)->size_mask)

sys/dev/drm/amd/lib/chash.c

160

#define CHASH_ADD(table, a, b) (((a) + (b)) & (table)->size_mask)

sys/dev/drm/amd/lib/chash.c

161

#define CHASH_SUB(table, a, b) (((a) - (b)) & (table)->size_mask)

sys/dev/drm/amd/lib/chash.c

162

#define CHASH_IN_RANGE(table, slot, first, last) \

sys/dev/drm/amd/lib/chash.c

163

(CHASH_SUB(table, slot, first) <= CHASH_SUB(table, last, first))

sys/dev/drm/amd/lib/chash.c

167

static void chash_table_dump(struct __chash_table *table)

sys/dev/drm/amd/lib/chash.c

169

struct chash_iter iter = CHASH_ITER_INIT(table, 0);

sys/dev/drm/amd/lib/chash.c

192

static int chash_table_check(struct __chash_table *table)

sys/dev/drm/amd/lib/chash.c

195

struct chash_iter iter = CHASH_ITER_INIT(table, 0);

sys/dev/drm/amd/lib/chash.c

196

struct chash_iter cur = CHASH_ITER_INIT(table, 0);

sys/dev/drm/amd/lib/chash.c

210

chash_table_dump(table);

sys/dev/drm/amd/lib/chash.c

225

BUG_ON(src.table == dst.table && src.slot == dst.slot);

sys/dev/drm/amd/lib/chash.c

226

BUG_ON(src.table->key_size != dst.table->key_size);

sys/dev/drm/amd/lib/chash.c

227

BUG_ON(src.table->value_size != dst.table->value_size);

sys/dev/drm/amd/lib/chash.c

229

if (dst.table->key_size == 4)

sys/dev/drm/amd/lib/chash.c

230

dst.table->keys32[dst.slot] = src.table->keys32[src.slot];

sys/dev/drm/amd/lib/chash.c

232

dst.table->keys64[dst.slot] = src.table->keys64[src.slot];

sys/dev/drm/amd/lib/chash.c

234

if (dst.table->value_size)

sys/dev/drm/amd/lib/chash.c

236

dst.table->value_size);

sys/dev/drm/amd/lib/chash.c

242

if (src.table == dst.table) {

sys/dev/drm/amd/lib/chash.c

243

dst.table->relocs++;

sys/dev/drm/amd/lib/chash.c

244

dst.table->reloc_dist +=

sys/dev/drm/amd/lib/chash.c

245

CHASH_SUB(dst.table, src.slot, dst.slot);

sys/dev/drm/amd/lib/chash.c

280

struct chash_iter first_redundant = CHASH_ITER_INIT(iter->table, -1);

sys/dev/drm/amd/lib/chash.c

298

chash_table_check(iter->table);

sys/dev/drm/amd/lib/chash.c

321

if (!CHASH_IN_RANGE(iter->table, cur_hash,

sys/dev/drm/amd/lib/chash.c

340

CHASH_ITER_INIT(iter->table, cur_hash);

sys/dev/drm/amd/lib/chash.c

359

iter->table->hits++;

sys/dev/drm/amd/lib/chash.c

360

iter->table->hits_steps += CHASH_SUB(iter->table, iter->slot, hash) + 1;

sys/dev/drm/amd/lib/chash.c

371

iter->table->hits_time_ns += local_clock() - ts1;

sys/dev/drm/amd/lib/chash.c

378

iter->table->miss++;

sys/dev/drm/amd/lib/chash.c

379

iter->table->miss_steps += (iter->slot < 0) ?

sys/dev/drm/amd/lib/chash.c

380

(1 << iter->table->bits) :

sys/dev/drm/amd/lib/chash.c

381

CHASH_SUB(iter->table, iter->slot, hash) + 1;

sys/dev/drm/amd/lib/chash.c

388

iter->table->miss_time_ns += local_clock() - ts1;

sys/dev/drm/amd/lib/chash.c

394

int __chash_table_copy_in(struct __chash_table *table, u64 key,

sys/dev/drm/amd/lib/chash.c

397

u32 hash = (table->key_size == 4) ?

sys/dev/drm/amd/lib/chash.c

398

hash_32(key, table->bits) : hash_64(key, table->bits);

sys/dev/drm/amd/lib/chash.c

399

struct chash_iter iter = CHASH_ITER_INIT(table, hash);

sys/dev/drm/amd/lib/chash.c

40

int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,

sys/dev/drm/amd/lib/chash.c

404

if (value && table->value_size)

sys/dev/drm/amd/lib/chash.c

406

table->value_size);

sys/dev/drm/amd/lib/chash.c

418

if (table->key_size == 4)

sys/dev/drm/amd/lib/chash.c

419

table->keys32[iter.slot] = key;

sys/dev/drm/amd/lib/chash.c

421

table->keys64[iter.slot] = key;

sys/dev/drm/amd/lib/chash.c

422

if (value && table->value_size)

sys/dev/drm/amd/lib/chash.c

423

memcpy(chash_iter_value(iter), value, table->value_size);

sys/dev/drm/amd/lib/chash.c

429

int __chash_table_copy_out(struct __chash_table *table, u64 key,

sys/dev/drm/amd/lib/chash.c

432

u32 hash = (table->key_size == 4) ?

sys/dev/drm/amd/lib/chash.c

433

hash_32(key, table->bits) : hash_64(key, table->bits);

sys/dev/drm/amd/lib/chash.c

434

struct chash_iter iter = CHASH_ITER_INIT(table, hash);

sys/dev/drm/amd/lib/chash.c

440

if (value && table->value_size)

sys/dev/drm/amd/lib/chash.c

441

memcpy(value, chash_iter_value(iter), table->value_size);

sys/dev/drm/amd/lib/chash.c

467

struct chash_table table;

sys/dev/drm/amd/lib/chash.c

477

ret = chash_table_alloc(&table, bits, key_size, sizeof(u64),

sys/dev/drm/amd/lib/chash.c

49

table->data = kcalloc(__CHASH_DATA_SIZE(bits, key_size, value_size),

sys/dev/drm/amd/lib/chash.c

498

ret = chash_table_copy_out(&table, find_count,

sys/dev/drm/amd/lib/chash.c

509

chash_table_dump(&table.table);

sys/dev/drm/amd/lib/chash.c

51

if (!table->data)

sys/dev/drm/amd/lib/chash.c

514

ret = chash_table_copy_in(&table, find_count,

sys/dev/drm/amd/lib/chash.c

525

ret = chash_table_remove(&table, rmv_count,

sys/dev/drm/amd/lib/chash.c

537

ret = chash_table_copy_in(&table, add_count, &value);

sys/dev/drm/amd/lib/chash.c

54

__CHASH_TABLE_INIT(table->table, table->data,

sys/dev/drm/amd/lib/chash.c

546

chash_table_dump_stats(&table);

sys/dev/drm/amd/lib/chash.c

547

chash_table_reset_stats(&table);

sys/dev/drm/amd/lib/chash.c

550

chash_table_free(&table);

sys/dev/drm/amd/lib/chash.c

65

void chash_table_free(struct chash_table *table)

sys/dev/drm/amd/lib/chash.c

67

kfree(table->data);

sys/dev/drm/amd/lib/chash.c

91

void __chash_table_dump_stats(struct __chash_table *table)

sys/dev/drm/amd/lib/chash.c

93

struct chash_iter iter = CHASH_ITER_INIT(table, 0);

sys/dev/drm/amd/powerplay/amd_powerplay.c

645

static int pp_dpm_get_pp_table(void *handle, char **table)

sys/dev/drm/amd/powerplay/amd_powerplay.c

654

*table = (char *)hwmgr->soft_pp_table;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

104

pp_atomctrl_mc_reg_table *table)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

119

table->mc_reg_address[i].s1 =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1200

ATOM_ASIC_INTERNAL_SS_INFO *table = NULL;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1204

table = (ATOM_ASIC_INTERNAL_SS_INFO *)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1209

return table;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

121

table->mc_reg_address[i].uc_pre_reg_data =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1220

ATOM_ASIC_INTERNAL_SS_INFO *table;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1226

table = asic_internal_ss_get_ss_table(hwmgr->adev);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1228

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1231

ssInfo = &table->asSpreadSpectrum[0];

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1233

while (((uint8_t *)ssInfo - (uint8_t *)table) <

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1234

le16_to_cpu(table->sHeader.usStructureSize)) {

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1250

if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) &&

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1251

(GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) ||

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1252

(GET_DATA_TABLE_MAJOR_REVISION(table) == 3)) {

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

129

table->last = i;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

136

pp_atomctrl_mc_reg_table *table)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1361

int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1375

table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1376

table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1377

table->entry[i].usFcw_pcc =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1379

table->entry[i].usFcw_trans_upper =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1381

table->entry[i].usRcw_trans_lower =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

159

result = atomctrl_set_mc_reg_address_table(reg_block, table);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

164

reg_block, table);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

51

pp_atomctrl_mc_reg_table *table)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

65

table->mc_reg_table_entry[num_ranges].mclk_max =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

69

for (i = 0, j = 1; i < table->last; i++) {

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

70

if ((table->mc_reg_address[i].uc_pre_reg_data &

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

72

table->mc_reg_table_entry[num_ranges].mc_data[i] =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

75

} else if ((table->mc_reg_address[i].uc_pre_reg_data &

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

77

table->mc_reg_table_entry[num_ranges].mc_data[i] =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

78

table->mc_reg_table_entry[num_ranges].mc_data[i-1];

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

90

table->num_entries = num_ranges;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

296

extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

320

extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

161

phm_ppt_v1_voltage_lookup_table *table;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

171

table = kzalloc(table_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

173

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

176

table->count = vddc_lookup_pp_tables->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

181

entries, table, i);

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

192

*lookup_table = table;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

322

struct phm_clock_array *table;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

331

table = kzalloc(table_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

333

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

336

table->count = (uint32_t)clk_volt_pp_table->count;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

338

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

342

table->values[i] = (uint32_t)dep_record->clk;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

344

*clk_table = table;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

590

const PPTable_Generic_SubTable_Header * table

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

609

if (table->ucRevId < 3) {

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

611

(ATOM_Tonga_PowerTune_Table *)table;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

638

(ATOM_Fiji_PowerTune_Table *)table;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1083

const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *table,

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1091

table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1097

uvd_table->count = table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1099

for (i = 0; i < table->numEntries; i++) {

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1101

&array->entries[table->entries[i].ucUVDClockInfoIndex];

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1102

uvd_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1116

const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table,

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1124

* table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1130

vce_table->count = table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1131

for (i = 0; i < table->numEntries; i++) {

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1132

const VCEClockInfo *entry = &array->entries[table->entries[i].ucVCEClockInfoIndex];

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1134

vce_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1148

const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1155

table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1161

samu_table->count = table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1163

for (i = 0; i < table->numEntries; i++) {

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1164

samu_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1165

samu_table->entries[i].samclk = ((unsigned long)table->entries[i].ucSAMClockHigh << 16)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1166

| le16_to_cpu(table->entries[i].usSAMClockLow);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1176

const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1183

table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1189

acp_table->count = (unsigned long)table->numEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1191

for (i = 0; i < table->numEntries; i++) {

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1192

acp_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1193

acp_table->entries[i].acpclk = ((unsigned long)table->entries[i].ucACPClockHigh << 16)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1194

| le16_to_cpu(table->entries[i].usACPClockLow);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1205

ATOM_PPLIB_Clock_Voltage_Dependency_Table *table;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1233

const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table =

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1238

table, array);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1305

table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1309

&hwmgr->dyn_state.vddc_dependency_on_sclk, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1313

table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1317

&hwmgr->dyn_state.vddci_dependency_on_mclk, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1321

table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1325

&hwmgr->dyn_state.vddc_dependency_on_mclk, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1348

table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1352

&hwmgr->dyn_state.mvdd_dependency_on_mclk, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1360

table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1363

&hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1371

const ATOM_PPLIB_CAC_Leakage_Table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1376

if (hwmgr == NULL || table == NULL || ptable == NULL)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1380

(sizeof(struct phm_cac_leakage_table) * table->ucNumEntries);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1387

cac_leakage_table->count = (ULONG)table->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1392

cac_leakage_table->entries[i].Vddc1 = le16_to_cpu(table->entries[i].usVddc1);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1393

cac_leakage_table->entries[i].Vddc2 = le16_to_cpu(table->entries[i].usVddc2);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1394

cac_leakage_table->entries[i].Vddc3 = le16_to_cpu(table->entries[i].usVddc3);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1396

cac_leakage_table->entries[i].Vddc = le16_to_cpu(table->entries[i].usVddc);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1397

cac_leakage_table->entries[i].Leakage = le32_to_cpu(table->entries[i].ulLeakageValue);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1516

struct phm_phase_shedding_limits_table *table;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1524

table = kzalloc(size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1526

if (table == NULL)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1529

table->count = (unsigned long)ptable->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1531

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1532

table->entries[i].Voltage = (unsigned long)le16_to_cpu(ptable->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1533

table->entries[i].Sclk = ((unsigned long)ptable->entries[i].ucSclkHigh << 16)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1535

table->entries[i].Mclk = ((unsigned long)ptable->entries[i].ucMclkHigh << 16)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1538

hwmgr->dyn_state.vddc_phase_shed_limits_table = table;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1548

const ATOM_PPLIB_POWERPLAYTABLE *table =

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

1551

get_vce_state_table(hwmgr, table);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

312

const ATOM_PowerTune_Table *table,

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

324

tdp_table->usTDP = le16_to_cpu(table->usTDP);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

325

tdp_table->usConfigurableTDP = le16_to_cpu(table->usConfigurableTDP);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

326

tdp_table->usTDC = le16_to_cpu(table->usTDC);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

327

tdp_table->usBatteryPowerLimit = le16_to_cpu(table->usBatteryPowerLimit);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

328

tdp_table->usSmallPowerLimit = le16_to_cpu(table->usSmallPowerLimit);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

329

tdp_table->usLowCACLeakage = le16_to_cpu(table->usLowCACLeakage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

330

tdp_table->usHighCACLeakage = le16_to_cpu(table->usHighCACLeakage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

377

const ATOM_PPLIB_Clock_Voltage_Dependency_Table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

385

* table->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

391

dep_table->count = (unsigned long)table->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

395

((unsigned long)table->entries[i].ucClockHigh << 16) |

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

396

le16_to_cpu(table->entries[i].usClockLow);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

398

(unsigned long)le16_to_cpu(table->entries[i].usVoltage);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

408

const struct phm_clock_voltage_dependency_table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

413

table_size = sizeof(unsigned long) + sizeof(unsigned long) * table->count;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

418

clock_table->count = (unsigned long)table->count;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

421

clock_table->values[i] = (unsigned long)table->entries[i].clk;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

430

const ATOM_PPLIB_Clock_Voltage_Limit_Table *table)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

432

limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) |

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

433

le16_to_cpu(table->entries[0].usSclkLow);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

434

limits->mclk = ((unsigned long)table->entries[0].ucMclkHigh << 16) |

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

435

le16_to_cpu(table->entries[0].usMclkLow);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

436

limits->vddc = (unsigned long)le16_to_cpu(table->entries[0].usVddc);

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

437

limits->vddci = (unsigned long)le16_to_cpu(table->entries[0].usVddci);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

1137

Watermarks_t *table = &(data->water_marks_table);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

1140

smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

1141

smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

134

struct phm_clock_and_voltage_limits *table)

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

424

DpmClocks_t *table = &(smu10_data->clock_table);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

427

result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

433

if (0 == result && table->DcefClocks[0].Freq != 0) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

103

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

109

for (i = 0; i < (int)table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

110

if (clock <= table->entries[i].clk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1146

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1150

if (NULL == table || table->count <= 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1153

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1154

data->sclk_dpm.hard_min_clk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1155

hwmgr->pstate_sclk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1160

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1161

clock = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1163

clock = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

117

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

118

if (clock >= table->entries[i].clk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1348

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1355

smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1356

smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1481

const struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1489

for (i = table->count - 1; i > 0; i--) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1490

if (limits->vddc >= table->entries[i].v) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1491

info->level = table->entries[i].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1611

struct phm_clock_voltage_dependency_table *table;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1620

table = hwmgr->dyn_state.vddc_dependency_on_sclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1622

clocks->clock[i] = table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1638

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1644

if ((NULL == table) || (table->count <= 0) || (clocks == NULL))

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1649

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1650

clocks->engine_max_clock = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1652

clocks->engine_max_clock = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1679

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1707

sclk = table->entries[sclk_index].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

255

struct phm_clock_and_voltage_limits *table)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

263

table->sclk = dep_table->entries[dep_table->count-1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

264

table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr,

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

267

table->mclk = sys_info->nbp_memory_clock[0];

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

440

void *table = NULL;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

457

ret = smum_download_powerplay_table(hwmgr, &table);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

459

PP_ASSERT_WITH_CODE((0 == ret && NULL != table),

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

462

clock_table = (struct SMU8_Fusion_ClkTable *)table;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

557

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

561

if (NULL == table || table->count <= 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

564

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

565

data->sclk_dpm.hard_min_clk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

569

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

570

clock = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

572

clock = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

583

struct phm_uvd_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

587

if (NULL == table || table->count <= 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

596

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

597

clock = table->entries[level].vclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

599

clock = table->entries[table->count - 1].vclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

610

struct phm_vce_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

614

if (NULL == table || table->count <= 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

623

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

624

clock = table->entries[level].ecclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

626

clock = table->entries[table->count - 1].ecclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

637

struct phm_acp_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

641

if (NULL == table || table->count <= 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

650

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

651

clock = table->entries[level].acpclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

653

clock = table->entries[table->count - 1].acpclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

686

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

694

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

697

if (level < table->count)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

698

data->sclk_dpm.soft_max_clk = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

700

data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

205

struct pp_atomctrl_voltage_table *table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

210

table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

213

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

216

table->mask_low = vol_table->mask_low;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

217

table->phase_delay = vol_table->phase_delay;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

223

for (j = 0; j < table->count; j++) {

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

224

if (vvalue == table->entries[j].value) {

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

231

table->entries[table->count].value = vvalue;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

232

table->entries[table->count].smio_low =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

234

table->count++;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

238

memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

239

kfree(table);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

240

table = NULL;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

342

int phm_reset_single_dpm_table(void *table,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

347

struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

358

void *table,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

362

struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

368

int32_t phm_get_dpm_level_enable_mask_value(void *table)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

372

struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

439

int phm_find_boot_level(void *table,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

444

struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

49

uint32_t *table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

52

table = kzalloc(array_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

53

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

534

struct phm_clock_voltage_dependency_table *table =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

540

if (!table || table->count <= 0

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

545

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

546

if (dal_power_level == table->entries[i].clk) {

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

547

req_vddc = table->entries[i].v;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

57

table[i] = le32_to_cpu(pptable_array[i]);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

59

*pptable_info_array = table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

660

void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

667

adev->mode_info.atom_context, table, size,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

705

struct watermarks *table = wt_table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

707

if (!table || !wm_with_clock_ranges)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

71

uint32_t *table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

714

table->WatermarkRow[1][i].MinClock =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

718

table->WatermarkRow[1][i].MaxClock =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

722

table->WatermarkRow[1][i].MinUclk =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

726

table->WatermarkRow[1][i].MaxUclk =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

730

table->WatermarkRow[1][i].WmSetting = (uint8_t)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

735

table->WatermarkRow[0][i].MinClock =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

739

table->WatermarkRow[0][i].MaxClock =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

74

table = kzalloc(array_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

743

table->WatermarkRow[0][i].MinUclk =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

747

table->WatermarkRow[0][i].MaxUclk =

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

75

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

751

table->WatermarkRow[0][i].WmSetting = (uint8_t)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

79

table[i] = le32_to_cpu(pptable_array[i]);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

81

*pptable_info_array = table;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

114

void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

80

extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

81

extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

82

extern int32_t phm_get_dpm_level_enable_mask_value(void *table);

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

87

extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1005

for (j = 0; j < table->count; j++) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1006

if (vvalue == table->entries[j].value) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1013

table->entries[table->count].value = vvalue;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1014

table->entries[table->count].smio_low =

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1016

table->count++;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1020

memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1021

kfree(table);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3408

struct vega10_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3412

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3413

if (table->dpm_levels[i].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3421

struct vega10_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3425

if (table->count <= MAX_REGULAR_DPM_NUMBER) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3426

for (i = table->count; i > 0; i--) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3427

if (table->dpm_levels[i - 1].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

4264

Watermarks_t *table = &(data->smc_state_table.water_marks_table);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

4268

smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

932

struct pp_atomfwctrl_voltage_table table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

939

VOLTAGE_OBJ_GPIO_LUT, &table);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

942

tmp = table.mask_low;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

988

struct pp_atomfwctrl_voltage_table *table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

992

table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

995

if (!table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

998

table->mask_low = vol_table->mask_low;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

999

table->phase_delay = vol_table->phase_delay;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1295

PPTable_t *table = &(data->smc_state_table.pp_table);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1297

table->SocketPowerLimit = cpu_to_le16(

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1299

table->TdcLimit = cpu_to_le16(tdp_table->usTDC);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1300

table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1301

table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1302

table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1303

table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1304

table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1305

table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1306

table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1307

table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1308

table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1309

table->LoadLineResistance =

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1311

table->FitLimit = 0; /* Not used for Vega10 */

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1313

table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1314

table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1315

table->Vr_I2C_address = tdp_table->ucVr_I2C_address;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1316

table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1318

table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1319

table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1321

table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1322

table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1324

table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1325

table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1021

phm_ppt_v1_voltage_lookup_table *table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1029

table = kzalloc(table_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1031

if (table == NULL)

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1034

table->count = vddc_lookup_pp_tables->ucNumEntries;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1037

table->entries[i].us_vdd =

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

1040

*lookup_table = table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

375

const Vega10_PPTable_Generic_SubTable_Header *table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

392

if (table->ucRevId == 5) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

393

power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

426

} else if (table->ucRevId == 6) {

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

427

power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

473

power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

759

const Vega10_PPTable_Generic_SubTable_Header *table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

766

(ATOM_Vega10_PCIE_Table *)table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

830

struct phm_clock_array *table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

838

table = kzalloc(table_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

840

if (!table)

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

843

table->count = (uint32_t)clk_volt_pp_table->count;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

845

for (i = 0; i < table->count; i++)

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

846

table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

848

*clk_table = table;

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

508

PPTable_t *table = &(data->smc_state_table.pp_table);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

513

table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

515

table->FanThrottlingRpm = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

517

table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

519

table->FanTargetTemperature = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

524

(uint32_t)table->FanTargetTemperature);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

526

table->FanPwmMin = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

528

table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

530

table->FanGainEdge = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

532

table->FanGainHotspot = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

534

table->FanGainLiquid = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

536

table->FanGainVrVddc = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

538

table->FanGainVrMvdd = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

540

table->FanGainPlx = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

542

table->FanGainHbm = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

544

table->FanZeroRpmEnable = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

546

table->FanStopTemp = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

548

table->FanStartTemp = hwmgr->thermal_controller.

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1000

table->dpm_levels[i].enabled = true;

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1784

Watermarks_t *table = &(data->smc_state_table.water_marks_table);

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1790

smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

968

struct vega12_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

972

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

973

if (table->dpm_levels[i].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

977

if (i >= table->count) {

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

979

table->dpm_levels[i].enabled = true;

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

986

struct vega12_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

989

PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

993

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

994

if (table->dpm_levels[i].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

259

PPTable_t *table = &(data->smc_state_table.pp_table);

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

263

(uint32_t)table->FanTargetTemperature);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1620

struct vega20_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1624

for (i = 0; i < table->count; i++) {

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1625

if (table->dpm_levels[i].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1628

if (i >= table->count) {

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1630

table->dpm_levels[i].enabled = true;

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1637

struct vega20_single_dpm_table *table)

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1641

PP_ASSERT_WITH_CODE(table != NULL,

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1644

PP_ASSERT_WITH_CODE(table->count > 0,

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1647

PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1651

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1652

if (table->dpm_levels[i].enabled)

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1657

table->dpm_levels[i].enabled = true;

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

2535

Watermarks_t *table = &(data->smc_state_table.water_marks_table);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

2541

smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

691

uint8_t *table;

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

695

table = kzalloc(array_size, GFP_KERNEL);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

696

if (NULL == table)

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

700

table[i] = le32_to_cpu(pptable_array[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

701

if (table[i])

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

705

*pptable_info_array = table;

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

328

PPTable_t *table = &(data->smc_state_table.pp_table);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

332

(uint32_t)table->FanTargetTemperature);

sys/dev/drm/amd/powerplay/inc/hwmgr.h

202

void **table);

sys/dev/drm/amd/powerplay/inc/hwmgr.h

218

int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */

sys/dev/drm/amd/powerplay/inc/smumgr.h

114

extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);

sys/dev/drm/amd/powerplay/inc/smumgr.h

85

extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1004

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1006

table->LinkLevel[i].PcieLaneCount =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1008

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1009

table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1010

table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1376

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1390

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1393

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1395

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1397

table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1399

table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1403

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1409

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1410

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1411

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1420

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1421

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1422

table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1423

table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1424

table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1425

table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1426

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1427

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1430

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1432

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1433

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1434

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1435

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1436

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1437

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1438

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1439

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1440

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1444

table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1445

table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1448

table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1451

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1453

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1457

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1460

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1480

table->MemoryACPILevel.DllCntl =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1482

table->MemoryACPILevel.MclkPwrmgtCntl =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1484

table->MemoryACPILevel.MpllAdFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1486

table->MemoryACPILevel.MpllDqFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1488

table->MemoryACPILevel.MpllFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1490

table->MemoryACPILevel.MpllFuncCntl_1 =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1492

table->MemoryACPILevel.MpllFuncCntl_2 =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1494

table->MemoryACPILevel.MpllSs1 =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1496

table->MemoryACPILevel.MpllSs2 =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1499

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1500

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1501

table->MemoryACPILevel.UpH = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1502

table->MemoryACPILevel.DownH = 100;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1503

table->MemoryACPILevel.VoltageDownH = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1505

table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1507

table->MemoryACPILevel.StutterEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1508

table->MemoryACPILevel.StrobeEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1509

table->MemoryACPILevel.EdcReadEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1510

table->MemoryACPILevel.EdcWriteEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1511

table->MemoryACPILevel.RttEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1517

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1525

table->UvdLevelCount = (uint8_t)(uvd_table->count);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1527

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1528

table->UvdLevel[count].VclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1530

table->UvdLevel[count].DclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1532

table->UvdLevel[count].MinVddc =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1534

table->UvdLevel[count].MinVddcPhases = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1537

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1541

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1544

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1548

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1549

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1550

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1551

CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1558

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1566

table->VceLevelCount = (uint8_t)(vce_table->count);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1567

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1569

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1570

table->VceLevel[count].Frequency = vce_table->entries[count].evclk;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1571

table->VceLevel[count].MinVoltage =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1573

table->VceLevel[count].MinPhases = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1576

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1581

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1583

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1584

CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1590

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1598

table->AcpLevelCount = (uint8_t)(acp_table->count);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1599

table->AcpBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1601

for (count = 0; count < table->AcpLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1602

table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1603

table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1604

table->AcpLevel[count].MinPhases = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1607

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1611

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1613

CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1614

CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1684

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1690

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1691

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1714

table->BootVddc = data->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1715

table->BootVddci = data->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1716

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1882

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1887

table->SVI2Enable = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1889

table->SVI2Enable = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1909

static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1915

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1919

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1926

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1929

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1934

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1945

SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1953

ci_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1957

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1962

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1965

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1968

result = ci_populate_ulv_state(hwmgr, &(table->Ulv));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1984

result = ci_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1988

result = ci_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1992

result = ci_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1996

result = ci_populate_smc_acp_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2006

result = ci_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2010

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2011

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2012

table->AcpBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2013

table->SamuBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2015

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2016

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2018

result = ci_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2028

table->UVDInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2029

table->VCEInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2030

table->ACPInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2031

table->SAMUInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2032

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2033

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2034

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2035

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2036

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2038

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2041

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2045

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2046

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2047

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2048

table->VddcVddciDelta = 4000;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2049

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2050

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2056

table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2057

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2059

result = ci_populate_vr_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2062

data->vr_config = table->VRConfig;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2064

ci_populate_smc_svi2_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2067

CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2069

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2070

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2072

table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2076

table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2081

table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2083

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2084

CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2085

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2086

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2087

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2088

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2089

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2090

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2091

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2092

table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2093

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2094

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2096

table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2097

table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2098

table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2103

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2536

static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2541

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2542

table->mc_reg_address[i].s0 =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2543

ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2544

? address : table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2549

static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2554

PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2556

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2559

for (i = 0; i < table->last; i++)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2560

ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2562

ni_table->last = table->last;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2564

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2566

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2567

for (j = 0; j < table->last; j++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2569

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2573

ni_table->num_entries = table->num_entries;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2579

struct ci_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2585

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2589

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2593

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2594

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2595

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2596

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2598

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2605

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2606

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2607

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2608

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2610

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2613

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2620

table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2621

table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2622

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2623

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2624

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2633

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2634

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2635

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2636

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2638

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2649

table->last = j;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2654

static int ci_set_valid_flag(struct ci_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2658

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2659

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2660

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2661

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2662

table->validflag |= (1 << i);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2675

pp_atomctrl_mc_reg_table *table;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2679

table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2681

if (NULL == table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2706

memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2708

result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2711

result = ci_copy_vbios_smc_reg_table(table, ni_table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2721

kfree(table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

840

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

846

table->VddcLevelCount = data->vddc_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

847

for (count = 0; count < table->VddcLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

850

&(table->VddcLevel[count]));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

855

table->VddcLevel[count].Smio = (uint8_t) count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

856

table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

857

table->SmioMaskVddcVid |= data->vddc_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

859

table->VddcLevel[count].Smio = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

863

CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

869

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

875

table->VddciLevelCount = data->vddci_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

877

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

880

&(table->VddciLevel[count]));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

883

table->VddciLevel[count].Smio = (uint8_t) count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

884

table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

885

table->SmioMaskVddciVid |= data->vddci_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

887

table->VddciLevel[count].Smio = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

891

CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

897

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

903

table->MvddLevelCount = data->mvdd_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

905

for (count = 0; count < table->MvddLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

908

&table->MvddLevel[count]);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

911

table->MvddLevel[count].Smio = (uint8_t) count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

912

table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

913

table->SmioMaskMvddVid |= data->mvdd_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

915

table->MvddLevel[count].Smio = 0;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

919

CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

926

SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

930

result = ci_populate_smc_vddc_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

934

result = ci_populate_smc_vdd_ci_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

938

result = ci_populate_smc_mvdd_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

995

static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1301

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1314

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1319

table->ACPILevel.SclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1323

table->ACPILevel.SclkFrequency,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1324

(uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1330

table->ACPILevel.SclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1332

table->ACPILevel.MinVoltage =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1338

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1343

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1344

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1345

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1354

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1355

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1356

table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1357

table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1358

table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1359

table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1360

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1361

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1363

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1364

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1365

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1366

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1367

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1368

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1369

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1370

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1371

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1372

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1373

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1377

table->MemoryACPILevel.MclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1381

table->MemoryACPILevel.MclkFrequency,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1382

(uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1387

table->MemoryACPILevel.MclkFrequency =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1389

table->MemoryACPILevel.MinVoltage =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1404

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1407

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1408

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1409

table->MemoryACPILevel.UpHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1410

table->MemoryACPILevel.DownHyst = 100;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1411

table->MemoryACPILevel.VoltageDownHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1412

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1415

table->MemoryACPILevel.StutterEnable = false;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1416

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1417

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1423

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1433

table->VceLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1434

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1436

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1437

table->VceLevel[count].Frequency = mm_table->entries[count].eclk;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1438

table->VceLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1439

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1441

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1444

table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1448

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1453

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1455

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1456

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1462

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1472

table->AcpLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1473

table->AcpBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1475

for (count = 0; count < table->AcpLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1476

table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1477

table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1479

table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1481

table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1485

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1489

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1491

CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1492

CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1559

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1569

table->UvdLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1570

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1572

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1573

table->UvdLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1574

table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1575

table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1576

table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1578

table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1580

table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1584

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1588

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1591

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1595

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1597

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1598

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1599

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1606

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1611

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1612

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1617

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1621

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1623

table->BootVddc = data->vbios_boot_state.vddc_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1625

table->BootVddci = data->vbios_boot_state.vddci_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1627

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1630

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1631

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1632

CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1824

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1830

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1835

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1844

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1847

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1850

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1855

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1858

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1861

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1930

struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1937

fiji_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1939

table->SystemFlags = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1943

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1947

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1950

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1953

result = fiji_populate_ulv_state(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1960

result = fiji_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1972

result = fiji_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1976

result = fiji_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1980

result = fiji_populate_smc_acp_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1992

result = fiji_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1996

result = fiji_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2016

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2017

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2018

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2019

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2020

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2021

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2024

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2027

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2028

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2029

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2030

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2031

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2032

table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2033

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2034

table->VRConfig = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2036

result = fiji_populate_vr_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2039

data->vr_config = table->VRConfig;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2040

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2041

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2044

table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2048

table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2055

table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2059

table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2070

table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2077

table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2079

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2086

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2090

table->ThermOutGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2091

table->ThermOutPolarity = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2092

table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2096

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2098

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2099

CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2100

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2101

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2102

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2103

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2104

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2105

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2106

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2112

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

757

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

775

table->BapmVddcVidLoSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

777

table->BapmVddcVidHiSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

785

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

789

result = fiji_populate_cac_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

823

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

825

return fiji_populate_ulv_level(hwmgr, &table->Ulv);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

829

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

839

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

841

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

843

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

844

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

845

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

846

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1423

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1438

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1441

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1443

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1445

table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1447

table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1451

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1457

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1458

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1459

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1468

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1469

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1470

table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1471

table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1472

table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1473

table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1474

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1475

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1479

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1481

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1482

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1483

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1484

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1485

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1486

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1487

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1488

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1489

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1492

table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1493

table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1496

table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1499

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1501

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1505

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1508

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1528

table->MemoryACPILevel.DllCntl =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1530

table->MemoryACPILevel.MclkPwrmgtCntl =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1532

table->MemoryACPILevel.MpllAdFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1534

table->MemoryACPILevel.MpllDqFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1536

table->MemoryACPILevel.MpllFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1538

table->MemoryACPILevel.MpllFuncCntl_1 =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1540

table->MemoryACPILevel.MpllFuncCntl_2 =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1542

table->MemoryACPILevel.MpllSs1 =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1544

table->MemoryACPILevel.MpllSs2 =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1547

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1548

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1549

table->MemoryACPILevel.UpHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1550

table->MemoryACPILevel.DownHyst = 100;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1551

table->MemoryACPILevel.VoltageDownHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1553

table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1555

table->MemoryACPILevel.StutterEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1556

table->MemoryACPILevel.StrobeEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1557

table->MemoryACPILevel.EdcReadEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1558

table->MemoryACPILevel.EdcWriteEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1559

table->MemoryACPILevel.RttEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1565

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1571

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1577

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1648

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1653

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1654

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1677

table->BootVddc = data->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1679

table->BootVddci = table->BootVddc;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1681

table->BootVddci = data->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1683

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1934

SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1941

iceland_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1946

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1951

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1954

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1966

result = iceland_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1978

result = iceland_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1982

result = iceland_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1986

result = iceland_populate_smc_acp_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1996

result = iceland_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2000

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2001

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2003

result = iceland_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2013

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2014

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2015

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2016

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2017

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2019

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2022

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2026

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2027

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2028

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2029

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2030

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2031

table->PCIeBootLinkLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2032

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2034

result = iceland_populate_smc_svi2_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2038

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2039

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2041

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2042

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2043

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2044

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2045

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2046

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2047

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2048

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2049

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2050

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2052

table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2053

table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2054

table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2059

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2466

static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2471

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2472

table->mc_reg_address[i].s0 =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2473

iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2474

? address : table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2479

static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2484

PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2486

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2489

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2490

ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2492

ni_table->last = table->last;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2494

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2496

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2497

for (j = 0; j < table->last; j++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2499

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2503

ni_table->num_entries = table->num_entries;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2509

struct iceland_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2515

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2519

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2523

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2524

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2525

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2526

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2528

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2535

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2536

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2537

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2538

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2540

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2543

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2551

table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2552

table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2553

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2554

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2555

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2564

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2565

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2566

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2567

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2569

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2580

table->last = j;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2585

static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2588

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2589

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2590

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2591

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2592

table->validflag |= (1<<i);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2605

pp_atomctrl_mc_reg_table *table;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2609

table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2611

if (NULL == table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2636

memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2638

result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2641

result = iceland_copy_vbios_smc_reg_table(table, ni_table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

2651

kfree(table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

618

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

624

table->VddcLevelCount = data->vddc_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

625

for (count = 0; count < table->VddcLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

628

&(table->VddcLevel[count]));

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

633

table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

635

table->VddcLevel[count].Smio = 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

638

CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

644

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

650

table->VddciLevelCount = data->vddci_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

652

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

655

&(table->VddciLevel[count]));

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

658

table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

660

table->VddciLevel[count].Smio |= 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

663

CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

669

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

675

table->MvddLevelCount = data->mvdd_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

677

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

680

&table->MvddLevel[count]);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

683

table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

685

table->MvddLevel[count].Smio |= 0;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

688

CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

695

SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

699

result = iceland_populate_smc_vddc_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

703

result = iceland_populate_smc_vdd_ci_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

707

result = iceland_populate_smc_mvdd_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

764

static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

773

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

775

table->LinkLevel[i].PcieLaneCount =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

777

table->LinkLevel[i].EnabledForActivity =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

779

table->LinkLevel[i].SPC =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

781

table->LinkLevel[i].DownThreshold =

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

783

table->LinkLevel[i].UpThreshold =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1199

SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1209

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1217

&table->ACPILevel.MinVoltage, &mvdd);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1223

result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1226

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1227

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1228

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1230

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1231

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1232

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1233

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1235

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1236

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1237

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1238

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1239

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1240

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1241

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1242

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1243

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1244

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1248

table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1251

table->MemoryACPILevel.MclkFrequency,

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1252

&table->MemoryACPILevel.MinVoltage, &mvdd);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1265

table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1267

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1269

table->MemoryACPILevel.StutterEnable = false;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1271

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1272

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1273

table->MemoryACPILevel.UpHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1274

table->MemoryACPILevel.DownHyst = 100;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1275

table->MemoryACPILevel.VoltageDownHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1276

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1279

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1280

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1286

SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1298

table->VceLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1299

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1301

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1302

table->VceLevel[count].Frequency = mm_table->entries[count].eclk;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1303

table->VceLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1304

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1316

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1318

table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1322

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1327

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1329

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1330

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1392

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1404

table->UvdLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1405

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1407

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1408

table->UvdLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1409

table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1410

table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1411

table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1422

table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1423

table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1427

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1431

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1434

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1438

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1440

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1441

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1442

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1449

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1454

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1455

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1460

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1464

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1466

table->BootVddc = data->vbios_boot_state.vddc_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1468

table->BootVddci = data->vbios_boot_state.vddci_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1470

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1473

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1474

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1475

CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1595

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1602

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1607

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1616

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1619

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1622

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1627

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1632

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1644

SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1663

table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1664

table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1665

table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1666

table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1667

table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1668

table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1669

table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1670

table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1671

table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1672

table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1673

table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1674

table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1675

table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1676

table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1677

table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1678

table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1679

table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1773

struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1781

polaris10_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1783

table->SystemFlags = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1786

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1790

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1793

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1796

result = polaris10_populate_ulv_state(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1803

result = polaris10_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1815

result = polaris10_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1819

result = polaris10_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1831

result = polaris10_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1835

result = polaris10_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1858

table->CurrSclkPllRange = 0xff;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1859

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1860

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1861

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1862

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1863

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1864

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1867

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1870

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1871

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1872

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1873

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1874

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1875

table->PCIeBootLinkLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1876

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1877

table->VRConfig = 0;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1879

result = polaris10_populate_vr_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1882

hw_data->vr_config = table->VRConfig;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1883

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1884

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1887

table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1889

table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1896

table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1900

table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1911

table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1918

table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1920

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1925

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1927

table->ThermOutGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1928

table->ThermOutPolarity = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1929

table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1938

table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1940

table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1944

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1946

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1947

CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1948

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1949

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1950

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1951

CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1952

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1953

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1954

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1955

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1961

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

428

SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

438

table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

439

table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

445

table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

447

table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

449

table->FanGainEdge = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

451

table->FanGainHotspot = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

460

table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

461

table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

646

SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

656

table->SmioTable2.Pattern[level].Voltage =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

659

table->SmioTable2.Pattern[level].Smio =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

661

table->Smio[level] |=

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

664

table->SmioMask2 = data->mvdd_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

666

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

673

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

684

table->SmioTable1.Pattern[level].Voltage =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

686

table->SmioTable1.Pattern[level].Smio = (uint8_t) level;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

688

table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

692

table->SmioMask1 = data->vddci_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

698

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

715

table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

716

table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

717

table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

724

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

726

polaris10_populate_smc_vddci_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

727

polaris10_populate_smc_mvdd_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

728

polaris10_populate_cac_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

760

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

762

return polaris10_populate_ulv_level(hwmgr, &table->Ulv);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

766

struct SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

776

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

778

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

780

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

781

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

782

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

783

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

798

SMU74_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

809

table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

810

table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

811

table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

813

table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

814

table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

816

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

817

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

818

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

827

table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

828

table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

829

table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

831

table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

832

table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

834

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

835

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

836

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

844

const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

880

sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

881

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

888

sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

895

sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

896

temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

116

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

137

memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

144

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

156

memcpy(priv->smu_tables.entry[table_id].table, table,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

197

&priv->smu_tables.entry[SMU10_WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

200

&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

241

&priv->smu_tables.entry[SMU10_WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

257

&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

271

&priv->smu_tables.entry[SMU10_WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

277

static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

282

ret = smu10_copy_table_from_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

284

ret = smu10_copy_table_to_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.h

37

void *table;

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

605

static int smu8_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

616

*table = (struct SMU8_Fusion_ClkTable *)smu8_smu->scratch_buffer[i].kaddr;

sys/dev/drm/amd/powerplay/smumgr/smumgr.c

118

int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)

sys/dev/drm/amd/powerplay/smumgr/smumgr.c

122

table);

sys/dev/drm/amd/powerplay/smumgr/smumgr.c

209

int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)

sys/dev/drm/amd/powerplay/smumgr/smumgr.c

212

return hwmgr->smumgr_funcs->smc_table_manager(hwmgr, table, table_id, rw);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1174

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1189

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1191

table->ACPILevel.MinVoltage =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1195

table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1199

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1206

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1207

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1208

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1217

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1218

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1219

table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1220

table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1221

table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1222

table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1223

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1224

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1228

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1230

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1231

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1232

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1233

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1234

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1235

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1236

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1237

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1238

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1241

table->MemoryACPILevel.MinVoltage =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1247

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1250

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1270

table->MemoryACPILevel.DllCntl =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1272

table->MemoryACPILevel.MclkPwrmgtCntl =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1274

table->MemoryACPILevel.MpllAdFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1276

table->MemoryACPILevel.MpllDqFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1278

table->MemoryACPILevel.MpllFuncCntl =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1280

table->MemoryACPILevel.MpllFuncCntl_1 =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1282

table->MemoryACPILevel.MpllFuncCntl_2 =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1284

table->MemoryACPILevel.MpllSs1 =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1286

table->MemoryACPILevel.MpllSs2 =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1289

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1290

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1291

table->MemoryACPILevel.UpHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1292

table->MemoryACPILevel.DownHyst = 100;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1293

table->MemoryACPILevel.VoltageDownHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1295

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1298

table->MemoryACPILevel.StutterEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1299

table->MemoryACPILevel.StrobeEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1300

table->MemoryACPILevel.EdcReadEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1301

table->MemoryACPILevel.EdcWriteEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1302

table->MemoryACPILevel.RttEnable = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1308

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1320

table->UvdLevelCount = (uint8_t) (mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1321

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1323

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1324

table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1325

table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1326

table->UvdLevel[count].MinVoltage.Vddc =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1329

table->UvdLevel[count].MinVoltage.VddGfx =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1333

table->UvdLevel[count].MinVoltage.Vddci =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1336

table->UvdLevel[count].MinVoltage.Phases = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1341

table->UvdLevel[count].VclkFrequency,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1348

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1351

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1356

table->UvdLevel[count].DclkDivider =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1359

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1360

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1368

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1380

table->VceLevelCount = (uint8_t) (mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1381

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1383

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1384

table->VceLevel[count].Frequency =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1386

table->VceLevel[count].MinVoltage.Vddc =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1389

table->VceLevel[count].MinVoltage.VddGfx =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1393

table->VceLevel[count].MinVoltage.Vddci =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1396

table->VceLevel[count].MinVoltage.Phases = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1400

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1405

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1407

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1414

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1425

table->AcpLevelCount = (uint8_t) (mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1426

table->AcpBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1428

for (count = 0; count < table->AcpLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1429

table->AcpLevel[count].Frequency =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1431

table->AcpLevel[count].MinVoltage.Vddc =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1434

table->AcpLevel[count].MinVoltage.VddGfx =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1438

table->AcpLevel[count].MinVoltage.Vddci =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1441

table->AcpLevel[count].MinVoltage.Phases = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1445

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1449

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1451

CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1523

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1529

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1530

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1557

table->BootVoltage.Vddc =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1560

table->BootVoltage.VddGfx =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1563

table->BootVoltage.Vddci =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1566

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1568

CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1747

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1755

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1759

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1767

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1772

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1782

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1785

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1791

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2226

SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2239

tonga_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2243

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2248

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2251

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2256

table->SystemFlags |= 0x40;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2259

result = tonga_populate_ulv_state(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2268

result = tonga_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2280

result = tonga_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2284

result = tonga_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2288

result = tonga_populate_smc_acp_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2301

result = tonga_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2305

result = tonga_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2320

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2321

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2322

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2323

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2324

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2325

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2328

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2331

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2332

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2333

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2334

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2335

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2350

table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2352

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2354

result = tonga_populate_vr_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2357

data->vr_config = table->VRConfig;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2358

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2359

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2363

table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2367

table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2374

table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2378

table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2398

table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2400

table->ThermOutPolarity =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2404

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2411

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2417

table->ThermOutGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2418

table->ThermOutPolarity = 1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2419

table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2423

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2424

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2425

CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2426

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2427

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2428

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2429

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2430

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2431

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2432

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2438

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2926

static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2931

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2932

table->mc_reg_address[i].s0 =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2933

tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2936

table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2941

static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2946

PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2948

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2951

for (i = 0; i < table->last; i++)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2952

ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2954

ni_table->last = table->last;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2956

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2958

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2959

for (j = 0; j < table->last; j++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2961

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2965

ni_table->num_entries = table->num_entries;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2971

struct tonga_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2977

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2981

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2986

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2987

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2988

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2989

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2991

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2998

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2999

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3000

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3001

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3003

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3006

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3013

table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3014

table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3015

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3016

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3017

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

302

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3025

table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3026

table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3027

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3028

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3030

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3041

table->last = j;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3046

static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3050

for (i = 0; i < table->last; i++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3051

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3052

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3053

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3054

table->validflag |= (1<<i);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3067

pp_atomctrl_mc_reg_table *table;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3071

table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3073

if (table == NULL)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

308

table->VddcLevelCount = data->vddc_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

309

for (count = 0; count < table->VddcLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

310

table->VddcTable[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3118

memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3120

result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3123

result = tonga_copy_vbios_smc_reg_table(table, ni_table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

313

CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3133

kfree(table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

319

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

325

table->VddGfxLevelCount = data->vddgfx_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

327

table->VddGfxTable[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

330

CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

336

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

341

table->VddciLevelCount = data->vddci_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

342

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

344

table->VddciTable[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

347

table->SmioTable1.Pattern[count].Voltage =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

350

table->SmioTable1.Pattern[count].Smio =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

352

table->Smio[count] |=

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

354

table->VddciTable[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

359

table->SmioMask1 = data->vddci_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

360

CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

366

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

372

table->MvddLevelCount = data->mvdd_voltage_table.count;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

373

for (count = 0; count < table->MvddLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

374

table->SmioTable2.Pattern[count].Voltage =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

377

table->SmioTable2.Pattern[count].Smio =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

379

table->Smio[count] |=

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

382

table->SmioMask2 = data->mvdd_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

384

CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

391

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

406

uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

407

uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

413

table->BapmVddcVidLoSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

415

table->BapmVddcVidHiSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

417

table->BapmVddcVidHiSidd2[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

426

table->BapmVddGfxVidHiSidd2[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

433

table->BapmVddGfxVidLoSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

435

table->BapmVddGfxVidHiSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

437

table->BapmVddGfxVidHiSidd2[count] =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

446

SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

450

result = tonga_populate_smc_vddc_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

455

result = tonga_populate_smc_vdd_ci_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

460

result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

465

result = tonga_populate_smc_mvdd_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

470

result = tonga_populate_cac_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

501

struct SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

503

return tonga_populate_ulv_level(hwmgr, &table->Ulv);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

506

static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

515

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

517

table->LinkLevel[i].PcieLaneCount =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

519

table->LinkLevel[i].EnabledForActivity =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

521

table->LinkLevel[i].SPC =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

523

table->LinkLevel[i].DownThreshold =

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

525

table->LinkLevel[i].UpThreshold =

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

197

&priv->smu_tables.entry[PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

212

&priv->smu_tables.entry[WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

228

&priv->smu_tables.entry[AVFSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

245

&priv->smu_tables.entry[TOOLSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

260

&priv->smu_tables.entry[AVFSFUSETABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

272

if (priv->smu_tables.entry[TOOLSTABLE].table)

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

275

&priv->smu_tables.entry[TOOLSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

279

&priv->smu_tables.entry[AVFSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

283

&priv->smu_tables.entry[WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

287

&priv->smu_tables.entry[PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

301

&priv->smu_tables.entry[PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

304

&priv->smu_tables.entry[WMTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

307

&priv->smu_tables.entry[AVFSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

308

if (priv->smu_tables.entry[TOOLSTABLE].table)

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

311

&priv->smu_tables.entry[TOOLSTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

314

&priv->smu_tables.entry[AVFSFUSETABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

335

static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

341

ret = vega10_copy_table_from_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

343

ret = vega10_copy_table_to_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

37

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

57

memcpy(table, priv->smu_tables.entry[table_id].table,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

64

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

75

memcpy(priv->smu_tables.entry[table_id].table, table,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.h

33

void *table;

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

223

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

237

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

253

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

268

&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

283

&priv->smu_tables.entry[TABLE_OVERDRIVE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

295

&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

297

if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].table)

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

300

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

304

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

308

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

323

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

326

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

327

if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].table)

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

330

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

333

&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

336

&priv->smu_tables.entry[TABLE_OVERDRIVE].table);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

354

static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

360

ret = vega12_copy_table_from_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

362

ret = vega12_copy_table_to_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

41

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

67

memcpy(table, priv->smu_tables.entry[table_id].table,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

79

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

91

memcpy(priv->smu_tables.entry[table_id].table, table,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.h

34

void *table;

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

164

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

192

memcpy(table, priv->smu_tables.entry[table_id].table,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

204

uint8_t *table, int16_t table_id)

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

217

memcpy(priv->smu_tables.entry[table_id].table, table,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

239

uint8_t *table, uint16_t workload_type)

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

245

memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

267

uint8_t *table, uint16_t workload_type)

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

289

memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

399

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

413

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

427

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

441

&priv->smu_tables.entry[TABLE_OVERDRIVE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

455

&priv->smu_tables.entry[TABLE_SMU_METRICS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

469

&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

481

&priv->smu_tables.entry[TABLE_SMU_METRICS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

485

&priv->smu_tables.entry[TABLE_OVERDRIVE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

489

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

493

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

497

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

512

&priv->smu_tables.entry[TABLE_PPTABLE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

515

&priv->smu_tables.entry[TABLE_WATERMARKS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

518

&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

521

&priv->smu_tables.entry[TABLE_OVERDRIVE].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

524

&priv->smu_tables.entry[TABLE_SMU_METRICS].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

527

&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

563

static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

569

ret = vega20_copy_table_from_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

571

ret = vega20_copy_table_to_smc(hwmgr, table, table_id);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.h

33

void *table;

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.h

55

uint8_t *table, uint16_t workload_type);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.h

57

uint8_t *table, uint16_t workload_type);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1109

SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1120

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1128

&table->ACPILevel.MinVoltage, &mvdd);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1135

&(table->ACPILevel.SclkSetting));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1140

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1141

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1142

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1144

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1145

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1146

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1147

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1149

CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1150

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1151

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1152

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1153

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1154

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1155

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1156

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1157

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1158

CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1162

table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1165

table->MemoryACPILevel.MclkFrequency,

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1166

&table->MemoryACPILevel.MinVoltage, &mvdd);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1184

table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1186

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1188

table->MemoryACPILevel.StutterEnable = false;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1190

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1191

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1192

table->MemoryACPILevel.UpHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1193

table->MemoryACPILevel.DownHyst = 100;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1194

table->MemoryACPILevel.VoltageDownHyst = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1195

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1198

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1199

CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1205

SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1217

table->VceLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1218

table->VceBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1220

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1221

table->VceLevel[count].Frequency = mm_table->entries[count].eclk;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1222

table->VceLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1223

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1235

table->VceLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1237

table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1241

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1246

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1248

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1249

CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1318

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1330

table->UvdLevelCount = (uint8_t)(mm_table->count);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1331

table->UvdBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1333

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1334

table->UvdLevel[count].MinVoltage = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1335

table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1336

table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1337

table->UvdLevel[count].MinVoltage |=

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1348

table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1349

table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1353

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1357

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1360

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1364

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1366

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1367

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1368

CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1375

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1380

table->GraphicsBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1381

table->MemoryBootLevel = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1386

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1390

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1392

table->BootVddc = data->vbios_boot_state.vddc_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1394

table->BootVddci = data->vbios_boot_state.vddci_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1396

table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1399

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1400

CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1401

CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1448

SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1458

table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1459

table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1465

table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1467

table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1469

table->FanGainEdge = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1471

table->FanGainHotspot = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1480

table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1481

table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1574

SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1592

table->BTCGB_VDROOP_TABLE[0].a0 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1594

table->BTCGB_VDROOP_TABLE[0].a1 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1596

table->BTCGB_VDROOP_TABLE[0].a2 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1598

table->BTCGB_VDROOP_TABLE[1].a0 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1600

table->BTCGB_VDROOP_TABLE[1].a1 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1602

table->BTCGB_VDROOP_TABLE[1].a2 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1604

table->AVFSGB_FUSE_TABLE[0].m1 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1606

table->AVFSGB_FUSE_TABLE[0].m2 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1608

table->AVFSGB_FUSE_TABLE[0].b =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1610

table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1611

table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1612

table->AVFSGB_FUSE_TABLE[1].m1 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1614

table->AVFSGB_FUSE_TABLE[1].m2 =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1616

table->AVFSGB_FUSE_TABLE[1].b =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1618

table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1619

table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1620

table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1676

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1684

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1689

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1698

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1701

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1704

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1710

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1720

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1724

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1732

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1932

struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1945

vegam_populate_smc_voltage_tables(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1947

table->SystemFlags = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1950

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1954

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1957

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1960

result = vegam_populate_ulv_state(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1967

result = vegam_populate_smc_link_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1979

result = vegam_populate_smc_acpi_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1983

result = vegam_populate_smc_vce_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1995

result = vegam_populate_smc_uvd_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1999

result = vegam_populate_smc_boot_level(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2023

table->CurrSclkPllRange = 0xff;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2024

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2025

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2026

table->GraphicsInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2027

table->VoltageInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2028

table->ThermalInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2029

table->TemperatureLimitHigh =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2032

table->TemperatureLimitLow =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2035

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2036

table->MemoryInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2037

table->VoltageResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2038

table->PhaseResponseTime = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2039

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2044

table->PCIeBootLinkLevel =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2046

table->PCIeGenInterval = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2047

table->VRConfig = 0;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2049

result = vegam_populate_vr_config(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2053

table->ThermGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2054

table->SclkStepSize = 0x4000;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2058

table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2060

table->VRHotLevel =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2063

table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2070

table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2077

table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2085

table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2092

table->ThermOutPolarity =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2095

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2102

table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2104

table->ThermOutGpio = 17;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2105

table->ThermOutPolarity = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2106

table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2118

table->Ulv.BifSclkDfs =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2121

table->LinkLevel[i - 1].BifSclkDfs =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2126

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2128

CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2129

CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2130

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2131

CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2132

CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2133

CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2134

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2135

CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2136

CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2137

CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2143

(uint8_t *)&(table->SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

449

SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

459

table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

462

table->SmioTable2.Pattern[level].Smio =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

464

table->Smio[level] |=

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

467

table->SmioMask2 = data->mvdd_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

469

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

476

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

487

table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

489

table->SmioTable1.Pattern[level].Smio = (uint8_t) level;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

491

table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

495

table->SmioMask1 = data->vddci_voltage_table.mask_low;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

501

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

518

table->BapmVddcVidLoSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

520

table->BapmVddcVidHiSidd[count] =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

522

table->BapmVddcVidHiSidd2[count] =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

530

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

532

vegam_populate_smc_vddci_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

533

vegam_populate_smc_mvdd_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

534

vegam_populate_cac_table(hwmgr, table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

563

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

565

return vegam_populate_ulv_level(hwmgr, &table->Ulv);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

569

struct SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

580

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

582

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

584

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

585

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

586

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

587

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

668

SMU75_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

679

table->SclkFcwRangeTable[i].vco_setting =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

681

table->SclkFcwRangeTable[i].postdiv =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

683

table->SclkFcwRangeTable[i].fcw_pcc =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

686

table->SclkFcwRangeTable[i].fcw_trans_upper =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

688

table->SclkFcwRangeTable[i].fcw_trans_lower =

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

691

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

692

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

693

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

704

table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

705

table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

706

table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

708

table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

709

table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

711

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

712

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

713

CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

721

const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

758

((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

760

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

768

((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

777

((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

779

temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/drm_hashtab.c

118

h_list = &ht->table[hashed_key];

sys/dev/drm/drm_hashtab.c

200

if (ht->table) {

sys/dev/drm/drm_hashtab.c

201

if ((PAGE_SIZE / sizeof(*ht->table)) >> ht->order)

sys/dev/drm/drm_hashtab.c

202

kfree(ht->table);

sys/dev/drm/drm_hashtab.c

204

kfree(ht->table);

sys/dev/drm/drm_hashtab.c

205

ht->table = NULL;

sys/dev/drm/drm_hashtab.c

46

ht->table = NULL;

sys/dev/drm/drm_hashtab.c

47

if (size <= PAGE_SIZE / sizeof(*ht->table))

sys/dev/drm/drm_hashtab.c

48

ht->table = kcalloc(size, sizeof(*ht->table), GFP_KERNEL);

sys/dev/drm/drm_hashtab.c

50

ht->table = kcalloc(size, sizeof(*ht->table), GFP_KERNEL);

sys/dev/drm/drm_hashtab.c

51

if (!ht->table) {

sys/dev/drm/drm_hashtab.c

68

h_list = &ht->table[hashed_key];

sys/dev/drm/drm_hashtab.c

81

h_list = &ht->table[hashed_key];

sys/dev/drm/drm_hashtab.c

99

h_list = &ht->table[hashed_key];

sys/dev/drm/i915/i915_cmd_parser.c

1013

__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)

sys/dev/drm/i915/i915_cmd_parser.c

1018

int ret = addr - i915_mmio_reg_offset(table[mid].addr);

sys/dev/drm/i915/i915_cmd_parser.c

1024

return &table[mid];

sys/dev/drm/i915/i915_cmd_parser.c

1032

const struct drm_i915_reg_table *table = engine->reg_tables;

sys/dev/drm/i915/i915_cmd_parser.c

1035

for (; count > 0; ++table, --count) {

sys/dev/drm/i915/i915_cmd_parser.c

1036

if (!table->master || is_master) {

sys/dev/drm/i915/i915_cmd_parser.c

1039

reg = __find_reg(table->regs, table->num_regs, addr);

sys/dev/drm/i915/i915_cmd_parser.c

182

const struct drm_i915_cmd_descriptor *table;

sys/dev/drm/i915/i915_cmd_parser.c

722

const struct drm_i915_cmd_table *table = &cmd_tables[i];

sys/dev/drm/i915/i915_cmd_parser.c

726

for (j = 0; j < table->count; j++) {

sys/dev/drm/i915/i915_cmd_parser.c

728

&table->table[j];

sys/dev/drm/i915/i915_cmd_parser.c

774

const struct drm_i915_reg_table *table;

sys/dev/drm/i915/i915_cmd_parser.c

777

table = &engine->reg_tables[i];

sys/dev/drm/i915/i915_cmd_parser.c

778

if (!check_sorted(engine, table->regs, table->num_regs))

sys/dev/drm/i915/i915_cmd_parser.c

822

const struct drm_i915_cmd_table *table = &cmd_tables[i];

sys/dev/drm/i915/i915_cmd_parser.c

824

for (j = 0; j < table->count; j++) {

sys/dev/drm/i915/i915_cmd_parser.c

826

&table->table[j];

sys/dev/drm/i915/intel_mocs.c

177

struct drm_i915_mocs_table *table)

sys/dev/drm/i915/intel_mocs.c

183

table->size = ARRAY_SIZE(skylake_mocs_table);

sys/dev/drm/i915/intel_mocs.c

184

table->table = skylake_mocs_table;

sys/dev/drm/i915/intel_mocs.c

187

table->size = ARRAY_SIZE(broxton_mocs_table);

sys/dev/drm/i915/intel_mocs.c

188

table->table = broxton_mocs_table;

sys/dev/drm/i915/intel_mocs.c

199

for (i = 0; i < table->size; i++)

sys/dev/drm/i915/intel_mocs.c

200

if (WARN_ON(table->table[i].l3cc_value &

sys/dev/drm/i915/intel_mocs.c

239

struct drm_i915_mocs_table table;

sys/dev/drm/i915/intel_mocs.c

242

if (!get_mocs_settings(dev_priv, &table))

sys/dev/drm/i915/intel_mocs.c

245

GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);

sys/dev/drm/i915/intel_mocs.c

247

for (index = 0; index < table.size; index++)

sys/dev/drm/i915/intel_mocs.c

249

table.table[index].control_value);

sys/dev/drm/i915/intel_mocs.c

261

table.table[0].control_value);

sys/dev/drm/i915/intel_mocs.c

275

const struct drm_i915_mocs_table *table)

sys/dev/drm/i915/intel_mocs.c

281

if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))

sys/dev/drm/i915/intel_mocs.c

290

for (index = 0; index < table->size; index++) {

sys/dev/drm/i915/intel_mocs.c

292

*cs++ = table->table[index].control_value;

sys/dev/drm/i915/intel_mocs.c

305

*cs++ = table->table[0].control_value;

sys/dev/drm/i915/intel_mocs.c

314

static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,

sys/dev/drm/i915/intel_mocs.c

318

return table->table[low].l3cc_value |

sys/dev/drm/i915/intel_mocs.c

319

table->table[high].l3cc_value << 16;

sys/dev/drm/i915/intel_mocs.c

334

const struct drm_i915_mocs_table *table)

sys/dev/drm/i915/intel_mocs.c

339

if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))

sys/dev/drm/i915/intel_mocs.c

348

for (i = 0; i < table->size/2; i++) {

sys/dev/drm/i915/intel_mocs.c

35

const struct drm_i915_mocs_entry *table;

sys/dev/drm/i915/intel_mocs.c

350

*cs++ = l3cc_combine(table, 2 * i, 2 * i + 1);

sys/dev/drm/i915/intel_mocs.c

353

if (table->size & 0x01) {

sys/dev/drm/i915/intel_mocs.c

356

*cs++ = l3cc_combine(table, 2 * i, 0);

sys/dev/drm/i915/intel_mocs.c

367

*cs++ = l3cc_combine(table, 0, 0);

sys/dev/drm/i915/intel_mocs.c

392

struct drm_i915_mocs_table table;

sys/dev/drm/i915/intel_mocs.c

395

if (!get_mocs_settings(dev_priv, &table))

sys/dev/drm/i915/intel_mocs.c

398

for (i = 0; i < table.size/2; i++)

sys/dev/drm/i915/intel_mocs.c

399

I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));

sys/dev/drm/i915/intel_mocs.c

402

if (table.size & 0x01) {

sys/dev/drm/i915/intel_mocs.c

403

I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));

sys/dev/drm/i915/intel_mocs.c

413

I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));

sys/dev/drm/include/drm/drm_hashtab.h

48

struct hlist_head *table;

sys/dev/drm/include/linux/scatterlist.h

186

void __sg_free_table(struct sg_table *table, unsigned int max_ents);

sys/dev/drm/include/linux/scatterlist.h

194

sg_free_table(struct sg_table *table)

sys/dev/drm/include/linux/scatterlist.h

196

__sg_free_table(table, SG_MAX_SINGLE_ALLOC);

sys/dev/drm/include/linux/scatterlist.h

199

int __sg_alloc_table(struct sg_table *table, unsigned int nents,

sys/dev/drm/include/linux/scatterlist.h

215

sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask)

sys/dev/drm/include/linux/scatterlist.h

219

ret = __sg_alloc_table(table, nents, SG_MAX_SINGLE_ALLOC,

sys/dev/drm/include/linux/scatterlist.h

222

__sg_free_table(table, SG_MAX_SINGLE_ALLOC);

sys/dev/drm/linux_scatterlist.c

103

table->sgl = sg;

sys/dev/drm/linux_scatterlist.c

118

__sg_free_table(struct sg_table *table, unsigned int max_ents)

sys/dev/drm/linux_scatterlist.c

122

if (unlikely(!table->sgl))

sys/dev/drm/linux_scatterlist.c

125

sgl = table->sgl;

sys/dev/drm/linux_scatterlist.c

126

while (table->orig_nents) {

sys/dev/drm/linux_scatterlist.c

127

unsigned int alloc_size = table->orig_nents;

sys/dev/drm/linux_scatterlist.c

145

table->orig_nents -= sg_size;

sys/dev/drm/linux_scatterlist.c

150

table->sgl = NULL;

sys/dev/drm/linux_scatterlist.c

56

__sg_alloc_table(struct sg_table *table, unsigned int nents,

sys/dev/drm/linux_scatterlist.c

62

memset(table, 0, sizeof(*table));

sys/dev/drm/linux_scatterlist.c

88

table->nents = ++table->orig_nents;

sys/dev/drm/linux_scatterlist.c

94

table->nents = table->orig_nents += sg_size;

sys/dev/drm/radeon/btc_dpm.c

1171

void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

sys/dev/drm/radeon/btc_dpm.c

1176

if ((table == NULL) || (table->count == 0)) {

sys/dev/drm/radeon/btc_dpm.c

1181

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/btc_dpm.c

1182

if (clock < table->entries[i].clk)

sys/dev/drm/radeon/btc_dpm.c

1183

clock = table->entries[i].clk;

sys/dev/drm/radeon/btc_dpm.c

1188

void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

sys/dev/drm/radeon/btc_dpm.c

1193

if ((table == NULL) || (table->count == 0))

sys/dev/drm/radeon/btc_dpm.c

1196

for (i= 0; i < table->count; i++) {

sys/dev/drm/radeon/btc_dpm.c

1197

if (clock <= table->entries[i].clk) {

sys/dev/drm/radeon/btc_dpm.c

1198

if (*voltage < table->entries[i].v)

sys/dev/drm/radeon/btc_dpm.c

1199

*voltage = (u16)((table->entries[i].v < max_voltage) ?

sys/dev/drm/radeon/btc_dpm.c

1200

table->entries[i].v : max_voltage);

sys/dev/drm/radeon/btc_dpm.c

1293

static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)

sys/dev/drm/radeon/btc_dpm.c

1297

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/btc_dpm.c

1298

if (voltage <= table->entries[i].value)

sys/dev/drm/radeon/btc_dpm.c

1299

return table->entries[i].value;

sys/dev/drm/radeon/btc_dpm.c

1302

return table->entries[table->count - 1].value;

sys/dev/drm/radeon/btc_dpm.c

1395

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/btc_dpm.c

1404

&table->ULVState.levels[0],

sys/dev/drm/radeon/btc_dpm.c

1407

table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;

sys/dev/drm/radeon/btc_dpm.c

1408

table->ULVState.levels[0].ACIndex = 1;

sys/dev/drm/radeon/btc_dpm.c

1410

table->ULVState.levels[1] = table->ULVState.levels[0];

sys/dev/drm/radeon/btc_dpm.c

1411

table->ULVState.levels[2] = table->ULVState.levels[0];

sys/dev/drm/radeon/btc_dpm.c

1413

table->ULVState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/btc_dpm.c

1424

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/btc_dpm.c

1426

int ret = cypress_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/btc_dpm.c

1429

table->ACPIState.levels[0].ACIndex = 0;

sys/dev/drm/radeon/btc_dpm.c

1430

table->ACPIState.levels[1].ACIndex = 0;

sys/dev/drm/radeon/btc_dpm.c

1431

table->ACPIState.levels[2].ACIndex = 0;

sys/dev/drm/radeon/btc_dpm.c

1629

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/btc_dpm.c

1632

memset(table, 0, sizeof(RV770_SMC_STATETABLE));

sys/dev/drm/radeon/btc_dpm.c

1634

cypress_populate_smc_voltage_tables(rdev, table);

sys/dev/drm/radeon/btc_dpm.c

1639

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/radeon/btc_dpm.c

1642

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/radeon/btc_dpm.c

1645

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/radeon/btc_dpm.c

1650

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/btc_dpm.c

1653

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

sys/dev/drm/radeon/btc_dpm.c

1656

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/btc_dpm.c

1659

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/btc_dpm.c

1661

ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/btc_dpm.c

1669

ret = btc_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/btc_dpm.c

1674

ret = btc_populate_ulv_state(rdev, table);

sys/dev/drm/radeon/btc_dpm.c

1679

table->driverState = table->initialState;

sys/dev/drm/radeon/btc_dpm.c

1683

(u8 *)table,

sys/dev/drm/radeon/btc_dpm.c

1898

static void btc_set_valid_flag(struct evergreen_mc_reg_table *table)

sys/dev/drm/radeon/btc_dpm.c

1902

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/btc_dpm.c

1903

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/radeon/btc_dpm.c

1904

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/radeon/btc_dpm.c

1905

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/radeon/btc_dpm.c

1906

table->valid_flag |= (1 << i);

sys/dev/drm/radeon/btc_dpm.c

1914

struct evergreen_mc_reg_table *table)

sys/dev/drm/radeon/btc_dpm.c

1920

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/radeon/btc_dpm.c

1921

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/radeon/btc_dpm.c

1924

table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;

sys/dev/drm/radeon/btc_dpm.c

1925

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;

sys/dev/drm/radeon/btc_dpm.c

1926

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/btc_dpm.c

1927

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/btc_dpm.c

1929

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/radeon/btc_dpm.c

1937

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;

sys/dev/drm/radeon/btc_dpm.c

1938

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;

sys/dev/drm/radeon/btc_dpm.c

1939

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/btc_dpm.c

1940

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/btc_dpm.c

1942

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/btc_dpm.c

1944

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/radeon/btc_dpm.c

1953

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;

sys/dev/drm/radeon/btc_dpm.c

1954

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;

sys/dev/drm/radeon/btc_dpm.c

1955

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/btc_dpm.c

1956

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/btc_dpm.c

1958

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/btc_dpm.c

1970

table->last = j;

sys/dev/drm/radeon/btc_dpm.c

1975

static void btc_set_s0_mc_reg_index(struct evergreen_mc_reg_table *table)

sys/dev/drm/radeon/btc_dpm.c

1980

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/btc_dpm.c

1981

table->mc_reg_address[i].s0 =

sys/dev/drm/radeon/btc_dpm.c

1982

btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/radeon/btc_dpm.c

1983

address : table->mc_reg_address[i].s1;

sys/dev/drm/radeon/btc_dpm.c

1987

static int btc_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,

sys/dev/drm/radeon/btc_dpm.c

1992

if (table->last > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/btc_dpm.c

1995

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/radeon/btc_dpm.c

1998

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/btc_dpm.c

1999

eg_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/radeon/btc_dpm.c

2000

eg_table->last = table->last;

sys/dev/drm/radeon/btc_dpm.c

2002

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/radeon/btc_dpm.c

2004

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/radeon/btc_dpm.c

2005

for(j = 0; j < table->last; j++)

sys/dev/drm/radeon/btc_dpm.c

2007

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/radeon/btc_dpm.c

2009

eg_table->num_entries = table->num_entries;

sys/dev/drm/radeon/btc_dpm.c

2017

struct atom_mc_reg_table *table;

sys/dev/drm/radeon/btc_dpm.c

2022

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/radeon/btc_dpm.c

2023

if (!table)

sys/dev/drm/radeon/btc_dpm.c

2039

ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);

sys/dev/drm/radeon/btc_dpm.c

2044

ret = btc_copy_vbios_mc_reg_table(table, eg_table);

sys/dev/drm/radeon/btc_dpm.c

2058

kfree(table);

sys/dev/drm/radeon/btc_dpm.h

47

void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

sys/dev/drm/radeon/btc_dpm.h

49

void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

sys/dev/drm/radeon/ci_dpm.c

1339

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

1345

table->FpsHighT = cpu_to_be16(tmp);

sys/dev/drm/radeon/ci_dpm.c

1348

table->FpsLowT = cpu_to_be16(tmp);

sys/dev/drm/radeon/ci_dpm.c

2253

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2258

table->VddcLevelCount = pi->vddc_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2259

for (count = 0; count < table->VddcLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2262

&table->VddcLevel[count]);

sys/dev/drm/radeon/ci_dpm.c

2265

table->VddcLevel[count].Smio |=

sys/dev/drm/radeon/ci_dpm.c

2268

table->VddcLevel[count].Smio = 0;

sys/dev/drm/radeon/ci_dpm.c

2270

table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);

sys/dev/drm/radeon/ci_dpm.c

2276

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2281

table->VddciLevelCount = pi->vddci_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2282

for (count = 0; count < table->VddciLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2285

&table->VddciLevel[count]);

sys/dev/drm/radeon/ci_dpm.c

2288

table->VddciLevel[count].Smio |=

sys/dev/drm/radeon/ci_dpm.c

2291

table->VddciLevel[count].Smio = 0;

sys/dev/drm/radeon/ci_dpm.c

2293

table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);

sys/dev/drm/radeon/ci_dpm.c

2299

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2304

table->MvddLevelCount = pi->mvdd_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2305

for (count = 0; count < table->MvddLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2308

&table->MvddLevel[count]);

sys/dev/drm/radeon/ci_dpm.c

2311

table->MvddLevel[count].Smio |=

sys/dev/drm/radeon/ci_dpm.c

2314

table->MvddLevel[count].Smio = 0;

sys/dev/drm/radeon/ci_dpm.c

2316

table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);

sys/dev/drm/radeon/ci_dpm.c

2322

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2326

ret = ci_populate_smc_vddc_table(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

2330

ret = ci_populate_smc_vddci_table(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

2334

ret = ci_populate_smc_mvdd_table(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

2661

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2668

table->LinkLevel[i].PcieGenSpeed =

sys/dev/drm/radeon/ci_dpm.c

2670

table->LinkLevel[i].PcieLaneCount =

sys/dev/drm/radeon/ci_dpm.c

2672

table->LinkLevel[i].EnabledForActivity = 1;

sys/dev/drm/radeon/ci_dpm.c

2673

table->LinkLevel[i].DownT = cpu_to_be32(5);

sys/dev/drm/radeon/ci_dpm.c

2674

table->LinkLevel[i].UpT = cpu_to_be32(30);

sys/dev/drm/radeon/ci_dpm.c

2683

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2689

table->UvdLevelCount =

sys/dev/drm/radeon/ci_dpm.c

2692

for (count = 0; count < table->UvdLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2693

table->UvdLevel[count].VclkFrequency =

sys/dev/drm/radeon/ci_dpm.c

2695

table->UvdLevel[count].DclkFrequency =

sys/dev/drm/radeon/ci_dpm.c

2697

table->UvdLevel[count].MinVddc =

sys/dev/drm/radeon/ci_dpm.c

2699

table->UvdLevel[count].MinVddcPhases = 1;

sys/dev/drm/radeon/ci_dpm.c

2703

table->UvdLevel[count].VclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2707

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2711

table->UvdLevel[count].DclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2715

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2717

table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);

sys/dev/drm/radeon/ci_dpm.c

2718

table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);

sys/dev/drm/radeon/ci_dpm.c

2719

table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);

sys/dev/drm/radeon/ci_dpm.c

2726

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2732

table->VceLevelCount =

sys/dev/drm/radeon/ci_dpm.c

2735

for (count = 0; count < table->VceLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2736

table->VceLevel[count].Frequency =

sys/dev/drm/radeon/ci_dpm.c

2738

table->VceLevel[count].MinVoltage =

sys/dev/drm/radeon/ci_dpm.c

2740

table->VceLevel[count].MinPhases = 1;

sys/dev/drm/radeon/ci_dpm.c

2744

table->VceLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2748

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2750

table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);

sys/dev/drm/radeon/ci_dpm.c

2751

table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);

sys/dev/drm/radeon/ci_dpm.c

2759

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2765

table->AcpLevelCount = (u8)

sys/dev/drm/radeon/ci_dpm.c

2768

for (count = 0; count < table->AcpLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2769

table->AcpLevel[count].Frequency =

sys/dev/drm/radeon/ci_dpm.c

2771

table->AcpLevel[count].MinVoltage =

sys/dev/drm/radeon/ci_dpm.c

2773

table->AcpLevel[count].MinPhases = 1;

sys/dev/drm/radeon/ci_dpm.c

2777

table->AcpLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2781

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2783

table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);

sys/dev/drm/radeon/ci_dpm.c

2784

table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);

sys/dev/drm/radeon/ci_dpm.c

2791

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

2797

table->SamuLevelCount =

sys/dev/drm/radeon/ci_dpm.c

2800

for (count = 0; count < table->SamuLevelCount; count++) {

sys/dev/drm/radeon/ci_dpm.c

2801

table->SamuLevel[count].Frequency =

sys/dev/drm/radeon/ci_dpm.c

2803

table->SamuLevel[count].MinVoltage =

sys/dev/drm/radeon/ci_dpm.c

2805

table->SamuLevel[count].MinPhases = 1;

sys/dev/drm/radeon/ci_dpm.c

2809

table->SamuLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2813

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2815

table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);

sys/dev/drm/radeon/ci_dpm.c

2816

table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);

sys/dev/drm/radeon/ci_dpm.c

3024

SMU7_Discrete_DpmTable *table)

sys/dev/drm/radeon/ci_dpm.c

3035

table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/ci_dpm.c

3038

table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3040

table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3042

table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/radeon/ci_dpm.c

3044

table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

3048

table->ACPILevel.SclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

3052

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

3053

table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

sys/dev/drm/radeon/ci_dpm.c

3054

table->ACPILevel.DeepSleepDivId = 0;

sys/dev/drm/radeon/ci_dpm.c

3062

table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

3063

table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.c

3064

table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ci_dpm.c

3065

table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ci_dpm.c

3066

table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/ci_dpm.c

3067

table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ci_dpm.c

3068

table->ACPILevel.CcPwrDynRm = 0;

sys/dev/drm/radeon/ci_dpm.c

3069

table->ACPILevel.CcPwrDynRm1 = 0;

sys/dev/drm/radeon/ci_dpm.c

3071

table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);

sys/dev/drm/radeon/ci_dpm.c

3072

table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);

sys/dev/drm/radeon/ci_dpm.c

3073

table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);

sys/dev/drm/radeon/ci_dpm.c

3074

table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);

sys/dev/drm/radeon/ci_dpm.c

3075

table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);

sys/dev/drm/radeon/ci_dpm.c

3076

table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);

sys/dev/drm/radeon/ci_dpm.c

3077

table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);

sys/dev/drm/radeon/ci_dpm.c

3078

table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);

sys/dev/drm/radeon/ci_dpm.c

3079

table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);

sys/dev/drm/radeon/ci_dpm.c

3080

table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);

sys/dev/drm/radeon/ci_dpm.c

3081

table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);

sys/dev/drm/radeon/ci_dpm.c

3083

table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;

sys/dev/drm/radeon/ci_dpm.c

3084

table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;

sys/dev/drm/radeon/ci_dpm.c

3088

table->MemoryACPILevel.MinVddci =

sys/dev/drm/radeon/ci_dpm.c

3091

table->MemoryACPILevel.MinVddci =

sys/dev/drm/radeon/ci_dpm.c

3096

table->MemoryACPILevel.MinMvdd = 0;

sys/dev/drm/radeon/ci_dpm.c

3098

table->MemoryACPILevel.MinMvdd =

sys/dev/drm/radeon/ci_dpm.c

3106

table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/ci_dpm.c

3107

table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/radeon/ci_dpm.c

3108

table->MemoryACPILevel.MpllAdFuncCntl =

sys/dev/drm/radeon/ci_dpm.c

3110

table->MemoryACPILevel.MpllDqFuncCntl =

sys/dev/drm/radeon/ci_dpm.c

3112

table->MemoryACPILevel.MpllFuncCntl =

sys/dev/drm/radeon/ci_dpm.c

3114

table->MemoryACPILevel.MpllFuncCntl_1 =

sys/dev/drm/radeon/ci_dpm.c

3116

table->MemoryACPILevel.MpllFuncCntl_2 =

sys/dev/drm/radeon/ci_dpm.c

3118

table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);

sys/dev/drm/radeon/ci_dpm.c

3119

table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);

sys/dev/drm/radeon/ci_dpm.c

3121

table->MemoryACPILevel.EnabledForThrottle = 0;

sys/dev/drm/radeon/ci_dpm.c

3122

table->MemoryACPILevel.EnabledForActivity = 0;

sys/dev/drm/radeon/ci_dpm.c

3123

table->MemoryACPILevel.UpH = 0;

sys/dev/drm/radeon/ci_dpm.c

3124

table->MemoryACPILevel.DownH = 100;

sys/dev/drm/radeon/ci_dpm.c

3125

table->MemoryACPILevel.VoltageDownH = 0;

sys/dev/drm/radeon/ci_dpm.c

3126

table->MemoryACPILevel.ActivityLevel =

sys/dev/drm/radeon/ci_dpm.c

3129

table->MemoryACPILevel.StutterEnable = false;

sys/dev/drm/radeon/ci_dpm.c

3130

table->MemoryACPILevel.StrobeEnable = false;

sys/dev/drm/radeon/ci_dpm.c

3131

table->MemoryACPILevel.EdcReadEnable = false;

sys/dev/drm/radeon/ci_dpm.c

3132

table->MemoryACPILevel.EdcWriteEnable = false;

sys/dev/drm/radeon/ci_dpm.c

3133

table->MemoryACPILevel.RttEnable = false;

sys/dev/drm/radeon/ci_dpm.c

3573

static int ci_find_boot_level(struct ci_single_dpm_table *table,

sys/dev/drm/radeon/ci_dpm.c

3579

for(i = 0; i < table->count; i++) {

sys/dev/drm/radeon/ci_dpm.c

3580

if (value == table->dpm_levels[i].value) {

sys/dev/drm/radeon/ci_dpm.c

3594

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

3602

ci_populate_smc_voltage_tables(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3607

table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/ci_dpm.c

3610

table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/ci_dpm.c

3613

table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/ci_dpm.c

3630

ci_populate_smc_link_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3632

ret = ci_populate_smc_acpi_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3636

ret = ci_populate_smc_vce_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3640

ret = ci_populate_smc_acp_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3644

ret = ci_populate_smc_samu_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3652

ret = ci_populate_smc_uvd_level(rdev, table);

sys/dev/drm/radeon/ci_dpm.c

3656

table->UvdBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3657

table->VceBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3658

table->AcpBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3659

table->SamuBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3660

table->GraphicsBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3661

table->MemoryBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

3671

table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

3672

table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

3673

table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

3681

table->UVDInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3682

table->VCEInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3683

table->ACPInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3684

table->SAMUInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3685

table->GraphicsVoltageChangeEnable = 1;

sys/dev/drm/radeon/ci_dpm.c

3686

table->GraphicsThermThrottleEnable = 1;

sys/dev/drm/radeon/ci_dpm.c

3687

table->GraphicsInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3688

table->VoltageInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3689

table->ThermalInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3690

table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *

sys/dev/drm/radeon/ci_dpm.c

3692

table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *

sys/dev/drm/radeon/ci_dpm.c

3694

table->MemoryVoltageChangeEnable = 1;

sys/dev/drm/radeon/ci_dpm.c

3695

table->MemoryInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3696

table->VoltageResponseTime = 0;

sys/dev/drm/radeon/ci_dpm.c

3697

table->VddcVddciDelta = 4000;

sys/dev/drm/radeon/ci_dpm.c

3698

table->PhaseResponseTime = 0;

sys/dev/drm/radeon/ci_dpm.c

3699

table->MemoryThermThrottleEnable = 1;

sys/dev/drm/radeon/ci_dpm.c

3700

table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;

sys/dev/drm/radeon/ci_dpm.c

3701

table->PCIeGenInterval = 1;

sys/dev/drm/radeon/ci_dpm.c

3703

table->SVI2Enable = 1;

sys/dev/drm/radeon/ci_dpm.c

3705

table->SVI2Enable = 0;

sys/dev/drm/radeon/ci_dpm.c

3707

table->ThermGpio = 17;

sys/dev/drm/radeon/ci_dpm.c

3708

table->SclkStepSize = 0x4000;

sys/dev/drm/radeon/ci_dpm.c

3710

table->SystemFlags = cpu_to_be32(table->SystemFlags);

sys/dev/drm/radeon/ci_dpm.c

3711

table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);

sys/dev/drm/radeon/ci_dpm.c

3712

table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);

sys/dev/drm/radeon/ci_dpm.c

3713

table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);

sys/dev/drm/radeon/ci_dpm.c

3714

table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);

sys/dev/drm/radeon/ci_dpm.c

3715

table->SclkStepSize = cpu_to_be32(table->SclkStepSize);

sys/dev/drm/radeon/ci_dpm.c

3716

table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);

sys/dev/drm/radeon/ci_dpm.c

3717

table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);

sys/dev/drm/radeon/ci_dpm.c

3718

table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);

sys/dev/drm/radeon/ci_dpm.c

3719

table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);

sys/dev/drm/radeon/ci_dpm.c

3720

table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);

sys/dev/drm/radeon/ci_dpm.c

3721

table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3722

table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3723

table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3728

(u8 *)&table->SystemFlags,

sys/dev/drm/radeon/ci_dpm.c

4137

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/ci_dpm.c

4140

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/ci_dpm.c

4141

if (table->entries[i].evclk >= min_evclk)

sys/dev/drm/radeon/ci_dpm.c

4145

return table->count - 1;

sys/dev/drm/radeon/ci_dpm.c

4371

struct ci_mc_reg_table *table)

sys/dev/drm/radeon/ci_dpm.c

4377

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/radeon/ci_dpm.c

4380

switch(table->mc_reg_address[i].s1 << 2) {

sys/dev/drm/radeon/ci_dpm.c

4383

table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;

sys/dev/drm/radeon/ci_dpm.c

4384

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;

sys/dev/drm/radeon/ci_dpm.c

4385

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4386

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ci_dpm.c

4387

((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/radeon/ci_dpm.c

4394

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;

sys/dev/drm/radeon/ci_dpm.c

4395

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;

sys/dev/drm/radeon/ci_dpm.c

4396

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4397

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ci_dpm.c

4398

(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/ci_dpm.c

4400

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/radeon/ci_dpm.c

4407

table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;

sys/dev/drm/radeon/ci_dpm.c

4408

table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;

sys/dev/drm/radeon/ci_dpm.c

4409

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4410

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ci_dpm.c

4411

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/radeon/ci_dpm.c

4420

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;

sys/dev/drm/radeon/ci_dpm.c

4421

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;

sys/dev/drm/radeon/ci_dpm.c

4422

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4423

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ci_dpm.c

4424

(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/ci_dpm.c

4436

table->last = j;

sys/dev/drm/radeon/ci_dpm.c

4514

static void ci_set_valid_flag(struct ci_mc_reg_table *table)

sys/dev/drm/radeon/ci_dpm.c

4518

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/ci_dpm.c

4519

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/radeon/ci_dpm.c

4520

if (table->mc_reg_table_entry[j-1].mc_data[i] !=

sys/dev/drm/radeon/ci_dpm.c

4521

table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/radeon/ci_dpm.c

4522

table->valid_flag |= 1 << i;

sys/dev/drm/radeon/ci_dpm.c

4529

static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)

sys/dev/drm/radeon/ci_dpm.c

4534

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/ci_dpm.c

4535

table->mc_reg_address[i].s0 =

sys/dev/drm/radeon/ci_dpm.c

4536

ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/radeon/ci_dpm.c

4537

address : table->mc_reg_address[i].s1;

sys/dev/drm/radeon/ci_dpm.c

4541

static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,

sys/dev/drm/radeon/ci_dpm.c

4546

if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4548

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/radeon/ci_dpm.c

4551

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/ci_dpm.c

4552

ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/radeon/ci_dpm.c

4554

ci_table->last = table->last;

sys/dev/drm/radeon/ci_dpm.c

4556

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/radeon/ci_dpm.c

4558

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/radeon/ci_dpm.c

4559

for (j = 0; j < table->last; j++)

sys/dev/drm/radeon/ci_dpm.c

4561

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/radeon/ci_dpm.c

4563

ci_table->num_entries = table->num_entries;

sys/dev/drm/radeon/ci_dpm.c

4569

struct ci_mc_reg_table *table)

sys/dev/drm/radeon/ci_dpm.c

4581

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/ci_dpm.c

4582

if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4584

switch(table->mc_reg_address[i].s1 >> 2) {

sys/dev/drm/radeon/ci_dpm.c

4586

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4587

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/radeon/ci_dpm.c

4588

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/radeon/ci_dpm.c

4589

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4590

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |

sys/dev/drm/radeon/ci_dpm.c

4595

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4596

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/radeon/ci_dpm.c

4597

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/radeon/ci_dpm.c

4598

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4599

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |

sys/dev/drm/radeon/ci_dpm.c

4604

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4605

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/radeon/ci_dpm.c

4606

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/radeon/ci_dpm.c

4607

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4608

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |

sys/dev/drm/radeon/ci_dpm.c

4613

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4614

if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||

sys/dev/drm/radeon/ci_dpm.c

4615

(table->mc_reg_table_entry[k].mclk_max == 137500))

sys/dev/drm/radeon/ci_dpm.c

4616

table->mc_reg_table_entry[k].mc_data[i] = 0;

sys/dev/drm/radeon/ci_dpm.c

4620

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4621

if (table->mc_reg_table_entry[k].mclk_max == 125000)

sys/dev/drm/radeon/ci_dpm.c

4622

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4623

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |

sys/dev/drm/radeon/ci_dpm.c

4625

else if (table->mc_reg_table_entry[k].mclk_max == 137500)

sys/dev/drm/radeon/ci_dpm.c

4626

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4627

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |

sys/dev/drm/radeon/ci_dpm.c

4632

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ci_dpm.c

4633

if (table->mc_reg_table_entry[k].mclk_max == 125000)

sys/dev/drm/radeon/ci_dpm.c

4634

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4635

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |

sys/dev/drm/radeon/ci_dpm.c

4637

else if (table->mc_reg_table_entry[k].mclk_max == 137500)

sys/dev/drm/radeon/ci_dpm.c

4638

table->mc_reg_table_entry[k].mc_data[i] =

sys/dev/drm/radeon/ci_dpm.c

4639

(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |

sys/dev/drm/radeon/ci_dpm.c

4661

struct atom_mc_reg_table *table;

sys/dev/drm/radeon/ci_dpm.c

4666

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/radeon/ci_dpm.c

4667

if (!table)

sys/dev/drm/radeon/ci_dpm.c

4691

ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);

sys/dev/drm/radeon/ci_dpm.c

4695

ret = ci_copy_vbios_mc_reg_table(table, ci_table);

sys/dev/drm/radeon/ci_dpm.c

4712

kfree(table);

sys/dev/drm/radeon/ci_dpm.c

5021

struct radeon_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/ci_dpm.c

5025

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5026

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5027

ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);

sys/dev/drm/radeon/ci_dpm.c

5032

struct radeon_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/ci_dpm.c

5036

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5037

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5038

ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);

sys/dev/drm/radeon/ci_dpm.c

5043

struct radeon_vce_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/ci_dpm.c

5047

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5048

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5049

ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);

sys/dev/drm/radeon/ci_dpm.c

5054

struct radeon_uvd_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/ci_dpm.c

5058

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5059

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5060

ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);

sys/dev/drm/radeon/ci_dpm.c

5065

struct radeon_phase_shedding_limits_table *table)

sys/dev/drm/radeon/ci_dpm.c

5069

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5070

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5071

ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);

sys/dev/drm/radeon/ci_dpm.c

5076

struct radeon_clock_and_voltage_limits *table)

sys/dev/drm/radeon/ci_dpm.c

5078

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5079

ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);

sys/dev/drm/radeon/ci_dpm.c

5080

ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);

sys/dev/drm/radeon/ci_dpm.c

5085

struct radeon_cac_leakage_table *table)

sys/dev/drm/radeon/ci_dpm.c

5089

if (table) {

sys/dev/drm/radeon/ci_dpm.c

5090

for (i = 0; i < table->count; i++)

sys/dev/drm/radeon/ci_dpm.c

5091

ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);

sys/dev/drm/radeon/cypress_dpm.c

1240

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/cypress_dpm.c

1247

table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1249

table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1251

table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1253

table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1255

table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1257

table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1260

table->initialState.levels[0].mclk.mclk770.vMPLL_SS =

sys/dev/drm/radeon/cypress_dpm.c

1262

table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =

sys/dev/drm/radeon/cypress_dpm.c

1265

table->initialState.levels[0].mclk.mclk770.mclk_value =

sys/dev/drm/radeon/cypress_dpm.c

1268

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1270

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1272

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/cypress_dpm.c

1274

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/radeon/cypress_dpm.c

1276

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/radeon/cypress_dpm.c

1279

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/radeon/cypress_dpm.c

1282

table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;

sys/dev/drm/radeon/cypress_dpm.c

1284

table->initialState.levels[0].ACIndex = 0;

sys/dev/drm/radeon/cypress_dpm.c

1289

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/cypress_dpm.c

1295

&table->initialState.levels[0].vddci);

sys/dev/drm/radeon/cypress_dpm.c

1298

&table->initialState.levels[0].mvdd);

sys/dev/drm/radeon/cypress_dpm.c

1301

table->initialState.levels[0].aT = cpu_to_be32(a_t);

sys/dev/drm/radeon/cypress_dpm.c

1303

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/cypress_dpm.c

1307

table->initialState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/cypress_dpm.c

1309

table->initialState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/cypress_dpm.c

1311

table->initialState.levels[0].gen2XSP = 1;

sys/dev/drm/radeon/cypress_dpm.c

1313

table->initialState.levels[0].gen2XSP = 0;

sys/dev/drm/radeon/cypress_dpm.c

1316

table->initialState.levels[0].strobeMode =

sys/dev/drm/radeon/cypress_dpm.c

1321

table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;

sys/dev/drm/radeon/cypress_dpm.c

1323

table->initialState.levels[0].mcFlags = 0;

sys/dev/drm/radeon/cypress_dpm.c

1326

table->initialState.levels[1] = table->initialState.levels[0];

sys/dev/drm/radeon/cypress_dpm.c

1327

table->initialState.levels[2] = table->initialState.levels[0];

sys/dev/drm/radeon/cypress_dpm.c

1329

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/cypress_dpm.c

1335

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/cypress_dpm.c

1358

table->ACPIState = table->initialState;

sys/dev/drm/radeon/cypress_dpm.c

1360

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/cypress_dpm.c

1366

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/cypress_dpm.c

1369

table->ACPIState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/cypress_dpm.c

1371

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/cypress_dpm.c

1373

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/cypress_dpm.c

1375

table->ACPIState.levels[0].gen2XSP = 1;

sys/dev/drm/radeon/cypress_dpm.c

1377

table->ACPIState.levels[0].gen2XSP = 0;

sys/dev/drm/radeon/cypress_dpm.c

1382

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/cypress_dpm.c

1383

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/cypress_dpm.c

1391

&table->ACPIState.levels[0].vddci);

sys/dev/drm/radeon/cypress_dpm.c

1437

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1439

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1441

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1443

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1445

table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1447

table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1449

table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;

sys/dev/drm/radeon/cypress_dpm.c

1451

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/cypress_dpm.c

1453

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/cypress_dpm.c

1455

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/cypress_dpm.c

1458

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/cypress_dpm.c

1460

cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/cypress_dpm.c

1463

table->ACPIState.levels[0].ACIndex = 1;

sys/dev/drm/radeon/cypress_dpm.c

1465

table->ACPIState.levels[1] = table->ACPIState.levels[0];

sys/dev/drm/radeon/cypress_dpm.c

1466

table->ACPIState.levels[2] = table->ACPIState.levels[0];

sys/dev/drm/radeon/cypress_dpm.c

1517

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/cypress_dpm.c

1522

table->highSMIO[i] = 0;

sys/dev/drm/radeon/cypress_dpm.c

1523

table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);

sys/dev/drm/radeon/cypress_dpm.c

1528

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/cypress_dpm.c

1537

table);

sys/dev/drm/radeon/cypress_dpm.c

1539

table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;

sys/dev/drm/radeon/cypress_dpm.c

1540

table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =

sys/dev/drm/radeon/cypress_dpm.c

1546

table->maxVDDCIndexInPPTable = i;

sys/dev/drm/radeon/cypress_dpm.c

1555

table);

sys/dev/drm/radeon/cypress_dpm.c

1557

table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;

sys/dev/drm/radeon/cypress_dpm.c

1558

table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =

sys/dev/drm/radeon/cypress_dpm.c

1619

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/cypress_dpm.c

1622

memset(table, 0, sizeof(RV770_SMC_STATETABLE));

sys/dev/drm/radeon/cypress_dpm.c

1624

cypress_populate_smc_voltage_tables(rdev, table);

sys/dev/drm/radeon/cypress_dpm.c

1629

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/radeon/cypress_dpm.c

1632

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/radeon/cypress_dpm.c

1635

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/radeon/cypress_dpm.c

1640

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/cypress_dpm.c

1643

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

sys/dev/drm/radeon/cypress_dpm.c

1646

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/cypress_dpm.c

1649

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/cypress_dpm.c

1651

ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/cypress_dpm.c

1655

ret = cypress_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/cypress_dpm.c

1659

table->driverState = table->initialState;

sys/dev/drm/radeon/cypress_dpm.c

1663

(u8 *)table, sizeof(RV770_SMC_STATETABLE),

sys/dev/drm/radeon/cypress_dpm.c

404

struct atom_voltage_table *table,

sys/dev/drm/radeon/cypress_dpm.c

409

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/cypress_dpm.c

410

if (value <= table->entries[i].value) {

sys/dev/drm/radeon/cypress_dpm.c

412

voltage->value = cpu_to_be16(table->entries[i].value);

sys/dev/drm/radeon/cypress_dpm.c

417

if (i == table->count)

sys/dev/drm/radeon/cypress_dpm.h

118

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/cypress_dpm.h

120

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/cypress_dpm.h

123

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/kv_dpm.c

1017

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1023

if (table == NULL || table->count == 0)

sys/dev/drm/radeon/kv_dpm.c

1027

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1028

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

1029

pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

1032

table->entries[i].clk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

1076

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1079

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

1082

if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1084

else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1086

else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)

sys/dev/drm/radeon/kv_dpm.c

1088

else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1090

else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1099

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

1103

if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1105

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1107

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)

sys/dev/drm/radeon/kv_dpm.c

1109

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1111

else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)

sys/dev/drm/radeon/kv_dpm.c

1423

struct radeon_uvd_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1429

if (table->count)

sys/dev/drm/radeon/kv_dpm.c

1430

pi->uvd_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1459

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1462

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1463

if (table->entries[i].evclk >= evclk)

sys/dev/drm/radeon/kv_dpm.c

1475

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1484

pi->vce_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1516

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1522

pi->samu_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1547

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1550

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1551

if (table->entries[i].clk >= 0) /* XXX */

sys/dev/drm/radeon/kv_dpm.c

1555

if (i >= table->count)

sys/dev/drm/radeon/kv_dpm.c

1556

i = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1580

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1586

pi->acp_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1708

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

1711

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

1713

if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||

sys/dev/drm/radeon/kv_dpm.c

1721

if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)

sys/dev/drm/radeon/kv_dpm.c

1727

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/drm/radeon/kv_dpm.c

1728

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/drm/radeon/kv_dpm.c

1734

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

1738

if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||

sys/dev/drm/radeon/kv_dpm.c

1746

if (table->entries[i].sclk_frequency <=

sys/dev/drm/radeon/kv_dpm.c

1754

table->entries[pi->highest_valid].sclk_frequency) >

sys/dev/drm/radeon/kv_dpm.c

1755

(table->entries[pi->lowest_valid].sclk_frequency -

sys/dev/drm/radeon/kv_dpm.c

1964

struct radeon_clock_and_voltage_limits *table)

sys/dev/drm/radeon/kv_dpm.c

1970

table->sclk =

sys/dev/drm/radeon/kv_dpm.c

1972

table->vddc =

sys/dev/drm/radeon/kv_dpm.c

1977

table->mclk = pi->sys_info.nbp_memory_clock[0];

sys/dev/drm/radeon/kv_dpm.c

2103

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

2107

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

2108

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

2110

(kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=

sys/dev/drm/radeon/kv_dpm.c

2117

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

2120

for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

2122

(kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=

sys/dev/drm/radeon/kv_dpm.c

2144

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

2164

for (i = table->count - 1; i >= 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

2165

if (stable_p_state_sclk >= table->entries[i].clk) {

sys/dev/drm/radeon/kv_dpm.c

2166

stable_p_state_sclk = table->entries[i].clk;

sys/dev/drm/radeon/kv_dpm.c

2172

stable_p_state_sclk = table->entries[0].clk;

sys/dev/drm/radeon/kv_dpm.c

2189

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

2195

ps->levels[i].sclk = table->entries[limit].clk;

sys/dev/drm/radeon/kv_dpm.c

2199

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

2207

ps->levels[i].sclk = table->entries[limit].sclk_frequency;

sys/dev/drm/radeon/kv_dpm.c

2348

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

2351

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

2355

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

2358

kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))

sys/dev/drm/radeon/kv_dpm.c

2361

kv_set_divider_value(rdev, i, table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

2364

table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

2371

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

2375

for (i = 0; i < table->num_max_dpm_entries; i++) {

sys/dev/drm/radeon/kv_dpm.c

2378

kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))

sys/dev/drm/radeon/kv_dpm.c

2381

kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);

sys/dev/drm/radeon/kv_dpm.c

2382

kv_set_vid(rdev, i, table->entries[i].vid_2bit);

sys/dev/drm/radeon/kv_dpm.c

715

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

718

if (table && table->count) {

sys/dev/drm/radeon/kv_dpm.c

720

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/drm/radeon/kv_dpm.c

727

struct sumo_sclk_voltage_mapping_table *table =

sys/dev/drm/radeon/kv_dpm.c

730

if (table->num_max_dpm_entries == 0)

sys/dev/drm/radeon/kv_dpm.c

734

if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)

sys/dev/drm/radeon/kv_dpm.c

817

struct radeon_uvd_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

823

if (table == NULL || table->count == 0)

sys/dev/drm/radeon/kv_dpm.c

827

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

829

(pi->high_voltage_t < table->entries[i].v))

sys/dev/drm/radeon/kv_dpm.c

832

pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);

sys/dev/drm/radeon/kv_dpm.c

833

pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);

sys/dev/drm/radeon/kv_dpm.c

834

pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

837

(u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);

sys/dev/drm/radeon/kv_dpm.c

839

(u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);

sys/dev/drm/radeon/kv_dpm.c

842

table->entries[i].vclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

848

table->entries[i].dclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

890

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

894

if (table == NULL || table->count == 0)

sys/dev/drm/radeon/kv_dpm.c

898

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

900

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/radeon/kv_dpm.c

903

pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);

sys/dev/drm/radeon/kv_dpm.c

904

pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

907

(u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);

sys/dev/drm/radeon/kv_dpm.c

910

table->entries[i].evclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

951

struct radeon_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/kv_dpm.c

957

if (table == NULL || table->count == 0)

sys/dev/drm/radeon/kv_dpm.c

961

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/kv_dpm.c

963

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/radeon/kv_dpm.c

966

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

967

pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

970

(u8)kv_get_clk_bypass(rdev, table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

973

table->entries[i].clk, false, &dividers);

sys/dev/drm/radeon/ni_dpm.c

1000

table->entries[i].v = pi->max_vddc;

sys/dev/drm/radeon/ni_dpm.c

1259

NISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/ni_dpm.c

1264

table->highSMIO[i] = 0;

sys/dev/drm/radeon/ni_dpm.c

1265

table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);

sys/dev/drm/radeon/ni_dpm.c

1270

NISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/ni_dpm.c

1277

ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);

sys/dev/drm/radeon/ni_dpm.c

1278

table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;

sys/dev/drm/radeon/ni_dpm.c

1279

table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =

sys/dev/drm/radeon/ni_dpm.c

1284

table->maxVDDCIndexInPPTable = i;

sys/dev/drm/radeon/ni_dpm.c

1291

ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);

sys/dev/drm/radeon/ni_dpm.c

1293

table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;

sys/dev/drm/radeon/ni_dpm.c

1294

table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =

sys/dev/drm/radeon/ni_dpm.c

1300

struct atom_voltage_table *table,

sys/dev/drm/radeon/ni_dpm.c

1306

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/ni_dpm.c

1307

if (value <= table->entries[i].value) {

sys/dev/drm/radeon/ni_dpm.c

1309

voltage->value = cpu_to_be16(table->entries[i].value);

sys/dev/drm/radeon/ni_dpm.c

1314

if (i >= table->count)

sys/dev/drm/radeon/ni_dpm.c

1681

NISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/ni_dpm.c

1690

table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/ni_dpm.c

1692

table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =

sys/dev/drm/radeon/ni_dpm.c

1694

table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/ni_dpm.c

1696

table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =

sys/dev/drm/radeon/ni_dpm.c

1698

table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/ni_dpm.c

1700

table->initialState.levels[0].mclk.vDLL_CNTL =

sys/dev/drm/radeon/ni_dpm.c

1702

table->initialState.levels[0].mclk.vMPLL_SS =

sys/dev/drm/radeon/ni_dpm.c

1704

table->initialState.levels[0].mclk.vMPLL_SS2 =

sys/dev/drm/radeon/ni_dpm.c

1706

table->initialState.levels[0].mclk.mclk_value =

sys/dev/drm/radeon/ni_dpm.c

1709

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/ni_dpm.c

1711

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/ni_dpm.c

1713

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/ni_dpm.c

1715

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =

sys/dev/drm/radeon/ni_dpm.c

1717

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/radeon/ni_dpm.c

1719

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/radeon/ni_dpm.c

1721

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/radeon/ni_dpm.c

1723

table->initialState.levels[0].arbRefreshState =

sys/dev/drm/radeon/ni_dpm.c

1726

table->initialState.levels[0].ACIndex = 0;

sys/dev/drm/radeon/ni_dpm.c

1730

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/ni_dpm.c

1735

&table->initialState.levels[0].vddc,

sys/dev/drm/radeon/ni_dpm.c

1739

table->initialState.levels[0].vddc.index,

sys/dev/drm/radeon/ni_dpm.c

1740

&table->initialState.levels[0].std_vddc);

sys/dev/drm/radeon/ni_dpm.c

1747

&table->initialState.levels[0].vddci);

sys/dev/drm/radeon/ni_dpm.c

1749

ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);

sys/dev/drm/radeon/ni_dpm.c

1752

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1754

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/ni_dpm.c

1757

table->initialState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/ni_dpm.c

1759

table->initialState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/ni_dpm.c

1762

table->initialState.levels[0].strobeMode =

sys/dev/drm/radeon/ni_dpm.c

1767

table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;

sys/dev/drm/radeon/ni_dpm.c

1769

table->initialState.levels[0].mcFlags = 0;

sys/dev/drm/radeon/ni_dpm.c

1772

table->initialState.levelCount = 1;

sys/dev/drm/radeon/ni_dpm.c

1774

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/ni_dpm.c

1776

table->initialState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/radeon/ni_dpm.c

1777

table->initialState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/radeon/ni_dpm.c

1778

table->initialState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/radeon/ni_dpm.c

1779

table->initialState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/radeon/ni_dpm.c

1782

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1785

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1791

NISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/ni_dpm.c

1809

table->ACPIState = table->initialState;

sys/dev/drm/radeon/ni_dpm.c

1811

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/ni_dpm.c

1816

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/ni_dpm.c

1821

&table->ACPIState.levels[0].vddc, &std_vddc);

sys/dev/drm/radeon/ni_dpm.c

1824

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/radeon/ni_dpm.c

1825

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/radeon/ni_dpm.c

1830

table->ACPIState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/ni_dpm.c

1832

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/ni_dpm.c

1834

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/ni_dpm.c

1840

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/ni_dpm.c

1845

&table->ACPIState.levels[0].vddc,

sys/dev/drm/radeon/ni_dpm.c

1849

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/radeon/ni_dpm.c

1850

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/radeon/ni_dpm.c

1852

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/ni_dpm.c

1860

&table->ACPIState.levels[0].vddci);

sys/dev/drm/radeon/ni_dpm.c

1903

table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);

sys/dev/drm/radeon/ni_dpm.c

1904

table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);

sys/dev/drm/radeon/ni_dpm.c

1905

table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);

sys/dev/drm/radeon/ni_dpm.c

1906

table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);

sys/dev/drm/radeon/ni_dpm.c

1907

table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/radeon/ni_dpm.c

1908

table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/ni_dpm.c

1910

table->ACPIState.levels[0].mclk.mclk_value = 0;

sys/dev/drm/radeon/ni_dpm.c

1912

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);

sys/dev/drm/radeon/ni_dpm.c

1913

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);

sys/dev/drm/radeon/ni_dpm.c

1914

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);

sys/dev/drm/radeon/ni_dpm.c

1915

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);

sys/dev/drm/radeon/ni_dpm.c

1917

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/ni_dpm.c

1919

ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/ni_dpm.c

1922

table->ACPIState.levels[0].ACIndex = 1;

sys/dev/drm/radeon/ni_dpm.c

1924

table->ACPIState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/radeon/ni_dpm.c

1925

table->ACPIState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/radeon/ni_dpm.c

1926

table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/radeon/ni_dpm.c

1927

table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/radeon/ni_dpm.c

1930

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1933

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1944

NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;

sys/dev/drm/radeon/ni_dpm.c

1946

memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE));

sys/dev/drm/radeon/ni_dpm.c

1948

ni_populate_smc_voltage_tables(rdev, table);

sys/dev/drm/radeon/ni_dpm.c

1953

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/radeon/ni_dpm.c

1956

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/radeon/ni_dpm.c

1959

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/radeon/ni_dpm.c

1964

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/ni_dpm.c

1967

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

sys/dev/drm/radeon/ni_dpm.c

1970

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/ni_dpm.c

1973

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/ni_dpm.c

1975

ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/ni_dpm.c

1979

ret = ni_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/ni_dpm.c

1983

table->driverState = table->initialState;

sys/dev/drm/radeon/ni_dpm.c

1985

table->ULVState = table->initialState;

sys/dev/drm/radeon/ni_dpm.c

1992

return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,

sys/dev/drm/radeon/ni_dpm.c

2712

struct ni_mc_reg_table *table)

sys/dev/drm/radeon/ni_dpm.c

2718

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/radeon/ni_dpm.c

2719

switch (table->mc_reg_address[i].s1) {

sys/dev/drm/radeon/ni_dpm.c

2724

table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;

sys/dev/drm/radeon/ni_dpm.c

2725

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;

sys/dev/drm/radeon/ni_dpm.c

2726

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/radeon/ni_dpm.c

2727

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ni_dpm.c

2729

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/radeon/ni_dpm.c

2735

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;

sys/dev/drm/radeon/ni_dpm.c

2736

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;

sys/dev/drm/radeon/ni_dpm.c

2737

for(k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/ni_dpm.c

2738

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ni_dpm.c

2740

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/ni_dpm.c

2742

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/radeon/ni_dpm.c

2750

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;

sys/dev/drm/radeon/ni_dpm.c

2751

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;

sys/dev/drm/radeon/ni_dpm.c

2752

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/radeon/ni_dpm.c

2753

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/ni_dpm.c

2755

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/ni_dpm.c

2763

table->last = j;

sys/dev/drm/radeon/ni_dpm.c

2820

static void ni_set_valid_flag(struct ni_mc_reg_table *table)

sys/dev/drm/radeon/ni_dpm.c

2824

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/ni_dpm.c

2825

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/radeon/ni_dpm.c

2826

if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/radeon/ni_dpm.c

2827

table->valid_flag |= 1 << i;

sys/dev/drm/radeon/ni_dpm.c

2834

static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table)

sys/dev/drm/radeon/ni_dpm.c

2839

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/ni_dpm.c

2840

table->mc_reg_address[i].s0 =

sys/dev/drm/radeon/ni_dpm.c

2841

ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/radeon/ni_dpm.c

2842

address : table->mc_reg_address[i].s1;

sys/dev/drm/radeon/ni_dpm.c

2845

static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,

sys/dev/drm/radeon/ni_dpm.c

2850

if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ni_dpm.c

2852

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/radeon/ni_dpm.c

2855

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/ni_dpm.c

2856

ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/radeon/ni_dpm.c

2857

ni_table->last = table->last;

sys/dev/drm/radeon/ni_dpm.c

2859

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/radeon/ni_dpm.c

2861

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/radeon/ni_dpm.c

2862

for (j = 0; j < table->last; j++)

sys/dev/drm/radeon/ni_dpm.c

2864

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/radeon/ni_dpm.c

2866

ni_table->num_entries = table->num_entries;

sys/dev/drm/radeon/ni_dpm.c

2875

struct atom_mc_reg_table *table;

sys/dev/drm/radeon/ni_dpm.c

2879

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/radeon/ni_dpm.c

2880

if (!table)

sys/dev/drm/radeon/ni_dpm.c

2897

ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);

sys/dev/drm/radeon/ni_dpm.c

2902

ret = ni_copy_vbios_mc_reg_table(table, ni_table);

sys/dev/drm/radeon/ni_dpm.c

2917

kfree(table);

sys/dev/drm/radeon/ni_dpm.c

990

struct radeon_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/ni_dpm.c

995

if (table) {

sys/dev/drm/radeon/ni_dpm.c

996

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/ni_dpm.c

997

if (0xff01 == table->entries[i].v) {

sys/dev/drm/radeon/radeon_combios.c

125

enum radeon_combios_table_offset table)

sys/dev/drm/radeon/radeon_combios.c

134

switch (table) {

sys/dev/drm/radeon/radeon_combios.c

3318

uint16_t table;

sys/dev/drm/radeon/radeon_combios.c

3325

table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);

sys/dev/drm/radeon/radeon_combios.c

3326

if (table)

sys/dev/drm/radeon/radeon_combios.c

3327

combios_parse_mmio_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3330

table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);

sys/dev/drm/radeon/radeon_combios.c

3331

if (table)

sys/dev/drm/radeon/radeon_combios.c

3332

combios_parse_pll_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3335

table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);

sys/dev/drm/radeon/radeon_combios.c

3336

if (table)

sys/dev/drm/radeon/radeon_combios.c

3337

combios_parse_mmio_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3341

table =

sys/dev/drm/radeon/radeon_combios.c

3343

if (table)

sys/dev/drm/radeon/radeon_combios.c

3344

combios_parse_mmio_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3347

table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);

sys/dev/drm/radeon/radeon_combios.c

3348

if (table)

sys/dev/drm/radeon/radeon_combios.c

3349

combios_parse_ram_reset_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3352

table =

sys/dev/drm/radeon/radeon_combios.c

3354

if (table)

sys/dev/drm/radeon/radeon_combios.c

3355

combios_parse_mmio_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

3408

table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);

sys/dev/drm/radeon/radeon_combios.c

3409

if (table)

sys/dev/drm/radeon/radeon_combios.c

3410

combios_parse_pll_table(dev, table);

sys/dev/drm/radeon/radeon_combios.c

358

if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)

sys/dev/drm/radeon/rv730_dpm.c

230

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv730_dpm.c

242

table->ACPIState = table->initialState;

sys/dev/drm/radeon/rv730_dpm.c

243

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/rv730_dpm.c

247

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv730_dpm.c

248

table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?

sys/dev/drm/radeon/rv730_dpm.c

250

table->ACPIState.levels[0].gen2XSP =

sys/dev/drm/radeon/rv730_dpm.c

254

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv730_dpm.c

255

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv730_dpm.c

297

table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);

sys/dev/drm/radeon/rv730_dpm.c

298

table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);

sys/dev/drm/radeon/rv730_dpm.c

299

table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);

sys/dev/drm/radeon/rv730_dpm.c

300

table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/radeon/rv730_dpm.c

301

table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/rv730_dpm.c

303

table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;

sys/dev/drm/radeon/rv730_dpm.c

305

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);

sys/dev/drm/radeon/rv730_dpm.c

306

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);

sys/dev/drm/radeon/rv730_dpm.c

307

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);

sys/dev/drm/radeon/rv730_dpm.c

309

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/rv730_dpm.c

311

rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/rv730_dpm.c

313

table->ACPIState.levels[1] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv730_dpm.c

314

table->ACPIState.levels[2] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv730_dpm.c

321

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv730_dpm.c

327

table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =

sys/dev/drm/radeon/rv730_dpm.c

329

table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =

sys/dev/drm/radeon/rv730_dpm.c

331

table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =

sys/dev/drm/radeon/rv730_dpm.c

333

table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/rv730_dpm.c

335

table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =

sys/dev/drm/radeon/rv730_dpm.c

337

table->initialState.levels[0].mclk.mclk730.vMPLL_SS =

sys/dev/drm/radeon/rv730_dpm.c

339

table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =

sys/dev/drm/radeon/rv730_dpm.c

342

table->initialState.levels[0].mclk.mclk730.mclk_value =

sys/dev/drm/radeon/rv730_dpm.c

345

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/rv730_dpm.c

347

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/rv730_dpm.c

349

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/rv730_dpm.c

351

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/radeon/rv730_dpm.c

353

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/radeon/rv730_dpm.c

356

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/radeon/rv730_dpm.c

359

table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;

sys/dev/drm/radeon/rv730_dpm.c

361

table->initialState.levels[0].seqValue =

sys/dev/drm/radeon/rv730_dpm.c

366

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/rv730_dpm.c

368

&table->initialState.levels[0].mvdd);

sys/dev/drm/radeon/rv730_dpm.c

372

table->initialState.levels[0].aT = cpu_to_be32(a_t);

sys/dev/drm/radeon/rv730_dpm.c

374

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/rv730_dpm.c

377

table->initialState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/rv730_dpm.c

379

table->initialState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv730_dpm.c

381

table->initialState.levels[0].gen2XSP = 1;

sys/dev/drm/radeon/rv730_dpm.c

383

table->initialState.levels[0].gen2XSP = 0;

sys/dev/drm/radeon/rv730_dpm.c

385

table->initialState.levels[1] = table->initialState.levels[0];

sys/dev/drm/radeon/rv730_dpm.c

386

table->initialState.levels[2] = table->initialState.levels[0];

sys/dev/drm/radeon/rv730_dpm.c

388

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/rv740_dpm.c

320

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv740_dpm.c

333

table->ACPIState = table->initialState;

sys/dev/drm/radeon/rv740_dpm.c

335

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/rv740_dpm.c

339

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv740_dpm.c

340

table->ACPIState.levels[0].gen2PCIE =

sys/dev/drm/radeon/rv740_dpm.c

343

table->ACPIState.levels[0].gen2XSP =

sys/dev/drm/radeon/rv740_dpm.c

347

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv740_dpm.c

348

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv740_dpm.c

378

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);

sys/dev/drm/radeon/rv740_dpm.c

379

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);

sys/dev/drm/radeon/rv740_dpm.c

380

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);

sys/dev/drm/radeon/rv740_dpm.c

381

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);

sys/dev/drm/radeon/rv740_dpm.c

382

table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/radeon/rv740_dpm.c

383

table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/rv740_dpm.c

385

table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;

sys/dev/drm/radeon/rv740_dpm.c

387

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);

sys/dev/drm/radeon/rv740_dpm.c

388

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);

sys/dev/drm/radeon/rv740_dpm.c

389

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);

sys/dev/drm/radeon/rv740_dpm.c

391

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/rv740_dpm.c

393

table->ACPIState.levels[1] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv740_dpm.c

394

table->ACPIState.levels[2] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv740_dpm.c

396

rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/rv770_dpm.c

1000

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/rv770_dpm.c

1002

rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/rv770_dpm.c

1004

table->ACPIState.levels[1] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv770_dpm.c

1005

table->ACPIState.levels[2] = table->ACPIState.levels[0];

sys/dev/drm/radeon/rv770_dpm.c

1029

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv770_dpm.c

1035

table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/rv770_dpm.c

1037

table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =

sys/dev/drm/radeon/rv770_dpm.c

1039

table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/rv770_dpm.c

1041

table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =

sys/dev/drm/radeon/rv770_dpm.c

1043

table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/rv770_dpm.c

1045

table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =

sys/dev/drm/radeon/rv770_dpm.c

1048

table->initialState.levels[0].mclk.mclk770.vMPLL_SS =

sys/dev/drm/radeon/rv770_dpm.c

1050

table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =

sys/dev/drm/radeon/rv770_dpm.c

1053

table->initialState.levels[0].mclk.mclk770.mclk_value =

sys/dev/drm/radeon/rv770_dpm.c

1056

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/rv770_dpm.c

1058

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/rv770_dpm.c

1060

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/rv770_dpm.c

1062

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/radeon/rv770_dpm.c

1064

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/radeon/rv770_dpm.c

1067

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/radeon/rv770_dpm.c

1070

table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;

sys/dev/drm/radeon/rv770_dpm.c

1072

table->initialState.levels[0].seqValue =

sys/dev/drm/radeon/rv770_dpm.c

1077

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/rv770_dpm.c

1079

&table->initialState.levels[0].mvdd);

sys/dev/drm/radeon/rv770_dpm.c

1082

table->initialState.levels[0].aT = cpu_to_be32(a_t);

sys/dev/drm/radeon/rv770_dpm.c

1084

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/rv770_dpm.c

1087

table->initialState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/rv770_dpm.c

1089

table->initialState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv770_dpm.c

1091

table->initialState.levels[0].gen2XSP = 1;

sys/dev/drm/radeon/rv770_dpm.c

1093

table->initialState.levels[0].gen2XSP = 0;

sys/dev/drm/radeon/rv770_dpm.c

1098

table->initialState.levels[0].strobeMode =

sys/dev/drm/radeon/rv770_dpm.c

1101

table->initialState.levels[0].strobeMode = 0;

sys/dev/drm/radeon/rv770_dpm.c

1104

table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;

sys/dev/drm/radeon/rv770_dpm.c

1106

table->initialState.levels[0].mcFlags = 0;

sys/dev/drm/radeon/rv770_dpm.c

1110

table->initialState.levels[1] = table->initialState.levels[0];

sys/dev/drm/radeon/rv770_dpm.c

1111

table->initialState.levels[2] = table->initialState.levels[0];

sys/dev/drm/radeon/rv770_dpm.c

1113

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/rv770_dpm.c

1119

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv770_dpm.c

1125

table->highSMIO[pi->vddc_table[i].vddc_index] =

sys/dev/drm/radeon/rv770_dpm.c

1127

table->lowSMIO[pi->vddc_table[i].vddc_index] =

sys/dev/drm/radeon/rv770_dpm.c

1131

table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;

sys/dev/drm/radeon/rv770_dpm.c

1132

table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =

sys/dev/drm/radeon/rv770_dpm.c

1141

table->maxVDDCIndexInPPTable =

sys/dev/drm/radeon/rv770_dpm.c

1148

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv770_dpm.c

1153

table->lowSMIO[MVDD_HIGH_INDEX] |=

sys/dev/drm/radeon/rv770_dpm.c

1155

table->lowSMIO[MVDD_LOW_INDEX] |=

sys/dev/drm/radeon/rv770_dpm.c

1158

table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_MVDD] = 0;

sys/dev/drm/radeon/rv770_dpm.c

1159

table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_MVDD] =

sys/dev/drm/radeon/rv770_dpm.c

1171

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/rv770_dpm.c

1174

memset(table, 0, sizeof(RV770_SMC_STATETABLE));

sys/dev/drm/radeon/rv770_dpm.c

1178

rv770_populate_smc_vddc_table(rdev, table);

sys/dev/drm/radeon/rv770_dpm.c

1179

rv770_populate_smc_mvdd_table(rdev, table);

sys/dev/drm/radeon/rv770_dpm.c

1184

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/radeon/rv770_dpm.c

1187

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/radeon/rv770_dpm.c

1191

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/radeon/rv770_dpm.c

1196

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/rv770_dpm.c

1199

table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK;

sys/dev/drm/radeon/rv770_dpm.c

1202

table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE;

sys/dev/drm/radeon/rv770_dpm.c

1206

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/rv770_dpm.c

1209

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/rv770_dpm.c

1212

ret = rv730_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/rv770_dpm.c

1214

ret = rv770_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/rv770_dpm.c

1219

ret = rv740_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/rv770_dpm.c

1221

ret = rv730_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/rv770_dpm.c

1223

ret = rv770_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/rv770_dpm.c

1227

table->driverState = table->initialState;

sys/dev/drm/radeon/rv770_dpm.c

1231

(const u8 *)table,

sys/dev/drm/radeon/rv770_dpm.c

920

RV770_SMC_STATETABLE *table)

sys/dev/drm/radeon/rv770_dpm.c

941

table->ACPIState = table->initialState;

sys/dev/drm/radeon/rv770_dpm.c

943

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/rv770_dpm.c

947

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv770_dpm.c

950

table->ACPIState.levels[0].gen2PCIE = 1;

sys/dev/drm/radeon/rv770_dpm.c

952

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv770_dpm.c

954

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv770_dpm.c

956

table->ACPIState.levels[0].gen2XSP = 1;

sys/dev/drm/radeon/rv770_dpm.c

958

table->ACPIState.levels[0].gen2XSP = 0;

sys/dev/drm/radeon/rv770_dpm.c

961

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/rv770_dpm.c

962

table->ACPIState.levels[0].gen2PCIE = 0;

sys/dev/drm/radeon/rv770_dpm.c

986

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

987

table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

988

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

989

table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

991

table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);

sys/dev/drm/radeon/rv770_dpm.c

992

table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);

sys/dev/drm/radeon/rv770_dpm.c

994

table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;

sys/dev/drm/radeon/rv770_dpm.c

996

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

997

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

998

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);

sys/dev/drm/radeon/rv770_dpm.h

187

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/rv770_dpm.h

190

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/rv770_dpm.h

208

RV770_SMC_STATETABLE *table);

sys/dev/drm/radeon/si_dpm.c

1747

const struct atom_voltage_table *table,

sys/dev/drm/radeon/si_dpm.c

2537

struct radeon_cac_leakage_table *table =

sys/dev/drm/radeon/si_dpm.c

2543

if (table == NULL)

sys/dev/drm/radeon/si_dpm.c

2549

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/si_dpm.c

2550

if (table->entries[i].vddc > *max)

sys/dev/drm/radeon/si_dpm.c

2551

*max = table->entries[i].vddc;

sys/dev/drm/radeon/si_dpm.c

2552

if (table->entries[i].vddc < *min)

sys/dev/drm/radeon/si_dpm.c

2553

*min = table->entries[i].vddc;

sys/dev/drm/radeon/si_dpm.c

2940

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/si_dpm.c

2944

(table && (table->count == 0))) {

sys/dev/drm/radeon/si_dpm.c

2949

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/si_dpm.c

2950

if ((evclk <= table->entries[i].evclk) &&

sys/dev/drm/radeon/si_dpm.c

2951

(ecclk <= table->entries[i].ecclk)) {

sys/dev/drm/radeon/si_dpm.c

2952

*voltage = table->entries[i].v;

sys/dev/drm/radeon/si_dpm.c

2960

*voltage = table->entries[table->count - 1].v;

sys/dev/drm/radeon/si_dpm.c

3896

const struct atom_voltage_table *table,

sys/dev/drm/radeon/si_dpm.c

3901

if ((table == NULL) || (limits == NULL))

sys/dev/drm/radeon/si_dpm.c

3904

data = table->mask_low;

sys/dev/drm/radeon/si_dpm.c

3913

if (table->count != num_levels)

sys/dev/drm/radeon/si_dpm.c

4042

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/si_dpm.c

4047

table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);

sys/dev/drm/radeon/si_dpm.c

4051

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/si_dpm.c

4067

si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);

sys/dev/drm/radeon/si_dpm.c

4068

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =

sys/dev/drm/radeon/si_dpm.c

4073

table->maxVDDCIndexInPPTable = i;

sys/dev/drm/radeon/si_dpm.c

4080

si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);

sys/dev/drm/radeon/si_dpm.c

4082

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =

sys/dev/drm/radeon/si_dpm.c

4088

si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);

sys/dev/drm/radeon/si_dpm.c

4090

table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =

sys/dev/drm/radeon/si_dpm.c

4097

si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);

sys/dev/drm/radeon/si_dpm.c

4099

table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =

sys/dev/drm/radeon/si_dpm.c

4114

const struct atom_voltage_table *table,

sys/dev/drm/radeon/si_dpm.c

4119

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/si_dpm.c

4120

if (value <= table->entries[i].value) {

sys/dev/drm/radeon/si_dpm.c

4122

voltage->value = cpu_to_be16(table->entries[i].value);

sys/dev/drm/radeon/si_dpm.c

4127

if (i >= table->count)

sys/dev/drm/radeon/si_dpm.c

4370

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/si_dpm.c

4379

table->initialState.levels[0].mclk.vDLL_CNTL =

sys/dev/drm/radeon/si_dpm.c

4381

table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/si_dpm.c

4383

table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4385

table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4387

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4389

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =

sys/dev/drm/radeon/si_dpm.c

4391

table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/si_dpm.c

4393

table->initialState.levels[0].mclk.vMPLL_SS =

sys/dev/drm/radeon/si_dpm.c

4395

table->initialState.levels[0].mclk.vMPLL_SS2 =

sys/dev/drm/radeon/si_dpm.c

4398

table->initialState.levels[0].mclk.mclk_value =

sys/dev/drm/radeon/si_dpm.c

4401

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4403

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/si_dpm.c

4405

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/si_dpm.c

4407

table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =

sys/dev/drm/radeon/si_dpm.c

4409

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =

sys/dev/drm/radeon/si_dpm.c

4411

table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =

sys/dev/drm/radeon/si_dpm.c

4414

table->initialState.levels[0].sclk.sclk_value =

sys/dev/drm/radeon/si_dpm.c

4417

table->initialState.levels[0].arbRefreshState =

sys/dev/drm/radeon/si_dpm.c

4420

table->initialState.levels[0].ACIndex = 0;

sys/dev/drm/radeon/si_dpm.c

4424

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4430

&table->initialState.levels[0].vddc,

sys/dev/drm/radeon/si_dpm.c

4434

table->initialState.levels[0].vddc.index,

sys/dev/drm/radeon/si_dpm.c

4435

&table->initialState.levels[0].std_vddc);

sys/dev/drm/radeon/si_dpm.c

4442

&table->initialState.levels[0].vddci);

sys/dev/drm/radeon/si_dpm.c

4450

&table->initialState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4452

si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);

sys/dev/drm/radeon/si_dpm.c

4455

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4457

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/si_dpm.c

4459

table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/drm/radeon/si_dpm.c

4462

table->initialState.levels[0].strobeMode =

sys/dev/drm/radeon/si_dpm.c

4467

table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;

sys/dev/drm/radeon/si_dpm.c

4469

table->initialState.levels[0].mcFlags = 0;

sys/dev/drm/radeon/si_dpm.c

4472

table->initialState.levelCount = 1;

sys/dev/drm/radeon/si_dpm.c

4474

table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/si_dpm.c

4476

table->initialState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/radeon/si_dpm.c

4477

table->initialState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/radeon/si_dpm.c

4478

table->initialState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/radeon/si_dpm.c

4479

table->initialState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/radeon/si_dpm.c

4480

table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;

sys/dev/drm/radeon/si_dpm.c

4483

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4486

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4492

SISLANDS_SMC_STATETABLE *table)

sys/dev/drm/radeon/si_dpm.c

4511

table->ACPIState = table->initialState;

sys/dev/drm/radeon/si_dpm.c

4513

table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

sys/dev/drm/radeon/si_dpm.c

4517

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4522

&table->ACPIState.levels[0].vddc, &std_vddc);

sys/dev/drm/radeon/si_dpm.c

4525

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/radeon/si_dpm.c

4526

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/radeon/si_dpm.c

4528

table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;

sys/dev/drm/radeon/si_dpm.c

4536

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4540

pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4545

&table->ACPIState.levels[0].vddc, &std_vddc);

sys/dev/drm/radeon/si_dpm.c

4549

table->ACPIState.levels[0].vddc.index,

sys/dev/drm/radeon/si_dpm.c

4550

&table->ACPIState.levels[0].std_vddc);

sys/dev/drm/radeon/si_dpm.c

4552

table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,

sys/dev/drm/radeon/si_dpm.c

4563

&table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4570

&table->ACPIState.levels[0].vddci);

sys/dev/drm/radeon/si_dpm.c

4581

table->ACPIState.levels[0].mclk.vDLL_CNTL =

sys/dev/drm/radeon/si_dpm.c

4583

table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =

sys/dev/drm/radeon/si_dpm.c

4585

table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4587

table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4589

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4591

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =

sys/dev/drm/radeon/si_dpm.c

4593

table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/si_dpm.c

4595

table->ACPIState.levels[0].mclk.vMPLL_SS =

sys/dev/drm/radeon/si_dpm.c

4597

table->ACPIState.levels[0].mclk.vMPLL_SS2 =

sys/dev/drm/radeon/si_dpm.c

4600

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =

sys/dev/drm/radeon/si_dpm.c

4602

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =

sys/dev/drm/radeon/si_dpm.c

4604

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =

sys/dev/drm/radeon/si_dpm.c

4606

table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =

sys/dev/drm/radeon/si_dpm.c

4609

table->ACPIState.levels[0].mclk.mclk_value = 0;

sys/dev/drm/radeon/si_dpm.c

4610

table->ACPIState.levels[0].sclk.sclk_value = 0;

sys/dev/drm/radeon/si_dpm.c

4612

si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);

sys/dev/drm/radeon/si_dpm.c

4615

table->ACPIState.levels[0].ACIndex = 0;

sys/dev/drm/radeon/si_dpm.c

4617

table->ACPIState.levels[0].dpm2.MaxPS = 0;

sys/dev/drm/radeon/si_dpm.c

4618

table->ACPIState.levels[0].dpm2.NearTDPDec = 0;

sys/dev/drm/radeon/si_dpm.c

4619

table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;

sys/dev/drm/radeon/si_dpm.c

4620

table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;

sys/dev/drm/radeon/si_dpm.c

4621

table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;

sys/dev/drm/radeon/si_dpm.c

4624

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4627

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4702

SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;

sys/dev/drm/radeon/si_dpm.c

4707

si_populate_smc_voltage_tables(rdev, table);

sys/dev/drm/radeon/si_dpm.c

4712

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;

sys/dev/drm/radeon/si_dpm.c

4715

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;

sys/dev/drm/radeon/si_dpm.c

4718

table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;

sys/dev/drm/radeon/si_dpm.c

4723

table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

sys/dev/drm/radeon/si_dpm.c

4727

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

sys/dev/drm/radeon/si_dpm.c

4731

table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

sys/dev/drm/radeon/si_dpm.c

4734

table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

sys/dev/drm/radeon/si_dpm.c

4737

table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;

sys/dev/drm/radeon/si_dpm.c

4740

table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;

sys/dev/drm/radeon/si_dpm.c

4746

ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);

sys/dev/drm/radeon/si_dpm.c

4750

ret = si_populate_smc_acpi_state(rdev, table);

sys/dev/drm/radeon/si_dpm.c

4754

table->driverState = table->initialState;

sys/dev/drm/radeon/si_dpm.c

4762

ret = si_populate_ulv_state(rdev, &table->ULVState);

sys/dev/drm/radeon/si_dpm.c

4776

table->ULVState = table->initialState;

sys/dev/drm/radeon/si_dpm.c

4780

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/drm/radeon/si_dpm.c

5359

struct si_mc_reg_table *table)

sys/dev/drm/radeon/si_dpm.c

5365

for (i = 0, j = table->last; i < table->last; i++) {

sys/dev/drm/radeon/si_dpm.c

5368

switch (table->mc_reg_address[i].s1 << 2) {

sys/dev/drm/radeon/si_dpm.c

5371

table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;

sys/dev/drm/radeon/si_dpm.c

5372

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;

sys/dev/drm/radeon/si_dpm.c

5373

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/radeon/si_dpm.c

5374

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/si_dpm.c

5376

((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);

sys/dev/drm/radeon/si_dpm.c

5382

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;

sys/dev/drm/radeon/si_dpm.c

5383

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;

sys/dev/drm/radeon/si_dpm.c

5384

for (k = 0; k < table->num_entries; k++) {

sys/dev/drm/radeon/si_dpm.c

5385

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/si_dpm.c

5387

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/si_dpm.c

5389

table->mc_reg_table_entry[k].mc_data[j] |= 0x100;

sys/dev/drm/radeon/si_dpm.c

5396

table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;

sys/dev/drm/radeon/si_dpm.c

5397

table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;

sys/dev/drm/radeon/si_dpm.c

5398

for (k = 0; k < table->num_entries; k++)

sys/dev/drm/radeon/si_dpm.c

5399

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/si_dpm.c

5400

(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;

sys/dev/drm/radeon/si_dpm.c

5408

table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;

sys/dev/drm/radeon/si_dpm.c

5409

table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;

sys/dev/drm/radeon/si_dpm.c

5410

for(k = 0; k < table->num_entries; k++)

sys/dev/drm/radeon/si_dpm.c

5411

table->mc_reg_table_entry[k].mc_data[j] =

sys/dev/drm/radeon/si_dpm.c

5413

(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);

sys/dev/drm/radeon/si_dpm.c

5423

table->last = j;

sys/dev/drm/radeon/si_dpm.c

5483

static void si_set_valid_flag(struct si_mc_reg_table *table)

sys/dev/drm/radeon/si_dpm.c

5487

for (i = 0; i < table->last; i++) {

sys/dev/drm/radeon/si_dpm.c

5488

for (j = 1; j < table->num_entries; j++) {

sys/dev/drm/radeon/si_dpm.c

5489

if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {

sys/dev/drm/radeon/si_dpm.c

5490

table->valid_flag |= 1 << i;

sys/dev/drm/radeon/si_dpm.c

5497

static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)

sys/dev/drm/radeon/si_dpm.c

5502

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/si_dpm.c

5503

table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?

sys/dev/drm/radeon/si_dpm.c

5504

address : table->mc_reg_address[i].s1;

sys/dev/drm/radeon/si_dpm.c

5508

static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,

sys/dev/drm/radeon/si_dpm.c

5513

if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/si_dpm.c

5515

if (table->num_entries > MAX_AC_TIMING_ENTRIES)

sys/dev/drm/radeon/si_dpm.c

5518

for (i = 0; i < table->last; i++)

sys/dev/drm/radeon/si_dpm.c

5519

si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;

sys/dev/drm/radeon/si_dpm.c

5520

si_table->last = table->last;

sys/dev/drm/radeon/si_dpm.c

5522

for (i = 0; i < table->num_entries; i++) {

sys/dev/drm/radeon/si_dpm.c

5524

table->mc_reg_table_entry[i].mclk_max;

sys/dev/drm/radeon/si_dpm.c

5525

for (j = 0; j < table->last; j++) {

sys/dev/drm/radeon/si_dpm.c

5527

table->mc_reg_table_entry[i].mc_data[j];

sys/dev/drm/radeon/si_dpm.c

5530

si_table->num_entries = table->num_entries;

sys/dev/drm/radeon/si_dpm.c

5538

struct atom_mc_reg_table *table;

sys/dev/drm/radeon/si_dpm.c

5543

table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);

sys/dev/drm/radeon/si_dpm.c

5544

if (!table)

sys/dev/drm/radeon/si_dpm.c

5562

ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);

sys/dev/drm/radeon/si_dpm.c

5566

ret = si_copy_vbios_mc_reg_table(table, si_table);

sys/dev/drm/radeon/si_dpm.c

5579

kfree(table);

sys/dev/drm/radeon/si_dpm.c

5871

struct radeon_clock_voltage_dependency_table *table)

sys/dev/drm/radeon/si_dpm.c

5877

if (table) {

sys/dev/drm/radeon/si_dpm.c

5878

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/si_dpm.c

5880

table->entries[i].v,

sys/dev/drm/radeon/si_dpm.c

5883

table->entries[i].v = leakage_voltage;

sys/dev/drm/radeon/si_dpm.c

5893

for (j = (table->count - 2); j >= 0; j--) {

sys/dev/drm/radeon/si_dpm.c

5894

table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?

sys/dev/drm/radeon/si_dpm.c

5895

table->entries[j].v : table->entries[j + 1].v;

sys/dev/drm/radeon/sumo_dpm.c

1574

ATOM_CLK_VOLT_CAPABILITY *table)

sys/dev/drm/radeon/sumo_dpm.c

1579

if (table[i].ulMaximumSupportedCLK == 0)

sys/dev/drm/radeon/sumo_dpm.c

1583

table[i].ulMaximumSupportedCLK;

sys/dev/drm/radeon/sumo_dpm.c

1596

ATOM_AVAILABLE_SCLK_LIST *table)

sys/dev/drm/radeon/sumo_dpm.c

1603

if (table[i].ulSupportedSCLK > prev_sclk) {

sys/dev/drm/radeon/sumo_dpm.c

1605

table[i].ulSupportedSCLK;

sys/dev/drm/radeon/sumo_dpm.c

1607

table[i].usVoltageIndex;

sys/dev/drm/radeon/sumo_dpm.c

1608

prev_sclk = table[i].ulSupportedSCLK;

sys/dev/drm/radeon/sumo_dpm.c

1618

ATOM_AVAILABLE_SCLK_LIST *table)

sys/dev/drm/radeon/sumo_dpm.c

1623

if (table[i].ulSupportedSCLK != 0) {

sys/dev/drm/radeon/sumo_dpm.c

1624

vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =

sys/dev/drm/radeon/sumo_dpm.c

1625

table[i].usVoltageID;

sys/dev/drm/radeon/sumo_dpm.c

1626

vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =

sys/dev/drm/radeon/sumo_dpm.c

1627

table[i].usVoltageIndex;

sys/dev/drm/radeon/sumo_dpm.h

198

ATOM_AVAILABLE_SCLK_LIST *table);

sys/dev/drm/radeon/sumo_dpm.h

201

ATOM_AVAILABLE_SCLK_LIST *table);

sys/dev/drm/radeon/trinity_dpm.c

1514

struct radeon_vce_clock_voltage_dependency_table *table =

sys/dev/drm/radeon/trinity_dpm.c

1518

(table && (table->count == 0))) {

sys/dev/drm/radeon/trinity_dpm.c

1523

for (i = 0; i < table->count; i++) {

sys/dev/drm/radeon/trinity_dpm.c

1524

if ((evclk <= table->entries[i].evclk) &&

sys/dev/drm/radeon/trinity_dpm.c

1525

(ecclk <= table->entries[i].ecclk)) {

sys/dev/drm/radeon/trinity_dpm.c

1526

*voltage = table->entries[i].v;

sys/dev/drm/radeon/trinity_dpm.c

1534

*voltage = table->entries[table->count - 1].v;

sys/dev/misc/ipmi/ipmi_smbios.c

180

void *table;

sys/dev/misc/ipmi/ipmi_smbios.c

197

table = pmap_mapbios(addr, header->length);

sys/dev/misc/ipmi/ipmi_smbios.c

199

header = table;

sys/dev/misc/ipmi/ipmi_smbios.c

206

table = pmap_mapbios(header->structure_table_address,

sys/dev/misc/ipmi/ipmi_smbios.c

208

smbios_walk_table(table, header->number_structures, smbios_ipmi_info,

sys/dev/misc/ipmi/ipmi_smbios.c

212

pmap_unmapbios((vm_offset_t)table, header->structure_table_length);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1877

bwn_ofdmtab_write_2(struct bwn_mac *mac, uint16_t table, uint16_t offset,

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1883

addr = table + offset;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1894

bwn_ofdmtab_write_4(struct bwn_mac *mac, uint16_t table, uint16_t offset,

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1900

addr = table + offset;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1913

bwn_gtab_write(struct bwn_mac *mac, uint16_t table, uint16_t offset,

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1917

BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, table + offset);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3075

uint16_t table;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3082

table = BWN_OFDMTAB_GAINX;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3084

table = BWN_OFDMTAB_GAINX_R1;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3086

bwn_ofdmtab_write_2(mac, table, i, first);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3089

bwn_ofdmtab_write_2(mac, table, i, second);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3105

uint16_t table;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3113

table = BWN_OFDMTAB_GAINX;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3115

table = BWN_OFDMTAB_GAINX_R1;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3121

bwn_ofdmtab_write_2(mac, table, i, tmp);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3125

bwn_ofdmtab_write_2(mac, table, i, i - start);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

3634

struct bwn_txgain_entry *table)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

3639

bwn_phy_lp_gaintbl_write(mac, i, table[i]);

sys/dev/netif/bwn/bwn/if_bwnreg.h

920

#define BWN_TAB_1(table, offset) \

sys/dev/netif/bwn/bwn/if_bwnreg.h

921

(((table) << 10) | (offset) | BWN_TAB_8BIT)

sys/dev/netif/bwn/bwn/if_bwnreg.h

922

#define BWN_TAB_2(table, offset) \

sys/dev/netif/bwn/bwn/if_bwnreg.h

923

(((table) << 10) | (offset) | BWN_TAB_16BIT)

sys/dev/netif/bwn/bwn/if_bwnreg.h

924

#define BWN_TAB_4(table, offset) \

sys/dev/netif/bwn/bwn/if_bwnreg.h

925

(((table) << 10) | (offset) | BWN_TAB_32BIT)

sys/dev/netif/de/if_de.c

1060

static const tulip_media_t table[] = {

sys/dev/netif/de/if_de.c

1110

return table[idx];

sys/dev/netif/iwm/if_iwm.c

5241

struct iwm_umac_error_event_table table;

sys/dev/netif/iwm/if_iwm.c

5252

if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/netif/iwm/if_iwm.c

5257

if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {

sys/dev/netif/iwm/if_iwm.c

5260

sc->sc_flags, table.valid);

sys/dev/netif/iwm/if_iwm.c

5263

device_printf(sc->sc_dev, "0x%08X | %s\n", table.error_id,

sys/dev/netif/iwm/if_iwm.c

5264

iwm_desc_lookup(table.error_id));

sys/dev/netif/iwm/if_iwm.c

5265

device_printf(sc->sc_dev, "0x%08X | umac branchlink1\n", table.blink1);

sys/dev/netif/iwm/if_iwm.c

5266

device_printf(sc->sc_dev, "0x%08X | umac branchlink2\n", table.blink2);

sys/dev/netif/iwm/if_iwm.c

5268

table.ilink1);

sys/dev/netif/iwm/if_iwm.c

5270

table.ilink2);

sys/dev/netif/iwm/if_iwm.c

5271

device_printf(sc->sc_dev, "0x%08X | umac data1\n", table.data1);

sys/dev/netif/iwm/if_iwm.c

5272

device_printf(sc->sc_dev, "0x%08X | umac data2\n", table.data2);

sys/dev/netif/iwm/if_iwm.c

5273

device_printf(sc->sc_dev, "0x%08X | umac data3\n", table.data3);

sys/dev/netif/iwm/if_iwm.c

5274

device_printf(sc->sc_dev, "0x%08X | umac major\n", table.umac_major);

sys/dev/netif/iwm/if_iwm.c

5275

device_printf(sc->sc_dev, "0x%08X | umac minor\n", table.umac_minor);

sys/dev/netif/iwm/if_iwm.c

5277

table.frame_pointer);

sys/dev/netif/iwm/if_iwm.c

5279

table.stack_pointer);

sys/dev/netif/iwm/if_iwm.c

5280

device_printf(sc->sc_dev, "0x%08X | last host cmd\n", table.cmd_header);

sys/dev/netif/iwm/if_iwm.c

5282

table.nic_isr_pref);

sys/dev/netif/iwm/if_iwm.c

5295

struct iwm_error_event_table table;

sys/dev/netif/iwm/if_iwm.c

5306

if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/netif/iwm/if_iwm.c

5311

if (!table.valid) {

sys/dev/netif/iwm/if_iwm.c

5316

if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {

sys/dev/netif/iwm/if_iwm.c

5319

sc->sc_flags, table.valid);

sys/dev/netif/iwm/if_iwm.c

5322

device_printf(sc->sc_dev, "0x%08X | %-28s\n", table.error_id,

sys/dev/netif/iwm/if_iwm.c

5323

iwm_desc_lookup(table.error_id));

sys/dev/netif/iwm/if_iwm.c

5325

table.trm_hw_status0);

sys/dev/netif/iwm/if_iwm.c

5327

table.trm_hw_status1);

sys/dev/netif/iwm/if_iwm.c

5328

device_printf(sc->sc_dev, "%08X | branchlink2\n", table.blink2);

sys/dev/netif/iwm/if_iwm.c

5329

device_printf(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1);

sys/dev/netif/iwm/if_iwm.c

5330

device_printf(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2);

sys/dev/netif/iwm/if_iwm.c

5331

device_printf(sc->sc_dev, "%08X | data1\n", table.data1);

sys/dev/netif/iwm/if_iwm.c

5332

device_printf(sc->sc_dev, "%08X | data2\n", table.data2);

sys/dev/netif/iwm/if_iwm.c

5333

device_printf(sc->sc_dev, "%08X | data3\n", table.data3);

sys/dev/netif/iwm/if_iwm.c

5334

device_printf(sc->sc_dev, "%08X | beacon time\n", table.bcon_time);

sys/dev/netif/iwm/if_iwm.c

5335

device_printf(sc->sc_dev, "%08X | tsf low\n", table.tsf_low);

sys/dev/netif/iwm/if_iwm.c

5336

device_printf(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi);

sys/dev/netif/iwm/if_iwm.c

5337

device_printf(sc->sc_dev, "%08X | time gp1\n", table.gp1);

sys/dev/netif/iwm/if_iwm.c

5338

device_printf(sc->sc_dev, "%08X | time gp2\n", table.gp2);

sys/dev/netif/iwm/if_iwm.c

5340

table.fw_rev_type);

sys/dev/netif/iwm/if_iwm.c

5341

device_printf(sc->sc_dev, "%08X | uCode version major\n", table.major);

sys/dev/netif/iwm/if_iwm.c

5342

device_printf(sc->sc_dev, "%08X | uCode version minor\n", table.minor);

sys/dev/netif/iwm/if_iwm.c

5343

device_printf(sc->sc_dev, "%08X | hw version\n", table.hw_ver);

sys/dev/netif/iwm/if_iwm.c

5344

device_printf(sc->sc_dev, "%08X | board version\n", table.brd_ver);

sys/dev/netif/iwm/if_iwm.c

5345

device_printf(sc->sc_dev, "%08X | hcmd\n", table.hcmd);

sys/dev/netif/iwm/if_iwm.c

5346

device_printf(sc->sc_dev, "%08X | isr0\n", table.isr0);

sys/dev/netif/iwm/if_iwm.c

5347

device_printf(sc->sc_dev, "%08X | isr1\n", table.isr1);

sys/dev/netif/iwm/if_iwm.c

5348

device_printf(sc->sc_dev, "%08X | isr2\n", table.isr2);

sys/dev/netif/iwm/if_iwm.c

5349

device_printf(sc->sc_dev, "%08X | isr3\n", table.isr3);

sys/dev/netif/iwm/if_iwm.c

5350

device_printf(sc->sc_dev, "%08X | isr4\n", table.isr4);

sys/dev/netif/iwm/if_iwm.c

5351

device_printf(sc->sc_dev, "%08X | last cmd Id\n", table.last_cmd_id);

sys/dev/netif/iwm/if_iwm.c

5352

device_printf(sc->sc_dev, "%08X | wait_event\n", table.wait_event);

sys/dev/netif/iwm/if_iwm.c

5353

device_printf(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control);

sys/dev/netif/iwm/if_iwm.c

5354

device_printf(sc->sc_dev, "%08X | l2p_duration\n", table.l2p_duration);

sys/dev/netif/iwm/if_iwm.c

5355

device_printf(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid);

sys/dev/netif/iwm/if_iwm.c

5356

device_printf(sc->sc_dev, "%08X | l2p_addr_match\n", table.l2p_addr_match);

sys/dev/netif/iwm/if_iwm.c

5357

device_printf(sc->sc_dev, "%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);

sys/dev/netif/iwm/if_iwm.c

5358

device_printf(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp);

sys/dev/netif/iwm/if_iwm.c

5359

device_printf(sc->sc_dev, "%08X | flow_handler\n", table.flow_handler);

sys/dev/raid/aac/aac.c

184

static const char *aac_describe_code(const struct aac_code_lookup *table,

sys/dev/raid/aac/aac.c

2766

aac_describe_code(const struct aac_code_lookup *table, u_int32_t code)

sys/dev/raid/aac/aac.c

2770

for (i = 0; table[i].string != NULL; i++)

sys/dev/raid/aac/aac.c

2771

if (table[i].code == code)

sys/dev/raid/aac/aac.c

2772

return(table[i].string);

sys/dev/raid/aac/aac.c

2773

return(table[i + 1].string);

sys/dev/raid/amr/amr_tables.h

67

extern char *amr_describe_code(struct amr_code_lookup *table, u_int32_t code);

sys/dev/raid/amr/amr_tables.h

80

amr_describe_code(struct amr_code_lookup *table, u_int32_t code)

sys/dev/raid/amr/amr_tables.h

84

for (i = 0; table[i].string != NULL; i++)

sys/dev/raid/amr/amr_tables.h

85

if (table[i].code == code)

sys/dev/raid/amr/amr_tables.h

86

return(table[i].string);

sys/dev/raid/amr/amr_tables.h

87

return(table[i+1].string);

sys/dev/raid/mly/mly_tables.h

38

static char *mly_describe_code(struct mly_code_lookup *table, u_int32_t code);

sys/dev/raid/mly/mly_tables.h

44

mly_describe_code(struct mly_code_lookup *table, u_int32_t code)

sys/dev/raid/mly/mly_tables.h

48

for (i = 0; table[i].string != NULL; i++)

sys/dev/raid/mly/mly_tables.h

49

if (table[i].code == code)

sys/dev/raid/mly/mly_tables.h

50

return(table[i].string);

sys/dev/raid/mly/mly_tables.h

51

return(table[i+1].string);

sys/dev/raid/mpr/mpr_table.c

64

mpr_describe_table(struct mpr_table_lookup *table, u_int code)

sys/dev/raid/mpr/mpr_table.c

68

for (i = 0; table[i].string != NULL; i++) {

sys/dev/raid/mpr/mpr_table.c

69

if (table[i].code == code)

sys/dev/raid/mpr/mpr_table.c

70

return(table[i].string);

sys/dev/raid/mpr/mpr_table.c

72

return(table[i+1].string);

sys/dev/raid/mpr/mpr_table.h

37

char * mpr_describe_table(struct mpr_table_lookup *table, u_int code);

sys/dev/raid/mps/mps_table.c

64

mps_describe_table(struct mps_table_lookup *table, u_int code)

sys/dev/raid/mps/mps_table.c

68

for (i = 0; table[i].string != NULL; i++) {

sys/dev/raid/mps/mps_table.c

69

if (table[i].code == code)

sys/dev/raid/mps/mps_table.c

70

return(table[i].string);

sys/dev/raid/mps/mps_table.c

72

return(table[i+1].string);

sys/dev/raid/mps/mps_table.h

37

char * mps_describe_table(struct mps_table_lookup *table, u_int code);

sys/dev/raid/twe/twe.c

1715

twe_describe_code(struct twe_code_lookup *table, u_int32_t code)

sys/dev/raid/twe/twe.c

1719

for (i = 0; table[i].string != NULL; i++)

sys/dev/raid/twe/twe.c

1720

if (table[i].code == code)

sys/dev/raid/twe/twe.c

1721

return(table[i].string);

sys/dev/raid/twe/twe.c

1722

return(table[i+1].string);

sys/dev/raid/twe/twe.c

206

int table, error = 0;

sys/dev/raid/twe/twe.c

234

table = TWE_PARAM_UNITINFO + unit;

sys/dev/raid/twe/twe.c

236

if (twe_get_param_4(sc, table, TWE_PARAM_UNITINFO_Capacity, &dr->td_size)) {

sys/dev/raid/twe/twe.c

242

if (twe_get_param_1(sc, table, TWE_PARAM_UNITINFO_Status, &dr->td_state)) {

sys/dev/raid/twe/twe.c

248

if (twe_get_param_2(sc, table, TWE_PARAM_UNITINFO_DescriptorSize, &dsize)) {

sys/dev/raid/twe/twe.c

254

if ((param = twe_get_param(sc, table, TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL)) == NULL) {

sys/dev/raid/twe/twe_tables.h

40

extern char *twe_describe_code(struct twe_code_lookup *table, u_int32_t code);

sys/dev/raid/vinum/vinummemory.c

65

expand_table(void **table, int oldsize, int newsize)

sys/dev/raid/vinum/vinummemory.c

74

if (*table != NULL) { /* already something there, */

sys/dev/raid/vinum/vinummemory.c

75

bcopy((char *) *table, (char *) temp, oldsize); /* copy it to the old table */

sys/dev/raid/vinum/vinummemory.c

76

Free(*table);

sys/dev/raid/vinum/vinummemory.c

78

*table = temp;

sys/dev/raid/vinum/vinumvar.h

642

#define EXPAND(table, element, oldcount, increment) \

sys/dev/raid/vinum/vinumvar.h

644

expand_table((void **) &table, \

sys/dev/video/fb/vga.c

443

map_mode_table(u_char *map[], u_char *table)

sys/dev/video/fb/vga.c

448

map[i] = table + i*V_MODE_PARAM_SIZE;

sys/kern/tty.c

2401

ttspeedtab(int speed, struct speedtab *table)

sys/kern/tty.c

2404

for ( ; table->sp_speed != -1; table++)

sys/kern/tty.c

2405

if (table->sp_speed == speed)

sys/kern/tty.c

2406

return (table->sp_code);

sys/libkern/scanc.c

38

scanc(u_int size, const u_char *cp, const u_char table[], int mask0)

sys/libkern/scanc.c

45

if (table[*cp] & mask)

sys/net/if.c

4126

if_ringmap_rdrtable(const struct if_ringmap *rm, int table[], int table_nent)

sys/net/if.c

4135

table[i] = grid_idx++ % rm->rm_cnt;

sys/net/if.c

4177

table[fix_idx] = grid_idx++ % rm->rm_cnt;

sys/net/if.c

4189

memcpy(&table[i * NETISR_CPUMAX], table,

sys/net/if.c

4190

NETISR_CPUMAX * sizeof(table[0]));

sys/net/if.c

4196

kprintf("%03d ", table[i]);

sys/net/if_ringmap.h

57

void if_ringmap_rdrtable(const struct if_ringmap *rm, int table[],

sys/net/pf/pf_ioctl.c

2609

struct pfr_table *table;

sys/net/pf/pf_ioctl.c

2617

table = kmalloc(sizeof(*table), M_TEMP, M_WAITOK);

sys/net/pf/pf_ioctl.c

2620

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2629

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2635

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2642

bzero(table, sizeof(*table));

sys/net/pf/pf_ioctl.c

2643

strlcpy(table->pfrt_anchor, ioe->anchor,

sys/net/pf/pf_ioctl.c

2644

sizeof(table->pfrt_anchor));

sys/net/pf/pf_ioctl.c

2645

if ((error = pfr_ina_begin(table,

sys/net/pf/pf_ioctl.c

2647

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2655

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2662

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2668

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2676

struct pfr_table *table;

sys/net/pf/pf_ioctl.c

2684

table = kmalloc(sizeof(*table), M_TEMP, M_WAITOK);

sys/net/pf/pf_ioctl.c

2687

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2696

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2702

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2709

bzero(table, sizeof(*table));

sys/net/pf/pf_ioctl.c

2710

strlcpy(table->pfrt_anchor, ioe->anchor,

sys/net/pf/pf_ioctl.c

2711

sizeof(table->pfrt_anchor));

sys/net/pf/pf_ioctl.c

2712

if ((error = pfr_ina_rollback(table,

sys/net/pf/pf_ioctl.c

2714

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2722

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2729

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2737

struct pfr_table *table;

sys/net/pf/pf_ioctl.c

2746

table = kmalloc(sizeof(*table), M_TEMP, M_WAITOK);

sys/net/pf/pf_ioctl.c

2750

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2759

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2766

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2777

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2786

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2796

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2807

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2816

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2823

bzero(table, sizeof(*table));

sys/net/pf/pf_ioctl.c

2824

strlcpy(table->pfrt_anchor, ioe->anchor,

sys/net/pf/pf_ioctl.c

2825

sizeof(table->pfrt_anchor));

sys/net/pf/pf_ioctl.c

2826

if ((error = pfr_ina_commit(table, ioe->ticket,

sys/net/pf/pf_ioctl.c

2828

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2836

kfree(table, M_TEMP);

sys/net/pf/pf_ioctl.c

2843

kfree(table, M_TEMP);

sys/net/wg/selftest/allowedips.c

100

LIST_INIT(&table->head);

sys/net/wg/selftest/allowedips.c

104

horrible_allowedips_flush(struct horrible_allowedips *table)

sys/net/wg/selftest/allowedips.c

108

LIST_FOREACH_MUTABLE(node, &table->head, entry, node_) {

sys/net/wg/selftest/allowedips.c

174

horrible_insert_ordered(struct horrible_allowedips *table,

sys/net/wg/selftest/allowedips.c

183

LIST_FOREACH(other, &table->head, entry) {

sys/net/wg/selftest/allowedips.c

200

LIST_INSERT_HEAD(&table->head, node, entry);

sys/net/wg/selftest/allowedips.c

208

horrible_allowedips_insert_v4(struct horrible_allowedips *table,

sys/net/wg/selftest/allowedips.c

223

horrible_insert_ordered(table, node);

sys/net/wg/selftest/allowedips.c

229

horrible_allowedips_insert_v6(struct horrible_allowedips *table,

sys/net/wg/selftest/allowedips.c

244

horrible_insert_ordered(table, node);

sys/net/wg/selftest/allowedips.c

250

horrible_allowedips_lookup_v4(const struct horrible_allowedips *table,

sys/net/wg/selftest/allowedips.c

256

LIST_FOREACH(node, &table->head, entry) {

sys/net/wg/selftest/allowedips.c

269

horrible_allowedips_lookup_v6(const struct horrible_allowedips *table,

sys/net/wg/selftest/allowedips.c

275

LIST_FOREACH(node, &table->head, entry) {

sys/net/wg/selftest/allowedips.c

98

horrible_allowedips_init(struct horrible_allowedips *table)

sys/net/zlib.c

3569

uInt table; /* table lengths (14 bits) */

sys/net/zlib.c

3837

s->sub.trees.table = t = (uInt)b & 0x3fff;

sys/net/zlib.c

3860

while (s->sub.trees.index < 4 + (s->sub.trees.table >> 10))

sys/net/zlib.c

3884

while (t = s->sub.trees.table,

sys/net/zlib.c

3909

t = s->sub.trees.table;

sys/net/zlib.c

3936

t = s->sub.trees.table;

sys/net/zlib.c

5232

local ptr_table table[MAX_PTR];

sys/net/zlib.c

5256

table[next_ptr].org_ptr = buf;

sys/net/zlib.c

5261

table[next_ptr++].new_ptr = buf;

sys/net/zlib.c

5275

if (ptr != table[n].new_ptr) continue;

sys/net/zlib.c

5277

farfree(table[n].org_ptr);

sys/net/zlib.c

5279

table[n-1] = table[n];

sys/netgraph7/ng_vlan.c

68

const struct ng_vlan_table *const table =

sys/netgraph7/ng_vlan.c

71

return table->n;

sys/netproto/802_11/wlan/ieee80211_scan_sta.c

528

const struct scanlist table[])

sys/netproto/802_11/wlan/ieee80211_scan_sta.c

568

if (checktable(table, c))

sys/netproto/802_11/wlan/ieee80211_scan_sta.c

593

const struct scanlist table[])

sys/netproto/802_11/wlan/ieee80211_scan_sta.c

604

for (scan = table; scan->list != NULL; scan++) {

sys/netproto/802_11/wlan/ieee80211_scan_sta.c

651

sweepchannels(ss, vap, table);

sys/sys/tty.h

259

int ttspeedtab (int speed, struct speedtab *table);

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

119

*(*table)++ = here; /* make a table to force an error */

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

120

*(*table)++ = here;

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

201

next = *table; /* current table to fill in */

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

284

(*table)[low].op = (unsigned char)curr;

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

285

(*table)[low].bits = (unsigned char)root;

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

286

(*table)[low].val = (unsigned short)(next - *table);

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

301

*table += used;

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.c

35

code FAR * FAR *table, unsigned FAR *bits,

sys/vfs/hammer2/zlib/hammer2_zlib_inftrees.h

61

unsigned codes, code FAR * FAR *table,

sys/vfs/isofs/cd9660/cd9660_rrip.c

470

RRIP_TABLE *table)

sys/vfs/isofs/cd9660/cd9660_rrip.c

511

for (ptable = table; ptable->func; ptable++) {

sys/vfs/isofs/cd9660/cd9660_rrip.c

581

for (ptable = table; ptable->func2; ptable++) {

sys/vfs/isofs/cd9660/cd9660_rrip.c

75

ISO_RRIP_ANALYZE *ana, RRIP_TABLE *table);

tools/tools/drm/radeon/mkregtable/mkregtable.c

547

unsigned *table;

tools/tools/drm/radeon/mkregtable/mkregtable.c

563

static void table_offset_add(struct table *t, struct offset *offset)

tools/tools/drm/radeon/mkregtable/mkregtable.c

568

static void table_init(struct table *t)

tools/tools/drm/radeon/mkregtable/mkregtable.c

573

t->table = NULL;

tools/tools/drm/radeon/mkregtable/mkregtable.c

576

static void table_print(struct table *t)

tools/tools/drm/radeon/mkregtable/mkregtable.c

594

printf("0x%08X,", t->table[id++]);

tools/tools/drm/radeon/mkregtable/mkregtable.c

601

static int table_build(struct table *t)

tools/tools/drm/radeon/mkregtable/mkregtable.c

607

t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry);

tools/tools/drm/radeon/mkregtable/mkregtable.c

608

if (t->table == NULL)

tools/tools/drm/radeon/mkregtable/mkregtable.c

610

memset(t->table, 0xff, sizeof(unsigned) * t->nentry);

tools/tools/drm/radeon/mkregtable/mkregtable.c

615

t->table[i] ^= m;

tools/tools/drm/radeon/mkregtable/mkregtable.c

621

static int parser_auth(struct table *t, const char *filename)

tools/tools/drm/radeon/mkregtable/mkregtable.c

699

struct table t;

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

319

static int doComputation(PTW_attackstate * state, uint8_t * key, int keylen, PTW_tableentry table[][n], sorthelper * sh2, int * strongbytes, int keylimit) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

339

if (doRound(table, 0, fixat, fixvalue, choices, key, keylen, state, 0, strongbytes) == 1) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

375

PTW_tableentry (*table)[n] = alloca(sizeof(PTW_tableentry) * n * keylen);

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

376

if (table == NULL) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

380

memcpy(table, state->table, sizeof(PTW_tableentry) * n * keylen);

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

384

qsort(&table[i][0], n, sizeof(PTW_tableentry), &compare);

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

397

sh[i][j-1].distance = table[i][0].votes - table[i][j].votes;

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

398

sh[i][j-1].value = table[i][j].b;

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

405

if (doComputation(state, keybuf, keylen, table, (sorthelper *) sh, strongbytes, simple)) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

410

getdrv(state->table, keylen, normal, ausreisser);

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

417

if (doComputation(state, keybuf, keylen, table, (sorthelper *) sh, strongbytes, onestrong)) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

423

if (doComputation(state, keybuf, keylen, table, (sorthelper *) sh, strongbytes, twostrong)) {

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

450

state->table[i][buf[i]].votes++;

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c

476

state->table[i][k].b = k;

tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.h

78

PTW_tableentry table[PTW_KEYHSBYTES][PTW_n];

usr.bin/getaddrinfo/getaddrinfo.c

226

const char *const *table, size_t n)

usr.bin/getaddrinfo/getaddrinfo.c

248

if ((table[i] != NULL) && (strcmp(string, table[i]) == 0))

usr.bin/indent/lexi.c

129

static char const *table[] = {

usr.bin/indent/lexi.c

201

if (i >= nitems(table) || table[i] == NULL ||

usr.bin/indent/lexi.c

202

table[i][s - 'A'] == ' ') {

usr.bin/indent/lexi.c

203

s = table[0][s - 'A'];

usr.bin/indent/lexi.c

206

s = table[i][s - 'A'];

usr.bin/indent/lexi.c

589

table['-'] = table['+'];

usr.bin/indent/lexi.c

590

table['8'] = table['9'];

usr.bin/indent/lexi.c

591

table['2'] = table['3'] = table['4'] = table['5'] = table['6'] = table['7'];

usr.bin/indent/lexi.c

592

table['A'] = table['C'] = table['D'] = table['c'] = table['d'] = table['a'];

usr.bin/indent/lexi.c

593

table['B'] = table['b'];

usr.bin/indent/lexi.c

594

table['E'] = table['e'];

usr.bin/indent/lexi.c

595

table['U'] = table['u'];

usr.bin/indent/lexi.c

596

table['X'] = table['x'];

usr.bin/indent/lexi.c

597

table['P'] = table['p'];

usr.bin/indent/lexi.c

598

table['F'] = table['f'];

usr.bin/locate/locate/fastfind.c

140

u_char table[UCHAR_MAX + 1];

usr.bin/locate/locate/fastfind.c

178

table[c] = 0;

usr.bin/locate/locate/fastfind.c

180

table[TOLOWER(*patend)] = 1;

usr.bin/locate/locate/fastfind.c

181

table[toupper(*patend)] = 1;

usr.bin/locate/locate/fastfind.c

243

if (table[c])

usr.bin/locate/locate/fastfind.c

259

if (table[bigram1[c]] ||

usr.bin/locate/locate/fastfind.c

260

table[bigram2[c]])

usr.bin/login/login_fbtab.c

107

syslog(LOG_ERR, "%s: bad entry: %s", table, cp ? cp : "(null)");

usr.bin/login/login_fbtab.c

112

login_protect(table, cp, prot, uid, gid);

usr.bin/login/login_fbtab.c

122

login_protect(const char *table, char *pattern, int mask, uid_t uid, gid_t gid)

usr.bin/login/login_fbtab.c

134

syslog(LOG_ERR, "%s: chflags(%s): %m", table, path);

usr.bin/login/login_fbtab.c

136

syslog(LOG_ERR, "%s: chmod(%s): %m", table, path);

usr.bin/login/login_fbtab.c

138

syslog(LOG_ERR, "%s: chown(%s): %m", table, path);

usr.bin/login/login_fbtab.c

89

const char *table;

usr.bin/login/login_fbtab.c

91

if ((fp = fopen(table = _PATH_FBTAB, "r")) == NULL

usr.bin/login/login_fbtab.c

92

&& (fp = fopen(table = _PATH_LOGINDEVPERM, "r")) == NULL)

usr.bin/mail/util.c

581

member(char *realfield, struct ignoretab *table)

usr.bin/mail/util.c

585

for (igp = table->i_head[hash(realfield)]; igp != NULL; igp = igp->i_link)

usr.bin/mkcsmapper/yacc.y

258

table = (void *)malloc(table_size * dst_unit_bits / 8);

usr.bin/mkcsmapper/yacc.y

259

if (table == NULL) {

usr.bin/mkcsmapper/yacc.y

275

(*putfunc)(table, i, val);

usr.bin/mkcsmapper/yacc.y

391

_region_init(&data, table, table_size*dst_unit_bits/8);

usr.bin/mkcsmapper/yacc.y

597

(*putfunc)(table, ofs++, dst);

usr.bin/mkcsmapper/yacc.y

66

static void *table = NULL;

usr.bin/u4bhidctl/usbhid.c

446

char *table = NULL;

usr.bin/u4bhidctl/usbhid.c

472

table = optarg;

usr.bin/u4bhidctl/usbhid.c

507

hid_init(table);

usr.bin/usbhidaction/usbhidaction.c

124

table = optarg;

usr.bin/usbhidaction/usbhidaction.c

141

hid_init(table);

usr.bin/usbhidaction/usbhidaction.c

87

const char *table = NULL;

usr.sbin/makefs/ffs/ffs_alloc.c

535

scanc(u_int size, const u_char *cp, const u_char table[], int mask)

usr.sbin/makefs/ffs/ffs_alloc.c

539

while (cp < end && (table[*cp] & mask) == 0)

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

119

*(*table)++ = here; /* make a table to force an error */

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

120

*(*table)++ = here;

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

201

next = *table; /* current table to fill in */

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

284

(*table)[low].op = (unsigned char)curr;

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

285

(*table)[low].bits = (unsigned char)root;

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

286

(*table)[low].val = (unsigned short)(next - *table);

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

301

*table += used;

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.c

35

code FAR * FAR *table, unsigned FAR *bits,

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_inftrees.h

61

unsigned codes, code FAR * FAR *table,

usr.sbin/mtree/only.c

54

static struct hentry *table[1024];

usr.sbin/mtree/only.c

72

*h = hash_str(str) % NELEM(table);

usr.sbin/mtree/only.c

74

for (e = table[*h]; e; e = e->next)

usr.sbin/mtree/only.c

93

e->next = table[h];

usr.sbin/mtree/only.c

94

table[h] = e;

usr.sbin/nscd/hashtable.h

103

#define HASHTABLE_GET_ENTRY(table, hash) (&((table)->entries[hash]))

usr.sbin/nscd/hashtable.h

108

#define HASHTABLE_FOREACH(table, var) \

usr.sbin/nscd/hashtable.h

109

for ((var) = &((table)->entries[0]); \

usr.sbin/nscd/hashtable.h

110

(var) < &((table)->entries[HASHTABLE_ENTRIES_COUNT(table)]);\

usr.sbin/nscd/hashtable.h

157

hashtable_index_t name##_CALCULATE_HASH(struct name *table, type *data) \

usr.sbin/nscd/hashtable.h

160

return HASH(data, table->entries_size); \

usr.sbin/nscd/hashtable.h

203

#define HASHTABLE_CALCULATE_HASH(name, table, data) \

usr.sbin/nscd/hashtable.h

204

(name##_CALCULATE_HASH((table), data))

usr.sbin/nscd/hashtable.h

69

#define HASHTABLE_ENTRIES_COUNT(table) ((table)->entries_size)

usr.sbin/nscd/hashtable.h

75

#define HASHTABLE_INIT(table, type, field, _entries_size) \

usr.sbin/nscd/hashtable.h

78

(table)->entries = (void *)calloc(1, \

usr.sbin/nscd/hashtable.h

79

sizeof(*(table)->entries) * (_entries_size)); \

usr.sbin/nscd/hashtable.h

80

(table)->entries_size = (_entries_size); \

usr.sbin/nscd/hashtable.h

81

for (var = 0; var < HASHTABLE_ENTRIES_COUNT(table); ++var) {\

usr.sbin/nscd/hashtable.h

82

(table)->entries[var].field.capacity = \

usr.sbin/nscd/hashtable.h

84

(table)->entries[var].field.size = 0; \

usr.sbin/nscd/hashtable.h

85

(table)->entries[var].field.values = (type *)malloc(\

usr.sbin/nscd/hashtable.h

88

assert((table)->entries[var].field.values != NULL);\

usr.sbin/nscd/hashtable.h

95

#define HASHTABLE_DESTROY(table, field) \

usr.sbin/nscd/hashtable.h

98

for (var = 0; var < HASHTABLE_ENTRIES_COUNT(table); ++var) {\

usr.sbin/nscd/hashtable.h

99

free((table)->entries[var].field.values); \

usr.sbin/pciconf/err.c

112

print_bits(const char *header, struct bit_table *table, uint32_t mask)

usr.sbin/pciconf/err.c

117

for (; table->desc != NULL; table++)

usr.sbin/pciconf/err.c

118

if (mask & table->mask) {

usr.sbin/pciconf/err.c

124

printf("%s\n", table->desc);

usr.sbin/pciconf/err.c

125

mask &= ~table->mask;

usr.sbin/pfctl/pfctl_table.c

101

table.pfrt_flags &= ~PFR_TFLAG_PERSIST; \

usr.sbin/pfctl/pfctl_table.c

129

struct pfr_table table;

usr.sbin/pfctl/pfctl_table.c

143

bzero(&table, sizeof(table));

usr.sbin/pfctl/pfctl_table.c

147

if (strlcpy(table.pfrt_name, tname,

usr.sbin/pfctl/pfctl_table.c

148

sizeof(table.pfrt_name)) >= sizeof(table.pfrt_name))

usr.sbin/pfctl/pfctl_table.c

151

if (strlcpy(table.pfrt_anchor, anchor,

usr.sbin/pfctl/pfctl_table.c

152

sizeof(table.pfrt_anchor)) >= sizeof(table.pfrt_anchor))

usr.sbin/pfctl/pfctl_table.c

158

RVTEST(pfr_clr_tables(&table, &ndel, flags));

usr.sbin/pfctl/pfctl_table.c

169

RVTEST(pfr_get_tstats(&table,

usr.sbin/pfctl/pfctl_table.c

172

RVTEST(pfr_get_tables(&table,

usr.sbin/pfctl/pfctl_table.c

190

RVTEST(pfr_del_tables(&table, 1, &ndel, flags));

usr.sbin/pfctl/pfctl_table.c

195

RVTEST(pfr_clr_addrs(&table, &ndel, flags));

usr.sbin/pfctl/pfctl_table.c

204

RVTEST(pfr_add_addrs(&table, b.pfrb_caddr, b.pfrb_size,

usr.sbin/pfctl/pfctl_table.c

218

RVTEST(pfr_del_addrs(&table, b.pfrb_caddr, b.pfrb_size,

usr.sbin/pfctl/pfctl_table.c

236

RVTEST(pfr_set_addrs(&table, b.pfrb_caddr, b.pfrb_size,

usr.sbin/pfctl/pfctl_table.c

271

RVTEST(pfr_get_astats(&table, b.pfrb_caddr,

usr.sbin/pfctl/pfctl_table.c

287

RVTEST(pfr_del_addrs(&table, b2.pfrb_caddr, b2.pfrb_size,

usr.sbin/pfctl/pfctl_table.c

304

RVTEST(pfr_get_astats(&table, b.pfrb_caddr,

usr.sbin/pfctl/pfctl_table.c

307

RVTEST(pfr_get_addrs(&table, b.pfrb_caddr,

usr.sbin/pfctl/pfctl_table.c

329

RVTEST(pfr_tst_addrs(&table, b.pfrb_caddr, b.pfrb_size,

usr.sbin/pfctl/pfctl_table.c

350

RVTEST(pfr_clr_tstats(&table, 1, &nzero, flags));

usr.sbin/pfctl/pfctl_table.c

87

table.pfrt_flags |= PFR_TFLAG_PERSIST; \

usr.sbin/pfctl/pfctl_table.c

90

(pfr_add_tables(&table, 1, &nadd, flags)) && \

usr.sbin/pfctl/pfctl_table.c

96

warn_namespace_collision(table.pfrt_name); \

usr.sbin/zic/zic.c

2456

byword(const char * const word, const struct lookup * const table)

usr.sbin/zic/zic.c

2461

if (word == NULL || table == NULL)

usr.sbin/zic/zic.c

2466

for (lp = table; lp->l_word != NULL; ++lp)

usr.sbin/zic/zic.c

2473

for (lp = table; lp->l_word != NULL; ++lp)