sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2757

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2988

const struct pipe_ctx pipe[],

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1090

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1125

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

251

const struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

437

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

505

struct pipe_ctx *primary_pipe,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

506

struct pipe_ctx *secondary_pipe)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

837

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

1002

pipe = &context->res_ctx.pipe_ctx[k];

sys/dev/drm/amd/display/dc/core/dc.c

1067

if (context->res_ctx.pipe_ctx[i].stream == NULL ||

sys/dev/drm/amd/display/dc/core/dc.c

1068

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

sys/dev/drm/amd/display/dc/core/dc.c

1069

context->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/drm/amd/display/dc/core/dc.c

1070

dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/core/dc.c

1115

const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

1117

if (plane_state == pipe_ctx->plane_state) {

sys/dev/drm/amd/display/dc/core/dc.c

1420

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

1422

if (!pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/core/dc.c

1423

pipe_ctx->stream &&

sys/dev/drm/amd/display/dc/core/dc.c

1424

pipe_ctx->stream == stream) {

sys/dev/drm/amd/display/dc/core/dc.c

1429

dc->hwss.set_drr(&pipe_ctx, 1,

sys/dev/drm/amd/display/dc/core/dc.c

1434

pipe_ctx->stream_res.tg &&

sys/dev/drm/amd/display/dc/core/dc.c

1435

pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)

sys/dev/drm/amd/display/dc/core/dc.c

1436

pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(

sys/dev/drm/amd/display/dc/core/dc.c

1437

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,

sys/dev/drm/amd/display/dc/core/dc.c

1438

pipe_ctx->stream->periodic_fn_vsync_delta);

sys/dev/drm/amd/display/dc/core/dc.c

1443

resource_build_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1444

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1459

core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);

sys/dev/drm/amd/display/dc/core/dc.c

1467

core_link_enable_stream(dc->current_state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1473

if (stream_update->abm_level && pipe_ctx->stream_res.abm) {

sys/dev/drm/amd/display/dc/core/dc.c

1474

if (pipe_ctx->stream_res.tg->funcs->is_blanked) {

sys/dev/drm/amd/display/dc/core/dc.c

1476

if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

sys/dev/drm/amd/display/dc/core/dc.c

1477

pipe_ctx->stream_res.abm->funcs->set_abm_level(

sys/dev/drm/amd/display/dc/core/dc.c

1478

pipe_ctx->stream_res.abm, stream->abm_level);

sys/dev/drm/amd/display/dc/core/dc.c

1480

pipe_ctx->stream_res.abm->funcs->set_abm_level(

sys/dev/drm/amd/display/dc/core/dc.c

1481

pipe_ctx->stream_res.abm, stream->abm_level);

sys/dev/drm/amd/display/dc/core/dc.c

1496

struct pipe_ctx *top_pipe_to_program = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

1518

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

1520

if (!pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/core/dc.c

1521

pipe_ctx->stream &&

sys/dev/drm/amd/display/dc/core/dc.c

1522

pipe_ctx->stream == stream) {

sys/dev/drm/amd/display/dc/core/dc.c

1525

top_pipe_to_program = pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc.c

1527

if (!pipe_ctx->plane_state)

sys/dev/drm/amd/display/dc/core/dc.c

1535

stream_get_status(context, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc.c

1538

dc, pipe_ctx->stream, stream_status->plane_count, context);

sys/dev/drm/amd/display/dc/core/dc.c

1558

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

1560

if (pipe_ctx->stream != stream)

sys/dev/drm/amd/display/dc/core/dc.c

1563

if (pipe_ctx->plane_state != plane_state)

sys/dev/drm/amd/display/dc/core/dc.c

1567

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1626

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

1628

if (pipe_ctx->plane_state != surface)

sys/dev/drm/amd/display/dc/core/dc.c

1631

resource_build_scaling_params(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

202

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

228

struct pipe_ctx *pipe =

sys/dev/drm/amd/display/dc/core/dc.c

229

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

257

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

262

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

307

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

311

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

332

struct pipe_ctx *pipes = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

336

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

sys/dev/drm/amd/display/dc/core/dc.c

338

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

370

struct pipe_ctx *pipes;

sys/dev/drm/amd/display/dc/core/dc.c

373

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

sys/dev/drm/amd/display/dc/core/dc.c

374

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

387

struct pipe_ctx *pipes;

sys/dev/drm/amd/display/dc/core/dc.c

390

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/drm/amd/display/dc/core/dc.c

393

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

411

struct pipe_ctx *pipes_affected[MAX_PIPES];

sys/dev/drm/amd/display/dc/core/dc.c

418

if (dc->current_state->res_ctx.pipe_ctx[j].stream

sys/dev/drm/amd/display/dc/core/dc.c

421

&dc->current_state->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

465

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

470

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

482

link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/drm/amd/display/dc/core/dc.c

705

dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/drm/amd/display/dc/core/dc.c

790

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

sys/dev/drm/amd/display/dc/core/dc.c

793

if (!ctx->res_ctx.pipe_ctx[i].stream ||

sys/dev/drm/amd/display/dc/core/dc.c

794

!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)

sys/dev/drm/amd/display/dc/core/dc.c

796

if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)

sys/dev/drm/amd/display/dc/core/dc.c

798

multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

815

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

sys/dev/drm/amd/display/dc/core/dc.c

818

if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)

sys/dev/drm/amd/display/dc/core/dc.c

821

unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

826

struct pipe_ctx *pipe_set[MAX_PIPES];

sys/dev/drm/amd/display/dc/core/dc.c

852

struct pipe_ctx *temp;

sys/dev/drm/amd/display/dc/core/dc.c

907

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

911

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

913

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

932

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

967

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_debug.c

321

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_debug.c

325

if (pipe_ctx->stream == NULL

sys/dev/drm/amd/display/dc/core/dc_debug.c

326

|| pipe_ctx->pipe_idx == underlay_idx)

sys/dev/drm/amd/display/dc/core/dc_debug.c

329

pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);

sys/dev/drm/amd/display/dc/core/dc_debug.c

334

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_debug.c

336

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/core/dc_debug.c

340

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/core/dc_debug.c

341

pipe_ctx->stream->timing.h_total,

sys/dev/drm/amd/display/dc/core/dc_debug.c

342

pipe_ctx->stream->timing.v_total,

sys/dev/drm/amd/display/dc/core/dc_link.c

1343

static void enable_stream_features(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1345

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

1366

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1368

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

1399

pipe_ctx->stream->signal,

sys/dev/drm/amd/display/dc/core/dc_link.c

1400

pipe_ctx->clock_source->id,

sys/dev/drm/amd/display/dc/core/dc_link.c

1428

enable_stream_features(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

1435

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1438

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

1444

status = enable_link_dp(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

1452

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1454

struct dc_link *link = pipe_ctx->stream->sink->link;

sys/dev/drm/amd/display/dc/core/dc_link.c

1468

return enable_link_dp(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

1471

static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1478

pipe_ctx->stream->ctx->dc_bios->integrated_info;

sys/dev/drm/amd/display/dc/core/dc_link.c

1568

static bool i2c_write(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1579

cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/drm/amd/display/dc/core/dc_link.c

1587

if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1588

pipe_ctx->stream->sink->link, &cmd))

sys/dev/drm/amd/display/dc/core/dc_link.c

1595

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1607

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_link.c

1619

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1642

pipe_ctx->stream->sink->link->ddc,

sys/dev/drm/amd/display/dc/core/dc_link.c

1652

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1672

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1695

pipe_ctx->stream->sink->link->ddc,

sys/dev/drm/amd/display/dc/core/dc_link.c

1705

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1724

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1736

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1748

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1761

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1768

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_link.c

1776

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1788

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1800

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1812

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1824

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1836

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1852

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1864

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1876

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1888

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1894

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_link.c

1904

i2c_success = i2c_write(pipe_ctx, slave_address,

sys/dev/drm/amd/display/dc/core/dc_link.c

1917

static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1919

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

1933

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

sys/dev/drm/amd/display/dc/core/dc_link.c

1934

unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &

sys/dev/drm/amd/display/dc/core/dc_link.c

1938

eng_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/drm/amd/display/dc/core/dc_link.c

1940

if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {

sys/dev/drm/amd/display/dc/core/dc_link.c

1941

write_i2c_retimer_setting(pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1944

write_i2c_default_retimer_setting(pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

1949

write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);

sys/dev/drm/amd/display/dc/core/dc_link.c

1953

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_link.c

1968

pipe_ctx->clock_source->id,

sys/dev/drm/amd/display/dc/core/dc_link.c

1970

pipe_ctx->stream->signal,

sys/dev/drm/amd/display/dc/core/dc_link.c

1973

if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

sys/dev/drm/amd/display/dc/core/dc_link.c

1977

static void enable_link_lvds(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

1979

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

1990

pipe_ctx->clock_source->id,

sys/dev/drm/amd/display/dc/core/dc_link.c

1998

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

2001

switch (pipe_ctx->stream->signal) {

sys/dev/drm/amd/display/dc/core/dc_link.c

2003

status = enable_link_dp(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2006

status = enable_link_edp(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2009

status = enable_link_dp_mst(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2015

enable_link_hdmi(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2019

enable_link_lvds(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2210

pipe_ctx[i].stream

sys/dev/drm/amd/display/dc/core/dc_link.c

2217

res_ctx.pipe_ctx[i].stream_res.tg->inst +

sys/dev/drm/amd/display/dc/core/dc_link.c

2292

static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

2300

bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);

sys/dev/drm/amd/display/dc/core/dc_link.c

2301

kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;

sys/dev/drm/amd/display/dc/core/dc_link.c

2374

static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

2376

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

2379

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2399

link, pipe_ctx->stream_res.stream_enc, &proposed_table);

sys/dev/drm/amd/display/dc/core/dc_link.c

2405

pipe_ctx->pipe_idx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2443

pbn = get_pbn_from_timing(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2454

static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

2456

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

2459

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2487

link, pipe_ctx->stream_res.stream_enc, &proposed_table);

sys/dev/drm/amd/display/dc/core/dc_link.c

2493

pipe_ctx->pipe_idx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2534

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_link.c

2536

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2537

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_link.c

2539

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_link.c

2541

if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {

sys/dev/drm/amd/display/dc/core/dc_link.c

2544

pipe_ctx->stream->signal);

sys/dev/drm/amd/display/dc/core/dc_link.c

2545

pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(

sys/dev/drm/amd/display/dc/core/dc_link.c

2546

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_link.c

2547

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/core/dc_link.c

2551

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_link.c

2552

pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(

sys/dev/drm/amd/display/dc/core/dc_link.c

2553

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_link.c

2557

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_link.c

2558

pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(

sys/dev/drm/amd/display/dc/core/dc_link.c

2559

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_link.c

2562

pipe_ctx->stream_res.audio != NULL);

sys/dev/drm/amd/display/dc/core/dc_link.c

2564

if (dc_is_dvi_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_link.c

2565

pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(

sys/dev/drm/amd/display/dc/core/dc_link.c

2566

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_link.c

2568

(pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?

sys/dev/drm/amd/display/dc/core/dc_link.c

2571

if (dc_is_lvds_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_link.c

2572

pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(

sys/dev/drm/amd/display/dc/core/dc_link.c

2573

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_link.c

2577

resource_build_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2578

core_dc->hwss.update_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2581

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/drm/amd/display/dc/core/dc_link.c

2582

pipe_ctx->stream->apply_edp_fast_boot_optimization) {

sys/dev/drm/amd/display/dc/core/dc_link.c

2583

pipe_ctx->stream->apply_edp_fast_boot_optimization = false;

sys/dev/drm/amd/display/dc/core/dc_link.c

2584

pipe_ctx->stream->dpms_off = false;

sys/dev/drm/amd/display/dc/core/dc_link.c

2588

if (pipe_ctx->stream->dpms_off)

sys/dev/drm/amd/display/dc/core/dc_link.c

2591

status = enable_link(state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2595

pipe_ctx->stream->sink->link->link_index,

sys/dev/drm/amd/display/dc/core/dc_link.c

2604

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

sys/dev/drm/amd/display/dc/core/dc_link.c

2610

core_dc->hwss.enable_audio_stream(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2613

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

sys/dev/drm/amd/display/dc/core/dc_link.c

2614

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/core/dc_link.c

2618

core_dc->hwss.enable_stream(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2620

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

sys/dev/drm/amd/display/dc/core/dc_link.c

2621

allocate_mst_payload(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2623

core_dc->hwss.unblank_stream(pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link.c

2624

&pipe_ctx->stream->sink->link->cur_link_settings);

sys/dev/drm/amd/display/dc/core/dc_link.c

2630

void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)

sys/dev/drm/amd/display/dc/core/dc_link.c

2632

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2634

core_dc->hwss.blank_stream(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2636

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

sys/dev/drm/amd/display/dc/core/dc_link.c

2637

deallocate_mst_payload(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_link.c

2639

core_dc->hwss.disable_stream(pipe_ctx, option);

sys/dev/drm/amd/display/dc/core/dc_link.c

2641

disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);

sys/dev/drm/amd/display/dc/core/dc_link.c

2644

void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/drm/amd/display/dc/core/dc_link.c

2646

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2648

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)

sys/dev/drm/amd/display/dc/core/dc_link.c

2651

core_dc->hwss.set_avmute(pipe_ctx, enable);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2515

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2519

enum dc_color_depth color_depth = pipe_ctx->

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2560

pipe_ctx->stream->bit_depth_params = params;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2561

pipe_ctx->stream_res.opp->funcs->

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2562

opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2563

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2564

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2571

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2573

pipe_ctx->stream->bit_depth_params = params;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2574

pipe_ctx->stream_res.opp->funcs->

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2575

opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2576

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2577

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2595

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2596

struct pipe_ctx *pipe_ctx = &pipes[0];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2607

pipe_ctx = &pipes[i];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2619

set_crtc_test_pattern(link, pipe_ctx, test_pattern);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2626

pipe_ctx,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2653

pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2734

set_crtc_test_pattern(link, pipe_ctx, test_pattern);

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

274

struct pipe_ctx *pipes =

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

275

&link->dc->current_state->res_ctx.pipe_ctx[0];

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

62

struct pipe_ctx *pipes =

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

63

link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1097

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/drm/amd/display/dc/core/dc_resource.c

1098

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1104

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1106

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1107

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1110

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1115

pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1116

pipe_ctx->plane_state->format);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1118

if (pipe_ctx->stream->timing.flags.INTERLACE)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1119

pipe_ctx->stream->dst.height *= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1121

calculate_scaling_ratios(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1123

calculate_viewport(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1125

if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1128

calculate_recout(pipe_ctx, &recout_full);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1134

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1136

pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1137

pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1139

pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1140

pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1141

if (pipe_ctx->stream->timing.flags.INTERLACE)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1142

pipe_ctx->plane_res.scl_data.v_active *= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1146

if (pipe_ctx->plane_res.xfm != NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1147

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1148

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1150

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1151

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1152

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1155

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1157

if (pipe_ctx->plane_res.xfm != NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1158

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1159

pipe_ctx->plane_res.xfm,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1160

&pipe_ctx->plane_res.scl_data,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1163

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1164

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1165

pipe_ctx->plane_res.dpp,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1166

&pipe_ctx->plane_res.scl_data,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1172

calculate_inits_and_adj_vp(pipe_ctx, &recout_full);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1179

pipe_ctx->plane_res.scl_data.viewport.height,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1180

pipe_ctx->plane_res.scl_data.viewport.width,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1181

pipe_ctx->plane_res.scl_data.viewport.x,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1182

pipe_ctx->plane_res.scl_data.viewport.y,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1188

if (pipe_ctx->stream->timing.flags.INTERLACE)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1189

pipe_ctx->stream->dst.height /= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1202

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

1203

context->res_ctx.pipe_ctx[i].stream != NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1204

if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))

sys/dev/drm/amd/display/dc/core/dc_resource.c

1211

struct pipe_ctx *find_idle_secondary_pipe(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1216

struct pipe_ctx *secondary_pipe = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1224

if (res_ctx->pipe_ctx[i].stream == NULL) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1225

secondary_pipe = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1235

struct pipe_ctx *resource_get_head_pipe_for_stream(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1241

if (res_ctx->pipe_ctx[i].stream == stream &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

1242

!res_ctx->pipe_ctx[i].top_pipe) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1243

return &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1250

static struct pipe_ctx *resource_get_tail_pipe_for_stream(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1254

struct pipe_ctx *head_pipe, *tail_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1274

static struct pipe_ctx *acquire_free_pipe_for_stream(

sys/dev/drm/amd/display/dc/core/dc_resource.c

1282

struct pipe_ctx *head_pipe = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1298

if (res_ctx->pipe_ctx[i].stream == stream &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

1299

!res_ctx->pipe_ctx[i].plane_state) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1300

return &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1325

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1327

if (pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

1328

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1329

pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1330

if (pipe_ctx->bottom_pipe)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1331

pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1333

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

sys/dev/drm/amd/display/dc/core/dc_resource.c

1334

pipe_ctx->stream_res.tg = pool->timing_generators[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1335

pipe_ctx->plane_res.hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1336

pipe_ctx->plane_res.ipp = pool->ipps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1337

pipe_ctx->plane_res.dpp = pool->dpps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1338

pipe_ctx->stream_res.opp = pool->opps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1339

pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1340

pipe_ctx->pipe_idx = i;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1342

pipe_ctx->stream = stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1358

struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1391

free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1447

struct pipe_ctx *pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1449

if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1450

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1452

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1453

pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1459

if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1460

pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1466

if (!pipe_ctx->top_pipe) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1467

pipe_ctx->plane_state = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1468

pipe_ctx->bottom_pipe = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1470

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

sys/dev/drm/amd/display/dc/core/dc_resource.c

1719

if (!res_ctx->pipe_ctx[i].stream) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1720

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1722

pipe_ctx->stream_res.tg = pool->timing_generators[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1723

pipe_ctx->plane_res.mi = pool->mis[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1724

pipe_ctx->plane_res.hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1725

pipe_ctx->plane_res.ipp = pool->ipps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1726

pipe_ctx->plane_res.xfm = pool->transforms[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1727

pipe_ctx->plane_res.dpp = pool->dpps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1728

pipe_ctx->stream_res.opp = pool->opps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1730

pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1731

pipe_ctx->pipe_idx = i;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1734

pipe_ctx->stream = stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1851

struct pipe_ctx *del_pipe = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1855

if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

1856

!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1857

del_pipe = &new_ctx->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1991

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2015

if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2018

pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/drm/amd/display/dc/core/dc_resource.c

2020

pipe_ctx->stream_res.stream_enc =

sys/dev/drm/amd/display/dc/core/dc_resource.c

2024

if (!pipe_ctx->stream_res.stream_enc)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2029

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2034

dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

2036

pipe_ctx->stream_res.audio = find_first_free_audio(

sys/dev/drm/amd/display/dc/core/dc_resource.c

2037

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2044

if (pipe_ctx->stream_res.audio)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2046

pipe_ctx->stream_res.audio, true);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2050

if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_resource.c

2051

pipe_ctx->stream_res.abm = pool->abm;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2055

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2056

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2099

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc_resource.c

2101

if (pipe_ctx->stream != stream)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2105

pipe_ctx->plane_state &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

2106

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

2107

result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2116

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

2122

pipe_ctx->clock_source);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2124

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2128

pipe_ctx->clock_source);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2163

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2165

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2178

unsigned int vic = pipe_ctx->stream->timing.vic;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2183

color_space = pipe_ctx->stream->output_color_space;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2344

switch (pipe_ctx->stream->timing.hdmi_vic) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

2582

struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

2585

cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];

sys/dev/drm/amd/display/dc/core/dc_resource.c

2588

cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];

sys/dev/drm/amd/display/dc/core/dc_resource.c

2618

void resource_build_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2621

struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2631

signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2635

set_avi_info_frame(&info->avi, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2637

set_vendor_info_packet(&info->vendor, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2639

set_spd_info_packet(&info->spd, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2641

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2644

set_vsc_info_packet(&info->vsc, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2646

set_spd_info_packet(&info->spd, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2648

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2661

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(

sys/dev/drm/amd/display/dc/core/dc_resource.c

2664

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2667

if (dc_is_dp_signal(pipe_ctx->stream->signal)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2668

|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2669

pipe_ctx->clock_source = pool->dp_clock_source;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2671

pipe_ctx->clock_source = NULL;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2674

pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(

sys/dev/drm/amd/display/dc/core/dc_resource.c

2676

pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2678

if (pipe_ctx->clock_source == NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2679

pipe_ctx->clock_source =

sys/dev/drm/amd/display/dc/core/dc_resource.c

2685

if (pipe_ctx->clock_source == NULL)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2690

pipe_ctx->clock_source);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2701

struct pipe_ctx *pipe_ctx_old,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2702

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2707

if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2710

if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2713

if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2716

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source

sys/dev/drm/amd/display/dc/core/dc_resource.c

2717

&& pipe_ctx_old->stream != pipe_ctx->stream)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2720

if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2723

if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))

sys/dev/drm/amd/display/dc/core/dc_resource.c

2726

if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))

sys/dev/drm/amd/display/dc/core/dc_resource.c

2729

if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2732

if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))

sys/dev/drm/amd/display/dc/core/dc_resource.c

387

const struct pipe_ctx *pipe_with_clk_src,

sys/dev/drm/amd/display/dc/core/dc_resource.c

388

const struct pipe_ctx *pipe)

sys/dev/drm/amd/display/dc/core/dc_resource.c

419

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

424

if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))

sys/dev/drm/amd/display/dc/core/dc_resource.c

425

return res_ctx->pipe_ctx[i].clock_source;

sys/dev/drm/amd/display/dc/core/dc_resource.c

487

static void calculate_viewport(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

489

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

490

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

491

struct scaler_data *data = &pipe_ctx->plane_res.scl_data;

sys/dev/drm/amd/display/dc/core/dc_resource.c

496

bool pri_split = pipe_ctx->bottom_pipe &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

497

pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

498

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

499

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

505

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

508

} else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)

sys/dev/drm/amd/display/dc/core/dc_resource.c

510

else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/drm/amd/display/dc/core/dc_resource.c

519

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/drm/amd/display/dc/core/dc_resource.c

520

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/drm/amd/display/dc/core/dc_resource.c

566

if (pipe_ctx->plane_state->horizontal_mirror) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

615

static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full)

sys/dev/drm/amd/display/dc/core/dc_resource.c

617

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

618

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

621

bool pri_split = pipe_ctx->bottom_pipe &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

622

pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

623

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

624

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

627

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/drm/amd/display/dc/core/dc_resource.c

628

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/drm/amd/display/dc/core/dc_resource.c

631

pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;

sys/dev/drm/amd/display/dc/core/dc_resource.c

633

pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x

sys/dev/drm/amd/display/dc/core/dc_resource.c

637

pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *

sys/dev/drm/amd/display/dc/core/dc_resource.c

639

if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >

sys/dev/drm/amd/display/dc/core/dc_resource.c

641

pipe_ctx->plane_res.scl_data.recout.width =

sys/dev/drm/amd/display/dc/core/dc_resource.c

643

- pipe_ctx->plane_res.scl_data.recout.x;

sys/dev/drm/amd/display/dc/core/dc_resource.c

645

pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;

sys/dev/drm/amd/display/dc/core/dc_resource.c

647

pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y

sys/dev/drm/amd/display/dc/core/dc_resource.c

651

pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *

sys/dev/drm/amd/display/dc/core/dc_resource.c

653

if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >

sys/dev/drm/amd/display/dc/core/dc_resource.c

655

pipe_ctx->plane_res.scl_data.recout.height =

sys/dev/drm/amd/display/dc/core/dc_resource.c

657

- pipe_ctx->plane_res.scl_data.recout.y;

sys/dev/drm/amd/display/dc/core/dc_resource.c

661

pipe_ctx->plane_res.scl_data.recout.y +=

sys/dev/drm/amd/display/dc/core/dc_resource.c

662

pipe_ctx->plane_res.scl_data.recout.height / 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

664

pipe_ctx->plane_res.scl_data.recout.height =

sys/dev/drm/amd/display/dc/core/dc_resource.c

665

(pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

667

pipe_ctx->plane_res.scl_data.recout.height /= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

679

pipe_ctx->plane_res.scl_data.recout.x +=

sys/dev/drm/amd/display/dc/core/dc_resource.c

680

pipe_ctx->plane_res.scl_data.recout.width / 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

682

pipe_ctx->plane_res.scl_data.recout.width =

sys/dev/drm/amd/display/dc/core/dc_resource.c

683

(pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

685

if (pipe_ctx->plane_res.scl_data.recout.width > 1)

sys/dev/drm/amd/display/dc/core/dc_resource.c

686

pipe_ctx->plane_res.scl_data.recout.width /= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

708

static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

710

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

711

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/core/dc_resource.c

718

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/drm/amd/display/dc/core/dc_resource.c

719

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/drm/amd/display/dc/core/dc_resource.c

722

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(

sys/dev/drm/amd/display/dc/core/dc_resource.c

725

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(

sys/dev/drm/amd/display/dc/core/dc_resource.c

730

pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

732

pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

734

pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(

sys/dev/drm/amd/display/dc/core/dc_resource.c

735

pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);

sys/dev/drm/amd/display/dc/core/dc_resource.c

736

pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(

sys/dev/drm/amd/display/dc/core/dc_resource.c

737

pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);

sys/dev/drm/amd/display/dc/core/dc_resource.c

739

pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;

sys/dev/drm/amd/display/dc/core/dc_resource.c

740

pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;

sys/dev/drm/amd/display/dc/core/dc_resource.c

742

if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8

sys/dev/drm/amd/display/dc/core/dc_resource.c

743

|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

744

pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

745

pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;

sys/dev/drm/amd/display/dc/core/dc_resource.c

747

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(

sys/dev/drm/amd/display/dc/core/dc_resource.c

748

pipe_ctx->plane_res.scl_data.ratios.horz, 19);

sys/dev/drm/amd/display/dc/core/dc_resource.c

749

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(

sys/dev/drm/amd/display/dc/core/dc_resource.c

750

pipe_ctx->plane_res.scl_data.ratios.vert, 19);

sys/dev/drm/amd/display/dc/core/dc_resource.c

751

pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(

sys/dev/drm/amd/display/dc/core/dc_resource.c

752

pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);

sys/dev/drm/amd/display/dc/core/dc_resource.c

753

pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(

sys/dev/drm/amd/display/dc/core/dc_resource.c

754

pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);

sys/dev/drm/amd/display/dc/core/dc_resource.c

757

static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct rect *recout_full)

sys/dev/drm/amd/display/dc/core/dc_resource.c

759

struct scaler_data *data = &pipe_ctx->plane_res.scl_data;

sys/dev/drm/amd/display/dc/core/dc_resource.c

760

struct rect src = pipe_ctx->plane_state->src_rect;

sys/dev/drm/amd/display/dc/core/dc_resource.c

768

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

771

} else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)

sys/dev/drm/amd/display/dc/core/dc_resource.c

773

else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/drm/amd/display/dc/core/dc_resource.c

776

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/drm/amd/display/dc/core/dc_resource.c

777

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

782

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270 &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

783

pipe_ctx->plane_state->horizontal_mirror) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

786

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

787

pipe_ctx->plane_state->horizontal_mirror) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

790

} else if (pipe_ctx->plane_state->horizontal_mirror)

sys/dev/drm/amd/display/dc/core/dc_stream.c

183

struct pipe_ctx *pipe_to_program = NULL;

sys/dev/drm/amd/display/dc/core/dc_stream.c

204

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_stream.c

206

if (pipe_ctx->stream != stream)

sys/dev/drm/amd/display/dc/core/dc_stream.c

210

pipe_to_program = pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_stream.c

214

core_dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_stream.c

216

core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_stream.c

232

struct pipe_ctx *pipe_to_program = NULL;

sys/dev/drm/amd/display/dc/core/dc_stream.c

249

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_stream.c

251

if (pipe_ctx->stream != stream ||

sys/dev/drm/amd/display/dc/core/dc_stream.c

252

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

sys/dev/drm/amd/display/dc/core/dc_stream.c

253

!pipe_ctx->plane_state ||

sys/dev/drm/amd/display/dc/core/dc_stream.c

254

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

sys/dev/drm/amd/display/dc/core/dc_stream.c

255

!pipe_ctx->plane_res.ipp)

sys/dev/drm/amd/display/dc/core/dc_stream.c

259

pipe_to_program = pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_stream.c

263

core_dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc_stream.c

280

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

sys/dev/drm/amd/display/dc/core/dc_stream.c

282

if (res_ctx->pipe_ctx[i].stream != stream)

sys/dev/drm/amd/display/dc/core/dc_stream.c

304

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

sys/dev/drm/amd/display/dc/core/dc_stream.c

306

if (res_ctx->pipe_ctx[i].stream != stream)

sys/dev/drm/amd/display/dc/core/dc_surface.c

119

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/core/dc_surface.c

120

&core_dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc_surface.c

122

if (pipe_ctx->plane_state != plane_state)

sys/dev/drm/amd/display/dc/core/dc_surface.c

125

core_dc->hwss.update_pending_status(pipe_ctx);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

551

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

553

if (!pipe_ctx->plane_state)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

556

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

557

pipe_ctx->plane_res.dpp,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

716

if (res_ctx->pipe_ctx[i].stream) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

717

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

719

signal_type = pipe_ctx->stream->sink->link->connector_signal;

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

531

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

139

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

141

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

145

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

148

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

150

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

752

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

754

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

757

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

759

resource_build_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

773

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1000

if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1004

pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1011

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1012

pipe_ctx->stream_res.stream_enc, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1016

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1018

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1020

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1021

pipe_ctx->stream_res.stream_enc, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1022

if (pipe_ctx->stream_res.audio) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1028

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1031

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1032

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1033

pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1035

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1036

pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1041

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1042

pipe_ctx->stream_res.audio = NULL;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1056

void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1058

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1060

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1062

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1063

pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1064

pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1066

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1067

pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1068

pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1070

dc->hwss.disable_audio_stream(pipe_ctx, option);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1074

pipe_ctx->stream_res.stream_enc->id,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1079

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1083

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1088

pipe_ctx->stream->timing.pix_clk_khz;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1091

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1092

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1099

void dce110_blank_stream(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1101

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1109

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1110

pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1114

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1116

if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1117

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1142

const struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1145

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1146

audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1148

audio_output->signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1182

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1185

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1188

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1191

if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1195

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1200

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1201

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1208

pipe_ctx->pll_settings.feedback_divider;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1212

pipe_ctx->stream_res.tg->inst + 1);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1218

pipe_ctx->pll_settings.ss_percentage;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1221

static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1224

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1226

switch (pipe_ctx->plane_res.scl_data.format) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1257

const struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1263

if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1268

get_surface_visual_confirm_color(pipe_ctx, &color);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1271

pipe_ctx->stream->output_color_space,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1274

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1275

pipe_ctx->plane_res.xfm,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1276

pipe_ctx->plane_res.scl_data.lb_params.depth,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1277

&pipe_ctx->stream->bit_depth_params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1279

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1285

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1288

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1289

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1293

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1294

&pipe_ctx->plane_res.scl_data);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1298

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1302

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1303

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1304

pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1314

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1315

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1322

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1324

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1325

pipe_ctx->clock_source,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1326

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1327

&pipe_ctx->pll_settings)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1332

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1333

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1339

if (pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1340

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1341

pipe_ctx->stream_res.tg, &params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1347

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1348

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1349

pipe_ctx->stream_res.tg, event_triggers);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1353

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1354

pipe_ctx->stream_res.tg)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1364

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1368

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1370

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1373

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1375

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1376

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1377

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1378

pipe_ctx->stream_res.audio->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1379

&pipe_ctx->stream->audio_info);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1381

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1382

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1383

pipe_ctx->stream_res.audio->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1384

&pipe_ctx->stream->audio_info,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1387

pipe_ctx->stream_res.audio->funcs->az_configure(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1388

pipe_ctx->stream_res.audio,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1389

pipe_ctx->stream->signal,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1391

&pipe_ctx->stream->audio_info);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1395

dc->hwss.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1398

if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1399

if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1405

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1406

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1409

pipe_ctx->stream->signal);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1411

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1412

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1417

core_link_enable_stream(context, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1419

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1421

pipe_ctx->stream->sink->link->psr_enabled = false;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1514

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1516

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1637

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1640

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1644

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1645

pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1646

pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1654

pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1655

pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1678

if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1681

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1682

res_ctx->pipe_ctx[i].plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1690

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1691

res_ctx->pipe_ctx[i].plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1704

static void set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1720

pipe_ctx[i]->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1721

pipe_ctx[i]->stream_res.tg, &params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1724

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1725

pipe_ctx[i]->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1730

static void get_position(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1739

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1742

static void set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1758

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1765

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1766

set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1780

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1782

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1786

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1789

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1791

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1805

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1820

if (res_ctx->pipe_ctx[i].stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1821

pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1828

ASSERT(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1831

if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1835

if (pipe_ctx->stream->sink->link->psr_enabled)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1839

if (!pipe_ctx->plane_state)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1843

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1861

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1864

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1865

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1885

struct pipe_ctx *pipe_ctx_old =

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1886

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1887

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1898

if (!pipe_ctx->stream ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1899

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1905

if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1955

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1957

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1960

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1963

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1966

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1969

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1971

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1972

pipe_ctx->stream_res.audio,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1973

pipe_ctx->stream->signal,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1983

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1985

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1988

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1991

if (!dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1994

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1997

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1999

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2000

pipe_ctx->stream_res.audio,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2001

pipe_ctx->stream->signal,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2032

struct pipe_ctx *pipe_ctx_old =

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2033

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2034

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2036

if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2039

if (pipe_ctx->stream == pipe_ctx_old->stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2040

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2042

pipe_ctx->clock_source, i);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2057

struct pipe_ctx *pipe_ctx_old =

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2058

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2059

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2061

if (pipe_ctx->stream == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2064

if (pipe_ctx->stream == pipe_ctx_old->stream)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2067

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2070

if (pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2074

pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2095

static void set_default_colors(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2100

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2101

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2103

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2107

pipe_ctx->stream->timing.display_color_depth;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2110

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2112

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2113

pipe_ctx->plane_res.xfm, &default_adjust);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2137

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2142

if (pipe_ctx->bottom_pipe) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2145

ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2147

if (pipe_ctx->bottom_pipe->plane_state->visible) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2148

if (pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2153

} else if (!pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2156

} else if (!pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2159

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2160

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2164

static void program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2172

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2177

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2180

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2183

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2185

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2190

pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2191

pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2198

static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2200

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2206

pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2207

pipe_ctx->plane_res.mi);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2210

pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2212

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2213

if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2214

pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2216

!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2268

struct pipe_ctx *grouped_pipes[])

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2313

struct pipe_ctx *grouped_pipes[])

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2422

const struct pipe_ctx *pipe_ctx = NULL;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2425

if (stream == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2426

pipe_ctx = &context->res_ctx.pipe_ctx[k];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2430

ASSERT(pipe_ctx != NULL);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2437

cfg->signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2438

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2599

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2601

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2602

struct pipe_ctx *old_pipe = NULL;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2603

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2612

old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2619

set_default_colors(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2620

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2623

pipe_ctx->stream->output_color_space;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2627

pipe_ctx->stream->csc_color_matrix.matrix[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2629

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2630

(pipe_ctx->plane_res.xfm, &tbl_entry);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2633

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2638

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2641

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2643

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2645

program_scaler(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2649

pipe_ctx->pipe_idx != underlay_idx) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2665

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2669

pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

267

dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2675

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2676

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2677

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2678

dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2680

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2681

dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2689

pipe_ctx->pipe_idx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2690

(void *) pipe_ctx->plane_state,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2691

pipe_ctx->plane_state->address.grph.addr.high_part,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2692

pipe_ctx->plane_state->address.grph.addr.low_part,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2693

pipe_ctx->plane_state->src_rect.x,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2694

pipe_ctx->plane_state->src_rect.y,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2695

pipe_ctx->plane_state->src_rect.width,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2696

pipe_ctx->plane_state->src_rect.height,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2697

pipe_ctx->plane_state->dst_rect.x,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2698

pipe_ctx->plane_state->dst_rect.y,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2699

pipe_ctx->plane_state->dst_rect.width,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

270

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2700

pipe_ctx->plane_state->dst_rect.height,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2701

pipe_ctx->plane_state->clip_rect.x,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2702

pipe_ctx->plane_state->clip_rect.y,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2703

pipe_ctx->plane_state->clip_rect.width,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2704

pipe_ctx->plane_state->clip_rect.height);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2710

pipe_ctx->pipe_idx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2711

pipe_ctx->plane_res.scl_data.viewport.width,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2712

pipe_ctx->plane_res.scl_data.viewport.height,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2713

pipe_ctx->plane_res.scl_data.viewport.x,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2714

pipe_ctx->plane_res.scl_data.viewport.y,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2715

pipe_ctx->plane_res.scl_data.recout.width,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2716

pipe_ctx->plane_res.scl_data.recout.height,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2717

pipe_ctx->plane_res.scl_data.recout.x,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2718

pipe_ctx->plane_res.scl_data.recout.y);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2733

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2734

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2736

if (stream == pipe_ctx->stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2737

if (!pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2738

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2739

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2744

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2746

if (pipe_ctx->stream != stream)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2750

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2751

pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2752

pipe_ctx->stream->timing.h_total,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2753

pipe_ctx->stream->timing.v_total,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2754

pipe_ctx->stream->timing.pix_clk_khz,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2757

dce110_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2759

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2761

program_surface_visibility(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2766

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2767

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2769

if ((stream == pipe_ctx->stream) &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2770

(!pipe_ctx->top_pipe) &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2771

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2772

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2776

static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2778

int fe_idx = pipe_ctx->plane_res.mi ?

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2779

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2782

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2795

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2800

static void program_csc_matrix(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2807

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2810

pipe_ctx->stream->output_color_space;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2814

tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2818

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2823

void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2825

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2826

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2827

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2829

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2830

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2831

.viewport = pipe_ctx->plane_res.scl_data.viewport,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2832

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2833

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2834

.rotation = pipe_ctx->plane_state->rotation,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2835

.mirror = pipe_ctx->plane_state->horizontal_mirror

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2838

if (pipe_ctx->plane_state->address.type

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2842

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2852

void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2854

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2856

if (pipe_ctx->plane_res.ipp &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2857

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2858

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2859

pipe_ctx->plane_res.ipp, attributes);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2861

if (pipe_ctx->plane_res.mi &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2862

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2863

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2864

pipe_ctx->plane_res.mi, attributes);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2866

if (pipe_ctx->plane_res.xfm &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2867

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2868

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2869

pipe_ctx->plane_res.xfm, attributes);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

595

dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

598

struct transform *xfm = pipe_ctx->plane_res.xfm;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

621

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

628

const struct dc_sink *sink = pipe_ctx->stream->sink;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

630

crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

631

crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

635

crtc_source_select.signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

637

crtc_source_select.sink_signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

639

switch (pipe_ctx->stream->timing.display_color_depth) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

669

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

674

ASSERT(pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

676

if (pipe_ctx->stream_res.stream_enc == NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

679

is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

680

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

686

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

687

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

688

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

690

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

691

pipe_ctx->stream_res.stream_enc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

692

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

695

void dce110_enable_stream(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

698

pipe_ctx->stream->sink->link->cur_link_settings.lane_count;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

700

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

701

struct dc_link *link = pipe_ctx->stream->sink->link;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

706

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

713

pipe_ctx->stream_res.stream_enc->id, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

717

dce110_update_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

734

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

735

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

736

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

990

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

992

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

997

if (pipe_ctx->stream_res.audio) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

44

void dce110_enable_stream(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

46

void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

48

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

51

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

53

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

54

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

56

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

58

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1016

static struct pipe_ctx *dce110_acquire_underlay(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1024

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1026

if (res_ctx->pipe_ctx[underlay_idx].stream)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1029

pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1030

pipe_ctx->plane_res.mi = pool->mis[underlay_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1032

pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1033

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1034

pipe_ctx->pipe_idx = underlay_idx;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1036

pipe_ctx->stream = stream;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1038

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1044

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1052

pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1056

pipe_ctx->stream_res.tg->funcs->enable_advanced_request(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1057

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1061

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1069

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1070

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1074

return pipe_ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

777

const struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

780

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

788

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

789

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

811

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

813

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

814

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

815

pipe_ctx->clock_source,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

816

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

817

&pipe_ctx->pll_settings);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

818

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

819

&pipe_ctx->stream->bit_depth_params);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

820

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

823

static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

825

if (pipe_ctx->pipe_idx != underlay_idx)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

827

if (!pipe_ctx->plane_state)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

829

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

839

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

841

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

844

if (!is_surface_pixel_format_supported(pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

848

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

852

resource_build_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

871

context->res_ctx.pipe_ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.h

41

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

799

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

801

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

804

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

806

resource_build_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

825

context->res_ctx.pipe_ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

889

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

892

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

895

if (dc_is_dp_signal(pipe_ctx->stream->signal)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

896

|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

897

pipe_ctx->clock_source =

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

900

pipe_ctx->clock_source = find_matching_pll(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

904

if (pipe_ctx->clock_source == NULL)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

910

pipe_ctx->clock_source);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1059

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1063

pipe_ctx->stream_res.tg = tg;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1064

pipe_ctx->pipe_idx = i;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1066

pipe_ctx->plane_res.hubp = hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1067

pipe_ctx->plane_res.dpp = dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1068

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1075

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1076

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1078

hwss1_plane_atomic_disconnect(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1090

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1092

dcn10_disable_plane(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1094

pipe_ctx->stream_res.tg = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1095

pipe_ctx->plane_res.hubp = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1143

struct pipe_ctx *pipe_ctx_old =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1144

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1145

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1153

if (!pipe_ctx->stream ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1154

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1166

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1168

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1169

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1170

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1172

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1174

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1181

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1193

static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1197

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1202

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1204

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1205

pipe_ctx->plane_res.hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1215

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1218

static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1221

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1273

dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1276

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1305

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1367

struct pipe_ctx *grouped_pipes[])

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1396

struct pipe_ctx *grouped_pipes[])

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1625

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1637

pipe_ctx->plane_res.hubp->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1640

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1643

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1644

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1685

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1692

static void program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1700

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1704

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1707

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1711

static void program_csc_matrix(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1715

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1716

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1717

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1719

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1720

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1725

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1730

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1731

program_csc_matrix(pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1736

static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1738

if (pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1740

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1745

static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1747

if (pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1749

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1754

static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1756

if (pipe_ctx->plane_state->visible)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1758

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1760

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1788

const struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1793

switch (pipe_ctx->plane_res.scl_data.format) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1824

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1830

struct pipe_ctx *top_pipe_ctx = pipe_ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1941

static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1943

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1945

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1949

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1957

pipe_ctx, &blnd_cfg.black_color);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1960

pipe_ctx, &blnd_cfg.black_color);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1963

dc, pipe_ctx->stream->output_color_space,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1975

if (pipe_ctx->plane_state->global_alpha)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1976

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1984

pipe_ctx->stream->output_color_space)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1999

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2025

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2029

static void update_scaler(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2032

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2036

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2037

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2039

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2040

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2045

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2048

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2049

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2050

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2077

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2081

&pipe_ctx->dlg_regs,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2082

&pipe_ctx->ttu_regs,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2083

&pipe_ctx->rq_regs,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2084

&pipe_ctx->pipe_dlg_param);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2087

size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2096

dc->hwss.update_mpcc(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2103

update_scaler(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2111

&pipe_ctx->plane_res.scl_data.viewport,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2112

&pipe_ctx->plane_res.scl_data.viewport_c);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2115

if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2116

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2117

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2122

program_gamut_remap(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2125

pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2126

pipe_ctx->stream->output_color_space,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2127

pipe_ctx->stream->csc_color_matrix.matrix,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2152

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2154

if (is_pipe_tree_visible(pipe_ctx))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2160

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2165

struct stream_resource *stream_res = &pipe_ctx->stream_res;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2166

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2199

static void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2202

pipe_ctx->plane_state->sdr_white_level, 80);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2210

if (pipe_ctx->plane_state->sdr_white_level > 80)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2213

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2214

pipe_ctx->plane_res.dpp, hw_mult);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2219

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2222

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2223

dcn10_enable_plane(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2225

update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2227

set_hdr_multiplier(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2229

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2230

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2231

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2232

dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2240

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2241

dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2246

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2249

if (pipe_ctx->top_pipe == NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2250

bool blank = !is_pipe_tree_visible(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2252

pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2253

pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2254

pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2255

pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2256

pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2258

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2259

pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2261

dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2265

if (pipe_ctx->plane_state != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2266

dcn10_program_pipe(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2269

if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2270

program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2314

static struct pipe_ctx *find_top_pipe_for_stream(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2322

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2323

struct pipe_ctx *old_pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2324

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2326

if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2329

if (pipe_ctx->stream != stream)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2332

if (!pipe_ctx->top_pipe)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2333

return pipe_ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2347

struct pipe_ctx *top_pipe_to_program =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2365

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2366

struct pipe_ctx *old_pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2367

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2374

if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2383

pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2387

if (!pipe_ctx->plane_state &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2409

dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2444

static void set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2460

pipe_ctx[i]->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2461

pipe_ctx[i]->stream_res.tg, &params);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2463

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2464

pipe_ctx[i]->stream_res.tg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2469

static void get_position(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2478

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2481

static void set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2495

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2496

set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2536

static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2539

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2543

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2544

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2548

pipe_ctx->stream_res.tg->funcs->program_stereo(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2549

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2571

struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2579

if (!pipe_ctx->stream_res.opp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2583

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2587

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2610

static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2612

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2613

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2619

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2620

pipe_ctx->plane_res.hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2630

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2646

static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2648

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2649

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2650

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2652

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2653

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2654

.viewport = pipe_ctx->plane_res.scl_data.viewport,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2655

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2656

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2657

.rotation = pipe_ctx->plane_state->rotation,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2658

.mirror = pipe_ctx->plane_state->horizontal_mirror

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2661

pos_cpy.x -= pipe_ctx->plane_state->dst_rect.x;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2662

pos_cpy.y -= pipe_ctx->plane_state->dst_rect.y;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2664

if (pipe_ctx->plane_state->address.type

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2672

static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2674

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2676

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2677

pipe_ctx->plane_res.hubp, attributes);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2678

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2679

pipe_ctx->plane_res.dpp, attributes->color_format);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2682

static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2684

uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2690

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2705

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2706

pipe_ctx->plane_res.dpp, &opt_attr);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

619

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

634

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

638

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

648

if (pipe_ctx->top_pipe != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

656

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

658

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

659

pipe_ctx->clock_source,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

660

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

661

&pipe_ctx->pll_settings)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

665

pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

666

pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

667

pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

668

pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

670

pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

672

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

673

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

681

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

683

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

684

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

692

if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

693

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

694

pipe_ctx->stream_res.tg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

697

if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

698

!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

699

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

700

hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

701

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

705

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

712

if (pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

713

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

714

pipe_ctx->stream_res.tg, &params);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

719

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

720

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

721

pipe_ctx->stream_res.tg, event_triggers);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

736

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

741

if (pipe_ctx->stream_res.stream_enc == NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

742

pipe_ctx->stream = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

748

if (!pipe_ctx->stream->dpms_off)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

749

core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

750

else if (pipe_ctx->stream_res.audio) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

751

dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

760

if (pipe_ctx->top_pipe == NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

761

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

763

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

767

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

773

pipe_ctx->stream = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

775

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

788

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

789

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

790

if (pipe_ctx != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

791

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

813

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

814

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

815

if (pipe_ctx != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

816

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

826

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

827

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

828

if (pipe_ctx != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

829

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

836

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

837

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

838

if (pipe_ctx != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

839

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

848

struct pipe_ctx *pipe_ctx =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

849

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

850

if (pipe_ctx != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

851

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

880

void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

882

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

883

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

887

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

898

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

909

static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

912

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

919

hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

924

"Power gated front end %d\n", pipe_ctx->pipe_idx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

931

static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

933

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

934

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

937

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

943

if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

944

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

945

pipe_ctx->stream_res.opp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

951

plane_atomic_power_down(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

953

pipe_ctx->stream = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

954

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

955

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

956

pipe_ctx->top_pipe = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

957

pipe_ctx->bottom_pipe = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

958

pipe_ctx->plane_state = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

961

static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

965

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

968

plane_atomic_disable(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

973

pipe_ctx->pipe_idx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

40

void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

46

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1013

static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1016

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1018

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1019

pipe_ctx->clock_source,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1020

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1021

&pipe_ctx->pll_settings);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1023

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1025

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1026

&pipe_ctx->stream->bit_depth_params);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1027

build_clamping_params(pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1035

struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1055

if (!pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1058

build_pipe_hw_param(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1082

static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1088

struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1089

struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

979

const struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

982

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

985

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

986

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/inc/core_types.h

107

struct pipe_ctx *(*acquire_idle_pipe_for_layer)(

sys/dev/drm/amd/display/dc/inc/core_types.h

228

struct pipe_ctx *top_pipe;

sys/dev/drm/amd/display/dc/inc/core_types.h

229

struct pipe_ctx *bottom_pipe;

sys/dev/drm/amd/display/dc/inc/core_types.h

240

struct pipe_ctx pipe_ctx[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

79

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/core_types.h

81

void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);

sys/dev/drm/amd/display/dc/inc/core_types.h

83

void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/drm/amd/display/dc/inc/dce_calcs.h

35

struct pipe_ctx;

sys/dev/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/inc/hw/link_encoder.h

42

struct pipe_ctx;

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

103

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

107

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

115

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

118

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

121

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

125

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

136

struct pipe_ctx *grouped_pipes[]);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

141

struct pipe_ctx *grouped_pipes[]);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

153

void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

155

void (*update_info_frame)(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

157

void (*enable_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

159

void (*disable_stream)(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

162

void (*unblank_stream)(struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

165

void (*blank_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

167

void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

169

void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

173

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

177

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

185

void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

188

void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

191

void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

195

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

200

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

203

void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

211

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

226

void (*set_cursor_position)(struct pipe_ctx *pipe);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

227

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

228

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

63

struct pipe_ctx;

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

88

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

91

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

96

struct pipe_ctx *pipe_ctx,

sys/dev/drm/amd/display/dc/inc/resource.h

118

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/resource.h

124

struct pipe_ctx *resource_get_head_pipe_for_stream(

sys/dev/drm/amd/display/dc/inc/resource.h

135

struct pipe_ctx *find_idle_secondary_pipe(

sys/dev/drm/amd/display/dc/inc/resource.h

164

struct pipe_ctx *pipe_ctx_old,

sys/dev/drm/amd/display/dc/inc/resource.h

165

struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/resource.h

89

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/resource.h

95

void resource_build_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

208

core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;