engine_id
uint32_t engine_id, uint32_t queue_id,
uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
uint32_t engine_id, uint32_t queue_id,
uint32_t engine_id, uint32_t queue_id,
unsigned int engine_id,
retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
uint32_t engine_id, uint32_t queue_id,
uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
switch (cntl->engine_id) {
bp_params->engine_id, &atom_engine_id))
if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
params.ucDigId = (uint8_t)(cntl->engine_id);
if (ENGINE_ID_DIGB == cntl->engine_id)
if (ENGINE_ID_DIGB == cntl->engine_id)
if (ENGINE_ID_DIGB == cntl->engine_id)
cmd->dig_encoder_sel_to_atom(cntl->engine_id);
params.ucDigEncoderSel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
params.digid = (uint8_t)(cntl->engine_id);
ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
bool (*engine_bp_to_atom)(enum engine_id engine_id,
uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
enum engine_id eng_id,
enum engine_id eng_id;
enum engine_id id)
enum engine_id engineId;
uint32_t engine_id;
DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
uint32_t engine_id,
dce_i2c_hw->engine_id = engine_id;
uint32_t engine_id,
engine_id,
uint32_t engine_id,
engine_id,
uint32_t engine_id,
engine_id,
uint32_t engine_id;
uint32_t engine_id,
uint32_t engine_id,
uint32_t engine_id,
uint32_t engine_id,
cntl.engine_id = enc->preferred_engine;
cntl.engine_id = ENGINE_ID_UNKNOWN;
enum engine_id engine,
enum engine_id engine)
cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.engine_id = enc->preferred_engine;
cntl.engine_id = enc->preferred_engine;
enum engine_id engine,
enum engine_id eng_id,
cntl.engine_id = enc110->base.id;
cntl.engine_id = enc110->base.id;
cntl.engine_id = enc110->base.id;
enum engine_id eng_id,
enum engine_id eng_id,
audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
enum engine_id eng_id,
enum engine_id eng_id,
enum engine_id eng_id,
enum engine_id eng_id,
enum engine_id engine,
enum engine_id engine)
cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.engine_id = enc->preferred_engine;
cntl.engine_id = enc->preferred_engine;
cntl.engine_id = ENGINE_ID_UNKNOWN;
enum engine_id engine,
enum engine_id eng_id,
enum engine_id eng_id,
cntl.engine_id = enc1->base.id;
cntl.engine_id = enc1->base.id;
enum engine_id eng_id,
uint32_t engine_id;
DC_I2C_DDC_SELECT, hw_engine->engine_id);
hw_engine->engine_id = arg->engine_id;
uint32_t engine_id;
uint32_t engine_id;
engine_dce110->engine_id = arg_dce110->engine_id;
uint32_t engine_id;
uint32_t engine_id;
sw_arg.engine_id = i;
hw_arg_dce110.engine_id = i;
aux_init_data.engine_id = i;
engine->engine_id,
mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
engine->engine_id = arg->engine_id;
if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
(arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
uint32_t engine_id;
uint32_t engine_id;
engine->engine_id = arg->engine_id;
uint32_t engine_id;
uint32_t engine_id;
sw_arg.engine_id = i;
hw_arg.engine_id = i;
arg.engine_id = i;
enum engine_id preferred_engine;
enum engine_id engine,
enum engine_id id;
enum engine_id eng_id, struct dc_context *ctx);
enum engine_id engine,
enum engine_id engine_id;
enum engine_id engine_id;
enum engine_id engine_id;
enum engine_id engine_id;
enum engine_id engine_id;
static inline enum engine_id dal_graphics_object_id_get_engine_id(
return (enum engine_id) id.id;
uint32_t engine_id, uint32_t queue_id,
int *engine_id)
if (engine_id)
*engine_id = i;
ee->engine_id = -1;
ee->engine_id = i;
int engine_id = -1, len;
ecode = i915_error_generate_code(dev_priv, error, &engine_id);
INTEL_GEN(dev_priv), engine_id, ecode);
if (engine_id != -1 && error->engine[engine_id].context.pid)
error->engine[engine_id].context.comm,
error->engine[engine_id].context.pid);
if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
engine_name(m->i915, ee->engine_id));
if (error->engine[i].engine_id != -1)
int engine_id;
static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
switch (engine_id) {
MISSING_CASE(engine_id);
header->engine_id = 0;
uint8_t engine_id; /* Slot number of the flow switching engine */