games/hunt/hunt/list.c
165
int enable;
games/hunt/hunt/list.c
178
enable = 1;
games/hunt/hunt/list.c
179
setsockopt(s, SOL_SOCKET, SO_BROADCAST, &enable, sizeof enable);
lib/libu4bhid/descr.c
46
hid_set_immed(int fd, int enable)
lib/libu4bhid/descr.c
49
ret = ioctl(fd, USB_SET_IMMED, &enable);
lib/libu4bhid/usbhid.h
88
int hid_set_immed(int fd, int enable);
lib/libusb/libusb.h
448
int libusb_set_auto_detach_kernel_driver(libusb_device_handle *dev, int enable);
lib/libusb/libusb10.c
916
libusb_set_auto_detach_kernel_driver(libusb_device_handle *dev, int enable)
lib/libusb/libusb10.c
918
dev->auto_detach = (enable ? 1 : 0);
sbin/hammer2/cmd_emergency.c
37
int cmd_emergency_mode(const char *sel_path __unused, int enable,
sbin/hammer2/cmd_emergency.c
52
if (ioctl(fd, HAMMER2IOC_EMERG_MODE, &enable) == 0) {
sbin/hammer2/cmd_emergency.c
53
if (enable)
sbin/hammer2/hammer2.h
155
int cmd_emergency_mode(const char *sel_path, int enable,
stand/boot/common/isapnp.h
244
u_char enable; /* pnp enable */
sys/bus/cam/cam_ccb.h
807
u_int8_t enable;
sys/bus/cam/scsi/scsi_targ_bh.c
249
immed_ccb->cel.enable = 1;
sys/bus/cam/scsi/scsi_targ_bh.c
370
ccb->cel.enable = 0;
sys/bus/cam/scsi/scsi_target.c
123
static cam_status targendislun(struct cam_path *path, int enable,
sys/bus/cam/scsi/scsi_target.c
389
targendislun(struct cam_path *path, int enable, int grp6_len, int grp7_len)
sys/bus/cam/scsi/scsi_target.c
401
en_ccb->enable = enable ? 1 : 0;
sys/bus/cam/scsi/scsi_target.c
406
enable ? "en" : "dis", status);
sys/bus/firewire/fwohci.c
2069
fwohci_set_intr(struct firewire_comm *fc, int enable)
sys/bus/firewire/fwohci.c
2075
device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
sys/bus/firewire/fwohci.c
2076
if (enable) {
sys/bus/isa/isavar.h
36
typedef void isa_config_cb(void *arg, struct isa_config *config, int enable);
sys/bus/isa/pnp.c
236
pnp_set_config(void *arg, struct isa_config *config, int enable)
sys/bus/isa/pnp.c
309
pnp_write(PNP_ACTIVATE, enable ? 1 : 0);
sys/bus/u4b/input/ukbd.c
2152
.enable = &ukbd_enable,
sys/bus/u4b/uvc/uvc_drv.c
1156
if (video->enable) {
sys/bus/u4b/uvc/uvc_drv.c
1284
video->enable = 1;
sys/bus/u4b/uvc/uvc_drv.c
1342
video->enable = 0;
sys/bus/u4b/uvc/uvc_drv.c
444
if (video->enable) {
sys/bus/u4b/uvc/uvc_drv.h
702
uint64_t enable;
sys/bus/u4b/uvc/uvc_v4l2.c
389
DPRINTF("enable:%lu\n", v->enable);
sys/bus/u4b/wlan/if_mtw.c
442
mtw_wlan_enable(struct mtw_softc *sc, int enable)
sys/bus/u4b/wlan/if_mtw.c
447
if (enable) {
sys/bus/u4b/wlan/if_urtwn.c
4714
urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable)
sys/bus/u4b/wlan/if_urtwn.c
4719
if (enable)
sys/cpu/x86_64/misc/cputimer_tsc.c
125
int enable = 1;
sys/cpu/x86_64/misc/cputimer_tsc.c
137
TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable);
sys/cpu/x86_64/misc/cputimer_tsc.c
138
if (!enable)
sys/dev/acpica/acpi.c
2697
acpi_wake_set_enable(device_t dev, int enable)
sys/dev/acpica/acpi.c
2708
if (enable) {
sys/dev/acpica/acpi.c
2866
int enable, error;
sys/dev/acpica/acpi.c
2870
enable = (acpi_get_flags(dev) & ACPI_FLAG_WAKE_ENABLED) ? 1 : 0;
sys/dev/acpica/acpi.c
2872
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/dev/acpica/acpi.c
2875
if (enable != 0 && enable != 1)
sys/dev/acpica/acpi.c
2878
return (acpi_wake_set_enable(dev, enable));
sys/dev/acpica/acpi_powerres.c
529
acpi_pwr_wake_enable(ACPI_HANDLE consumer, int enable)
sys/dev/acpica/acpi_powerres.c
553
if (enable)
sys/dev/acpica/acpivar.h
373
int acpi_wake_set_enable(device_t dev, int enable);
sys/dev/acpica/acpivar.h
431
ACPI_STATUS acpi_pwr_wake_enable(ACPI_HANDLE consumer, int enable);
sys/dev/disk/ahci/ahci.c
4049
int feature, int enable)
sys/dev/disk/ahci/ahci.c
4062
xa->fis->features = enable ? ATA_SF_SATAFT_ENA : ATA_SF_SATAFT_DIS;
sys/dev/disk/ahci/ahci.h
605
int feature, int enable);
sys/dev/disk/buslogic/btreg.h
188
u_int8_t enable;
sys/dev/disk/buslogic/btreg.h
192
u_int8_t enable;
sys/dev/disk/buslogic/btreg.h
229
u_int8_t enable;
sys/dev/disk/buslogic/btreg.h
304
u_int8_t enable;
sys/dev/disk/isp/isp_freebsd.c
3608
ccb->cel.enable = 1;
sys/dev/disk/isp/isp_freebsd.c
3620
ccb->cel.enable = 1;
sys/dev/disk/isp/isp_freebsd.c
4409
if (ccb->cel.enable) {
sys/dev/disk/mpt/mpt.c
201
.enable = mpt_stdenable,
sys/dev/disk/mpt/mpt.c
2203
error = pers->enable(mpt);
sys/dev/disk/mpt/mpt.h
181
mpt_enable_handler_t *enable; /* enable device */
sys/dev/disk/mpt/mpt_cam.c
179
.enable = mpt_cam_enable,
sys/dev/disk/mpt/mpt_cam.c
3660
if (ccb->cel.enable)
sys/dev/disk/mpt/mpt_raid.c
112
struct mpt_raid_volume *mpt_vol, int enable);
sys/dev/disk/mpt/mpt_raid.c
863
int enable)
sys/dev/disk/mpt/mpt_raid.c
878
if ((enabled && enable)
sys/dev/disk/mpt/mpt_raid.c
879
|| (!enabled && !enable))
sys/dev/disk/mpt/mpt_raid.c
890
enable ? MPI_RAID_ACTION_ENABLE_VOLUME
sys/dev/disk/mpt/mpt_raid.c
897
enable ? "Enable" : "Disable");
sys/dev/disk/mpt/mpt_raid.c
905
enable ? "Enable" : "Disable",
sys/dev/disk/mpt/mpt_raid.c
93
.enable = mpt_raid_enable,
sys/dev/disk/mpt/mpt_user.c
68
.enable = mpt_user_enable,
sys/dev/disk/nvme/nvme.c
100
if (enable) {
sys/dev/disk/nvme/nvme.c
110
(enable ? "enable" : "disable"));
sys/dev/disk/nvme/nvme.c
60
nvme_enable(nvme_softc_t *sc, int enable)
sys/dev/disk/nvme/nvme.c
67
if (enable == 0 && (reg & NVME_CONFIG_EN)) {
sys/dev/disk/nvme/nvme.c
73
} else if (enable && (reg & NVME_CONFIG_EN) == 0) {
sys/dev/disk/nvme/nvme.c
84
if (enable == 0 && (reg & NVME_STATUS_RDY) == 0) {
sys/dev/disk/nvme/nvme.c
88
if (enable && (reg & NVME_STATUS_RDY)) {
sys/dev/disk/nvme/nvme.h
289
int nvme_enable(nvme_softc_t *sc, int enable);
sys/dev/disk/sili/sili.h
898
int sili_pm_set_feature(struct sili_port *ap, int feature, int enable);
sys/dev/disk/sili/sili_pm.c
544
sili_pm_set_feature(struct sili_port *ap, int feature, int enable)
sys/dev/disk/sili/sili_pm.c
553
xa->fis->command = enable ? ATA_C_SATA_FEATURE_ENA :
sys/dev/drm/amd/amdgpu/amdgpu.h
749
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
755
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
757
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
761
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
763
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
774
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
778
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu.h
782
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_acp.c
519
bool enable = state == AMD_PG_STATE_GATE ? true : false;
sys/dev/drm/amd/amdgpu/amdgpu_acp.c
523
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
sys/dev/drm/amd/amdgpu/amdgpu_gfx.c
390
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/amdgpu_gfx.c
401
if (!enable)
sys/dev/drm/amd/amdgpu/amdgpu_gfx.c
406
if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
sys/dev/drm/amd/amdgpu/amdgpu_gfx.c
408
} else if (!enable && adev->gfx.gfx_off_state) {
sys/dev/drm/amd/amdgpu/amdgpu_gfx.h
359
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_gmc.h
81
void (*set_prt)(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
1960
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
1965
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
1970
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
1975
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
sys/dev/drm/amd/amdgpu/amdgpu_pm.h
39
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_pm.h
40
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1959
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1966
adev->mman.buffer_funcs_enabled == enable)
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1969
if (enable) {
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1988
if (enable)
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1993
adev->mman.buffer_funcs_enabled = enable;
sys/dev/drm/amd/amdgpu/amdgpu_ttm.h
84
bool enable);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2166
bool enable;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2169
enable = !!atomic_read(&adev->vm_manager.num_prt_users);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2170
adev->gmc.gmc_funcs->set_prt(adev, enable);
sys/dev/drm/amd/amdgpu/atombios_crtc.c
242
int enable,
sys/dev/drm/amd/amdgpu/atombios_crtc.c
251
if (enable) {
sys/dev/drm/amd/amdgpu/atombios_crtc.c
295
args.v3.ucEnable = enable;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1042
bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1047
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
1583
bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1587
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
1632
static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1637
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
1772
static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1776
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2037
bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2041
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2095
bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2099
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
2151
static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2156
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
3249
static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
3255
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4075
static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4086
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
4119
return (amdgpu_ci_send_msg_to_smc(adev, enable ?
sys/dev/drm/amd/amdgpu/ci_dpm.c
4124
static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4135
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
4151
return (amdgpu_ci_send_msg_to_smc(adev, enable ?
sys/dev/drm/amd/amdgpu/ci_dpm.c
4157
static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4168
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
4183
return (amdgpu_ci_send_msg_to_smc(adev, enable ?
sys/dev/drm/amd/amdgpu/ci_dpm.c
4188
static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4199
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
4215
return (amdgpu_ci_send_msg_to_smc(adev, enable ?
sys/dev/drm/amd/amdgpu/ci_dpm.c
649
static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
656
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
665
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
674
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
683
if (enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
739
static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
748
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
756
ci_do_enable_didt(adev, enable);
sys/dev/drm/amd/amdgpu/ci_dpm.c
764
static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
770
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
822
static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
829
if (enable) {
sys/dev/drm/amd/amdgpu/ci_dpm.c
847
bool enable)
sys/dev/drm/amd/amdgpu/ci_dpm.c
853
if (enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
343
static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
374
if (enable) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
400
static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
405
if (!enable) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
412
if (enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
898
bool enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
902
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
919
bool enable)
sys/dev/drm/amd/amdgpu/cik_sdma.c
923
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1391
bool enable)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1397
enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1724
static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1735
if (enable && dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1737
if (!enable && !dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1740
if (!enable && dig->afmt->pin) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1745
dig->afmt->enabled = enable;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1748
enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1796
static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1804
if (enable)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1810
static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1816
if (enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1417
bool enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1423
enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1766
static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1777
if (enable && dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1779
if (!enable && !dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1782
if (!enable && dig->afmt->pin) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1787
dig->afmt->enabled = enable;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1790
enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1838
static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1846
if (enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1852
static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1858
if (enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1345
bool enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1351
enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1653
static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1664
if (enable && dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1666
if (!enable && !dig->afmt->enabled)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1669
if (!enable && dig->afmt->pin) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1674
dig->afmt->enabled = enable;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1677
enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1725
static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1733
if (enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1739
static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1745
if (enable)
sys/dev/drm/amd/amdgpu/df_v1_7.c
106
bool enable)
sys/dev/drm/amd/amdgpu/df_v1_7.c
109
ForceParWrRMW, enable);
sys/dev/drm/amd/amdgpu/df_v1_7.c
37
bool enable)
sys/dev/drm/amd/amdgpu/df_v1_7.c
41
if (enable) {
sys/dev/drm/amd/amdgpu/df_v1_7.c
71
bool enable)
sys/dev/drm/amd/amdgpu/df_v1_7.c
78
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
sys/dev/drm/amd/amdgpu/df_v3_6.c
38
bool enable)
sys/dev/drm/amd/amdgpu/df_v3_6.c
42
if (enable) {
sys/dev/drm/amd/amdgpu/df_v3_6.c
74
bool enable)
sys/dev/drm/amd/amdgpu/df_v3_6.c
81
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2397
static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2401
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2669
static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2673
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3119
static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3121
gfx_v7_0_cp_gfx_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3122
gfx_v7_0_cp_compute_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3140
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3144
if (enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3375
static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3380
if (enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3591
static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3597
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3634
static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3638
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3720
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3724
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3735
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3740
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3749
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3754
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3762
static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3767
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3775
static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3780
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3857
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3861
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3928
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3933
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3942
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3947
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4007
static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4009
gfx_v7_0_enable_gfx_cgpg(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4010
gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4011
gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3951
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3955
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3956
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3957
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3958
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4111
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4113
WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4117
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4119
WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4122
static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4124
WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4186
static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4191
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4390
static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4394
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4858
static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4860
gfx_v8_0_cp_gfx_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4861
gfx_v8_0_cp_compute_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5384
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5391
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5393
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5397
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5399
WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5403
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5405
WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5409
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5411
WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5415
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5417
WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5420
if (!enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5425
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5427
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5441
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5467
cz_update_gfx_cg_power_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5469
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5474
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5482
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5487
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5492
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5663
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5670
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5767
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5775
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5859
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5861
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5865
gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5866
gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5871
gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5872
gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1063
static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1065
WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2061
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2065
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2066
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2067
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2068
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2231
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2237
if (enable == true) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2299
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2307
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2313
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2321
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2327
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2335
enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2341
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2348
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2354
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2361
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2365
if (!enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2371
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2378
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2384
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2391
enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2532
static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2537
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2538
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2539
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2540
if (!enable) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2737
static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2741
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3339
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3341
gfx_v9_0_cp_gfx_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3342
gfx_v9_0_cp_compute_enable(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3667
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3671
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3684
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3689
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3694
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3703
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3708
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3774
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3781
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3822
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3828
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3870
bool enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3872
if (enable) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3876
gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3878
gfx_v9_0_update_3d_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3880
gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3885
gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3887
gfx_v9_0_update_3d_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3889
gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3903
bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3907
if (!enable) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3925
gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3928
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3930
if (enable)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3934
if (!enable) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
541
static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
545
if (enable && !adev->gmc.prt_warning) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
552
CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
554
CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
556
TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
558
TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
560
L2_CACHE_STORE_INVALID_ENTRIES, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
562
L1_TLB_STORE_INVALID_ENTRIES, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
564
MASK_PDE0_FAULT, enable);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
567
if (enable) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
821
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
828
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
838
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
845
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
855
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
861
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
878
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
884
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
894
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
900
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1525
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1529
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1605
bool enable)
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1609
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
768
static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
772
if (enable && !adev->gmc.prt_warning) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
779
CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
781
CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
783
TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
785
TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
787
L2_CACHE_STORE_INVALID_ENTRIES, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
789
L1_TLB_STORE_INVALID_ENTRIES, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
791
MASK_PDE0_FAULT, enable);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
794
if (enable) {
sys/dev/drm/amd/amdgpu/kv_dpm.c
118
static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1210
static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1212
return amdgpu_kv_notify_message_to_smu(adev, enable ?
sys/dev/drm/amd/amdgpu/kv_dpm.c
1247
static void kv_dpm_enable_bapm(void *handle, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1254
ret = amdgpu_kv_smc_bapm_enable(adev, enable);
sys/dev/drm/amd/amdgpu/kv_dpm.c
128
if (enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1470
static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1472
return amdgpu_kv_notify_message_to_smu(adev, enable ?
sys/dev/drm/amd/amdgpu/kv_dpm.c
1476
static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1478
return amdgpu_kv_notify_message_to_smu(adev, enable ?
sys/dev/drm/amd/amdgpu/kv_dpm.c
1482
static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1484
return amdgpu_kv_notify_message_to_smu(adev, enable ?
sys/dev/drm/amd/amdgpu/kv_dpm.c
1488
static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1490
return amdgpu_kv_notify_message_to_smu(adev, enable ?
sys/dev/drm/amd/amdgpu/kv_dpm.c
1858
bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
1863
if (enable) {
sys/dev/drm/amd/amdgpu/kv_dpm.c
2322
u32 index, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
2326
pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
sys/dev/drm/amd/amdgpu/kv_dpm.c
460
static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
467
if (enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
476
if (enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
485
if (enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
49
bool enable);
sys/dev/drm/amd/amdgpu/kv_dpm.c
494
if (enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
502
static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
513
if (enable) {
sys/dev/drm/amd/amdgpu/kv_dpm.c
521
kv_do_enable_didt(adev, enable);
sys/dev/drm/amd/amdgpu/kv_dpm.c
562
static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
568
if (enable) {
sys/dev/drm/amd/amdgpu/kv_dpm.c
719
u32 index, bool enable)
sys/dev/drm/amd/amdgpu/kv_dpm.c
723
pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
sys/dev/drm/amd/amdgpu/kv_dpm.h
223
int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/kv_dpm.h
224
int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/kv_smc.c
106
int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_smc.c
108
if (enable)
sys/dev/drm/amd/amdgpu/kv_smc.c
114
int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/kv_smc.c
116
if (enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
277
bool enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
282
if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
410
bool enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
422
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
473
bool enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
479
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
489
bool enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
495
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
505
bool enable)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
511
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
sys/dev/drm/amd/amdgpu/mmhub_v1_0.h
36
bool enable);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
102
if (enable) {
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
148
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
153
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
176
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
181
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
46
static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
48
if (enable)
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
92
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
94
WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
98
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
132
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
139
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
150
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
161
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
171
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
176
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
47
static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
49
if (enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
89
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
91
WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
95
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
127
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
133
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
138
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
45
static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
47
if (enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
87
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
89
WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
93
bool enable)
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
97
if (enable) {
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
376
static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
381
if (!enable) {
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
388
if (enable)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1450
bool enable)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1455
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1489
bool enable)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1494
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
550
static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
581
if (enable) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
611
static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
616
if (!enable) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
623
if (enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1523
bool enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1527
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1588
bool enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1592
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
604
static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
636
AUTO_CTXSW_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
637
if (enable && amdgpu_sdma_phase_quantum) {
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
658
static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
663
if (enable == false) {
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
670
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
819
sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
823
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
sys/dev/drm/amd/amdgpu/si_dpm.c
2535
bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
2542
if (enable) {
sys/dev/drm/amd/amdgpu/si_dpm.c
2899
bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
2907
if (enable) {
sys/dev/drm/amd/amdgpu/si_dpm.c
3773
bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
3777
if (enable) {
sys/dev/drm/amd/amdgpu/si_dpm.c
3800
static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
3802
if (enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
4048
bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
4050
if (enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
4191
static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
4195
if (enable) {
sys/dev/drm/amd/amdgpu/si_dpm.c
6162
static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
6164
if (enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
6393
bool enable)
sys/dev/drm/amd/amdgpu/si_dpm.c
6397
if (enable) {
sys/dev/drm/amd/amdgpu/sislands_smc.h
412
void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
sys/dev/drm/amd/amdgpu/soc15.c
476
bool enable)
sys/dev/drm/amd/amdgpu/soc15.c
478
adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
sys/dev/drm/amd/amdgpu/soc15.c
479
adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
sys/dev/drm/amd/amdgpu/soc15.c
879
static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/soc15.c
886
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
sys/dev/drm/amd/amdgpu/soc15.c
902
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
sys/dev/drm/amd/amdgpu/soc15.c
912
static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/soc15.c
918
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
sys/dev/drm/amd/amdgpu/soc15.c
941
static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/soc15.c
947
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
sys/dev/drm/amd/amdgpu/soc15.c
957
bool enable)
sys/dev/drm/amd/amdgpu/soc15.c
963
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
147
bool enable);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
586
bool enable)
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
590
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
47
bool enable);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
611
static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
624
if (enable) {
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
746
bool enable)
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
750
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
775
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
777
if (enable) {
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1256
static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1277
if (enable) {
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1403
bool enable)
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1407
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1432
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1434
if (enable) {
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
54
bool enable);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
623
bool enable)
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
629
if (enable) {
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1684
static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1688
if (enable)
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1703
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1705
uvd_v7_0_set_bypass_mode(adev, enable);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1710
if (enable) {
sys/dev/drm/amd/amdgpu/vce_v2_0.c
383
static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
sys/dev/drm/amd/amdgpu/vce_v2_0.c
386
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
sys/dev/drm/amd/amdgpu/vce_v3_0.c
748
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/vce_v3_0.c
762
if (!enable) {
sys/dev/drm/amd/amdgpu/vce_v3_0.c
776
vce_v3_0_set_vce_sw_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
873
static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
sys/dev/drm/amd/amdgpu/vce_v4_0.c
877
if (enable)
sys/dev/drm/amd/amdgpu/vce_v4_0.c
889
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
895
vce_v4_0_set_bypass_mode(adev, enable);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
908
if (enable) {
sys/dev/drm/amd/amdgpu/vce_v4_0.c
922
vce_v4_0_set_vce_sw_clock_gating(adev, enable);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1228
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1230
if (enable) {
sys/dev/drm/amd/amdgpu/vi.c
1273
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
1279
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
sys/dev/drm/amd/amdgpu/vi.c
1293
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
1299
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
sys/dev/drm/amd/amdgpu/vi.c
1309
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
1315
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
sys/dev/drm/amd/amdgpu/vi.c
1325
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
1331
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
sys/dev/drm/amd/amdgpu/vi.c
1342
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
1348
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
sys/dev/drm/amd/amdgpu/vi.c
873
bool enable)
sys/dev/drm/amd/amdgpu/vi.c
882
if (enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1978
bool enable = false;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2015
dm_new_crtc_state->freesync_enabled = enable;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2186
if (!crtc_state->enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2197
return !crtc_state->enable || !crtc_state->active;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3008
static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3015
return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4184
bool enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4195
if (enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4247
position->enable = false;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4275
position->enable = true;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4309
if (!position.enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4775
new_crtc_state->enable,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5158
bool enable,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5188
if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5196
if (aconnector && enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5250
new_crtc_state->enable,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5258
if (!enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5333
if (!(enable && aconnector && new_crtc_state->enable &&
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5376
bool enable,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5404
if (!enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5669
if (!new_crtc_state->enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
186
bool enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
209
if (enable) {
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
310
bool enable)
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
334
if (!enable)
sys/dev/drm/amd/display/dc/bios/bios_parser.c
787
bool enable)
sys/dev/drm/amd/display/dc/bios/bios_parser.c
795
bp, bp_params, enable);
sys/dev/drm/amd/display/dc/bios/bios_parser.c
828
bool enable)
sys/dev/drm/amd/display/dc/bios/bios_parser.c
835
return bp->cmd_tbl.enable_crtc(bp, id, enable);
sys/dev/drm/amd/display/dc/bios/bios_parser2.c
1061
bool enable)
sys/dev/drm/amd/display/dc/bios/bios_parser2.c
1068
return bp->cmd_tbl.enable_crtc(bp, id, enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1227
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1231
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1235
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1263
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1270
if ((enable == true) && (bp_params->percentage > 0))
sys/dev/drm/amd/display/dc/bios/command_table.c
1307
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1321
if ((enable == true) && (bp_params->percentage > 0)) {
sys/dev/drm/amd/display/dc/bios/command_table.c
1359
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1391
if (enable == true) {
sys/dev/drm/amd/display/dc/bios/command_table.c
1542
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1547
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1573
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1578
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1591
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1600
enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1612
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1621
enable,
sys/dev/drm/amd/display/dc/bios/command_table.c
1640
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1643
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
1666
struct bios_parser *bp, bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1671
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1683
struct bios_parser *bp, bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
1688
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
2024
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
2043
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
2054
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
2076
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.c
2093
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table.c
2102
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table.h
51
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.h
57
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.h
62
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table.h
67
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.h
70
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.h
80
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table.h
84
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.c
543
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.c
562
bool enable)
sys/dev/drm/amd/display/dc/bios/command_table2.c
573
if (enable)
sys/dev/drm/amd/display/dc/bios/command_table2.c
574
params.enable = ATOM_ENABLE;
sys/dev/drm/amd/display/dc/bios/command_table2.c
576
params.enable = ATOM_DISABLE;
sys/dev/drm/amd/display/dc/bios/command_table2.c
673
ps.param.enable =
sys/dev/drm/amd/display/dc/bios/command_table2.h
51
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.h
57
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table2.h
62
bool enable,
sys/dev/drm/amd/display/dc/bios/command_table2.h
67
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.h
70
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.h
80
bool enable);
sys/dev/drm/amd/display/dc/bios/command_table2.h
84
bool enable);
sys/dev/drm/amd/display/dc/calcs/calcs_logger.h
388
DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]);
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1076
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1094
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1115
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1121
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1134
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1165
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1194
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1277
if (data->enable[k]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1283
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1298
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1317
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1363
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1381
if (data->enable[k]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1416
if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1425
if (data->enable[k]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1438
if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1440
if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1473
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1481
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1495
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1655
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1705
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1717
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1790
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1812
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1829
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1846
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1853
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1888
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1925
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1935
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1963
if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
198
data->enable[0] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
1987
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
199
data->enable[1] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
2008
if (data->enable[k]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
202
data->enable[0] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
203
data->enable[1] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
208
data->enable[0] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
209
data->enable[1] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
214
data->enable[2] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
215
data->enable[3] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
218
data->enable[2] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
219
data->enable[3] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
224
data->enable[2] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
225
data->enable[3] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
291
data->enable[i] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
295
data->enable[i] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
299
data->enable[i] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
303
data->enable[i] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
307
data->enable[i] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
311
data->enable[i] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
316
data->enable[i] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
349
data->enable[maximum_number_of_surfaces - 2] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
350
data->enable[maximum_number_of_surfaces - 1] = 1;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
353
data->enable[maximum_number_of_surfaces - 2] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
354
data->enable[maximum_number_of_surfaces - 1] = 0;
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
416
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
502
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
522
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
537
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
571
if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
577
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
629
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
786
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
861
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
874
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
930
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
945
if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
950
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
960
if (data->enable[i]) {
sys/dev/drm/amd/display/dc/calcs/dce_calcs.c
990
if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c
265
input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c
925
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
sys/dev/drm/amd/display/dc/core/dc.c
1153
if (u->plane_info->dcc.enable != u->surface->dcc.enable
sys/dev/drm/amd/display/dc/core/dc.c
1681
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
sys/dev/drm/amd/display/dc/core/dc.c
1687
return dal_irq_service_set(dc->res_pool->irqs, src, enable);
sys/dev/drm/amd/display/dc/core/dc.c
254
bool enable, bool continuous)
sys/dev/drm/amd/display/dc/core/dc.c
283
param.enable = enable;
sys/dev/drm/amd/display/dc/core/dc_debug.c
165
plane_state->dcc.enable,
sys/dev/drm/amd/display/dc/core/dc_link.c
2245
bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
sys/dev/drm/amd/display/dc/core/dc_link.c
2251
dmcu->funcs->set_psr_enable(dmcu, enable, wait);
sys/dev/drm/amd/display/dc/core/dc_link.c
2644
void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/drm/amd/display/dc/core/dc_link.c
2651
core_dc->hwss.set_avmute(pipe_ctx, enable);
sys/dev/drm/amd/display/dc/core/dc_link.c
2670
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
sys/dev/drm/amd/display/dc/core/dc_link.c
2674
if (enable) {
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
2742
void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
2747
if (enable)
sys/dev/drm/amd/display/dc/dc.h
745
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
sys/dev/drm/amd/display/dc/dc_bios_types.h
107
bool enable);
sys/dev/drm/amd/display/dc/dc_bios_types.h
120
bool enable);
sys/dev/drm/amd/display/dc/dc_hw_types.h
148
bool enable;
sys/dev/drm/amd/display/dc/dc_hw_types.h
401
bool enable;
sys/dev/drm/amd/display/dc/dc_link.h
149
bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
sys/dev/drm/amd/display/dc/dc_link.h
215
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
sys/dev/drm/amd/display/dc/dc_stream.h
291
bool enable,
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
115
static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
130
if (enable)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
142
if (enable) {
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
514
static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
528
if (psr_state == 0 && !enable)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
536
if (enable)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.c
553
if (enable) {
sys/dev/drm/amd/display/dc/dce/dce_hwseq.c
155
bool enable)
sys/dev/drm/amd/display/dc/dce/dce_hwseq.c
157
if (enable) {
sys/dev/drm/amd/display/dc/dce/dce_hwseq.c
41
unsigned int fe_inst, bool enable)
sys/dev/drm/amd/display/dc/dce/dce_hwseq.c
44
DCFE_CLOCK_ENABLE, enable);
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
528
unsigned int inst, bool enable);
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
538
bool enable);
sys/dev/drm/amd/display/dc/dce/dce_ipp.c
53
REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
135
bool enable)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
140
REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1022
bool enable)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1025
unsigned int value = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1463
bool enable)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1470
REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1574
int tg_inst, bool enable)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1578
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
1114
void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
1117
pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
2840
pos_cpy.enable = false;
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
2843
pos_cpy.enable = false;
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
933
bool enable)
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
945
if (enable && is_panel_backlight_on(hws)) {
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
956
__func__, (enable ? "On":"Off"));
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
958
cntl.action = enable ?
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
58
void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
83
bool enable);
sys/dev/drm/amd/display/dc/dce110/dce110_mem_input_v.c
653
enable(mem_input110);
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
1411
bool enable,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
1418
if (enable) {
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
2111
if (!params->enable)
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.h
245
bool enable,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
386
bool enable,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
392
if (enable) {
sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c
688
bool enable,
sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c
702
enable ? 0 : 1,
sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c
120
bool enable,
sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c
127
if (enable) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
457
uint32_t cur_en = pos->enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
491
bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
495
if (enable) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1498
bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c
101
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c
103
return enable ? true : false;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c
98
uint32_t enable = 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
1094
uint32_t cur_en = pos->enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
1159
void hubp1_clk_cntl(struct hubp *hubp, bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
1162
uint32_t clk_enable = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
182
if (!dcc->enable) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
481
void hubp1_dcc_control(struct hubp *hubp, bool enable,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
484
uint32_t dcc_en = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
505
hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
705
bool enable,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
730
void hubp1_clk_cntl(struct hubp *hubp, bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2666
pos_cpy.enable = false;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
365
bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
369
if (enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
105
bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
110
REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
335
mpcc->sm_cfg.enable = false;
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
89
MPCC_SM_EN, sm_cfg->enable,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
301
bool enable,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
311
if (!enable) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
372
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
375
uint32_t regval = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
180
bool enable,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
183
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
1320
if (!params->enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
348
void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
352
uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
419
void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
423
if (enable) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
528
void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
551
void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1300
bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1307
REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1412
int tg_inst, bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1416
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
882
bool enable)
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
885
unsigned int value = enable ? 1 : 0;
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
496
int tg_inst, bool enable);
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
500
bool enable);
sys/dev/drm/amd/display/dc/dm_helpers.h
58
bool enable);
sys/dev/drm/amd/display/dc/dm_helpers.h
79
bool enable);
sys/dev/drm/amd/display/dc/dml/display_mode_structs.h
426
unsigned char enable;
sys/dev/drm/amd/display/dc/inc/core_types.h
83
void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/drm/amd/display/dc/inc/dc_link_dp.h
63
void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
sys/dev/drm/amd/display/dc/inc/dce_calcs.h
368
bool enable[maximum_number_of_surfaces];
sys/dev/drm/amd/display/dc/inc/hw/dmcu.h
50
void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
163
bool enable);
sys/dev/drm/amd/display/dc/inc/hw/hubp.h
121
void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
sys/dev/drm/amd/display/dc/inc/hw/hubp.h
66
void (*dcc_control)(struct hubp *hubp, bool enable,
sys/dev/drm/amd/display/dc/inc/hw/mem_input.h
96
void (*dcc_control)(struct mem_input *mem_input, bool enable,
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
68
bool enable;
sys/dev/drm/amd/display/dc/inc/hw/opp.h
297
bool enable,
sys/dev/drm/amd/display/dc/inc/hw/opp.h
302
bool enable);
sys/dev/drm/amd/display/dc/inc/hw/stream_encoder.h
159
bool enable);
sys/dev/drm/amd/display/dc/inc/hw/stream_encoder.h
162
struct stream_encoder *enc, bool enable);
sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h
122
bool enable;
sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h
189
bool enable, const struct dc_crtc_timing *timing);
sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h
201
void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h
206
void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h
84
int enable;
sys/dev/drm/amd/display/dc/inc/hw_sequencer.h
203
void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/drm/amd/display/dc/inc/hw_sequencer.h
220
bool enable);
sys/dev/drm/amd/display/dc/inc/hw_sequencer.h
223
bool enable);
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
179
bool enable)
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
197
bool enable)
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
210
if (enable) {
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
217
dal_irq_service_set_generic(irq_service, info, enable);
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
42
bool enable);
sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
51
bool enable);
sys/dev/drm/amd/display/dc/irq/irq_service.c
104
bool enable)
sys/dev/drm/amd/display/dc/irq/irq_service.c
119
return info->funcs->set(irq_service, info, enable);
sys/dev/drm/amd/display/dc/irq/irq_service.c
121
dal_irq_service_set_generic(irq_service, info, enable);
sys/dev/drm/amd/display/dc/irq/irq_service.c
91
bool enable)
sys/dev/drm/amd/display/dc/irq/irq_service.c
97
(info->enable_value[enable ? 0 : 1] & info->enable_mask);
sys/dev/drm/amd/display/dc/irq/irq_service.h
40
bool enable);
sys/dev/drm/amd/display/dc/irq/irq_service.h
83
bool enable);
sys/dev/drm/amd/display/dc/virtual/virtual_stream_encoder.c
58
bool enable) {}
sys/dev/drm/amd/display/include/irq_service_interface.h
40
bool enable);
sys/dev/drm/amd/include/atomfirmware.h
2447
uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
sys/dev/drm/amd/include/atomfirmware.h
2458
uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
sys/dev/drm/amd/include/kgd_pp_interface.h
212
void (*enable_bapm)(void *handle, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
443
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
446
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
340
static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
342
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
28
static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
30
return smum_send_msg_to_smc(hwmgr, enable ?
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
35
static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
37
return smum_send_msg_to_smc(hwmgr, enable ?
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
419
int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
423
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
36
int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1437
static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1442
if (enable) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
853
static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
855
uint32_t en = enable ? 1 : 0;
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
889
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1824
static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1829
if (enable &&
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1876
static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1881
if (enable && phm_cap_enabled(
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
783
static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
788
if (enable) {
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2340
static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2345
if (enable) {
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2884
static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2889
if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2890
pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2892
enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2895
data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3564
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3570
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3574
data->smu_features[GNLD_DPM_VCE].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4383
int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4384
int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4390
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4394
data->smu_features[GNLD_DPM_UVD].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
443
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
854
static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
857
uint32_t en = (enable ? 1 : 0);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
931
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
37
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
40
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1145
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1152
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1156
data->smu_features[GNLD_DPM_VCE].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2127
int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2128
int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2135
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2139
data->smu_features[GNLD_DPM_UVD].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2351
static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2353
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
452
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
35
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
38
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1814
int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1821
if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1822
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1829
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1834
data->smu_features[GNLD_DPM_VCE].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2981
int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2988
if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2989
if (enable)
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2996
enable,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3001
data->smu_features[GNLD_DPM_UVD].enabled = enable;
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
35
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
38
if (enable)
sys/dev/drm/amd/powerplay/inc/hwmgr.h
304
int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/inc/hwmgr.h
310
int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
92
bool enable, uint32_t feature_mask)
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
94
int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.h
46
bool enable, uint32_t feature_mask);
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
114
bool enable, uint64_t feature_mask)
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
121
if (enable) {
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.h
52
bool enable, uint64_t feature_mask);
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
296
bool enable, uint64_t feature_mask)
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
304
if (enable) {
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.h
51
bool enable, uint64_t feature_mask);
sys/dev/drm/drm_atomic.c
329
if (state->active && !state->enable) {
sys/dev/drm/drm_atomic.c
339
WARN_ON(state->enable && !state->mode_blob)) {
sys/dev/drm/drm_atomic.c
346
WARN_ON(!state->enable && state->mode_blob)) {
sys/dev/drm/drm_atomic.c
377
drm_printf(p, "\tenable=%d\n", state->enable);
sys/dev/drm/drm_atomic_helper.c
1007
if (new_crtc_state->enable && funcs->prepare)
sys/dev/drm/drm_atomic_helper.c
1094
crtc->enabled = new_crtc_state->enable;
sys/dev/drm/drm_atomic_helper.c
1104
if (new_crtc_state->enable)
sys/dev/drm/drm_atomic_helper.c
1128
if (new_crtc_state->enable && funcs->mode_set_nofb) {
sys/dev/drm/drm_atomic_helper.c
1253
if (new_crtc_state->enable) {
sys/dev/drm/drm_atomic_helper.c
1288
if (funcs->enable)
sys/dev/drm/drm_atomic_helper.c
1289
funcs->enable(encoder);
sys/dev/drm/drm_atomic_helper.c
454
if (!new_crtc_state->enable)
sys/dev/drm/drm_atomic_helper.c
606
if (old_crtc_state->enable != new_crtc_state->enable) {
sys/dev/drm/drm_atomic_helper.c
628
if (new_crtc_state->enable != has_connectors) {
sys/dev/drm/drm_atomic_helper.c
683
new_crtc_state->enable ? 'y' : 'n',
sys/dev/drm/drm_atomic_helper.c
770
if (!crtc_state->enable && !can_update_disabled) {
sys/dev/drm/drm_atomic_helper.c
787
if (crtc_state->enable)
sys/dev/drm/drm_atomic_uapi.c
148
state->enable = true;
sys/dev/drm/drm_atomic_uapi.c
153
state->enable = false;
sys/dev/drm/drm_atomic_uapi.c
87
state->enable = true;
sys/dev/drm/drm_atomic_uapi.c
92
state->enable = false;
sys/dev/drm/drm_bridge.c
348
if (bridge->funcs->enable)
sys/dev/drm/drm_bridge.c
349
bridge->funcs->enable(bridge);
sys/dev/drm/drm_crtc.c
434
if (crtc->state->enable) {
sys/dev/drm/drm_dp_dual_mode_helper.c
349
struct i2c_adapter *adapter, bool enable)
sys/dev/drm/drm_dp_dual_mode_helper.c
351
uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE;
sys/dev/drm/drm_dp_dual_mode_helper.c
369
enable ? "enable" : "disable",
sys/dev/drm/drm_dp_dual_mode_helper.c
378
enable ? "enabling" : "disabling",
sys/dev/drm/drm_dp_dual_mode_helper.c
388
enable ? "enabling" : "disabling");
sys/dev/drm/drm_fb_helper.c
2185
bool enable;
sys/dev/drm/drm_fb_helper.c
2191
enable = connector->status == connector_status_connected;
sys/dev/drm/drm_fb_helper.c
2193
enable = connector->status != connector_status_disconnected;
sys/dev/drm/drm_fb_helper.c
2195
return enable;
sys/dev/drm/drm_plane_helper.c
158
.enable = crtc->enabled,
sys/dev/drm/drm_scdc_helper.c
164
bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
sys/dev/drm/drm_scdc_helper.c
175
if (enable)
sys/dev/drm/drm_simple_kms_helper.c
58
if (has_primary != state->enable)
sys/dev/drm/drm_simple_kms_helper.c
71
if (!pipe->funcs || !pipe->funcs->enable)
sys/dev/drm/drm_simple_kms_helper.c
75
pipe->funcs->enable(pipe, crtc->state, plane->state);
sys/dev/drm/drm_vblank.c
1797
get_seq->active = crtc->state->enable;
sys/dev/drm/i915/dvo.h
66
void (*dpms)(struct intel_dvo_device *dvo, bool enable);
sys/dev/drm/i915/dvo_ch7017.c
166
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable);
sys/dev/drm/i915/dvo_ch7017.c
334
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_ch7017.c
348
if (enable) {
sys/dev/drm/i915/dvo_ch7xxx.c
314
static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_ch7xxx.c
316
if (enable)
sys/dev/drm/i915/dvo_ivch.c
342
static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_ivch.c
353
if (enable)
sys/dev/drm/i915/dvo_ivch.c
360
if (enable)
sys/dev/drm/i915/dvo_ivch.c
372
if (((vr30 & VR30_PANEL_ON) != 0) == enable)
sys/dev/drm/i915/dvo_ns2501.c
655
static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_ns2501.c
659
DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
sys/dev/drm/i915/dvo_ns2501.c
661
if (enable) {
sys/dev/drm/i915/dvo_sil164.c
211
static void sil164_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_sil164.c
220
if (enable)
sys/dev/drm/i915/dvo_tfp410.c
237
static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/drm/i915/dvo_tfp410.c
244
if (enable)
sys/dev/drm/i915/i915_drv.h
1117
bool enable;
sys/dev/drm/i915/i915_drv.h
1164
bool enable;
sys/dev/drm/i915/i915_drv.h
1391
void (*enable)(struct i915_perf_stream *stream);
sys/dev/drm/i915/i915_drv.h
3506
bool enable);
sys/dev/drm/i915/i915_drv.h
3558
u32 enable, u32 deemphasis);
sys/dev/drm/i915/i915_drv.h
867
void (*enable)(struct drm_i915_private *dev_priv,
sys/dev/drm/i915/i915_perf.c
1957
.enable = i915_oa_stream_enable,
sys/dev/drm/i915/i915_perf.c
2367
if (stream->ops->enable)
sys/dev/drm/i915/i915_perf.c
2368
stream->ops->enable(stream);
sys/dev/drm/i915/i915_pmu.c
105
enable &= ~BIT(I915_SAMPLE_BUSY);
sys/dev/drm/i915/i915_pmu.c
1087
WARN_ON(i915->pmu.enable);
sys/dev/drm/i915/i915_pmu.c
110
return enable;
sys/dev/drm/i915/i915_pmu.c
172
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
sys/dev/drm/i915/i915_pmu.c
192
if (val && (engine->pmu.enable &
sys/dev/drm/i915/i915_pmu.c
225
if (dev_priv->pmu.enable &
sys/dev/drm/i915/i915_pmu.c
242
if (dev_priv->pmu.enable &
sys/dev/drm/i915/i915_pmu.c
599
i915->pmu.enable |= BIT_ULL(bit);
sys/dev/drm/i915/i915_pmu.c
619
engine->pmu.enable |= BIT(sample);
sys/dev/drm/i915/i915_pmu.c
660
engine->pmu.enable &= ~BIT(sample);
sys/dev/drm/i915/i915_pmu.c
670
i915->pmu.enable &= ~BIT_ULL(bit);
sys/dev/drm/i915/i915_pmu.c
75
u64 enable;
sys/dev/drm/i915/i915_pmu.c
82
enable = i915->pmu.enable;
sys/dev/drm/i915/i915_pmu.c
88
enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
sys/dev/drm/i915/i915_pmu.c
97
enable &= ~ENGINE_SAMPLE_MASK;
sys/dev/drm/i915/i915_pmu.h
67
u64 enable;
sys/dev/drm/i915/intel_audio.c
757
bool enable)
sys/dev/drm/i915/intel_audio.c
776
if (enable) {
sys/dev/drm/i915/intel_bios.c
554
dev_priv->vbt.psr.enable = driver->psr_enabled;
sys/dev/drm/i915/intel_cdclk.c
2158
if (!crtc_state->base.enable)
sys/dev/drm/i915/intel_cdclk.c
2269
if (crtc_state->base.enable)
sys/dev/drm/i915/intel_cdclk.c
2359
if (!crtc_state->base.enable)
sys/dev/drm/i915/intel_crt.c
1010
crt->base.enable = hsw_enable_crt;
sys/dev/drm/i915/intel_crt.c
1025
crt->base.enable = intel_enable_crt;
sys/dev/drm/i915/intel_ddi.c
1913
bool enable)
sys/dev/drm/i915/intel_ddi.c
1931
if (enable)
sys/dev/drm/i915/intel_ddi.c
2227
ddi_translations[level].enable,
sys/dev/drm/i915/intel_ddi.c
307
u8 enable; /* scale enable */
sys/dev/drm/i915/intel_ddi.c
3807
intel_encoder->enable = intel_enable_ddi;
sys/dev/drm/i915/intel_display.c
10360
if (possible_crtc->state->enable) {
sys/dev/drm/i915/intel_display.c
10407
crtc_state->base.active = crtc_state->base.enable = true;
sys/dev/drm/i915/intel_display.c
10869
if (mode_changed && crtc_state->enable &&
sys/dev/drm/i915/intel_display.c
12543
if (!crtc_state->enable) {
sys/dev/drm/i915/intel_display.c
13375
if (!crtc_state->base.enable)
sys/dev/drm/i915/intel_display.c
15849
crtc_state->base.active = crtc_state->base.enable =
sys/dev/drm/i915/intel_display.c
15852
crtc->base.enabled = crtc_state->base.enable;
sys/dev/drm/i915/intel_display.c
4642
static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
sys/dev/drm/i915/intel_display.c
4648
if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
sys/dev/drm/i915/intel_display.c
4655
if (enable)
sys/dev/drm/i915/intel_display.c
4658
DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
sys/dev/drm/i915/intel_display.c
4939
if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
sys/dev/drm/i915/intel_display.c
509
skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
sys/dev/drm/i915/intel_display.c
514
if (enable)
sys/dev/drm/i915/intel_display.c
521
skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
sys/dev/drm/i915/intel_display.c
526
if (enable)
sys/dev/drm/i915/intel_display.c
5558
encoder->enable(encoder, crtc_state, conn_state);
sys/dev/drm/i915/intel_display.c
6499
if (crtc_state->base.enable && crtc_state->has_pch_encoder)
sys/dev/drm/i915/intel_dp.c
2676
bool enable)
sys/dev/drm/i915/intel_dp.c
2685
if (is_enabled == enable)
sys/dev/drm/i915/intel_dp.c
2689
enable ? "enable" : "disable");
sys/dev/drm/i915/intel_dp.c
2691
if (enable)
sys/dev/drm/i915/intel_dp.c
5518
bool enable)
sys/dev/drm/i915/intel_dp.c
6712
intel_encoder->enable = vlv_enable_dp;
sys/dev/drm/i915/intel_dp.c
6719
intel_encoder->enable = vlv_enable_dp;
sys/dev/drm/i915/intel_dp.c
6724
intel_encoder->enable = g4x_enable_dp;
sys/dev/drm/i915/intel_dp_aux_backlight.c
27
static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
sys/dev/drm/i915/intel_dp_aux_backlight.c
274
panel->backlight.enable = intel_dp_aux_enable_backlight;
sys/dev/drm/i915/intel_dp_aux_backlight.c
41
if (enable)
sys/dev/drm/i915/intel_dp_aux_backlight.c
49
enable ? "enable" : "disable");
sys/dev/drm/i915/intel_dp_mst.c
564
intel_encoder->enable = intel_mst_enable_dp;
sys/dev/drm/i915/intel_dpio_phy.c
265
u32 enable, u32 deemphasis)
sys/dev/drm/i915/intel_dpio_phy.c
288
if (enable)
sys/dev/drm/i915/intel_dpll_mgr.c
1431
.enable = skl_ddi_pll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
1437
.enable = skl_ddi_dpll0_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
1873
.enable = bxt_ddi_pll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
193
pll->info->funcs->enable(dev_priv, pll);
sys/dev/drm/i915/intel_dpll_mgr.c
2401
.enable = cnl_ddi_pll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
3201
.enable = icl_pll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
470
.enable = ibx_pch_dpll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
862
.enable = hsw_ddi_wrpll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
868
.enable = hsw_ddi_spll_enable,
sys/dev/drm/i915/intel_dpll_mgr.c
891
.enable = hsw_ddi_lcpll_enable,
sys/dev/drm/i915/intel_dpll_mgr.h
230
void (*enable)(struct drm_i915_private *dev_priv,
sys/dev/drm/i915/intel_drv.h
1194
bool enable,
sys/dev/drm/i915/intel_drv.h
1372
enum i915_pipe pipe, bool enable);
sys/dev/drm/i915/intel_drv.h
1375
bool enable);
sys/dev/drm/i915/intel_drv.h
1453
bool enable);
sys/dev/drm/i915/intel_drv.h
1873
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
sys/dev/drm/i915/intel_drv.h
246
void (*enable)(struct intel_encoder *,
sys/dev/drm/i915/intel_drv.h
312
void (*enable)(const struct intel_crtc_state *crtc_state,
sys/dev/drm/i915/intel_drv.h
316
void (*power)(struct intel_connector *, bool enable);
sys/dev/drm/i915/intel_drv.h
386
bool enable);
sys/dev/drm/i915/intel_dsi_dcs_backlight.c
171
panel->backlight.enable = dcs_enable_backlight;
sys/dev/drm/i915/intel_dvo.c
426
intel_encoder->enable = intel_enable_dvo;
sys/dev/drm/i915/intel_fifo_underrun.c
108
bool enable, bool old)
sys/dev/drm/i915/intel_fifo_underrun.c
115
if (enable) {
sys/dev/drm/i915/intel_fifo_underrun.c
127
enum i915_pipe pipe, bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
133
if (enable)
sys/dev/drm/i915/intel_fifo_underrun.c
159
bool enable, bool old)
sys/dev/drm/i915/intel_fifo_underrun.c
162
if (enable) {
sys/dev/drm/i915/intel_fifo_underrun.c
181
enum i915_pipe pipe, bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
185
if (enable)
sys/dev/drm/i915/intel_fifo_underrun.c
193
bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
199
if (enable)
sys/dev/drm/i915/intel_fifo_underrun.c
226
bool enable, bool old)
sys/dev/drm/i915/intel_fifo_underrun.c
230
if (enable) {
sys/dev/drm/i915/intel_fifo_underrun.c
250
enum i915_pipe pipe, bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
259
crtc->cpu_fifo_underrun_disabled = !enable;
sys/dev/drm/i915/intel_fifo_underrun.c
262
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
sys/dev/drm/i915/intel_fifo_underrun.c
264
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
sys/dev/drm/i915/intel_fifo_underrun.c
266
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
sys/dev/drm/i915/intel_fifo_underrun.c
268
broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
sys/dev/drm/i915/intel_fifo_underrun.c
290
enum i915_pipe pipe, bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
297
enable);
sys/dev/drm/i915/intel_fifo_underrun.c
319
bool enable)
sys/dev/drm/i915/intel_fifo_underrun.c
338
crtc->pch_fifo_underrun_disabled = !enable;
sys/dev/drm/i915/intel_fifo_underrun.c
343
enable);
sys/dev/drm/i915/intel_fifo_underrun.c
347
enable, old);
sys/dev/drm/i915/intel_guc_log.c
61
static int guc_action_control_log(struct intel_guc *guc, bool enable,
sys/dev/drm/i915/intel_guc_log.c
66
(enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |
sys/dev/drm/i915/intel_hdmi.c
1079
bool enable)
sys/dev/drm/i915/intel_hdmi.c
1083
if (!enable)
sys/dev/drm/i915/intel_hdmi.c
1086
ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
sys/dev/drm/i915/intel_hdmi.c
1089
enable ? "Enable" : "Disable", ret);
sys/dev/drm/i915/intel_hdmi.c
2452
intel_encoder->enable = vlv_enable_hdmi;
sys/dev/drm/i915/intel_hdmi.c
2458
intel_encoder->enable = vlv_enable_hdmi;
sys/dev/drm/i915/intel_hdmi.c
2463
intel_encoder->enable = cpt_enable_hdmi;
sys/dev/drm/i915/intel_hdmi.c
2465
intel_encoder->enable = ibx_enable_hdmi;
sys/dev/drm/i915/intel_hdmi.c
2467
intel_encoder->enable = g4x_enable_hdmi;
sys/dev/drm/i915/intel_hdmi.c
543
bool enable,
sys/dev/drm/i915/intel_hdmi.c
567
if (!enable) {
sys/dev/drm/i915/intel_hdmi.c
693
bool enable,
sys/dev/drm/i915/intel_hdmi.c
710
if (!enable) {
sys/dev/drm/i915/intel_hdmi.c
746
bool enable,
sys/dev/drm/i915/intel_hdmi.c
761
if (!enable) {
sys/dev/drm/i915/intel_hdmi.c
789
bool enable,
sys/dev/drm/i915/intel_hdmi.c
806
if (!enable) {
sys/dev/drm/i915/intel_hdmi.c
842
bool enable,
sys/dev/drm/i915/intel_hdmi.c
857
if (!enable) {
sys/dev/drm/i915/intel_hdmi.c
874
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
sys/dev/drm/i915/intel_hdmi.c
884
enable ? "Enabling" : "Disabling");
sys/dev/drm/i915/intel_hdmi.c
887
adapter, enable);
sys/dev/drm/i915/intel_i2c.c
145
bool enable)
sys/dev/drm/i915/intel_i2c.c
151
if (!enable)
sys/dev/drm/i915/intel_i2c.c
159
bool enable)
sys/dev/drm/i915/intel_i2c.c
164
if (!enable)
sys/dev/drm/i915/intel_i2c.c
172
bool enable)
sys/dev/drm/i915/intel_i2c.c
177
if (!enable)
sys/dev/drm/i915/intel_lvds.c
939
intel_encoder->enable = intel_enable_lvds;
sys/dev/drm/i915/intel_opregion.c
362
bool enable)
sys/dev/drm/i915/intel_opregion.c
385
if (!enable)
sys/dev/drm/i915/intel_opregion.h
64
bool enable);
sys/dev/drm/i915/intel_opregion.h
89
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
sys/dev/drm/i915/intel_overlay.c
192
bool enable)
sys/dev/drm/i915/intel_overlay.c
198
if (enable)
sys/dev/drm/i915/intel_overlay.c
206
if (enable)
sys/dev/drm/i915/intel_panel.c
1116
panel->backlight.enable(crtc_state, conn_state);
sys/dev/drm/i915/intel_panel.c
1193
bool enable = bd->props.power == FB_BLANK_UNBLANK &&
sys/dev/drm/i915/intel_panel.c
1195
panel->backlight.power(connector, enable);
sys/dev/drm/i915/intel_panel.c
1930
panel->backlight.enable = bxt_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1937
panel->backlight.enable = cnp_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1945
panel->backlight.enable = lpt_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1955
panel->backlight.enable = pch_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1963
panel->backlight.enable = pwm_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1969
panel->backlight.enable = vlv_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1977
panel->backlight.enable = i965_enable_backlight;
sys/dev/drm/i915/intel_panel.c
1984
panel->backlight.enable = i9xx_enable_backlight;
sys/dev/drm/i915/intel_pm.c
2710
if (!result->enable)
sys/dev/drm/i915/intel_pm.c
2713
result->enable = result->pri_val <= max->pri &&
sys/dev/drm/i915/intel_pm.c
2717
ret = result->enable;
sys/dev/drm/i915/intel_pm.c
2724
if (level == 0 && !result->enable) {
sys/dev/drm/i915/intel_pm.c
2738
result->enable = true;
sys/dev/drm/i915/intel_pm.c
2776
result->enable = true;
sys/dev/drm/i915/intel_pm.c
308
static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
sys/dev/drm/i915/intel_pm.c
315
if (enable)
sys/dev/drm/i915/intel_pm.c
3210
a_wm->enable &= b_wm->enable;
sys/dev/drm/i915/intel_pm.c
3245
ret_wm->enable = true;
sys/dev/drm/i915/intel_pm.c
3259
if (!wm->enable)
sys/dev/drm/i915/intel_pm.c
3260
ret_wm->enable = false;
sys/dev/drm/i915/intel_pm.c
3296
wm->enable = false;
sys/dev/drm/i915/intel_pm.c
330
static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
sys/dev/drm/i915/intel_pm.c
3306
if (wm->enable)
sys/dev/drm/i915/intel_pm.c
3323
wm->enable = false;
sys/dev/drm/i915/intel_pm.c
3331
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
sys/dev/drm/i915/intel_pm.c
337
if (enable)
sys/dev/drm/i915/intel_pm.c
3374
if (r->enable)
sys/dev/drm/i915/intel_pm.c
3401
if (WARN_ON(!r->enable))
sys/dev/drm/i915/intel_pm.c
3423
if (r1->wm[level].enable)
sys/dev/drm/i915/intel_pm.c
3425
if (r2->wm[level].enable)
sys/dev/drm/i915/intel_pm.c
349
static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
sys/dev/drm/i915/intel_pm.c
356
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
sys/dev/drm/i915/intel_pm.c
360
I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
sys/dev/drm/i915/intel_pm.c
365
if (enable)
sys/dev/drm/i915/intel_pm.c
373
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
sys/dev/drm/i915/intel_pm.c
384
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
sys/dev/drm/i915/intel_pm.c
3913
if (!crtc_state->enable)
sys/dev/drm/i915/intel_pm.c
392
trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
sys/dev/drm/i915/intel_pm.c
395
enableddisabled(enable),
sys/dev/drm/i915/intel_pm.c
4091
if (!crtc_state->base.enable)
sys/dev/drm/i915/intel_pm.c
4133
if (!cstate->base.enable)
sys/dev/drm/i915/intel_pm.c
438
bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
sys/dev/drm/i915/intel_pm.c
443
ret = _intel_set_memory_cxsr(dev_priv, enable);
sys/dev/drm/i915/intel_pm.c
445
dev_priv->wm.vlv.cxsr = enable;
sys/dev/drm/i915/intel_pm.c
447
dev_priv->wm.g4x.cxsr = enable;
sys/dev/drm/i915/intel_pm.c
5648
active->wm[0].enable = true;
sys/dev/drm/i915/intel_pm.c
5662
active->wm[level].enable = true;
sys/dev/drm/i915/intel_psr.c
1069
i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
sys/dev/drm/i915/intel_psr.c
841
bool enable;
sys/dev/drm/i915/intel_psr.c
878
enable = psr_global_enabled(val);
sys/dev/drm/i915/intel_psr.c
880
if (!enable || switching_psr(dev_priv, crtc_state, mode))
sys/dev/drm/i915/intel_psr.c
889
if (dev_priv->psr.prepared && enable)
sys/dev/drm/i915/intel_ringbuffer.h
418
u32 enable;
sys/dev/drm/i915/intel_runtime_pm.c
1462
bool enable)
sys/dev/drm/i915/intel_runtime_pm.c
1468
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
sys/dev/drm/i915/intel_runtime_pm.c
1480
ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
sys/dev/drm/i915/intel_runtime_pm.c
159
power_well->desc->ops->enable(dev_priv, power_well);
sys/dev/drm/i915/intel_runtime_pm.c
2022
.enable = i9xx_always_on_power_well_noop,
sys/dev/drm/i915/intel_runtime_pm.c
2029
.enable = chv_pipe_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2036
.enable = chv_dpio_cmn_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2053
.enable = i830_pipes_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2076
.enable = hsw_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2083
.enable = gen9_dc_off_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2090
.enable = bxt_dpio_cmn_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2147
.enable = vlv_display_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2154
.enable = vlv_dpio_cmn_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2161
.enable = vlv_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
2714
.enable = icl_combo_phy_aux_power_well_enable,
sys/dev/drm/i915/intel_runtime_pm.c
3140
i915_reg_t reg, bool enable)
sys/dev/drm/i915/intel_runtime_pm.c
3145
val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);
sys/dev/drm/i915/intel_runtime_pm.c
3151
if ((enable && !status) || (!enable && status)) {
sys/dev/drm/i915/intel_runtime_pm.c
3153
enable ? "enable" : "disable");
sys/dev/drm/i915/intel_runtime_pm.c
3708
disp2d->desc->ops->enable(dev_priv, disp2d);
sys/dev/drm/i915/intel_runtime_pm.c
874
struct i915_power_well *power_well, bool enable)
sys/dev/drm/i915/intel_runtime_pm.c
882
state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
sys/dev/drm/i915/intel_sdvo.c
3101
intel_encoder->enable = intel_enable_sdvo;
sys/dev/drm/i915/intel_sdvo_regs.h
581
unsigned int enable:1;
sys/dev/drm/i915/intel_sprite.c
1267
if (crtc_state->base.enable &&
sys/dev/drm/i915/intel_tv.c
1512
intel_encoder->enable = intel_enable_tv;
sys/dev/drm/i915/vlv_dsi.c
1776
intel_encoder->enable = intel_dsi_enable_nop;
sys/dev/drm/include/drm/drm_audio_component.h
32
void (*codec_wake_override)(struct device *, bool enable);
sys/dev/drm/include/drm/drm_bridge.h
239
void (*enable)(struct drm_bridge *bridge);
sys/dev/drm/include/drm/drm_crtc.h
107
bool enable;
sys/dev/drm/include/drm/drm_dp_dual_mode_helper.h
112
struct i2c_adapter *adapter, bool enable);
sys/dev/drm/include/drm/drm_modeset_helper_vtables.h
722
void (*enable)(struct drm_encoder *encoder);
sys/dev/drm/include/drm/drm_panel.h
166
if (panel && panel->funcs && panel->funcs->enable)
sys/dev/drm/include/drm/drm_panel.h
167
return panel->funcs->enable(panel);
sys/dev/drm/include/drm/drm_panel.h
74
int (*enable)(struct drm_panel *panel);
sys/dev/drm/include/drm/drm_scdc_helper.h
134
bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
sys/dev/drm/include/drm/drm_simple_kms_helper.h
66
void (*enable)(struct drm_simple_display_pipe *pipe,
sys/dev/drm/radeon/atombios_crtc.c
442
int enable,
sys/dev/drm/radeon/atombios_crtc.c
451
if (enable) {
sys/dev/drm/radeon/atombios_crtc.c
496
args.v3.ucEnable = enable;
sys/dev/drm/radeon/atombios_crtc.c
515
args.v2.ucEnable = enable;
sys/dev/drm/radeon/atombios_crtc.c
523
args.v1.ucEnable = enable;
sys/dev/drm/radeon/atombios_crtc.c
525
if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
sys/dev/drm/radeon/atombios_crtc.c
535
args.lvds_ss_2.ucEnable = enable;
sys/dev/drm/radeon/atombios_crtc.c
537
if (enable == ATOM_DISABLE) {
sys/dev/drm/radeon/atombios_crtc.c
545
args.lvds_ss.ucEnable = enable;
sys/dev/drm/radeon/atombios_encoders.c
1594
atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
sys/dev/drm/radeon/atombios_encoders.c
1621
if (enable)
sys/dev/drm/radeon/btc_dpm.c
1331
bool enable)
sys/dev/drm/radeon/btc_dpm.c
1337
if (enable) {
sys/dev/drm/radeon/btc_dpm.c
1373
bool enable)
sys/dev/drm/radeon/btc_dpm.c
1375
btc_enable_bif_dynamic_pcie_gen2(rdev, enable);
sys/dev/drm/radeon/btc_dpm.c
1377
if (enable)
sys/dev/drm/radeon/btc_dpm.c
1472
bool enable)
sys/dev/drm/radeon/btc_dpm.c
1477
if (enable) {
sys/dev/drm/radeon/btc_dpm.c
1527
bool enable)
sys/dev/drm/radeon/btc_dpm.c
1532
if (enable) {
sys/dev/drm/radeon/btc_dpm.c
1582
bool enable)
sys/dev/drm/radeon/btc_dpm.c
1587
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
1465
bool enable)
sys/dev/drm/radeon/ci_dpm.c
1469
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
1514
static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
1519
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
1653
static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
1657
if (enable)
sys/dev/drm/radeon/ci_dpm.c
1939
bool enable)
sys/dev/drm/radeon/ci_dpm.c
1943
if (enable)
sys/dev/drm/radeon/ci_dpm.c
1997
bool enable)
sys/dev/drm/radeon/ci_dpm.c
2001
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
2053
static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
2058
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
3139
static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
3145
if (enable)
sys/dev/drm/radeon/ci_dpm.c
3965
static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
3976
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
4009
return (ci_send_msg_to_smc(rdev, enable ?
sys/dev/drm/radeon/ci_dpm.c
4014
static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
4025
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
4041
return (ci_send_msg_to_smc(rdev, enable ?
sys/dev/drm/radeon/ci_dpm.c
4047
static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
4058
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
4073
return (ci_send_msg_to_smc(rdev, enable ?
sys/dev/drm/radeon/ci_dpm.c
4078
static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
4089
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
4105
return (ci_send_msg_to_smc(rdev, enable ?
sys/dev/drm/radeon/ci_dpm.c
518
static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
sys/dev/drm/radeon/ci_dpm.c
525
if (enable)
sys/dev/drm/radeon/ci_dpm.c
534
if (enable)
sys/dev/drm/radeon/ci_dpm.c
543
if (enable)
sys/dev/drm/radeon/ci_dpm.c
552
if (enable)
sys/dev/drm/radeon/ci_dpm.c
608
static int ci_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
617
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
625
ci_do_enable_didt(rdev, enable);
sys/dev/drm/radeon/ci_dpm.c
633
static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
639
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
691
static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ci_dpm.c
698
if (enable) {
sys/dev/drm/radeon/ci_dpm.c
716
bool enable)
sys/dev/drm/radeon/ci_dpm.c
722
if (enable)
sys/dev/drm/radeon/ci_dpm.c
941
bool enable)
sys/dev/drm/radeon/ci_dpm.c
946
if (enable) {
sys/dev/drm/radeon/cik.c
132
bool enable);
sys/dev/drm/radeon/cik.c
3889
static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
3891
if (enable)
sys/dev/drm/radeon/cik.c
4243
static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
4245
if (enable)
sys/dev/drm/radeon/cik.c
4771
static void cik_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
4773
cik_cp_gfx_enable(rdev, enable);
sys/dev/drm/radeon/cik.c
4774
cik_cp_compute_enable(rdev, enable);
sys/dev/drm/radeon/cik.c
5785
bool enable)
sys/dev/drm/radeon/cik.c
5789
if (enable)
sys/dev/drm/radeon/cik.c
5796
static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
5801
if (enable)
sys/dev/drm/radeon/cik.c
6017
static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
6023
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
sys/dev/drm/radeon/cik.c
6053
static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
6057
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
sys/dev/drm/radeon/cik.c
6147
bool enable)
sys/dev/drm/radeon/cik.c
6154
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
sys/dev/drm/radeon/cik.c
6164
bool enable)
sys/dev/drm/radeon/cik.c
6171
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
sys/dev/drm/radeon/cik.c
6181
bool enable)
sys/dev/drm/radeon/cik.c
6185
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
sys/dev/drm/radeon/cik.c
6202
bool enable)
sys/dev/drm/radeon/cik.c
6206
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
sys/dev/drm/radeon/cik.c
6230
bool enable)
sys/dev/drm/radeon/cik.c
6234
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
sys/dev/drm/radeon/cik.c
6256
bool enable)
sys/dev/drm/radeon/cik.c
6262
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
sys/dev/drm/radeon/cik.c
6274
bool enable)
sys/dev/drm/radeon/cik.c
6280
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
sys/dev/drm/radeon/cik.c
6290
bool enable)
sys/dev/drm/radeon/cik.c
6296
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
sys/dev/drm/radeon/cik.c
6306
u32 block, bool enable)
sys/dev/drm/radeon/cik.c
6312
if (enable) {
sys/dev/drm/radeon/cik.c
6324
cik_enable_mc_mgcg(rdev, enable);
sys/dev/drm/radeon/cik.c
6325
cik_enable_mc_ls(rdev, enable);
sys/dev/drm/radeon/cik.c
6330
cik_enable_sdma_mgcg(rdev, enable);
sys/dev/drm/radeon/cik.c
6331
cik_enable_sdma_mgls(rdev, enable);
sys/dev/drm/radeon/cik.c
6335
cik_enable_bif_mgls(rdev, enable);
sys/dev/drm/radeon/cik.c
6340
cik_enable_uvd_mgcg(rdev, enable);
sys/dev/drm/radeon/cik.c
6344
cik_enable_hdp_mgcg(rdev, enable);
sys/dev/drm/radeon/cik.c
6345
cik_enable_hdp_ls(rdev, enable);
sys/dev/drm/radeon/cik.c
6349
vce_v2_0_enable_mgcg(rdev, enable);
sys/dev/drm/radeon/cik.c
6380
bool enable)
sys/dev/drm/radeon/cik.c
6385
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
sys/dev/drm/radeon/cik.c
6394
bool enable)
sys/dev/drm/radeon/cik.c
6399
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
sys/dev/drm/radeon/cik.c
6407
static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
6412
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
sys/dev/drm/radeon/cik.c
6420
static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
6425
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
sys/dev/drm/radeon/cik.c
6522
bool enable)
sys/dev/drm/radeon/cik.c
6526
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
sys/dev/drm/radeon/cik.c
6608
bool enable)
sys/dev/drm/radeon/cik.c
6613
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
sys/dev/drm/radeon/cik.c
6622
bool enable)
sys/dev/drm/radeon/cik.c
6627
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
sys/dev/drm/radeon/cik.c
6687
static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik.c
6689
cik_enable_gfx_cgpg(rdev, enable);
sys/dev/drm/radeon/cik.c
6690
cik_enable_gfx_static_mgpg(rdev, enable);
sys/dev/drm/radeon/cik.c
6691
cik_enable_gfx_dynamic_mgpg(rdev, enable);
sys/dev/drm/radeon/cik_sdma.c
302
static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik_sdma.c
313
if (enable)
sys/dev/drm/radeon/cik_sdma.c
329
void cik_sdma_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/cik_sdma.c
334
if (enable == false) {
sys/dev/drm/radeon/cik_sdma.c
345
if (enable)
sys/dev/drm/radeon/cik_sdma.c
352
cik_sdma_ctx_switch_enable(rdev, enable);
sys/dev/drm/radeon/cypress_dpm.c
120
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
124
if (enable) {
sys/dev/drm/radeon/cypress_dpm.c
172
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
177
if (enable) {
sys/dev/drm/radeon/cypress_dpm.c
221
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
225
if (enable) {
sys/dev/drm/radeon/cypress_dpm.c
245
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
247
if (enable)
sys/dev/drm/radeon/cypress_dpm.c
254
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
256
if (enable)
sys/dev/drm/radeon/cypress_dpm.c
50
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
56
if (enable) {
sys/dev/drm/radeon/cypress_dpm.c
87
bool enable)
sys/dev/drm/radeon/cypress_dpm.c
89
cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
sys/dev/drm/radeon/cypress_dpm.c
91
if (enable)
sys/dev/drm/radeon/cypress_dpm.h
141
bool enable);
sys/dev/drm/radeon/cypress_dpm.h
150
bool enable);
sys/dev/drm/radeon/cypress_dpm.h
152
bool enable);
sys/dev/drm/radeon/evergreen_hdmi.c
423
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/evergreen_hdmi.c
424
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/radeon/evergreen_hdmi.c
434
if (enable) {
sys/dev/drm/radeon/evergreen_hdmi.c
458
dig->afmt->enabled = enable;
sys/dev/drm/radeon/evergreen_hdmi.c
461
enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
sys/dev/drm/radeon/evergreen_hdmi.c
464
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/evergreen_hdmi.c
465
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/radeon/evergreen_hdmi.c
476
if (enable && connector &&
sys/dev/drm/radeon/evergreen_hdmi.c
513
dig->afmt->enabled = enable;
sys/dev/drm/radeon/kv_dpm.c
1122
static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1124
return kv_notify_message_to_smu(rdev, enable ?
sys/dev/drm/radeon/kv_dpm.c
1157
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1163
ret = kv_smc_bapm_enable(rdev, enable);
sys/dev/drm/radeon/kv_dpm.c
1169
static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1174
if (enable)
sys/dev/drm/radeon/kv_dpm.c
1396
static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1398
return kv_notify_message_to_smu(rdev, enable ?
sys/dev/drm/radeon/kv_dpm.c
1402
static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1404
return kv_notify_message_to_smu(rdev, enable ?
sys/dev/drm/radeon/kv_dpm.c
1408
static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1410
return kv_notify_message_to_smu(rdev, enable ?
sys/dev/drm/radeon/kv_dpm.c
1414
static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
1416
return kv_notify_message_to_smu(rdev, enable ?
sys/dev/drm/radeon/kv_dpm.c
1788
bool enable)
sys/dev/drm/radeon/kv_dpm.c
1793
if (enable) {
sys/dev/drm/radeon/kv_dpm.c
2251
u32 index, bool enable)
sys/dev/drm/radeon/kv_dpm.c
2255
pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
sys/dev/drm/radeon/kv_dpm.c
328
static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
335
if (enable)
sys/dev/drm/radeon/kv_dpm.c
344
if (enable)
sys/dev/drm/radeon/kv_dpm.c
353
if (enable)
sys/dev/drm/radeon/kv_dpm.c
362
if (enable)
sys/dev/drm/radeon/kv_dpm.c
370
static int kv_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
38
bool enable);
sys/dev/drm/radeon/kv_dpm.c
381
if (enable) {
sys/dev/drm/radeon/kv_dpm.c
389
kv_do_enable_didt(rdev, enable);
sys/dev/drm/radeon/kv_dpm.c
430
static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_dpm.c
436
if (enable) {
sys/dev/drm/radeon/kv_dpm.c
633
u32 index, bool enable)
sys/dev/drm/radeon/kv_dpm.c
637
pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
sys/dev/drm/radeon/kv_dpm.h
194
int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/kv_dpm.h
195
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/kv_smc.c
102
int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_smc.c
104
if (enable)
sys/dev/drm/radeon/kv_smc.c
110
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/kv_smc.c
112
if (enable)
sys/dev/drm/radeon/ni.c
1471
static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/ni.c
1473
if (enable)
sys/dev/drm/radeon/ni_dpm.c
2598
bool enable)
sys/dev/drm/radeon/ni_dpm.c
2605
if (enable) {
sys/dev/drm/radeon/ni_dpm.c
3379
bool enable)
sys/dev/drm/radeon/ni_dpm.c
3386
if (enable) {
sys/dev/drm/radeon/ni_dpm.c
3459
bool enable)
sys/dev/drm/radeon/ni_dpm.c
3468
if (enable) {
sys/dev/drm/radeon/ni_dpm.c
3498
bool enable)
sys/dev/drm/radeon/ni_dpm.c
3500
ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
sys/dev/drm/radeon/ni_dpm.c
3502
if (enable)
sys/dev/drm/radeon/ni_dpm.c
916
bool enable)
sys/dev/drm/radeon/ni_dpm.c
921
if (enable) {
sys/dev/drm/radeon/ni_dpm.c
944
bool enable)
sys/dev/drm/radeon/ni_dpm.c
949
if (enable) {
sys/dev/drm/radeon/ni_dpm.c
972
bool enable)
sys/dev/drm/radeon/ni_dpm.c
977
if (enable) {
sys/dev/drm/radeon/r100.c
591
unsigned enable = 0;
sys/dev/drm/radeon/r100.c
596
enable |= 1 << radeon_connector->hpd.hpd;
sys/dev/drm/radeon/r100.c
599
radeon_irq_kms_enable_hpd(rdev, enable);
sys/dev/drm/radeon/r600.c
1002
enable |= 1 << radeon_connector->hpd.hpd;
sys/dev/drm/radeon/r600.c
1005
radeon_irq_kms_enable_hpd(rdev, enable);
sys/dev/drm/radeon/r600.c
945
unsigned enable = 0;
sys/dev/drm/radeon/r600_dpm.c
243
void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
247
if (enable) {
sys/dev/drm/radeon/r600_dpm.c
267
void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
269
if (enable)
sys/dev/drm/radeon/r600_dpm.c
275
void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
277
if (enable)
sys/dev/drm/radeon/r600_dpm.c
288
void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
290
if (enable)
sys/dev/drm/radeon/r600_dpm.c
304
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
306
if (enable)
sys/dev/drm/radeon/r600_dpm.c
312
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
314
if (enable)
sys/dev/drm/radeon/r600_dpm.c
320
void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/r600_dpm.c
322
if (enable)
sys/dev/drm/radeon/r600_dpm.c
447
u32 index, bool enable)
sys/dev/drm/radeon/r600_dpm.c
449
if (enable)
sys/dev/drm/radeon/r600_dpm.c
458
u32 index, bool enable)
sys/dev/drm/radeon/r600_dpm.c
460
if (enable)
sys/dev/drm/radeon/r600_dpm.c
469
u32 index, bool enable)
sys/dev/drm/radeon/r600_dpm.c
471
if (enable)
sys/dev/drm/radeon/r600_dpm.c
563
enum r600_power_level index, bool enable)
sys/dev/drm/radeon/r600_dpm.c
567
if (enable)
sys/dev/drm/radeon/r600_dpm.h
141
void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
142
void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
143
void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
145
void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
147
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
148
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
149
void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/r600_dpm.h
173
u32 index, bool enable);
sys/dev/drm/radeon/r600_dpm.h
175
u32 index, bool enable);
sys/dev/drm/radeon/r600_dpm.h
177
u32 index, bool enable);
sys/dev/drm/radeon/r600_dpm.h
196
enum r600_power_level index, bool enable);
sys/dev/drm/radeon/r600_hdmi.c
478
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/r600_hdmi.c
479
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
sys/dev/drm/radeon/r600_hdmi.c
492
if (enable)
sys/dev/drm/radeon/r600_hdmi.c
496
if (enable) {
sys/dev/drm/radeon/r600_hdmi.c
504
if (enable) {
sys/dev/drm/radeon/r600_hdmi.c
512
if (enable) {
sys/dev/drm/radeon/r600_hdmi.c
520
if (enable)
sys/dev/drm/radeon/r600_hdmi.c
534
if (enable)
sys/dev/drm/radeon/r600_hdmi.c
540
dig->afmt->enabled = enable;
sys/dev/drm/radeon/r600_hdmi.c
543
enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
sys/dev/drm/radeon/radeon.h
1595
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon.h
1596
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon.h
1917
void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/radeon.h
1970
void (*set_clock_gating)(struct radeon_device *rdev, int enable);
sys/dev/drm/radeon/radeon.h
1979
int (*enable)(struct radeon_device *rdev);
sys/dev/drm/radeon/radeon.h
1994
void (*enable_bapm)(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon.h
2795
#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
sys/dev/drm/radeon/radeon.h
3008
bool enable, const char *name,
sys/dev/drm/radeon/radeon_asic.c
1088
.enable = &rv6xx_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1181
.enable = &rs780_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1287
.enable = &rv770_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1407
.enable = &cypress_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1501
.enable = &sumo_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1594
.enable = &btc_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1742
.enable = &ni_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
1863
.enable = &trinity_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
2001
.enable = &si_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
2171
.enable = &ci_dpm_enable,
sys/dev/drm/radeon/radeon_asic.c
2284
.enable = &kv_dpm_enable,
sys/dev/drm/radeon/radeon_asic.h
1040
void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon_asic.h
37
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
sys/dev/drm/radeon/radeon_asic.h
43
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
sys/dev/drm/radeon/radeon_asic.h
717
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon_asic.h
833
u32 block, bool enable);
sys/dev/drm/radeon/radeon_asic.h
921
void cik_sdma_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon_asic.h
978
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/radeon_atombios.c
2995
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
sys/dev/drm/radeon/radeon_atombios.c
3000
args.ucEnable = enable;
sys/dev/drm/radeon/radeon_audio.c
108
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/radeon_audio.c
109
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/radeon_audio.c
110
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
sys/dev/drm/radeon/radeon_audio.c
137
.enable = r600_audio_enable,
sys/dev/drm/radeon/radeon_audio.c
143
.enable = r600_audio_enable,
sys/dev/drm/radeon/radeon_audio.c
149
.enable = dce4_audio_enable,
sys/dev/drm/radeon/radeon_audio.c
155
.enable = dce6_audio_enable,
sys/dev/drm/radeon/radeon_audio.c
276
if (rdev->audio.funcs->enable)
sys/dev/drm/radeon/radeon_audio.c
277
rdev->audio.funcs->enable(rdev, pin, enable_mask);
sys/dev/drm/radeon/radeon_audio.h
40
void (*enable)(struct radeon_device *rdev,
sys/dev/drm/radeon/radeon_clocks.c
472
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
sys/dev/drm/radeon/radeon_clocks.c
476
if (enable) {
sys/dev/drm/radeon/radeon_dp_mst.c
27
enum radeon_hpd_id hpd, bool enable)
sys/dev/drm/radeon/radeon_dp_mst.c
41
if (enable)
sys/dev/drm/radeon/radeon_dp_mst.c
50
if (enable) {
sys/dev/drm/radeon/radeon_irq_kms.c
572
bool enable, const char *name, unsigned n)
sys/dev/drm/radeon/radeon_irq_kms.c
577
if (!!(tmp & mask) == enable)
sys/dev/drm/radeon/radeon_irq_kms.c
580
if (enable) {
sys/dev/drm/radeon/radeon_pm.c
1183
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/radeon_pm.c
1191
enable |= rdev->pm.dpm.sd > 0;
sys/dev/drm/radeon/radeon_pm.c
1192
enable |= rdev->pm.dpm.hd > 0;
sys/dev/drm/radeon/radeon_pm.c
1194
radeon_dpm_powergate_uvd(rdev, !enable);
sys/dev/drm/radeon/radeon_pm.c
1197
if (enable) {
sys/dev/drm/radeon/radeon_pm.c
1225
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/radeon_pm.c
1227
if (enable) {
sys/dev/drm/radeon/rs600.c
401
unsigned enable = 0;
sys/dev/drm/radeon/rs600.c
418
enable |= 1 << radeon_connector->hpd.hpd;
sys/dev/drm/radeon/rs600.c
421
radeon_irq_kms_enable_hpd(rdev, enable);
sys/dev/drm/radeon/rs780_dpm.c
303
static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/rs780_dpm.c
305
if (enable)
sys/dev/drm/radeon/rs780_dpm.c
313
static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/rs780_dpm.c
315
if (enable)
sys/dev/drm/radeon/rs780_dpm.c
72
static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/rv6xx_dpm.c
1171
static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1173
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1256
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1258
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1265
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1267
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1391
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1395
if (enable) {
sys/dev/drm/radeon/rv6xx_dpm.c
1410
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1415
r600_enable_thermal_protection(rdev, enable);
sys/dev/drm/radeon/rv6xx_dpm.c
1473
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1475
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1496
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
1500
if (enable) {
sys/dev/drm/radeon/rv6xx_dpm.c
330
u32 index, bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
332
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
353
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
355
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
362
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
364
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
371
u32 index, bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
373
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
89
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
94
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
968
bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
972
if (enable)
sys/dev/drm/radeon/rv6xx_dpm.c
981
static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/rv6xx_dpm.c
983
if (enable) {
sys/dev/drm/radeon/rv740_dpm.c
402
bool enable)
sys/dev/drm/radeon/rv740_dpm.c
404
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
1338
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
1340
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
135
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
1365
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
1367
rv770_enable_bif_dynamic_pcie_gen2(rdev, enable);
sys/dev/drm/radeon/rv770_dpm.c
1369
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
137
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
148
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
152
if (enable) {
sys/dev/drm/radeon/rv770_dpm.c
1856
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
1860
if (enable) {
sys/dev/drm/radeon/rv770_dpm.c
218
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
220
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
74
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
776
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
778
if (enable)
sys/dev/drm/radeon/rv770_dpm.c
785
bool enable)
sys/dev/drm/radeon/rv770_dpm.c
789
if (enable) {
sys/dev/drm/radeon/rv770_dpm.c
80
if (enable) {
sys/dev/drm/radeon/rv770_dpm.h
194
bool enable);
sys/dev/drm/radeon/rv770_dpm.h
210
bool enable);
sys/dev/drm/radeon/rv770_dpm.h
244
bool enable);
sys/dev/drm/radeon/rv770_dpm.h
246
bool enable);
sys/dev/drm/radeon/rv770_dpm.h
248
bool enable);
sys/dev/drm/radeon/rv770_dpm.h
251
bool enable);
sys/dev/drm/radeon/si.c
125
bool enable);
sys/dev/drm/radeon/si.c
3450
static void si_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si.c
3452
if (enable)
sys/dev/drm/radeon/si.c
5132
bool enable)
sys/dev/drm/radeon/si.c
5138
if (enable)
sys/dev/drm/radeon/si.c
5144
if (!enable) {
sys/dev/drm/radeon/si.c
5216
static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si.c
5221
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
sys/dev/drm/radeon/si.c
5241
bool enable)
sys/dev/drm/radeon/si.c
5245
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
sys/dev/drm/radeon/si.c
5342
bool enable)
sys/dev/drm/radeon/si.c
5348
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
sys/dev/drm/radeon/si.c
5382
bool enable)
sys/dev/drm/radeon/si.c
5386
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
sys/dev/drm/radeon/si.c
5438
bool enable)
sys/dev/drm/radeon/si.c
5442
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
sys/dev/drm/radeon/si.c
5483
bool enable)
sys/dev/drm/radeon/si.c
5490
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
sys/dev/drm/radeon/si.c
5500
bool enable)
sys/dev/drm/radeon/si.c
5507
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
sys/dev/drm/radeon/si.c
5517
bool enable)
sys/dev/drm/radeon/si.c
5522
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
sys/dev/drm/radeon/si.c
5554
bool enable)
sys/dev/drm/radeon/si.c
5560
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
sys/dev/drm/radeon/si.c
5572
bool enable)
sys/dev/drm/radeon/si.c
5578
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
sys/dev/drm/radeon/si.c
5588
bool enable)
sys/dev/drm/radeon/si.c
5594
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
sys/dev/drm/radeon/si.c
5604
u32 block, bool enable)
sys/dev/drm/radeon/si.c
5609
if (enable) {
sys/dev/drm/radeon/si.c
5620
si_enable_mc_mgcg(rdev, enable);
sys/dev/drm/radeon/si.c
5621
si_enable_mc_ls(rdev, enable);
sys/dev/drm/radeon/si.c
5625
si_enable_dma_mgcg(rdev, enable);
sys/dev/drm/radeon/si.c
5629
si_enable_bif_mgls(rdev, enable);
sys/dev/drm/radeon/si.c
5634
si_enable_uvd_mgcg(rdev, enable);
sys/dev/drm/radeon/si.c
5639
si_enable_hdp_mgcg(rdev, enable);
sys/dev/drm/radeon/si.c
5640
si_enable_hdp_ls(rdev, enable);
sys/dev/drm/radeon/si.c
5834
static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si.c
5839
if (enable)
sys/dev/drm/radeon/si.c
5845
if (!enable) {
sys/dev/drm/radeon/si_dpm.c
1744
extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/si_dpm.c
2440
bool enable)
sys/dev/drm/radeon/si_dpm.c
2447
if (enable) {
sys/dev/drm/radeon/si_dpm.c
2801
bool enable)
sys/dev/drm/radeon/si_dpm.c
2809
if (enable) {
sys/dev/drm/radeon/si_dpm.c
3318
bool enable)
sys/dev/drm/radeon/si_dpm.c
3322
if (enable) {
sys/dev/drm/radeon/si_dpm.c
3345
static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si_dpm.c
3347
if (enable)
sys/dev/drm/radeon/si_dpm.c
3592
bool enable)
sys/dev/drm/radeon/si_dpm.c
3594
if (enable)
sys/dev/drm/radeon/si_dpm.c
3729
static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si_dpm.c
3733
if (enable) {
sys/dev/drm/radeon/si_dpm.c
5713
static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/si_dpm.c
5715
if (enable)
sys/dev/drm/radeon/si_dpm.c
5959
bool enable)
sys/dev/drm/radeon/si_dpm.c
5963
if (enable) {
sys/dev/drm/radeon/sumo_dpm.c
106
static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
114
if (enable) {
sys/dev/drm/radeon/sumo_dpm.c
277
static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
279
if (enable)
sys/dev/drm/radeon/sumo_dpm.c
583
static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
590
enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
sys/dev/drm/radeon/sumo_dpm.c
593
enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
sys/dev/drm/radeon/sumo_dpm.c
596
enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
sys/dev/drm/radeon/sumo_dpm.c
599
enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
sys/dev/drm/radeon/sumo_dpm.c
620
static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
622
if (enable)
sys/dev/drm/radeon/sumo_dpm.c
718
bool enable)
sys/dev/drm/radeon/sumo_dpm.c
722
if (enable) {
sys/dev/drm/radeon/sumo_dpm.c
872
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
882
if (enable)
sys/dev/drm/radeon/sumo_dpm.c
891
static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
893
if (enable) {
sys/dev/drm/radeon/sumo_dpm.c
91
static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
93
if (enable)
sys/dev/drm/radeon/sumo_dpm.c
955
static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_dpm.c
957
if (enable) {
sys/dev/drm/radeon/sumo_dpm.h
195
void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/sumo_dpm.h
216
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/sumo_smc.c
208
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/sumo_smc.c
213
boost_disable |= (enable ? 0 : 1);
sys/dev/drm/radeon/trinity_dpm.c
1094
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/trinity_dpm.c
1100
trinity_dpm_bapm_enable(rdev, enable);
sys/dev/drm/radeon/trinity_dpm.c
345
extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/trinity_dpm.c
408
bool enable)
sys/dev/drm/radeon/trinity_dpm.c
413
if (enable) {
sys/dev/drm/radeon/trinity_dpm.c
448
bool enable)
sys/dev/drm/radeon/trinity_dpm.c
450
if (enable) {
sys/dev/drm/radeon/trinity_dpm.c
491
bool enable)
sys/dev/drm/radeon/trinity_dpm.c
496
if (enable) {
sys/dev/drm/radeon/trinity_dpm.c
508
bool enable)
sys/dev/drm/radeon/trinity_dpm.c
510
if (enable) {
sys/dev/drm/radeon/trinity_dpm.c
522
bool enable)
sys/dev/drm/radeon/trinity_dpm.c
526
if (enable) {
sys/dev/drm/radeon/trinity_dpm.c
739
u32 index, bool enable)
sys/dev/drm/radeon/trinity_dpm.c
746
if (enable)
sys/dev/drm/radeon/trinity_dpm.h
122
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/trinity_dpm.h
123
int trinity_dpm_config(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/trinity_dpm.h
129
bool enable);
sys/dev/drm/radeon/trinity_smc.c
101
if (enable)
sys/dev/drm/radeon/trinity_smc.c
56
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/trinity_smc.c
58
if (enable)
sys/dev/drm/radeon/trinity_smc.c
64
int trinity_dpm_config(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/trinity_smc.c
66
if (enable)
sys/dev/drm/radeon/trinity_smc.c
99
bool enable)
sys/dev/drm/radeon/vce_v1_0.c
102
void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/drm/radeon/vce_v1_0.c
103
void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/vce_v1_0.c
107
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
sys/dev/drm/radeon/vce_v2_0.c
111
void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/drm/radeon/vce_v2_0.c
115
if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
sys/dev/misc/ipmi/ipmi.c
946
int enable;
sys/dev/misc/ipmi/ipmi.c
952
enable = sc->ipmi_wdog_enable;
sys/dev/misc/ipmi/ipmi.c
955
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/dev/misc/ipmi/ipmi.c
960
sc->ipmi_wdog_enable = enable;
sys/dev/misc/kbd/atkbd.c
143
(*sw->enable)(*kbd);
sys/dev/misc/kbd/atkbd.c
248
.enable = atkbd_enable,
sys/dev/misc/kbd/kbdreg.h
189
kbd_enable_t *enable;
sys/dev/misc/kbd/kbdsw.c
131
error = (*kbdsw[kbd->kb_index]->enable)(kbd);
sys/dev/misc/kbdmux/kbdmux.c
1211
if ((error = (*sw->enable)(kbd)) != 0) {
sys/dev/misc/kbdmux/kbdmux.c
262
.enable = kbdmux_enable,
sys/dev/misc/vkbd/vkbd.c
254
if ((error = (*sw->enable)(kbd)) != 0) {
sys/dev/misc/vkbd/vkbd.c
714
.enable = vkbd_enable,
sys/dev/netif/ath/ath/if_ath.c
6406
ath_node_powersave(struct ieee80211_node *ni, int enable)
sys/dev/netif/ath/ath/if_ath.c
6420
!! enable);
sys/dev/netif/ath/ath/if_ath.c
6426
!! enable);
sys/dev/netif/ath/ath/if_ath.c
6430
if (enable)
sys/dev/netif/ath/ath/if_ath.c
6436
avp->av_node_ps(ni, enable);
sys/dev/netif/ath/ath/if_ath.c
6441
avp->av_node_ps(ni, enable);
sys/dev/netif/ath/ath/if_ath.c
6481
ath_node_set_tim(struct ieee80211_node *ni, int enable)
sys/dev/netif/ath/ath/if_ath.c
6491
an->an_stack_psq = enable;
sys/dev/netif/ath/ath/if_ath.c
6519
if (enable && an->an_tim_set == 1) {
sys/dev/netif/ath/ath/if_ath.c
6525
enable);
sys/dev/netif/ath/ath/if_ath.c
6532
enable);
sys/dev/netif/ath/ath/if_ath.c
6535
} else if (enable) {
sys/dev/netif/ath/ath/if_ath.c
6541
enable);
sys/dev/netif/ath/ath/if_ath.c
6548
enable);
sys/dev/netif/ath/ath/if_ath.c
6552
changed = avp->av_set_tim(ni, enable);
sys/dev/netif/ath/ath/if_ath.c
6560
enable);
sys/dev/netif/ath/ath/if_ath.c
6567
enable);
sys/dev/netif/ath/ath/if_ath.c
6571
changed = avp->av_set_tim(ni, enable);
sys/dev/netif/ath/ath/if_ath.c
6581
enable);
sys/dev/netif/ath/ath/if_ath.c
6588
enable);
sys/dev/netif/ath/ath/if_ath.c
6592
changed = avp->av_set_tim(ni, enable);
sys/dev/netif/ath/ath/if_ath.c
6605
enable);
sys/dev/netif/ath/ath/if_ath.c
6612
enable);
sys/dev/netif/ath/ath/if_ath.c
6628
return (avp->av_set_tim(ni, enable));
sys/dev/netif/ath/ath/if_ath.c
6655
int enable)
sys/dev/netif/ath/ath/if_ath.c
6677
if (enable) {
sys/dev/netif/ath/ath/if_ath_misc.h
95
struct ieee80211_node *ni, int enable);
sys/dev/netif/ath/ath/if_ath_sysctl.c
766
int error, enable;
sys/dev/netif/ath/ath/if_ath_sysctl.c
768
enable = (sc->sc_alq.sc_alq_isactive);
sys/dev/netif/ath/ath/if_ath_sysctl.c
770
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/dev/netif/ath/ath/if_ath_sysctl.c
773
else if (enable)
sys/dev/netif/ath/ath_hal/ah_osdep.c
217
ath_hal_setlogging(int enable)
sys/dev/netif/ath/ath_hal/ah_osdep.c
221
if (enable) {
sys/dev/netif/ath/ath_hal/ah_osdep.c
242
int error, enable;
sys/dev/netif/ath/ath_hal/ah_osdep.c
244
enable = (ath_hal_alq != NULL);
sys/dev/netif/ath/ath_hal/ah_osdep.c
245
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/dev/netif/ath/ath_hal/ah_osdep.c
249
return (ath_hal_setlogging(enable));
sys/dev/netif/ath/ath_hal/ar5212/ar5212_ani.c
151
const struct ar5212AniParams *params5, HAL_BOOL enable)
sys/dev/netif/ath/ath_hal/ar5212/ar5212_ani.c
172
if (enable) { /* Enable ani now */
sys/dev/netif/ath/ath_hal/ar5416/ar5416.h
263
const struct ieee80211_channel *chan, HAL_BOOL enable);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_ani.c
132
const struct ar5212AniParams *params5, HAL_BOOL enable)
sys/dev/netif/ath/ath_hal/ar5416/ar5416_ani.c
149
if (enable) { /* Enable ani now */
sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c
563
HAL_BOOL enable)
sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c
576
HALASSERT(enable == AH_FALSE);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c
578
if (enable == AH_TRUE)
sys/dev/netif/bwn/bwn/if_bwn.c
2614
bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
sys/dev/netif/bwn/bwn/if_bwn.c
2625
if (enable)
sys/dev/netif/bwn/bwn/if_bwn.c
2631
if (enable)
sys/dev/netif/ig_hal/e1000_82575.c
2274
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
sys/dev/netif/ig_hal/e1000_82575.c
2291
if (enable) {
sys/dev/netif/ig_hal/e1000_82575.c
2312
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
sys/dev/netif/ig_hal/e1000_82575.c
2319
if (enable)
sys/dev/netif/ig_hal/e1000_82575.c
2328
if (enable)
sys/dev/netif/ig_hal/e1000_82575.c
2349
void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
sys/dev/netif/ig_hal/e1000_82575.c
2353
if (enable)
sys/dev/netif/ig_hal/e1000_82575.h
479
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
sys/dev/netif/ig_hal/e1000_82575.h
480
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
sys/dev/netif/ig_hal/e1000_82575.h
481
void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
sys/dev/netif/ig_hal/e1000_ich8lan.c
2758
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
sys/dev/netif/ig_hal/e1000_ich8lan.c
2777
if (enable) {
sys/dev/netif/ig_hal/e1000_ich8lan.h
341
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
sys/dev/netif/iwm/if_iwm.c
1709
cmd.enable = 1;
sys/dev/netif/iwm/if_iwmreg.h
5336
uint8_t enable;
sys/dev/netif/iwn/if_iwn.c
6608
cmd.ucode.once.enable = 0xffffffff;
sys/dev/netif/iwn/if_iwn.c
7672
cmd.ucode.once.enable = htole32(0xffffffff);
sys/dev/netif/iwn/if_iwnreg.h
841
uint32_t enable;
sys/dev/netif/ix/ixgbe_api.c
1209
void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
sys/dev/netif/ix/ixgbe_api.c
1213
hw->mac.ops.set_source_address_pruning(hw, enable, pool);
sys/dev/netif/ix/ixgbe_api.c
1223
void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
sys/dev/netif/ix/ixgbe_api.c
1226
hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
sys/dev/netif/ix/ixgbe_api.h
209
void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
sys/dev/netif/ix/ixgbe_api.h
211
void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,
sys/dev/netif/ix/ixgbe_common.c
4385
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
sys/dev/netif/ix/ixgbe_common.c
4395
if (enable)
sys/dev/netif/ix/ixgbe_common.c
4409
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
sys/dev/netif/ix/ixgbe_common.c
4419
if (enable)
sys/dev/netif/ix/ixgbe_common.h
155
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
sys/dev/netif/ix/ixgbe_common.h
156
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
sys/dev/netif/ix/ixgbe_x550.c
1047
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
sys/dev/netif/ix/ixgbe_x550.c
1059
if (enable)
sys/dev/netif/ix/ixgbe_x550.c
1076
bool enable, int vf)
sys/dev/netif/ix/ixgbe_x550.c
1085
if (enable)
sys/dev/netif/ix/ixgbe_x550.h
61
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
sys/dev/netif/ix/ixgbe_x550.h
64
bool enable, int vf);
sys/dev/netif/mxge/if_mxge.c
736
mxge_dummy_rdma(mxge_softc_t *sc, int enable)
sys/dev/netif/mxge/if_mxge.c
765
buf[5] = htobe32(enable); /* enable? */
sys/dev/netif/mxge/if_mxge.c
780
(enable ? "enable" : "disable"), confirm, *confirm);
sys/dev/netif/oce/oce_hw.h
1938
uint32_t enable;
sys/dev/netif/oce/oce_if.c
1884
if (!aic->enable) {
sys/dev/netif/oce/oce_if.h
1019
int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable);
sys/dev/netif/oce/oce_if.h
1038
uint8_t loopback_type, uint8_t enable);
sys/dev/netif/oce/oce_if.h
516
boolean_t enable;
sys/dev/netif/oce/oce_mbox.c
1335
uint8_t loopback_type, uint8_t enable)
sys/dev/netif/oce/oce_mbox.c
1355
fwcmd->params.req.loopback_state = enable;
sys/dev/netif/oce/oce_mbox.c
820
oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable)
sys/dev/netif/oce/oce_mbox.c
838
if (enable) {
sys/dev/netif/oce/oce_queue.c
125
aic->enable = TRUE;
sys/dev/raid/aac/aac.c
115
static void aac_sa_set_interrupts(struct aac_softc *sc, int enable);
sys/dev/raid/aac/aac.c
137
static void aac_rx_set_interrupts(struct aac_softc *sc, int enable);
sys/dev/raid/aac/aac.c
164
static void aac_rkt_set_interrupts(struct aac_softc *sc, int enable);
sys/dev/raid/aac/aac.c
2545
aac_sa_set_interrupts(struct aac_softc *sc, int enable)
sys/dev/raid/aac/aac.c
2547
fwprintf(sc, HBA_FLAGS_DBG_FUNCTION_ENTRY_B, "%sable interrupts", enable ? "en" : "dis");
sys/dev/raid/aac/aac.c
2549
if (enable) {
sys/dev/raid/aac/aac.c
2557
aac_rx_set_interrupts(struct aac_softc *sc, int enable)
sys/dev/raid/aac/aac.c
2559
fwprintf(sc, HBA_FLAGS_DBG_FUNCTION_ENTRY_B, "%sable interrupts", enable ? "en" : "dis");
sys/dev/raid/aac/aac.c
2561
if (enable) {
sys/dev/raid/aac/aac.c
2572
aac_rkt_set_interrupts(struct aac_softc *sc, int enable)
sys/dev/raid/aac/aac.c
2574
fwprintf(sc, HBA_FLAGS_DBG_FUNCTION_ENTRY_B, "%sable interrupts", enable ? "en" : "dis");
sys/dev/raid/aac/aac.c
2576
if (enable) {
sys/dev/raid/aac/aacvar.h
246
void (*aif_set_interrupts)(struct aac_softc *sc, int enable);
sys/dev/raid/hpt27xx/him.h
236
HPT_U8 enable;
sys/dev/raid/hpt27xx/him.h
241
HPT_U8 enable;
sys/dev/raid/hpt27xx/himfuncs.h
56
_HIM_INTERFACE(void, route_irq, (void *adapter, HPT_BOOL enable))
sys/dev/raid/hpt27xx/himfuncs.h
81
_HIM_INTERFACE(HPT_BOOL, intr_control, (void * adapter, HPT_BOOL enable))
sys/dev/raid/hpt27xx/hptintf.h
2097
int hpt_set_perfmon_status(int ctlr_id, int enable);
sys/dev/raid/hpt27xx/ldm.h
229
void ldm_set_autorebuild(PVBUS vbus, int enable);
sys/dev/raid/hptmv/entry.c
1102
int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
sys/dev/raid/hptmv/entry.c
1117
if (enable) {
sys/dev/raid/hptmv/entry.c
1140
int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
sys/dev/raid/hptmv/entry.c
1145
int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
sys/dev/raid/hptmv/entry.c
1161
if (enable) {
sys/dev/raid/hptmv/entry.c
1184
int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
sys/dev/raid/hptmv/entry.c
1200
if (enable) {
sys/dev/raid/hptmv/global.h
183
int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth);
sys/dev/raid/hptmv/global.h
184
int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth);
sys/dev/raid/hptmv/global.h
185
int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable);
sys/dev/raid/hptmv/global.h
186
int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable);
sys/dev/raid/hptrr/him.h
210
HPT_U8 enable;
sys/dev/raid/hptrr/him.h
215
HPT_U8 enable;
sys/dev/raid/hptrr/himfuncs.h
57
_HIM_INTERFACE(void, route_irq, (void *adapter, HPT_BOOL enable))
sys/dev/raid/hptrr/himfuncs.h
82
_HIM_INTERFACE(HPT_BOOL, intr_control, (void * adapter, HPT_BOOL enable))
sys/dev/raid/hptrr/ldm.h
225
void ldm_set_autorebuild(PVBUS vbus, int enable);
sys/dev/raid/ida/ida_pci.c
120
ida_v4_int_enable(struct ida_softc *ida, int enable)
sys/dev/raid/ida/ida_pci.c
122
if (enable)
sys/dev/raid/ida/ida_pci.c
127
enable ? INT_ENABLE_42XX : INT_DISABLE_42XX);
sys/dev/raid/ida/ida_pci.c
80
ida_v3_int_enable(struct ida_softc *ida, int enable)
sys/dev/raid/ida/ida_pci.c
82
if (enable)
sys/dev/raid/ida/ida_pci.c
86
ida_outl(ida, R_INT_MASK, enable ? INT_ENABLE : INT_DISABLE);
sys/dev/sound/pci/atiixp.c
872
uint32_t status, enable, detected_codecs;
sys/dev/sound/pci/atiixp.c
911
enable = atiixp_rd(sc, ATI_REG_IER);
sys/dev/sound/pci/atiixp.c
912
enable &= ~detected_codecs;
sys/dev/sound/pci/atiixp.c
913
atiixp_wr(sc, ATI_REG_IER, enable);
sys/dev/sound/pci/aureal.c
235
au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
sys/dev/sound/pci/aureal.c
241
x |= (enable << c);
sys/dev/sound/pci/emu10k1.c
459
emu_enastop(struct sc_info *sc, char channel, int enable)
sys/dev/sound/pci/emu10k1.c
465
emu_wrptr(sc, 0, reg, enable);
sys/dev/sound/pci/emu10kx.c
1451
emu_vstop(struct emu_sc_info *sc, char channel, int enable)
sys/dev/sound/pci/emu10kx.c
1459
emu_wrptr(sc, 0, reg, enable);
sys/dev/sound/pci/emu10kx.c
407
static void emu_vstop(struct emu_sc_info *sc, char channel, int enable);
sys/dev/sound/pci/hda/hdaa.c
1179
(w->enable == 0) ? " [DISABLED]" : "");
sys/dev/sound/pci/hda/hdaa.c
1247
else if (cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
222
if (ctl->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2277
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2322
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2328
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2396
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2444
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2473
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2482
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2554
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2583
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2629
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2725
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2732
if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
sys/dev/sound/pci/hda/hdaa.c
2815
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
2831
if (ctl->enable == 0 ||
sys/dev/sound/pci/hda/hdaa.c
2903
uint32_t data, dir, enable, wake, unsol, sticky;
sys/dev/sound/pci/hda/hdaa.c
2908
enable = hda_command(dev,
sys/dev/sound/pci/hda/hdaa.c
2920
if ((enable & (1 << i)) == 0) {
sys/dev/sound/pci/hda/hdaa.c
3004
w->enable = 1;
sys/dev/sound/pci/hda/hdaa.c
3041
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3052
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3081
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3099
ctls[cnt].enable = 1;
sys/dev/sound/pci/hda/hdaa.c
3141
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3143
ctls[cnt].enable = 1;
sys/dev/sound/pci/hda/hdaa.c
3164
ctls[cnt].enable = 1;
sys/dev/sound/pci/hda/hdaa.c
3198
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3240
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3265
as[cnt].enable = 1;
sys/dev/sound/pci/hda/hdaa.c
3276
as[cnt].enable = 0;
sys/dev/sound/pci/hda/hdaa.c
3283
as[cnt].enable = 0;
sys/dev/sound/pci/hda/hdaa.c
3327
as[i].enable?"":" (disabled)");
sys/dev/sound/pci/hda/hdaa.c
3355
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3466
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3506
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3558
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3658
if (w3 == NULL || w3->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3700
if (w3 == NULL || w3->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3703
if (w4 == NULL || w4->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3756
if (w2 == NULL || w2->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3811
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3927
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
3968
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4016
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4046
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4073
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4103
if (as[j].enable)
sys/dev/sound/pci/hda/hdaa.c
4139
if (as[j].enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4162
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4166
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4187
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4193
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4202
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4217
if (ctl->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4219
if (ctl->widget->enable == 0 ||
sys/dev/sound/pci/hda/hdaa.c
4221
ctl->childwidget->enable == 0)) {
sys/dev/sound/pci/hda/hdaa.c
4226
ctl->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4243
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4249
if (cw == NULL || cw->enable == 0) {
sys/dev/sound/pci/hda/hdaa.c
4272
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4287
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4297
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4321
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4324
w->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4336
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4356
if (ctl && ctl->enable) {
sys/dev/sound/pci/hda/hdaa.c
4361
ctl->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4366
if (ctl && ctl->enable) {
sys/dev/sound/pci/hda/hdaa.c
4371
ctl->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4375
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4391
if (ctl && ctl->enable) {
sys/dev/sound/pci/hda/hdaa.c
4396
ctl->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4415
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4451
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4464
if (cw == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4495
if (ctl->enable == 0 || ctl->childwidget == NULL)
sys/dev/sound/pci/hda/hdaa.c
4523
ctl->enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4553
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4618
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4660
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4669
if (wc == NULL || wc->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4767
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4825
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4866
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4896
if (as[j].enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4928
as[j].enable = 0;
sys/dev/sound/pci/hda/hdaa.c
4934
if (as[j].enable == 0)
sys/dev/sound/pci/hda/hdaa.c
4985
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5025
if (cw == NULL || cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5068
if (w->enable == 0) {
sys/dev/sound/pci/hda/hdaa.c
5075
} else if (w->bindas < 0 || as[w->bindas].enable == 0) {
sys/dev/sound/pci/hda/hdaa.c
5139
if (ctl->enable == 0 || ctl->ossmask != 0) {
sys/dev/sound/pci/hda/hdaa.c
520
if (w1 == NULL || w1->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5333
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5503
if (as[i].enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5536
if (as[i].enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5597
if (ctl->enable == 0 ||
sys/dev/sound/pci/hda/hdaa.c
5598
ctl->widget->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
571
if (w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
5786
(w->enable == 0)?" DISA":"");
sys/dev/sound/pci/hda/hdaa.c
5846
(w->enable == 0) ? " [DISABLED]" : "");
sys/dev/sound/pci/hda/hdaa.c
5908
else if (cw->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5931
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
5959
if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
sys/dev/sound/pci/hda/hdaa.c
5997
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
6032
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
6054
if (w == NULL || w->enable == 0)
sys/dev/sound/pci/hda/hdaa.c
626
if (w == NULL || w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
6277
(ctl->enable == 0) ? " [DISABLED]" :
sys/dev/sound/pci/hda/hdaa.c
6312
w->enable = 1;
sys/dev/sound/pci/hda/hdaa.c
6362
uint32_t data = 0, enable = 0, dir = 0;
sys/dev/sound/pci/hda/hdaa.c
6370
enable = hda_command(dev,
sys/dev/sound/pci/hda/hdaa.c
6379
if ((enable & (1 << i)) == 0) {
sys/dev/sound/pci/hda/hdaa.c
6835
if (w == NULL || w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
6918
if (w == NULL || w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
723
if (w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
786
if (w == NULL || w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.c
839
if (w == NULL || w->enable == 0 || w->type !=
sys/dev/sound/pci/hda/hdaa.h
139
int enable;
sys/dev/sound/pci/hda/hdaa.h
152
u_char enable;
sys/dev/sound/pci/hda/hdaa.h
98
int enable;
sys/dev/sound/pci/hda/hdaa_patches.c
506
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
583
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
587
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
590
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
593
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
596
w->enable = 0;
sys/dev/sound/pci/hda/hdaa_patches.c
659
w->enable = 0;
sys/dev/sound/pci/hda/hdac.c
229
uint8_t enable;
sys/dev/sound/pci/t4dwave.c
333
tr_enaint(struct tr_chinfo *ch, int enable)
sys/dev/sound/pci/t4dwave.c
346
i |= (enable? 1 : 0) << chan;
sys/dev/sound/pci/vibes.c
317
u_int32_t count, enable;
sys/dev/sound/pci/vibes.c
341
enable = sv_indirect_get(sc, SV_REG_ENABLE) | SV_RECORD_ENABLE;
sys/dev/sound/pci/vibes.c
342
sv_indirect_set(sc, SV_REG_ENABLE, enable);
sys/dev/sound/pci/vibes.c
347
enable = sv_indirect_get(sc, SV_REG_ENABLE) & ~SV_RECORD_ENABLE;
sys/dev/sound/pci/vibes.c
348
sv_indirect_set(sc, SV_REG_ENABLE, enable);
sys/dev/sound/pci/vibes.c
389
u_int32_t count, enable, speed;
sys/dev/sound/pci/vibes.c
417
enable = sv_indirect_get(sc, SV_REG_ENABLE);
sys/dev/sound/pci/vibes.c
418
enable = (enable | SV_PLAY_ENABLE) & ~SV_PLAYBACK_PAUSE;
sys/dev/sound/pci/vibes.c
419
sv_indirect_set(sc, SV_REG_ENABLE, enable);
sys/dev/sound/pci/vibes.c
424
enable = sv_indirect_get(sc, SV_REG_ENABLE) & ~SV_PLAY_ENABLE;
sys/dev/sound/pci/vibes.c
425
sv_indirect_set(sc, SV_REG_ENABLE, enable);
sys/dev/sound/pcm/ac97.c
1013
mask |= codec->mix[i].enable? 1 << i : 0;
sys/dev/sound/pcm/ac97.c
441
if (e->reg && e->enable && e->bits) {
sys/dev/sound/pcm/ac97.c
509
printf("ac97_setmixer: reg=%d, bits=%d, enable=%d\n", e->reg, e->bits, e->enable);
sys/dev/sound/pcm/ac97.c
52
unsigned enable:1; /* entry is enabled */
sys/dev/sound/pcm/ac97.c
692
k = codec->noext? codec->mix[i].enable : 1;
sys/dev/sound/pcm/ac97.c
735
codec->mix[i].enable = 1;
sys/dev/sound/pcm/ac97.c
743
codec->mix[i].enable = 1;
sys/dev/sound/pcm/ac97.c
745
codec->mix[i].enable = 0;
sys/dev/sound/pcm/ac97.c
747
codec->mix[i].enable = 0;
sys/dev/sound/pcm/ac97.c
751
printf("mixch %d, en=%d, b=%d\n", i, codec->mix[i].enable, codec->mix[i].bits);
sys/dev/sound/pcm/ac97.c
949
if (codec->mix[SOUND_MIXER_OGAIN].enable)
sys/dev/sound/pcm/ac97.c
951
if (codec->mix[SOUND_MIXER_PHONEOUT].enable)
sys/dev/sound/pcm/ac97.c
953
if (codec->mix[SOUND_MIXER_VOLUME].enable)
sys/dev/sound/pcm/ac97.c
973
codec->mix[SOUND_MIXER_OGAIN].enable = 1;
sys/dev/sound/pcm/ac97.c
974
codec->mix[SOUND_MIXER_PHONEOUT].enable = 1;
sys/dev/virtual/hyperv/vmbus/vmbus.c
167
.enable = cputimer_intr_default_enable,
sys/dev/virtual/nvmm/x86/nvmm_x86_svm.c
2659
bool enable = arg != NULL;
sys/dev/virtual/nvmm/x86/nvmm_x86_svm.c
2667
if (!enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_svm.c
2672
if (enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_svm.c
2679
if (enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c
3506
bool enable = arg != NULL;
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c
3509
if (enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c
3519
if (!enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c
3524
if (enable) {
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c
3531
if (enable) {
sys/dev/virtual/vmware/pvscsi/pvscsi.c
404
static int pvscsi_setup_req_call(struct pvscsi_softc *sc, uint32_t enable)
sys/dev/virtual/vmware/pvscsi/pvscsi.c
420
cmd.enable = enable;
sys/dev/virtual/vmware/pvscsi/pvscsi.c
71
static int pvscsi_setup_req_call(struct pvscsi_softc *sc, uint32_t enable);
sys/dev/virtual/vmware/pvscsi/pvscsi.h
166
uint32_t enable;
sys/dev/virtual/vmware/vmxnet3/if_vmx.c
650
int enable = 1;
sys/dev/virtual/vmware/vmxnet3/if_vmx.c
652
sc->vmx_irq_type = pci_alloc_1intr(sc->vmx_dev, enable, &rid,
sys/kern/kern_cputimer.c
383
cti->enable(cti);
sys/kern/subr_bus.c
1800
device_set_async_attach(device_t dev, int enable)
sys/kern/subr_bus.c
1802
if (enable)
sys/net/ip6fw/ip6_fw.c
120
SYSCTL_INT(_net_inet6_ip6_fw, OID_AUTO, enable, CTLFLAG_RW,
sys/net/ipfw/ip_fw2.c
5860
ipfw_ctl_set_disable(uint32_t disable, uint32_t enable)
sys/net/ipfw/ip_fw2.c
5868
enable |= (1 << IPFW_DEFAULT_SET);
sys/net/ipfw/ip_fw2.c
5869
set_disable = (ipfw_ctx[mycpuid]->ipfw_set_disable | disable) & ~enable;
sys/net/ipfw/ip_fw2.c
685
SYSCTL_PROC(_net_inet_ip_fw, OID_AUTO, enable, CTLTYPE_INT | CTLFLAG_RW,
sys/net/ipfw/ip_fw2.c
7146
int enable = nmsg->lmsg.u.ms_result;
sys/net/ipfw/ip_fw2.c
7150
if (fw_enable == enable)
sys/net/ipfw/ip_fw2.c
7153
fw_enable = enable;
sys/net/ipfw/ip_fw2.c
7166
int enable, error;
sys/net/ipfw/ip_fw2.c
7168
enable = fw_enable;
sys/net/ipfw/ip_fw2.c
7169
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/net/ipfw/ip_fw2.c
7175
nmsg.lmsg.u.ms_result = enable;
sys/net/ipfw3/ip_fw3.c
1361
int enable = lmsg->u.ms_result;
sys/net/ipfw3/ip_fw3.c
1363
if (sysctl_var_fw3_enable == enable)
sys/net/ipfw3/ip_fw3.c
1366
sysctl_var_fw3_enable = enable;
sys/net/ipfw3/ip_fw3.c
1381
int enable, error;
sys/net/ipfw3/ip_fw3.c
1383
enable = sysctl_var_fw3_enable;
sys/net/ipfw3/ip_fw3.c
1384
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/net/ipfw3/ip_fw3.c
1391
lmsg->u.ms_result = enable;
sys/net/ipfw3/ip_fw3.c
149
SYSCTL_PROC(_net_inet_ip_fw3, OID_AUTO, enable, CTLTYPE_INT | CTLFLAG_RW,
sys/net/netmap/netmap_freebsd.c
96
netmap_catch_packet_steering(struct netmap_generic_adapter *na, int enable)
sys/net/netmap/netmap_freebsd.c
98
if (enable) {
sys/net/netmap/netmap_generic.c
179
int generic_netmap_register(struct netmap_adapter *na, int enable)
sys/net/netmap/netmap_generic.c
194
if (enable) { /* Enable netmap mode. */
sys/net/netmap/netmap_kern.h
919
int generic_netmap_register(struct netmap_adapter *na, int enable);
sys/net/netmap/netmap_kern.h
925
void netmap_catch_packet_steering(struct netmap_generic_adapter *na, int enable);
sys/netbt/hci.h
2451
int (*enable)(device_t);
sys/netbt/hci_unit.c
156
err = (*unit->hci_if->enable)(unit->hci_dev);
sys/netbt/hci_unit.c
88
KKASSERT(hci_if->enable != NULL);
sys/netgraph/mppc/ng_mppc.c
256
if (cfg->enable) {
sys/netgraph/mppc/ng_mppc.c
363
if (!priv->xmit.cfg.enable) {
sys/netgraph/mppc/ng_mppc.c
378
if (!priv->recv.cfg.enable) {
sys/netgraph/mppc/ng_mppc.c
621
priv->recv.cfg.enable = 0;
sys/netgraph/mppc/ng_mppc.h
72
u_char enable; /* enable */
sys/netgraph7/bluetooth/include/ng_l2cap.h
562
u_int16_t enable; /* 0x00 - disable */
sys/netgraph7/bluetooth/l2cap/ng_l2cap_ulpi.c
1578
if (ip->enable)
sys/netgraph7/bluetooth/l2cap/ng_l2cap_ulpi.c
1589
if (ip->enable)
sys/netgraph7/bluetooth/l2cap/ng_l2cap_ulpi.c
1596
if (ip->enable)
sys/netgraph7/bluetooth/l2cap/ng_l2cap_ulpi.c
1603
if (ip->enable)
sys/netgraph7/deflate/ng_deflate.c
235
if (cfg->enable) {
sys/netgraph7/deflate/ng_deflate.c
242
if (priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.c
247
priv->cfg.enable = 0;
sys/netgraph7/deflate/ng_deflate.c
253
if (priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.c
266
priv->cfg.enable = 0;
sys/netgraph7/deflate/ng_deflate.c
275
priv->cfg.enable = 0;
sys/netgraph7/deflate/ng_deflate.c
333
if (!priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.c
379
if (priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.c
401
if (priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.c
406
priv->cfg.enable = 0;
sys/netgraph7/deflate/ng_deflate.c
674
if (priv->cfg.enable) {
sys/netgraph7/deflate/ng_deflate.h
44
u_char enable; /* node enabled */
sys/netgraph7/mppc/ng_mppc.c
271
if (cfg->enable) {
sys/netgraph7/mppc/ng_mppc.c
367
if (!priv->xmit.cfg.enable) {
sys/netgraph7/mppc/ng_mppc.c
382
if (!priv->recv.cfg.enable) {
sys/netgraph7/mppc/ng_mppc.c
635
priv->recv.cfg.enable = 0;
sys/netgraph7/mppc/ng_mppc.h
73
u_char enable; /* enable */
sys/netgraph7/ng_pred1.c
304
if (!priv->cfg.enable) {
sys/netgraph7/ng_pred1.h
44
u_char enable; /* node enabled */
sys/netproto/802_11/ieee80211_power.h
80
void ieee80211_node_pwrsave(struct ieee80211_node *, int enable);
sys/netproto/802_11/ieee80211_power.h
81
void ieee80211_sta_pwrsave(struct ieee80211vap *, int enable);
sys/netproto/802_11/wlan/ieee80211_alq.c
103
int error, enable;
sys/netproto/802_11/wlan/ieee80211_alq.c
105
enable = (ieee80211_alq != NULL);
sys/netproto/802_11/wlan/ieee80211_alq.c
106
error = sysctl_handle_int(oidp, &enable, 0, req);
sys/netproto/802_11/wlan/ieee80211_alq.c
110
return (ieee80211_alq_setlogging(enable));
sys/netproto/802_11/wlan/ieee80211_alq.c
70
ieee80211_alq_setlogging(int enable)
sys/netproto/802_11/wlan/ieee80211_alq.c
74
if (enable) {
sys/netproto/802_11/wlan/ieee80211_power.c
484
ieee80211_node_pwrsave(struct ieee80211_node *ni, int enable)
sys/netproto/802_11/wlan/ieee80211_power.c
490
if (enable) {
sys/netproto/802_11/wlan/ieee80211_power.c
526
ieee80211_sta_pwrsave(struct ieee80211vap *vap, int enable)
sys/netproto/802_11/wlan/ieee80211_power.c
530
if (!((enable != 0) ^ ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) != 0)))
sys/netproto/802_11/wlan/ieee80211_power.c
534
"sta power save mode %s", enable ? "on" : "off");
sys/netproto/802_11/wlan/ieee80211_power.c
535
if (!enable) {
sys/platform/pc64/apic/lapic.c
96
.enable = lapic_timer_intr_enable,
sys/platform/pc64/isa/clock.c
173
.enable = cputimer_intr_default_enable,
sys/platform/vkernel64/platform/systimer.c
109
.enable = cputimer_intr_default_enable,
sys/sys/bus.h
398
void device_set_async_attach(device_t dev, int enable);
sys/sys/fbio.h
177
short enable; /* nonzero => cursor on, 0 => cursor off */
sys/sys/systimer.h
203
void (*enable)
usr.bin/flame_graph/collect.c
171
int enable;
usr.bin/flame_graph/collect.c
173
enable = 0;
usr.bin/flame_graph/collect.c
175
NULL, NULL, &enable, sizeof(enable)) < 0) {
usr.bin/flame_graph/collect.c
49
int enable;
usr.bin/flame_graph/collect.c
62
enable = 1;
usr.bin/flame_graph/collect.c
65
NULL, NULL, &enable, sizeof(enable)) < 0) {
usr.sbin/inetd/inetd.c
1268
enable(sep);
usr.sbin/inetd/inetd.c
200
void enable(struct servtab *);
usr.sbin/inetd/inetd.c
896
enable(sep);
usr.sbin/inetd/inetd.c
994
enable(sep);
usr.sbin/ppp/physical.c
790
physical_SetRtsCts(struct physical *p, int enable)
usr.sbin/ppp/physical.c
792
p->cfg.rts_cts = enable ? 1 : 0;
