sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2211

struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2282

struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2430

struct dc_plane_state *dc_plane_state,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2439

if (!fill_rects_from_plane_state(plane_state, dc_plane_state))

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2444

dc_plane_state,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2454

ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2456

dc_transfer_func_release(dc_plane_state->in_transfer_func);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2457

dc_plane_state->in_transfer_func = NULL;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3541

struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4489

struct dc_plane_state **plane_states,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4587

struct dc_plane_state *plane_states_constructed[MAX_SURFACES];

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5443

struct dc_plane_state *dc_new_plane_state;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5536

struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.h

183

struct dc_plane_state;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.h

187

struct dc_plane_state *dc_state;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.h

276

struct dc_plane_state *dc_plane_state);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

244

struct dc_plane_state *dc_plane_state)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

254

dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

255

dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

261

dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

262

dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

281

dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

282

ret = mod_color_calculate_degamma_params(dc_plane_state->in_transfer_func, gamma, true);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

285

dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;

sys/dev/drm/amd/display/dc/core/dc.c

1110

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc.c

1555

struct dc_plane_state *plane_state = srf_updates[i].surface;

sys/dev/drm/amd/display/dc/core/dc.c

1580

struct dc_plane_state **plane_states,

sys/dev/drm/amd/display/dc/core/dc.c

1613

struct dc_plane_state *surface = srf_updates[i].surface;

sys/dev/drm/amd/display/dc/core/dc_debug.c

60

const struct dc_plane_state *const *plane_states,

sys/dev/drm/amd/display/dc/core/dc_debug.c

67

const struct dc_plane_state *plane_state = plane_states[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1106

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1353

struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1427

struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1507

struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };

sys/dev/drm/amd/display/dc/core/dc_resource.c

1560

struct dc_plane_state * const *plane_states,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2891

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_resource.c

489

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

617

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_resource.c

710

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/core/dc_surface.c

131

void dc_plane_state_retain(struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_surface.c

138

struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);

sys/dev/drm/amd/display/dc/core/dc_surface.c

143

void dc_plane_state_release(struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_surface.c

38

static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_surface.c

49

static void destruct(struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_surface.c

64

void enable_surface_flip_reporting(struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/core/dc_surface.c

71

struct dc_plane_state *dc_create_plane_state(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc_surface.c

75

struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),

sys/dev/drm/amd/display/dc/core/dc_surface.c

99

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dc.h

155

struct dc_plane_state;

sys/dev/drm/amd/display/dc/dc.h

542

struct dc_plane_state *surface;

sys/dev/drm/amd/display/dc/dc.h

562

struct dc_plane_state *dc_create_plane_state(struct dc *dc);

sys/dev/drm/amd/display/dc/dc.h

564

const struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/dc.h

566

void dc_plane_state_retain(struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/dc.h

567

void dc_plane_state_release(struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/dc.h

599

struct dc_plane_state *plane_states[MAX_SURFACES];

sys/dev/drm/amd/display/dc/dc.h

603

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/dc_stream.h

165

struct dc_plane_state **plane_states,

sys/dev/drm/amd/display/dc/dc_stream.h

204

struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/dc_stream.h

210

struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/dc_stream.h

221

struct dc_plane_state * const *plane_states,

sys/dev/drm/amd/display/dc/dc_stream.h

40

struct dc_plane_state *plane_states[MAX_SURFACE_NUM];

sys/dev/drm/amd/display/dc/dc_types.h

37

struct dc_plane_state;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

847

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.h

42

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2185

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2200

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

240

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2603

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

268

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

931

enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

954

struct dc_plane_state *plane =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1168

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1197

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1219

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1904

const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1924

static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2050

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2612

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1131

static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1141

static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/inc/core_types.h

112

enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);

sys/dev/drm/amd/display/dc/inc/core_types.h

124

struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/inc/core_types.h

216

struct dc_plane_state *plane_state;

sys/dev/drm/amd/display/dc/inc/core_types.h

42

void enable_surface_flip_reporting(struct dc_plane_state *plane_state,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

122

const struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/inc/resource.h

129

struct dc_plane_state *const *plane_state,

sys/dev/drm/amd/display/include/logger_interface.h

47

const struct dc_plane_state *const *plane_states,

sys/dev/drm/amd/display/modules/freesync/freesync.c

845

const struct dc_plane_state *plane,

sys/dev/drm/amd/display/modules/inc/mod_freesync.h

157

const struct dc_plane_state *plane,