crypto/libressl/crypto/evp/names.c

164

struct doall_cipher *dc = arg;

crypto/libressl/crypto/evp/names.c

167

dc->fn(NULL, nm->name, nm->data, dc->arg);

crypto/libressl/crypto/evp/names.c

169

dc->fn((const EVP_CIPHER *)nm->data, nm->name, NULL, dc->arg);

crypto/libressl/crypto/evp/names.c

176

struct doall_cipher dc;

crypto/libressl/crypto/evp/names.c

181

dc.fn = fn;

crypto/libressl/crypto/evp/names.c

182

dc.arg = arg;

crypto/libressl/crypto/evp/names.c

183

OBJ_NAME_do_all(OBJ_NAME_TYPE_CIPHER_METH, do_all_cipher_fn, &dc);

crypto/libressl/crypto/evp/names.c

190

struct doall_cipher dc;

crypto/libressl/crypto/evp/names.c

195

dc.fn = fn;

crypto/libressl/crypto/evp/names.c

196

dc.arg = arg;

crypto/libressl/crypto/evp/names.c

198

do_all_cipher_fn, &dc);

crypto/libressl/crypto/evp/names.c

210

struct doall_md *dc = arg;

crypto/libressl/crypto/evp/names.c

213

dc->fn(NULL, nm->name, nm->data, dc->arg);

crypto/libressl/crypto/evp/names.c

215

dc->fn((const EVP_MD *)nm->data, nm->name, NULL, dc->arg);

crypto/libressl/crypto/evp/names.c

222

struct doall_md dc;

crypto/libressl/crypto/evp/names.c

227

dc.fn = fn;

crypto/libressl/crypto/evp/names.c

228

dc.arg = arg;

crypto/libressl/crypto/evp/names.c

229

OBJ_NAME_do_all(OBJ_NAME_TYPE_MD_METH, do_all_md_fn, &dc);

crypto/libressl/crypto/evp/names.c

236

struct doall_md dc;

crypto/libressl/crypto/evp/names.c

241

dc.fn = fn;

crypto/libressl/crypto/evp/names.c

242

dc.arg = arg;

crypto/libressl/crypto/evp/names.c

243

OBJ_NAME_do_all_sorted(OBJ_NAME_TYPE_MD_METH, do_all_md_fn, &dc);

crypto/openssh/authfd.c

486

encode_dest_constraint(struct sshbuf *m, const struct dest_constraint *dc)

crypto/openssh/authfd.c

493

if ((r = encode_dest_constraint_hop(b, &dc->from)) != 0 ||

crypto/openssh/authfd.c

494

(r = encode_dest_constraint_hop(b, &dc->to)) != 0 ||

crypto/openssh/ssh-add.c

761

struct dest_constraint *dc;

crypto/openssh/ssh-add.c

764

dc = xcalloc(1, sizeof(*dc));

crypto/openssh/ssh-add.c

768

parse_dest_constraint_hop(os, &dc->to, hostkey_files);

crypto/openssh/ssh-add.c

772

parse_dest_constraint_hop(os, &dc->from, hostkey_files);

crypto/openssh/ssh-add.c

773

parse_dest_constraint_hop(cp, &dc->to, hostkey_files);

crypto/openssh/ssh-add.c

774

if (dc->from.user != NULL) {

crypto/openssh/ssh-add.c

781

dc->from.user ? dc->from.user : "", dc->from.user ? "@" : "",

crypto/openssh/ssh-add.c

782

dc->from.hostname ? dc->from.hostname : "(ORIGIN)", dc->from.nkeys,

crypto/openssh/ssh-add.c

783

dc->to.user ? dc->to.user : "", dc->to.user ? "@" : "",

crypto/openssh/ssh-add.c

784

dc->to.hostname ? dc->to.hostname : "(ANY)", dc->to.nkeys);

crypto/openssh/ssh-add.c

786

(*dcp)[(*ndcp)++] = dc;

crypto/openssh/ssh-agent.c

1127

parse_dest_constraint(struct sshbuf *m, struct dest_constraint *dc)

crypto/openssh/ssh-agent.c

1135

memset(dc, '\0', sizeof(*dc));

crypto/openssh/ssh-agent.c

1143

if ((r = parse_dest_constraint_hop(frombuf, &dc->from)) != 0 ||

crypto/openssh/ssh-agent.c

1144

(r = parse_dest_constraint_hop(tobuf, &dc->to)) != 0)

crypto/openssh/ssh-agent.c

1152

dc->from.hostname ? dc->from.hostname : "(ORIGIN)", dc->from.nkeys,

crypto/openssh/ssh-agent.c

1153

dc->to.user ? dc->to.user : "", dc->to.user ? "@" : "",

crypto/openssh/ssh-agent.c

1154

dc->to.hostname ? dc->to.hostname : "(ANY)", dc->to.nkeys);

crypto/openssh/ssh-agent.c

1156

if ((dc->from.hostname == NULL) != (dc->from.nkeys == 0) ||

crypto/openssh/ssh-agent.c

1157

dc->from.user != NULL) {

crypto/openssh/ssh-agent.c

1162

if (dc->to.hostname == NULL || dc->to.nkeys == 0) {

games/battlestar/fly.c

100

dc = 1;

games/battlestar/fly.c

105

dc = 5;

games/battlestar/fly.c

253

if (column + dc < COLS - 1 && column + dc > 0)

games/battlestar/fly.c

254

column += dc;

games/battlestar/fly.c

42

static int dr = 0, dc = 0;

games/battlestar/fly.c

89

dc = -1;

games/battlestar/fly.c

95

dc = -5;

games/rogue/monster.c

499

short dr, dc;

games/rogue/monster.c

505

dc = monster->col - col;

games/rogue/monster.c

506

if ((dc >= 2) || (dc <= -2)) {

games/sail/dr_2.c

232

*col -= dc[*dir] * dist;

games/sail/dr_2.c

241

*col -= dc[winddir];

games/sail/dr_3.c

248

sp->file->col -= dc[sp->file->dir] * dist;

games/sail/dr_3.c

259

sp->file->col -= dc[winddir];

games/sail/extern.h

247

extern const char dr[], dc[];

games/sail/extern.h

80

#define sterncol(sp) ((sp)->file->col + dc[(sp)->file->dir])

games/sail/globals.c

563

const char dc[] = { 0, 0, -1, -1, -1, 0, 1, 1, 1 };

games/sail/misc.c

153

Dc += dc[to->file->dir];

games/sail/misc.c

169

Dc += dc[on->file->dir];

games/sail/misc.c

71

stern2c += dc[to->file->dir];

games/sail/misc.c

73

stern1c += dc[from->file->dir];

games/sail/pl_7.c

695

wmove(slot_w, Y - dr[winddir], 1 - dc[winddir]);

games/sail/pl_7.c

714

mvwaddch(slot_w, Y + dr[winddir], 1 + dc[winddir], '+');

lib/libc/gen/glob.c

682

Char *dc;

lib/libc/gen/glob.c

704

dc = pathend;

lib/libc/gen/glob.c

706

while (dc < pathend_last) {

lib/libc/gen/glob.c

713

if ((*dc++ = wc) == EOS)

lib/libc/gen/glob.c

721

err = glob2(pathbuf, --dc, pathend_last, restpattern,

lib/libssh/openbsd-compat/glob.c

743

Char *dc;

lib/libssh/openbsd-compat/glob.c

757

dc = pathend;

lib/libssh/openbsd-compat/glob.c

759

while (dc < pathend_last && (*dc++ = *sc++) != EOS)

lib/libssh/openbsd-compat/glob.c

761

if (dc >= pathend_last) {

lib/libssh/openbsd-compat/glob.c

762

*dc = EOS;

lib/libssh/openbsd-compat/glob.c

771

err = glob2(pathbuf, pathbuf_last, --dc, pathend_last,

sbin/hammer2/cmd_service.c

850

struct diskcon *dc;

sbin/hammer2/cmd_service.c

871

TAILQ_FOREACH(dc, &diskconq, entry) {

sbin/hammer2/cmd_service.c

872

if (strcmp(dc->disk, disk) == 0)

sbin/hammer2/cmd_service.c

876

if (dc)

sbin/hammer2/cmd_service.c

908

dc = malloc(sizeof(*dc));

sbin/hammer2/cmd_service.c

909

dc->disk = strdup(disk);

sbin/hammer2/cmd_service.c

911

TAILQ_INSERT_TAIL(&diskconq, dc, entry);

sbin/hammer2/cmd_service.c

920

info->handle = dc;

sbin/hammer2/cmd_service.c

921

info->label = strdup(dc->disk);

sbin/hammer2/cmd_service.c

929

struct diskcon *dc = handle;

sbin/hammer2/cmd_service.c

931

fprintf(stderr, "DISK_DISCONNECT %s\n", dc->disk);

sbin/hammer2/cmd_service.c

934

TAILQ_REMOVE(&diskconq, dc, entry);

sbin/hammer2/cmd_service.c

936

free(dc->disk);

sbin/hammer2/cmd_service.c

937

free(dc);

sbin/ifconfig/ifieee80211.c

2217

const struct ieee80211_devcaps_req *dc)

sbin/ifconfig/ifieee80211.c

2255

IEEE80211_CHAN_B, &dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2258

IEEE80211_CHAN_G, &dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2261

IEEE80211_CHAN_A, &dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2262

if (!LIST_EMPTY(&rd->bands_11na) && dc->dc_htcaps != 0) {

sbin/ifconfig/ifieee80211.c

2265

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2266

if (dc->dc_htcaps & IEEE80211_HTCAP_CHWIDTH40) {

sbin/ifconfig/ifieee80211.c

2269

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2272

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2275

if (!LIST_EMPTY(&rd->bands_11ng) && dc->dc_htcaps != 0) {

sbin/ifconfig/ifieee80211.c

2278

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2279

if (dc->dc_htcaps & IEEE80211_HTCAP_CHWIDTH40) {

sbin/ifconfig/ifieee80211.c

2282

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2285

&dc->dc_chaninfo);

sbin/ifconfig/ifieee80211.c

2291

memcpy(ci, &dc->dc_chaninfo,

sbin/ifconfig/ifieee80211.c

2292

IEEE80211_CHANINFO_SPACE(&dc->dc_chaninfo));

sbin/ifconfig/ifieee80211.c

3938

struct ieee80211_devcaps_req *dc;

sbin/ifconfig/ifieee80211.c

3941

dc = malloc(IEEE80211_DEVCAPS_SIZE(MAXCHAN));

sbin/ifconfig/ifieee80211.c

3943

dc = malloc(IEEE80211_DEVCAPS_SIZE(1));

sbin/ifconfig/ifieee80211.c

3944

if (dc == NULL)

sbin/ifconfig/ifieee80211.c

3946

dc->dc_chaninfo.ic_nchans = verbose ? MAXCHAN : 1;

sbin/ifconfig/ifieee80211.c

3947

getdevcaps(s, dc);

sbin/ifconfig/ifieee80211.c

3948

printb("drivercaps", dc->dc_drivercaps, IEEE80211_C_BITS);

sbin/ifconfig/ifieee80211.c

3949

if (dc->dc_cryptocaps != 0 || verbose) {

sbin/ifconfig/ifieee80211.c

3951

printb("cryptocaps", dc->dc_cryptocaps, IEEE80211_CRYPTO_BITS);

sbin/ifconfig/ifieee80211.c

3953

if (dc->dc_htcaps != 0 || verbose) {

sbin/ifconfig/ifieee80211.c

3955

printb("htcaps", dc->dc_htcaps, IEEE80211_HTCAP_BITS);

sbin/ifconfig/ifieee80211.c

3959

chaninfo = &dc->dc_chaninfo; /* XXX */

sbin/ifconfig/ifieee80211.c

3960

print_channels(s, &dc->dc_chaninfo, 1/*allchans*/, verbose);

sbin/ifconfig/ifieee80211.c

3962

free(dc);

sbin/ifconfig/ifieee80211.c

454

getdevcaps(int s, struct ieee80211_devcaps_req *dc)

sbin/ifconfig/ifieee80211.c

456

if (get80211(s, IEEE80211_IOC_DEVCAPS, dc,

sbin/ifconfig/ifieee80211.c

457

IEEE80211_DEVCAPS_SPACE(dc)) < 0)

sbin/ifconfig/ifieee80211.c

466

struct ieee80211_devcaps_req *dc;

sbin/ifconfig/ifieee80211.c

512

dc = malloc(IEEE80211_DEVCAPS_SIZE(MAXCHAN));

sbin/ifconfig/ifieee80211.c

513

if (dc == NULL)

sbin/ifconfig/ifieee80211.c

515

dc->dc_chaninfo.ic_nchans = MAXCHAN;

sbin/ifconfig/ifieee80211.c

516

getdevcaps(s, dc);

sbin/ifconfig/ifieee80211.c

519

printf("drivercaps: 0x%x\n", dc->dc_drivercaps);

sbin/ifconfig/ifieee80211.c

520

printf("cryptocaps: 0x%x\n", dc->dc_cryptocaps);

sbin/ifconfig/ifieee80211.c

521

printf("htcaps : 0x%x\n", dc->dc_htcaps);

sbin/ifconfig/ifieee80211.c

522

memcpy(chaninfo, &dc->dc_chaninfo,

sbin/ifconfig/ifieee80211.c

523

IEEE80211_CHANINFO_SPACE(&dc->dc_chaninfo));

sbin/ifconfig/ifieee80211.c

524

print_channels(s, &dc->dc_chaninfo, true /* allchans */,

sbin/ifconfig/ifieee80211.c

528

req = malloc(IEEE80211_REGDOMAIN_SIZE(dc->dc_chaninfo.ic_nchans));

sbin/ifconfig/ifieee80211.c

532

regdomain_makechannels(req, dc);

sbin/ifconfig/ifieee80211.c

553

free(dc);

sys/bus/u4b/usb_hub.c

2295

devclass_t dc;

sys/bus/u4b/usb_hub.c

2301

dc = usb_devclass_ptr;

sys/bus/u4b/usb_hub.c

2302

if (dc == NULL) {

sys/bus/u4b/usb_hub.c

2309

max = devclass_get_maxunit(dc);

sys/bus/u4b/usb_hub.c

2311

dev = devclass_get_device(dc, max);

sys/bus/u4b/usb_pf.c

101

devclass_t dc;

sys/bus/u4b/usb_pf.c

108

dc = devclass_find(usbusname);

sys/bus/u4b/usb_pf.c

109

if (dc == NULL)

sys/bus/u4b/usb_pf.c

111

error = devclass_get_devices(dc, &devlp, &devlcnt);

sys/bus/u4b/usb_pf.c

133

devclass_t dc;

sys/bus/u4b/usb_pf.c

135

dc = devclass_find(usbusname);

sys/bus/u4b/usb_pf.c

136

if (dc == NULL)

sys/bus/u4b/usb_pf.c

138

dev = devclass_get_device(dc, unit);

sys/bus/u4b/usbdi.h

336

#define USB_DEV_CLASS(dc) \

sys/bus/u4b/usbdi.h

337

.match_flag_dev_class = 1, .bDeviceClass = (dc)

sys/dev/apple/smc/smc_io.c

440

uint32_t dc, bc, exp;

sys/dev/apple/smc/smc_io.c

443

dc = d; bc = 0;

sys/dev/apple/smc/smc_io.c

444

while (dc >>= 1) ++bc;

sys/dev/drm/amd/amdgpu/amdgpu_drv.c

352

MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");

sys/dev/drm/amd/amdgpu/amdgpu_drv.c

353

module_param_named(dc, amdgpu_dc, int, 0444);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1299

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1336

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1358

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1387

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1421

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1444

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1612

dc_resource_state_copy_construct_current(adev->dm.dc, state->context);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1759

if (plane_id >= dm->dc->caps.max_streams)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1817

link_cnt = dm->dc->caps.max_links;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1824

total_overlay_planes = dm->dc->caps.max_slave_planes;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1825

total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1843

for (i = 0; i < dm->dc->caps.max_streams; i++)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1849

dm->display_indexes_num = dm->dc->caps.max_streams;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1880

link = dc_get_link_at_index(dm->dc, i);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1934

dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1940

for (i = 0; i < dm->dc->caps.max_planes; i++)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3015

return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3337

dc_result = dc_validate_stream(adev->dm.dc, stream);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3376

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3390

if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

353

if (adev->dm.dc->fbc_compressor == NULL)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3589

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3598

if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3724

acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3725

acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

376

adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4009

ddc_service->ctx->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4065

struct dc *dc = dm->dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4066

struct dc_link *link = dc_get_link_at_index(dc, link_index);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

438

adev->dm.dc = dc_create(&init_data);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

440

if (adev->dm.dc) {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4467

dc_commit_updates_for_stream(adev->dm.dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

447

adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4488

struct dc *dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4564

dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4674

if (false == commit_planes_to_stream(dm->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

469

adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

470

adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4760

dc_resource_state_copy_construct_current(dm->dc, dc_state);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4837

WARN_ON(!dc_commit_state(dm->dc, dc_state));

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4897

dm->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

510

if (adev->dm.dc)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

511

dc_destroy(&adev->dm.dc);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5272

dm->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5313

dm->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5374

static int dm_update_planes_state(struct dc *dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5427

dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5463

dc_new_plane_state = dc_create_plane_state(dc);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5494

dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5519

dm_determine_update_type_for_commit(struct dc *dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5612

update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5640

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5682

ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5700

ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5742

ret = dm_determine_update_type_for_commit(dc, state, &update_type);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5771

if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5792

static bool is_dp_capable_without_timing_msa(struct dc *dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5858

adev->dm.dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

717

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

839

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

842

dc_resume(dm->dc);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.h

55

struct dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.h

75

struct dc *dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

145

if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

85

if (dc_stream_configure_crc(stream_state->ctx->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

95

if (dc_stream_configure_crc(stream_state->ctx->dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

145

struct dc *dc = (struct dc *)link->dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

230

dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

322

struct dc *dc = (struct dc *)link->dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

413

dc_link_set_drive_settings(dc, &link_lane_settings, link);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

735

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

742

if (!dc->hwss.log_hw_state)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

745

dc->hwss.log_hw_state(dc, &log_ctx);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

774

struct dc *dc = adev->dm.dc;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

780

if (dc->hwss.log_hw_state)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

781

dc->hwss.log_hw_state(dc, NULL);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

357

dc_interrupt_set(adev->dm.dc, src, false);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

384

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

410

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

483

adev->dm.dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

487

dc_interrupt_ack(adev->dm.dc, src);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

525

dc_interrupt_set(adev->dm.dc, src, st);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

556

dc_interrupt_set(adev->dm.dc, irq_source, st);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

636

dc_interrupt_set(adev->dm.dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

642

dc_interrupt_set(adev->dm.dc,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

667

dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

670

dc_interrupt_set(adev->dm.dc,

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3016

if (ctx->dc->debug.bandwidth_calcs_trace) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3067

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3097

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3125

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3153

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3188

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3218

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3246

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3274

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3308

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3337

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3365

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3393

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3441

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3469

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3497

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3525

if (ctx->dc->caps.max_slave_planes) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1002

(dc->debug.sr_exit_time_dpm0_ns

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1003

|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1005

if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1007

dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1008

if (dc->debug.sr_exit_time_dpm0_ns)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1009

v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1010

dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1011

dc->dml.soc.sr_exit_time_us = v->sr_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1027

if (dc->debug.voltage_align_fclk)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1059

if (dc->debug.max_disp_clk == true)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1060

context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1063

dc->debug.min_disp_clk_khz) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1065

dc->debug.min_disp_clk_khz;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1073

(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1077

(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1081

(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1085

(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1158

dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1174

dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1183

dc->dml.soc.sr_enter_plus_exit_time_us =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1184

dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1185

dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1192

bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1206

const struct dc *dc,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1217

if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1220

} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1222

} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1224

} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1230

if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1233

} else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1235

} else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1237

} else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1244

if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1247

} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1249

} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1251

} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1259

unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1261

if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1264

} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1266

} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1268

} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1276

if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1279

} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1281

} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1283

} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1296

const struct dc *dc,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1304

dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1306

dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1310

dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1314

dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1317

dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1323

dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1325

dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1327

dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1329

dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1331

dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1352

void dcn_bw_update_from_pplib(struct dc *dc)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1354

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1369

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1370

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1373

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1376

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1389

dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1390

dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1391

dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1392

dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1399

void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1401

struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1410

min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1411

min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1412

socclk_khz = dc->dcn_soc->socclk * 1000;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1436

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1462

void dcn_bw_sync_calcs_and_dml(struct dc *dc)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1499

dc->dcn_soc->sr_exit_time * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1500

dc->dcn_soc->sr_enter_plus_exit_time * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1501

dc->dcn_soc->urgent_latency * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1502

dc->dcn_soc->write_back_latency * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1503

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1504

dc->dcn_soc->max_request_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1505

dc->dcn_soc->dcfclkv_max0p9 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1506

dc->dcn_soc->dcfclkv_nom0p8 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1507

dc->dcn_soc->dcfclkv_mid0p72 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1508

dc->dcn_soc->dcfclkv_min0p65 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1509

dc->dcn_soc->max_dispclk_vmax0p9 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1510

dc->dcn_soc->max_dispclk_vnom0p8 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1511

dc->dcn_soc->max_dispclk_vmid0p72 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1512

dc->dcn_soc->max_dispclk_vmin0p65 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1513

dc->dcn_soc->max_dppclk_vmax0p9 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1514

dc->dcn_soc->max_dppclk_vnom0p8 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1515

dc->dcn_soc->max_dppclk_vmid0p72 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1516

dc->dcn_soc->max_dppclk_vmin0p65 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1517

dc->dcn_soc->socclk * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1518

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1519

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1520

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1521

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1522

dc->dcn_soc->phyclkv_max0p9 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1523

dc->dcn_soc->phyclkv_nom0p8 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1524

dc->dcn_soc->phyclkv_mid0p72 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1525

dc->dcn_soc->phyclkv_min0p65 * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1526

dc->dcn_soc->downspreading * 100,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1527

dc->dcn_soc->round_trip_ping_latency_cycles,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1528

dc->dcn_soc->urgent_out_of_order_return_per_channel,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1529

dc->dcn_soc->number_of_channels,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1530

dc->dcn_soc->vmm_page_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1531

dc->dcn_soc->dram_clock_change_latency * 1000,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1532

dc->dcn_soc->return_bus_width);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1567

dc->dcn_ip->rob_buffer_size_in_kbyte,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1568

dc->dcn_ip->det_buffer_size_in_kbyte,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1569

dc->dcn_ip->dpp_output_buffer_pixels,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1570

dc->dcn_ip->opp_output_buffer_lines,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1571

dc->dcn_ip->pixel_chunk_size_in_kbyte,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1572

dc->dcn_ip->pte_enable,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1573

dc->dcn_ip->pte_chunk_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1574

dc->dcn_ip->meta_chunk_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1575

dc->dcn_ip->writeback_chunk_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1576

dc->dcn_ip->odm_capability,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1577

dc->dcn_ip->dsc_capability,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1578

dc->dcn_ip->line_buffer_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1579

dc->dcn_ip->max_line_buffer_lines,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1580

dc->dcn_ip->is_line_buffer_bpp_fixed,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1581

dc->dcn_ip->line_buffer_fixed_bpp,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1582

dc->dcn_ip->writeback_luma_buffer_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1583

dc->dcn_ip->writeback_chroma_buffer_size,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1584

dc->dcn_ip->max_num_dpp,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1585

dc->dcn_ip->max_num_writeback,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1586

dc->dcn_ip->max_dchub_topscl_throughput,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1587

dc->dcn_ip->max_pscl_tolb_throughput,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1588

dc->dcn_ip->max_lb_tovscl_throughput,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1589

dc->dcn_ip->max_vscl_tohscl_throughput,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1590

dc->dcn_ip->max_hscl_ratio,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1591

dc->dcn_ip->max_vscl_ratio,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1592

dc->dcn_ip->max_hscl_taps,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1593

dc->dcn_ip->max_vscl_taps,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1594

dc->dcn_ip->pte_buffer_size_in_requests,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1595

dc->dcn_ip->dispclk_ramping_margin,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1596

dc->dcn_ip->under_scan_factor * 100,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1597

dc->dcn_ip->max_inter_dcn_tile_repeaters,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1598

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1599

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1600

dc->dcn_ip->dcfclk_cstate_latency);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1602

dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1603

dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1604

dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1605

dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1606

dc->dml.soc.ideal_dram_bw_after_urgent_percent =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1607

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1608

dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1609

dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1610

dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1611

dc->dcn_soc->round_trip_ping_latency_cycles;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1612

dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1613

dc->dcn_soc->urgent_out_of_order_return_per_channel;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1614

dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1615

dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1616

dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1617

dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1619

dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1620

dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1621

dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1622

dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1623

dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1624

dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1625

dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1626

dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1627

dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1628

dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1629

dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1630

dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1631

dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1632

dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1633

dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1634

dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1635

dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1636

dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1637

dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1638

dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1639

dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1640

dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1641

dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1642

dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1643

dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1645

dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1646

dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1647

dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1648

dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1649

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1650

dc->dml.ip.bug_forcing_LC_req_same_size_fixed =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1651

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1652

dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

260

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

275

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

39

dc->ctx->logger

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

435

const struct dc *dc,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

440

struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

476

input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

485

dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

618

static bool dcn_bw_apply_registry_override(struct dc *dc)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

623

if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

624

&& dc->debug.sr_exit_time_ns) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

626

dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

629

if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

630

!= dc->debug.sr_enter_plus_exit_time_ns

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

631

&& dc->debug.sr_enter_plus_exit_time_ns) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

633

dc->dcn_soc->sr_enter_plus_exit_time =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

634

dc->debug.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

637

if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

638

&& dc->debug.urgent_latency_ns) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

640

dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

643

if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

644

!= dc->debug.percent_of_ideal_drambw

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

645

&& dc->debug.percent_of_ideal_drambw) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

647

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

648

dc->debug.percent_of_ideal_drambw;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

651

if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

652

!= dc->debug.dram_clock_change_latency_ns

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

653

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

655

dc->dcn_soc->dram_clock_change_latency =

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

656

dc->debug.dram_clock_change_latency_ns / 1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

702

struct dc *dc,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

705

const struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

713

if (dcn_bw_apply_registry_override(dc))

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

714

dcn_bw_sync_calcs_and_dml(dc);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

718

v->sr_exit_time = dc->dcn_soc->sr_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

719

v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

720

v->urgent_latency = dc->dcn_soc->urgent_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

721

v->write_back_latency = dc->dcn_soc->write_back_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

723

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

725

v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

726

v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

727

v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

728

v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

730

v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

731

v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

732

v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

733

v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

735

v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

736

v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

737

v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

738

v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

740

v->socclk = dc->dcn_soc->socclk;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

742

v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

743

v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

744

v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

745

v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

747

v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

748

v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

749

v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

750

v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

752

v->downspreading = dc->dcn_soc->downspreading;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

753

v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

754

v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

755

v->number_of_channels = dc->dcn_soc->number_of_channels;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

756

v->vmm_page_size = dc->dcn_soc->vmm_page_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

757

v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

758

v->return_bus_width = dc->dcn_soc->return_bus_width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

760

v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

761

v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

762

v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

763

v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

764

v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

765

v->pte_enable = dc->dcn_ip->pte_enable;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

766

v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

767

v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

768

v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

769

v->odm_capability = dc->dcn_ip->odm_capability;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

770

v->dsc_capability = dc->dcn_ip->dsc_capability;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

771

v->line_buffer_size = dc->dcn_ip->line_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

772

v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

773

v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

774

v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

775

v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

776

v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

777

v->max_num_dpp = dc->dcn_ip->max_num_dpp;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

778

v->max_num_writeback = dc->dcn_ip->max_num_writeback;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

779

v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

780

v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

781

v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

782

v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

783

v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

784

v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

785

v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

786

v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

787

v->under_scan_factor = dc->dcn_ip->under_scan_factor;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

788

v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

789

v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

790

v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

792

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

794

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

920

if (dc->debug.optimized_watermark) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

935

v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

989

hack_bounding_box(v, &dc->debug, context);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

996

&& dc->debug.force_single_disp_pipe_split) {

sys/dev/drm/amd/display/dc/core/dc.c

1007

dc->hwss.setup_stereo)

sys/dev/drm/amd/display/dc/core/dc.c

1008

dc->hwss.setup_stereo(pipe, dc);

sys/dev/drm/amd/display/dc/core/dc.c

1020

dc_enable_stereo(dc, context, dc_streams, context->stream_count);

sys/dev/drm/amd/display/dc/core/dc.c

1023

dc->hwss.set_bandwidth(dc, context, true);

sys/dev/drm/amd/display/dc/core/dc.c

1026

dc_release_state(dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1028

dc->current_state = context;

sys/dev/drm/amd/display/dc/core/dc.c

1030

dc_retain_state(dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1032

dc->hwss.optimize_shared_resources(dc);

sys/dev/drm/amd/display/dc/core/dc.c

1037

bool dc_commit_state(struct dc *dc, struct dc_state *context)

sys/dev/drm/amd/display/dc/core/dc.c

1042

if (false == context_changed(dc, context))

sys/dev/drm/amd/display/dc/core/dc.c

1051

dc_stream_log(dc, stream);

sys/dev/drm/amd/display/dc/core/dc.c

1054

result = dc_commit_state_no_check(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

1059

bool dc_post_update_surfaces_to_stream(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc.c

1062

struct dc_state *context = dc->current_state;

sys/dev/drm/amd/display/dc/core/dc.c

1064

post_surface_trace(dc);

sys/dev/drm/amd/display/dc/core/dc.c

1066

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/drm/amd/display/dc/core/dc.c

1070

dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/core/dc.c

1073

dc->optimized_required = false;

sys/dev/drm/amd/display/dc/core/dc.c

1075

dc->hwss.set_bandwidth(dc, context, true);

sys/dev/drm/amd/display/dc/core/dc.c

119

link_init_params.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc.c

122

link_init_params.link_index = dc->link_count;

sys/dev/drm/amd/display/dc/core/dc.c

123

link_init_params.dc = dc;

sys/dev/drm/amd/display/dc/core/dc.c

1240

static enum surface_update_type det_surface_update(const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1243

const struct dc_state *context = dc->current_state;

sys/dev/drm/amd/display/dc/core/dc.c

127

dc->links[dc->link_count] = link;

sys/dev/drm/amd/display/dc/core/dc.c

128

link->dc = dc;

sys/dev/drm/amd/display/dc/core/dc.c

129

++dc->link_count;

sys/dev/drm/amd/display/dc/core/dc.c

1298

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1332

det_surface_update(dc, &updates[i]);

sys/dev/drm/amd/display/dc/core/dc.c

1344

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1356

type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);

sys/dev/drm/amd/display/dc/core/dc.c

1382

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1386

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/core/dc.c

1410

static void commit_planes_do_stream_update(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1419

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

142

link->link_index = dc->link_count;

sys/dev/drm/amd/display/dc/core/dc.c

1429

dc->hwss.set_drr(&pipe_ctx, 1,

sys/dev/drm/amd/display/dc/core/dc.c

143

dc->links[dc->link_count] = link;

sys/dev/drm/amd/display/dc/core/dc.c

144

dc->link_count++;

sys/dev/drm/amd/display/dc/core/dc.c

1444

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1448

dc_stream_set_gamut_remap(dc, stream);

sys/dev/drm/amd/display/dc/core/dc.c

1451

dc_stream_program_csc_matrix(dc, stream);

sys/dev/drm/amd/display/dc/core/dc.c

146

link->ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc.c

1460

dc->hwss.pplib_apply_display_requirements(

sys/dev/drm/amd/display/dc/core/dc.c

1461

dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1462

notify_display_count_to_smu(dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1464

dc->hwss.pplib_apply_display_requirements(

sys/dev/drm/amd/display/dc/core/dc.c

1465

dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1466

notify_display_count_to_smu(dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1467

core_link_enable_stream(dc->current_state, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

147

link->dc = dc;

sys/dev/drm/amd/display/dc/core/dc.c

1487

static void commit_planes_for_stream(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1499

dc->hwss.set_bandwidth(dc, context, false);

sys/dev/drm/amd/display/dc/core/dc.c

1500

context_clock_trace(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

1505

commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);

sys/dev/drm/amd/display/dc/core/dc.c

1512

dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);

sys/dev/drm/amd/display/dc/core/dc.c

1517

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

1537

dc->hwss.apply_ctx_for_surface(

sys/dev/drm/amd/display/dc/core/dc.c

1538

dc, pipe_ctx->stream, stream_status->plane_count, context);

sys/dev/drm/amd/display/dc/core/dc.c

1543

context_timing_trace(dc, &context->res_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1551

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);

sys/dev/drm/amd/display/dc/core/dc.c

1557

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

1567

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/core/dc.c

1571

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

sys/dev/drm/amd/display/dc/core/dc.c

1575

void dc_commit_updates_for_stream(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1586

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc.c

1590

context = dc->current_state;

sys/dev/drm/amd/display/dc/core/dc.c

1593

dc, srf_updates, surface_count, stream_update, stream_status);

sys/dev/drm/amd/display/dc/core/dc.c

1596

update_surface_trace(dc, srf_updates, surface_count);

sys/dev/drm/amd/display/dc/core/dc.c

161

enc_init.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc.c

1625

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

1637

dc,

sys/dev/drm/amd/display/dc/core/dc.c

1645

if (dc->current_state != context) {

sys/dev/drm/amd/display/dc/core/dc.c

1647

struct dc_state *old = dc->current_state;

sys/dev/drm/amd/display/dc/core/dc.c

1649

dc->current_state = context;

sys/dev/drm/amd/display/dc/core/dc.c

1655

dc_post_update_surfaces_to_stream(dc);

sys/dev/drm/amd/display/dc/core/dc.c

1661

uint8_t dc_get_current_stream_count(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc.c

1663

return dc->current_state->stream_count;

sys/dev/drm/amd/display/dc/core/dc.c

1666

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)

sys/dev/drm/amd/display/dc/core/dc.c

1668

if (i < dc->current_state->stream_count)

sys/dev/drm/amd/display/dc/core/dc.c

1669

return dc->current_state->streams[i];

sys/dev/drm/amd/display/dc/core/dc.c

1674

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1678

return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);

sys/dev/drm/amd/display/dc/core/dc.c

1681

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)

sys/dev/drm/amd/display/dc/core/dc.c

1684

if (dc == NULL)

sys/dev/drm/amd/display/dc/core/dc.c

1687

return dal_irq_service_set(dc->res_pool->irqs, src, enable);

sys/dev/drm/amd/display/dc/core/dc.c

1690

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)

sys/dev/drm/amd/display/dc/core/dc.c

1692

dal_irq_service_ack(dc->res_pool->irqs, src);

sys/dev/drm/amd/display/dc/core/dc.c

1696

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1703

dc_resource_state_construct(dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1705

dc->hwss.init_hw(dc);

sys/dev/drm/amd/display/dc/core/dc.c

1708

ASSERT(dc->current_state->stream_count == 0);

sys/dev/drm/amd/display/dc/core/dc.c

1715

refcount = dc->current_state->refcount;

sys/dev/drm/amd/display/dc/core/dc.c

1716

dc_resource_state_destruct(dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

1717

memset(dc->current_state, 0,

sys/dev/drm/amd/display/dc/core/dc.c

1718

sizeof(*dc->current_state));

sys/dev/drm/amd/display/dc/core/dc.c

1720

dc->current_state->refcount = refcount;

sys/dev/drm/amd/display/dc/core/dc.c

1727

void dc_resume(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc.c

1732

for (i = 0; i < dc->link_count; i++)

sys/dev/drm/amd/display/dc/core/dc.c

1733

core_link_resume(dc->links[i]);

sys/dev/drm/amd/display/dc/core/dc.c

1737

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

1742

struct dc_link *link = dc->links[link_index];

sys/dev/drm/amd/display/dc/core/dc.c

1745

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc.c

194

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

202

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

206

dc->hwss.set_drr(&pipe,

sys/dev/drm/amd/display/dc/core/dc.c

217

bool dc_stream_get_crtc_position(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

229

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

232

dc->hwss.get_position(&pipe, 1, &position);

sys/dev/drm/amd/display/dc/core/dc.c

253

bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,

sys/dev/drm/amd/display/dc/core/dc.c

262

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

303

bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,

sys/dev/drm/amd/display/dc/core/dc.c

311

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

336

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

sys/dev/drm/amd/display/dc/core/dc.c

338

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

366

bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)

sys/dev/drm/amd/display/dc/core/dc.c

373

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

sys/dev/drm/amd/display/dc/core/dc.c

374

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

375

dc->hwss.program_gamut_remap(pipes);

sys/dev/drm/amd/display/dc/core/dc.c

383

bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)

sys/dev/drm/amd/display/dc/core/dc.c

390

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/drm/amd/display/dc/core/dc.c

393

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

394

dc->hwss.program_csc_matrix(pipes,

sys/dev/drm/amd/display/dc/core/dc.c

404

void dc_stream_set_static_screen_events(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

418

if (dc->current_state->res_ctx.pipe_ctx[j].stream

sys/dev/drm/amd/display/dc/core/dc.c

421

&dc->current_state->res_ctx.pipe_ctx[j];

sys/dev/drm/amd/display/dc/core/dc.c

426

dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);

sys/dev/drm/amd/display/dc/core/dc.c

429

void dc_link_set_drive_settings(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

436

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

437

if (dc->links[i] == link)

sys/dev/drm/amd/display/dc/core/dc.c

441

if (i >= dc->link_count)

sys/dev/drm/amd/display/dc/core/dc.c

444

dc_link_dp_set_drive_settings(dc->links[i], lt_settings);

sys/dev/drm/amd/display/dc/core/dc.c

447

void dc_link_perform_link_training(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

453

for (i = 0; i < dc->link_count; i++)

sys/dev/drm/amd/display/dc/core/dc.c

455

dc->links[i],

sys/dev/drm/amd/display/dc/core/dc.c

460

void dc_link_set_preferred_link_settings(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

470

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

482

link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/drm/amd/display/dc/core/dc.c

519

static void destruct(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc.c

521

dc_release_state(dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

522

dc->current_state = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

524

destroy_links(dc);

sys/dev/drm/amd/display/dc/core/dc.c

526

dc_destroy_resource_pool(dc);

sys/dev/drm/amd/display/dc/core/dc.c

528

if (dc->ctx->gpio_service)

sys/dev/drm/amd/display/dc/core/dc.c

529

dal_gpio_service_destroy(&dc->ctx->gpio_service);

sys/dev/drm/amd/display/dc/core/dc.c

531

if (dc->ctx->i2caux)

sys/dev/drm/amd/display/dc/core/dc.c

532

dal_i2caux_destroy(&dc->ctx->i2caux);

sys/dev/drm/amd/display/dc/core/dc.c

534

if (dc->ctx->created_bios)

sys/dev/drm/amd/display/dc/core/dc.c

535

dal_bios_parser_destroy(&dc->ctx->dc_bios);

sys/dev/drm/amd/display/dc/core/dc.c

537

kfree(dc->ctx);

sys/dev/drm/amd/display/dc/core/dc.c

538

dc->ctx = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

540

kfree(dc->bw_vbios);

sys/dev/drm/amd/display/dc/core/dc.c

541

dc->bw_vbios = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

543

kfree(dc->bw_dceip);

sys/dev/drm/amd/display/dc/core/dc.c

544

dc->bw_dceip = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

547

kfree(dc->dcn_soc);

sys/dev/drm/amd/display/dc/core/dc.c

548

dc->dcn_soc = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

550

kfree(dc->dcn_ip);

sys/dev/drm/amd/display/dc/core/dc.c

551

dc->dcn_ip = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

556

static bool construct(struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

575

dc->bw_dceip = dc_dceip;

sys/dev/drm/amd/display/dc/core/dc.c

583

dc->bw_vbios = dc_vbios;

sys/dev/drm/amd/display/dc/core/dc.c

591

dc->dcn_soc = dcn_soc;

sys/dev/drm/amd/display/dc/core/dc.c

599

dc->dcn_ip = dcn_ip;

sys/dev/drm/amd/display/dc/core/dc.c

61

dc->ctx->logger

sys/dev/drm/amd/display/dc/core/dc.c

610

dc_ctx->dc = dc;

sys/dev/drm/amd/display/dc/core/dc.c

613

dc->ctx = dc_ctx;

sys/dev/drm/amd/display/dc/core/dc.c

615

dc->current_state = dc_create_state();

sys/dev/drm/amd/display/dc/core/dc.c

617

if (!dc->current_state) {

sys/dev/drm/amd/display/dc/core/dc.c

671

dc->res_pool = dc_create_resource_pool(

sys/dev/drm/amd/display/dc/core/dc.c

672

dc,

sys/dev/drm/amd/display/dc/core/dc.c

676

if (!dc->res_pool)

sys/dev/drm/amd/display/dc/core/dc.c

679

dc_resource_state_construct(dc, dc->current_state);

sys/dev/drm/amd/display/dc/core/dc.c

681

if (!create_links(dc, init_params->num_virtual_links))

sys/dev/drm/amd/display/dc/core/dc.c

688

destruct(dc);

sys/dev/drm/amd/display/dc/core/dc.c

692

static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

sys/dev/drm/amd/display/dc/core/dc.c

701

dc_resource_state_copy_construct(dc->current_state, dangling_context);

sys/dev/drm/amd/display/dc/core/dc.c

703

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

705

dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/drm/amd/display/dc/core/dc.c

715

dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);

sys/dev/drm/amd/display/dc/core/dc.c

716

dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);

sys/dev/drm/amd/display/dc/core/dc.c

720

current_ctx = dc->current_state;

sys/dev/drm/amd/display/dc/core/dc.c

721

dc->current_state = dangling_context;

sys/dev/drm/amd/display/dc/core/dc.c

729

struct dc *dc_create(const struct dc_init_data *init_params)

sys/dev/drm/amd/display/dc/core/dc.c

731

struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);

sys/dev/drm/amd/display/dc/core/dc.c

734

if (NULL == dc)

sys/dev/drm/amd/display/dc/core/dc.c

737

if (false == construct(dc, init_params))

sys/dev/drm/amd/display/dc/core/dc.c

741

dc->hwss.init_hw(dc);

sys/dev/drm/amd/display/dc/core/dc.c

743

full_pipe_count = dc->res_pool->pipe_count;

sys/dev/drm/amd/display/dc/core/dc.c

744

if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)

sys/dev/drm/amd/display/dc/core/dc.c

746

dc->caps.max_streams = min(

sys/dev/drm/amd/display/dc/core/dc.c

748

dc->res_pool->stream_enc_count);

sys/dev/drm/amd/display/dc/core/dc.c

75

static void destroy_links(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc.c

750

dc->caps.max_links = dc->link_count;

sys/dev/drm/amd/display/dc/core/dc.c

751

dc->caps.max_audios = dc->res_pool->audio_count;

sys/dev/drm/amd/display/dc/core/dc.c

752

dc->caps.linear_pitch_alignment = 64;

sys/dev/drm/amd/display/dc/core/dc.c

755

dc->versions.dc_ver = DC_VER;

sys/dev/drm/amd/display/dc/core/dc.c

757

if (dc->res_pool->dmcu != NULL)

sys/dev/drm/amd/display/dc/core/dc.c

758

dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;

sys/dev/drm/amd/display/dc/core/dc.c

760

dc->config = init_params->flags;

sys/dev/drm/amd/display/dc/core/dc.c

762

dc->build_id = DC_BUILD_ID;

sys/dev/drm/amd/display/dc/core/dc.c

768

return dc;

sys/dev/drm/amd/display/dc/core/dc.c

771

kfree(dc);

sys/dev/drm/amd/display/dc/core/dc.c

777

void dc_destroy(struct dc **dc)

sys/dev/drm/amd/display/dc/core/dc.c

779

destruct(*dc);

sys/dev/drm/amd/display/dc/core/dc.c

780

kfree(*dc);

sys/dev/drm/amd/display/dc/core/dc.c

781

*dc = NULL;

sys/dev/drm/amd/display/dc/core/dc.c

785

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

789

int pipe_count = dc->res_pool->pipe_count;

sys/dev/drm/amd/display/dc/core/dc.c

79

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

80

if (NULL != dc->links[i])

sys/dev/drm/amd/display/dc/core/dc.c

803

dc->hwss.enable_per_frame_crtc_position_reset(

sys/dev/drm/amd/display/dc/core/dc.c

804

dc, multisync_count, multisync_pipes);

sys/dev/drm/amd/display/dc/core/dc.c

809

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

81

link_destroy(&dc->links[i]);

sys/dev/drm/amd/display/dc/core/dc.c

814

int pipe_count = dc->res_pool->pipe_count;

sys/dev/drm/amd/display/dc/core/dc.c

86

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

875

dc->hwss.enable_timing_synchronization(

sys/dev/drm/amd/display/dc/core/dc.c

876

dc, group_index, group_size, pipe_set);

sys/dev/drm/amd/display/dc/core/dc.c

883

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

888

if (context->stream_count != dc->current_state->stream_count)

sys/dev/drm/amd/display/dc/core/dc.c

891

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

892

if (dc->current_state->streams[i] != context->streams[i])

sys/dev/drm/amd/display/dc/core/dc.c

900

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc.c

91

struct dc_bios *bios = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/core/dc.c

913

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

916

dc->hwss.setup_stereo)

sys/dev/drm/amd/display/dc/core/dc.c

917

dc->hwss.setup_stereo(pipe, dc);

sys/dev/drm/amd/display/dc/core/dc.c

928

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

sys/dev/drm/amd/display/dc/core/dc.c

93

dc->link_count = 0;

sys/dev/drm/amd/display/dc/core/dc.c

930

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/core/dc.c

936

disable_dangling_plane(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

942

dc->hwss.enable_accelerated_mode(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

944

dc->hwss.set_bandwidth(dc, context, false);

sys/dev/drm/amd/display/dc/core/dc.c

956

dc->hwss.apply_ctx_for_surface(

sys/dev/drm/amd/display/dc/core/dc.c

957

dc, context->streams[i],

sys/dev/drm/amd/display/dc/core/dc.c

963

dc->hwss.ready_shared_resources(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

966

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

968

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);

sys/dev/drm/amd/display/dc/core/dc.c

971

result = dc->hwss.apply_ctx_to_hw(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

979

enable_timing_multisync(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

980

program_timing_sync(dc, context);

sys/dev/drm/amd/display/dc/core/dc.c

992

dc->hwss.apply_ctx_for_surface(

sys/dev/drm/amd/display/dc/core/dc.c

993

dc, context->streams[i],

sys/dev/drm/amd/display/dc/core/dc_debug.c

179

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_debug.c

184

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_debug.c

300

void post_surface_trace(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc_debug.c

302

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_debug.c

309

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_debug.c

313

struct dc *core_dc = dc;

sys/dev/drm/amd/display/dc/core/dc_debug.c

317

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_debug.c

348

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_debug.c

352

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_debug.c

44

if (dc->debug.surface_trace) \

sys/dev/drm/amd/display/dc/core/dc_debug.c

49

if (dc->debug.timing_trace) \

sys/dev/drm/amd/display/dc/core/dc_debug.c

54

if (dc->debug.clock_trace) \

sys/dev/drm/amd/display/dc/core/dc_debug.c

59

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_debug.c

64

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/core/dc_hw_sequencer.c

204

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_link.c

1081

struct dc_bios *bios = init_params->dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/core/dc_link.c

1090

link->dc = init_params->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

1103

if (link->dc->res_pool->funcs->link_init)

sys/dev/drm/amd/display/dc/core/dc_link.c

1104

link->dc->res_pool->funcs->link_init(link);

sys/dev/drm/amd/display/dc/core/dc_link.c

1184

link->link_enc = link->dc->res_pool->funcs->link_enc_create(

sys/dev/drm/amd/display/dc/core/dc_link.c

1441

link->dc->hwss.edp_power_control(link, true);

sys/dev/drm/amd/display/dc/core/dc_link.c

1442

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/drm/amd/display/dc/core/dc_link.c

1579

cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/drm/amd/display/dc/core/dc_link.c

212

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/drm/amd/display/dc/core/dc_link.c

2171

struct abm *abm = link->ctx->dc->res_pool->abm;

sys/dev/drm/amd/display/dc/core/dc_link.c

2182

struct dc *core_dc = link->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2234

struct dc *core_dc = link->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2247

struct dc *core_dc = link->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2536

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2632

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

2646

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_link.c

422

struct audio_support *aud_support = &link->dc->res_pool->audio_support;

sys/dev/drm/amd/display/dc/core/dc_link.c

616

struct audio_support *aud_support = &link->dc->res_pool->audio_support;

sys/dev/drm/amd/display/dc/core/dc_link_ddc.c

421

.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };

sys/dev/drm/amd/display/dc/core/dc_link_ddc.c

613

.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };

sys/dev/drm/amd/display/dc/core/dc_link_ddc.c

655

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1035

link->ctx->dc->debug_data.ltFailCount++;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1108

if (link->dc->debug.skip_detection_link_training) {

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1126

dp_cs = link->dc->res_pool->dp_clock_source;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1853

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1859

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2595

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2625

link->dc->hwss.unblank_stream(

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

154

link->dc->hwss.edp_power_control(link, false);

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

275

&link->dc->current_state->res_ctx.pipe_ctx[0];

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

296

link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

321

link->dc->hwss.enable_stream(&pipes[i]);

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

323

link->dc->hwss.unblank_stream(&pipes[i],

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

63

link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

65

link->dc->res_pool->dp_clock_source;

sys/dev/drm/amd/display/dc/core/dc_resource.c

105

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

115

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

119

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1196

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

123

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

127

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

131

num_virtual_links, dc, asic_id);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1351

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1357

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/core/dc_resource.c

136

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

140

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1425

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1432

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/core/dc_resource.c

149

num_virtual_links, dc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1501

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1526

if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))

sys/dev/drm/amd/display/dc/core/dc_resource.c

1533

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1551

if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))

sys/dev/drm/amd/display/dc/core/dc_resource.c

1558

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1573

return add_all_planes_for_stream(dc, stream, &set, 1, context);

sys/dev/drm/amd/display/dc/core/dc_resource.c

160

if (dc->ctx->dc_bios->funcs->get_firmware_info(

sys/dev/drm/amd/display/dc/core/dc_resource.c

161

dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

170

void dc_destroy_resource_pool(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc_resource.c

172

if (dc) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

173

if (dc->res_pool)

sys/dev/drm/amd/display/dc/core/dc_resource.c

174

dc->res_pool->funcs->destroy(&dc->res_pool);

sys/dev/drm/amd/display/dc/core/dc_resource.c

176

kfree(dc->hwseq);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1821

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1825

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1828

if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1837

res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1845

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1850

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1862

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1869

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1874

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1877

if (dc->res_pool->funcs->remove_stream_from_ctx)

sys/dev/drm/amd/display/dc/core/dc_resource.c

1878

dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1984

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1988

const struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1990

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2065

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2068

dc_resource_state_copy_construct(dc->current_state, dst_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2073

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2076

dst_ctx->dis_clk = dc->res_pool->dccg;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2080

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2089

if (dc->res_pool->funcs->validate_global) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

209

struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2090

result = dc->res_pool->funcs->validate_global(dc, new_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2098

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

2104

if (dc->res_pool->funcs->get_default_swizzle_mode &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

2107

result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2121

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2124

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2127

dc->res_pool,

sys/dev/drm/amd/display/dc/core/dc_resource.c

213

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2133

result = resource_build_scaling_params_for_context(dc, new_ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2136

if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))

sys/dev/drm/amd/display/dc/core/dc_resource.c

220

create_funcs->read_dce_straps(dc->ctx, &straps);

sys/dev/drm/amd/display/dc/core/dc_resource.c

259

dc->caps.dynamic_audio = false;

sys/dev/drm/amd/display/dc/core/dc_resource.c

261

dc->caps.dynamic_audio = true;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2655

const struct dc *dc,

sys/dev/drm/amd/display/dc/core/dc_resource.c

2660

const struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2673

if (!dc->config.disable_disp_pll_sharing)

sys/dev/drm/amd/display/dc/core/dc_resource.c

274

dc->hwseq = create_funcs->create_hwseq(ctx);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2864

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2866

struct dc *core_dc = dc;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2891

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2896

if (dc->res_pool->funcs->validate_plane)

sys/dev/drm/amd/display/dc/core/dc_resource.c

2897

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

sys/dev/drm/amd/display/dc/core/dc_resource.c

375

if (stream1->ctx->dc->caps.disable_dp_clk_share)

sys/dev/drm/amd/display/dc/core/dc_stream.c

163

struct dc *dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

165

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/drm/amd/display/dc/core/dc_stream.c

166

if (stream == dc->current_state->streams[i])

sys/dev/drm/amd/display/dc/core/dc_stream.c

167

return &dc->current_state->stream_status[i];

sys/dev/drm/amd/display/dc/core/dc_stream.c

181

struct dc *core_dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

199

core_dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

230

struct dc *core_dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

244

core_dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

275

struct dc *core_dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

299

struct dc *core_dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_stream.c

322

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)

sys/dev/drm/amd/display/dc/core/dc_stream.c

33

#define DC_LOGGER dc->ctx->logger

sys/dev/drm/amd/display/dc/core/dc_stream.c

49

if (stream->ctx->dc->caps.dual_link_dvi &&

sys/dev/drm/amd/display/dc/core/dc_surface.c

102

struct dc *core_dc;

sys/dev/drm/amd/display/dc/core/dc_surface.c

107

!plane_state->ctx->dc) {

sys/dev/drm/amd/display/dc/core/dc_surface.c

113

core_dc = plane_state->ctx->dc;

sys/dev/drm/amd/display/dc/core/dc_surface.c

71

struct dc_plane_state *dc_create_plane_state(struct dc *dc)

sys/dev/drm/amd/display/dc/core/dc_surface.c

73

struct dc *core_dc = dc;

sys/dev/drm/amd/display/dc/dc.h

154

struct dc;

sys/dev/drm/amd/display/dc/dc.h

160

bool (*get_dcc_compression_cap)(const struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

355

struct dc *dc_create(const struct dc_init_data *init_params);

sys/dev/drm/amd/display/dc/dc.h

357

void dc_destroy(struct dc **dc);

sys/dev/drm/amd/display/dc/dc.h

562

struct dc_plane_state *dc_create_plane_state(struct dc *dc);

sys/dev/drm/amd/display/dc/dc.h

590

struct dc *dc);

sys/dev/drm/amd/display/dc/dc.h

603

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

sys/dev/drm/amd/display/dc/dc.h

608

struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

613

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

621

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

635

bool dc_commit_state(struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/dc.h

742

struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

745

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);

sys/dev/drm/amd/display/dc/dc.h

746

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);

sys/dev/drm/amd/display/dc/dc.h

748

struct dc *dc, uint32_t link_index);

sys/dev/drm/amd/display/dc/dc.h

755

struct dc *dc,

sys/dev/drm/amd/display/dc/dc.h

757

void dc_resume(struct dc *dc);

sys/dev/drm/amd/display/dc/dc_link.h

104

const struct dc *dc;

sys/dev/drm/amd/display/dc/dc_link.h

136

static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)

sys/dev/drm/amd/display/dc/dc_link.h

138

return dc->links[link_index];

sys/dev/drm/amd/display/dc/dc_link.h

224

void dc_link_set_drive_settings(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_link.h

227

void dc_link_perform_link_training(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_link.h

230

void dc_link_set_preferred_link_settings(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_link.h

242

struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

160

void dc_commit_updates_for_stream(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

170

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);

sys/dev/drm/amd/display/dc/dc_stream.h

172

uint8_t dc_get_current_stream_count(struct dc *dc);

sys/dev/drm/amd/display/dc/dc_stream.h

173

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);

sys/dev/drm/amd/display/dc/dc_stream.h

191

struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

196

struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

202

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

208

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

214

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

219

const struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

225

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);

sys/dev/drm/amd/display/dc/dc_stream.h

240

struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

247

struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

279

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

283

bool dc_stream_get_crtc_position(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

289

bool dc_stream_configure_crc(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

294

bool dc_stream_get_crc(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

300

void dc_stream_set_static_screen_events(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

308

bool dc_stream_set_gamut_remap(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

311

bool dc_stream_program_csc_matrix(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_stream.h

315

bool dc_stream_get_crtc_position(struct dc *dc,

sys/dev/drm/amd/display/dc/dc_types.h

77

struct dc *dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

283

struct dc *core_dc = ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

300

struct dc *core_dc = clk->ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

348

struct dc_debug_options *debug = &clk_dce->base.ctx->dc->debug;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

541

struct dc *dc = dccg->ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

550

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

551

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

575

struct dc *dc = dccg->ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

577

&dc->res_pool->pp_smu_req;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

579

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

632

clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

651

clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

689

struct dc *dc,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

715

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

902

struct dc_debug_options *debug = &ctx->dc->debug;

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

47

void dce_pipe_control_lock(struct dc *dc,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

53

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

530

void dce_pipe_control_lock(struct dc *dc,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

263

if (ctx->dc->caps.psp_setup_panel_mode)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

655

if (enc110->base.ctx->dc->debug.hdmi20_disable &&

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

774

if (enc110->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

272

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

297

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

330

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/drm/amd/display/dc/dce/dce_transform.c

158

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

109

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

121

if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

123

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

125

dc->prev_display_config = *pp_display_cfg;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

132

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

156

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

163

req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

165

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

167

dc->res_pool->dccg->funcs->update_clocks(

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

168

dc->res_pool->dccg,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

172

dce100_pplib_apply_display_requirements(dc, context);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

178

void dce100_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

180

dce110_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

182

dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

183

dc->hwss.set_bandwidth = dce100_set_bandwidth;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

184

dc->hwss.pplib_apply_display_requirements =

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

73

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

80

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

34

void dce100_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

37

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

41

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

1040

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

1042

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

1047

dce100_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

1058

struct dc *dc)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

1066

if (construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

748

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

766

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

772

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

811

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

821

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

827

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

830

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

833

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

867

struct dc *dc,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

871

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

960

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

972

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

973

dc->caps.i2c_speed_in_khz = 40;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

974

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

975

dc->caps.dual_link_dvi = true;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

976

dc->caps.disable_dp_clk_share = true;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.h

34

struct dc;

sys/dev/drm/amd/display/dc/dce100/dce100_resource.h

40

struct dc *dc);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.h

45

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1018

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1023

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1026

!dc->debug.az_endpoint_mute_only) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1038

if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1041

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1060

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1070

dc->hwss.disable_audio_stream(pipe_ctx, option);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1095

link->dc->hwss.edp_backlight_control(link, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1105

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1256

static void program_scaler(const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1267

if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1270

color_space_to_black_color(dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1300

struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1303

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1312

color_space_to_black_color(dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1366

struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1395

dc->hwss.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1428

static void power_down_encoders(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1437

for (i = 0; i < dc->res_pool->stream_enc_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1438

dc->res_pool->stream_enc[i]->funcs->dp_blank(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1439

dc->res_pool->stream_enc[i]);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1442

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1443

connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1447

if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1448

dp_receiver_power_ctrl(dc->links[i], false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1453

dc->links[i]->link_enc->funcs->disable_output(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1454

dc->links[i]->link_enc, signal);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1458

static void power_down_controllers(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1462

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1463

dc->res_pool->timing_generators[i]->funcs->disable_crtc(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1464

dc->res_pool->timing_generators[i]);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1468

static void power_down_clock_sources(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1472

if (dc->res_pool->dp_clock_source->funcs->cs_power_down(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1473

dc->res_pool->dp_clock_source) == false)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1476

for (i = 0; i < dc->res_pool->clk_src_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1477

if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1478

dc->res_pool->clock_sources[i]) == false)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1483

static void power_down_all_hw_blocks(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1485

power_down_encoders(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1487

power_down_controllers(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1489

power_down_clock_sources(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1491

if (dc->fbc_compressor)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1492

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1496

struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1500

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1502

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1503

tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1508

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1514

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1515

dc->hwss.disable_plane(dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1516

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1520

static struct dc_link *get_link_for_edp(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1524

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1525

if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1526

return dc->links[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1532

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1545

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1546

if (dc->links[i]->local_sink &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1547

dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1548

link = dc->links[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1563

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1567

struct dc_link *edp_link = get_link_for_edp(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1573

if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1574

(dc->ctx->dce_version == DCE_VERSION_8_1) ||

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1575

(dc->ctx->dce_version == DCE_VERSION_8_3))

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1583

edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1601

dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1604

power_down_all_hw_blocks(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1605

disable_vga_and_power_gate_all_controllers(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1607

dc->hwss.edp_power_control(edp_link_to_turnoff, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1609

bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1630

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1634

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1644

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1758

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1760

if (dc->fbc_compressor)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1773

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1800

static bool should_enable_fbc(struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1809

ASSERT(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1812

if (!dc->ctx->fbc_gpu_addr)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1819

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1852

static void enable_fbc(struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1857

if (should_enable_fbc(dc, context, &pipe_idx)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1860

struct compressor *compr = dc->fbc_compressor;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1867

compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1877

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1886

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

189

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1915

pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1918

dc->res_pool,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1922

dc->hwss.disable_plane(dc, pipe_ctx_old);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1930

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1954

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

196

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

197

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1981

if (i == dc->res_pool->pipe_count) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1982

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2011

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2014

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2020

dc->hwss.reset_hw_ctx_wrap(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2031

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2033

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2041

dce_crtc_switch_to_clk_src(dc->hwseq,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2046

dc->hwss.enable_display_power_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2047

dc, i, dc->ctx->dc_bios,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2051

if (dc->fbc_compressor)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2052

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2054

dce110_setup_audio_dto(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2056

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2058

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2076

dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2086

if (dc->fbc_compressor)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2087

enable_fbc(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2136

static void program_surface_visibility(const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2159

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2182

static void update_plane_addr(const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2220

void dce110_power_down(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2222

power_down_all_hw_blocks(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2223

disable_vga_and_power_gate_all_controllers(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2265

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2270

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2311

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2315

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2343

static void init_hw(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2350

bp = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2351

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2352

xfm = dc->res_pool->transforms[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2355

dc->hwss.enable_display_power_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2356

dc, i, bp,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2358

dc->hwss.enable_display_power_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2359

dc, i, bp,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2361

dc->hwss.enable_display_pipe_clock_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2362

dc->ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2366

dce_clock_gating_power_up(dc->hwseq, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2369

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2374

struct dc_link *link = dc->links[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2377

dc->hwss.edp_power_control(link, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2382

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2383

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2393

for (i = 0; i < dc->res_pool->audio_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2394

struct audio *audio = dc->res_pool->audios[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2398

abm = dc->res_pool->abm;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2404

if (dc->fbc_compressor)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2405

dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2487

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2496

if (dc->sclk_lvls.num_levels == 0)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2499

for (i = 0; i < dc->sclk_lvls.num_levels; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2500

if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2501

return dc->sclk_lvls.clocks_in_khz[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2509

return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2513

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2533

dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2546

pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2561

if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2563

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2565

dc->prev_display_config = *pp_display_cfg;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2569

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2574

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2577

req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2580

dce110_set_displaymarks(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2582

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2587

dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2595

pplib_apply_display_requirements(dc, context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2599

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2606

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2611

if (dc->current_state)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2612

old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2617

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2645

program_scaler(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2648

if (dc->fbc_compressor && old_pipe->stream &&

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2651

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2653

enable_fbc(dc, dc->current_state);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2667

if (dc->config.gpu_vm_support)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2678

dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2681

dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2722

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2732

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2734

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2739

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2743

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2757

dce110_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2759

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2761

program_surface_visibility(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2765

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2767

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2772

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2776

static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2782

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2785

dc->hwss.enable_display_power_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2786

dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2788

dc->res_pool->transforms[fe_idx]->funcs->transform_reset(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2789

dc->res_pool->transforms[fe_idx]);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2793

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2830

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2872

static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2874

static void optimize_shared_resources(struct dc *dc) {}

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2920

void dce110_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2922

dc->hwss = dce110_funcs;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

854

struct dce_hwseq *hwseq = ctx->dc->hwseq;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

936

struct dce_hwseq *hws = ctx->dc->hwseq;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

992

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

32

struct dc;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

36

void dce110_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

39

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

59

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

61

void dce110_power_down(struct dc *dc);

sys/dev/drm/amd/display/dc/dce110/dce110_mem_input_v.c

763

if (ctx->dc->debug.disable_stutter) {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1004

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1007

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1011

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1021

struct dc *dc = stream->ctx->dc;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1038

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1040

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1042

dc->hwss.enable_display_power_gating(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1043

dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1067

color_space_to_black_color(dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1129

ctx->dc->caps.max_slave_planes = 1;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1130

ctx->dc->caps.max_slave_planes = 1;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1135

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1141

dc->ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1145

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1147

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1149

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1151

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1153

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1155

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1157

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1159

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1161

dc->sclk_lvls = clks;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1165

dc->ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1168

dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1170

dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1172

dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1177

dc->ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1181

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1183

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1186

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1203

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1208

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1225

dc->caps.max_downscale_ratio = 150;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1226

dc->caps.i2c_speed_in_khz = 100;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1227

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1228

dc->caps.is_apu = true;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1306

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1372

if (dc->config.fbc_support)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1373

dc->fbc_compressor = dce110_compressor_create(ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1378

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1383

dce110_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1385

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1387

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1389

bw_calcs_data_update_from_pplib(dc);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1400

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1409

if (construct(num_virtual_links, dc, pool, asic_id))

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

58

dc->ctx->logger

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

835

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

845

dc->res_pool->underlay_pipe_index))

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

858

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

868

dc->ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

869

dc->bw_dceip,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

870

dc->bw_vbios,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

872

dc->res_pool->pipe_count,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

883

if (memcmp(&dc->current_state->bw.dce,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

988

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

998

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.h

45

struct dc *dc,

sys/dev/drm/amd/display/dc/dce110/dce110_transform_v.c

238

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

114

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

121

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

155

void dce112_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

160

dce110_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

161

dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.h

33

void dce112_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1000

dc->ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1004

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1006

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1008

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1010

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1012

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1014

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1016

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1018

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1023

dc->ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1027

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1029

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1032

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1040

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1042

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1044

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1046

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1048

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1050

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1052

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1054

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1059

dc->ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1068

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1070

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1073

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1124

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1140

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1144

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1158

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1159

dc->caps.i2c_speed_in_khz = 100;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1160

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1161

dc->caps.dual_link_dvi = true;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1252

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1323

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1327

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1330

dce112_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1332

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1334

bw_calcs_data_update_from_pplib(dc);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1345

struct dc *dc)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1353

if (construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

65

dc->ctx->logger

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

795

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

812

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

822

dc->ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

823

dc->bw_dceip,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

824

dc->bw_vbios,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

826

dc->res_pool->pipe_count,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

835

if (memcmp(&dc->current_state->bw.dce,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

883

const struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

898

dc->res_pool->dp_clock_source;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

901

&context->res_ctx, dc->res_pool,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

909

dc->res_pool,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

936

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

942

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

945

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

949

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

956

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

983

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

994

dc->ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.h

36

struct dc *dc);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.h

39

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.h

46

struct dc *dc,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.h

50

struct dc *dc,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

153

struct dc *dc,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

162

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

249

void dce120_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

254

dce110_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

255

dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

256

dc->hwss.update_dchub = dce120_update_dchub;

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.h

33

void dce120_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1010

irq_init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1100

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1105

if (!dce120_hw_sequencer_create(dc))

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1108

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1110

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1112

bw_calcs_data_update_from_pplib(dc);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1129

struct dc *dc)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

1137

if (construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

482

bool dce120_hw_sequencer_create(struct dc *dc)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

487

dce120_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

776

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

787

dc->ctx,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

801

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

803

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

805

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

807

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

809

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

811

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

813

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

815

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

820

dc->ctx,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

842

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

844

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

847

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

898

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

911

struct dc *dc,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

916

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

931

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

932

dc->caps.i2c_speed_in_khz = 100;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

933

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

934

dc->caps.dual_link_dvi = true;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

935

dc->caps.psp_setup_panel_mode = true;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

937

dc->debug = debug_defaults;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce120/dce120_resource.h

36

struct dc *dc);

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

75

void dce80_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

77

dce110_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

79

dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

80

dc->hwss.pipe_control_lock = dce_pipe_control_lock;

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

81

dc->hwss.set_bandwidth = dce100_set_bandwidth;

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.h

33

void dce80_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1035

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1036

dc->caps.disable_dp_clk_share = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1038

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1043

dce80_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1054

struct dc *dc)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1062

if (dce80_construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1071

struct dc *dc,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1075

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1092

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1093

dc->caps.i2c_speed_in_khz = 40;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1094

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1095

dc->caps.is_apu = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1177

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1245

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1246

dc->caps.disable_dp_clk_share = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1248

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1253

dce80_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1264

struct dc *dc)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1272

if (dce81_construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1281

struct dc *dc,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1285

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1302

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1303

dc->caps.i2c_speed_in_khz = 40;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1304

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1305

dc->caps.is_apu = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1383

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1451

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1452

dc->caps.disable_dp_clk_share = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1454

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1459

dce80_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1470

struct dc *dc)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1478

if (dce83_construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

800

struct dc *dc,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

832

struct dc *dc,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

861

struct dc *dc,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

865

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

882

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

883

dc->caps.i2c_speed_in_khz = 40;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

884

dc->caps.max_cursor_size = 128;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

885

dc->caps.dual_link_dvi = true;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

967

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.h

31

struct dc;

sys/dev/drm/amd/display/dc/dce80/dce80_resource.h

36

struct dc *dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.h

40

struct dc *dc);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.h

44

struct dc *dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

161

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

162

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

198

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

473

if (dpp->base.ctx->dc->debug.use_max_lb)

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

518

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

629

if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

654

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

257

uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

755

struct dc *dc = hubbub->ctx->dc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

764

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

807

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h

166

struct dc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1004

hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1006

bios_golden_init(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1015

hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1016

hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1018

disable_vga(dc->hwseq);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1021

for (i = 0; i < dc->link_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1026

struct dc_link *link = dc->links[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1029

dc->hwss.edp_power_control(link, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1035

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1036

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1045

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1046

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1055

dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1057

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1058

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1060

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1061

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1073

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1074

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1075

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1076

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1078

hwss1_plane_atomic_disconnect(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1081

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1082

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1088

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1089

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1092

dcn10_disable_plane(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1101

if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1104

for (i = 0; i < dc->res_pool->audio_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1105

struct audio *audio = dc->res_pool->audios[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1121

if (!dc->debug.disable_clock_gate) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1130

enable_power_gating_plane(dc->hwseq, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1132

memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1136

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1142

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1144

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1157

reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1193

static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

120

static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

122

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

123

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1232

!dpp_base->ctx->dc->debug.always_use_regamma

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1304

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1314

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1315

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1322

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1323

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1364

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1369

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1394

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1398

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1624

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1628

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1630

if (dc->debug.sanity_checks) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1631

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1634

undo_DEGVIDCN10_253_wa(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1636

power_on_plane(dc->hwseq,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1684

if (dc->config.gpu_vm_support)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1687

if (dc->debug.sanity_checks) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1688

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1724

static void dcn10_program_output_csc(struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1941

static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1948

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1955

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1958

} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1963

dc, pipe_ctx->stream->output_color_space,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2010

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2012

dc->res_pool->mpc, mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2015

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2044

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2060

dc->res_pool->dccg->clks.dispclk_khz / 2;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2067

dc->res_pool->dccg->clks.dppclk_khz = should_divided_by_2 ?

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2068

dc->res_pool->dccg->clks.dispclk_khz / 2 :

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2069

dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2096

dc->hwss.update_mpcc(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2116

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2117

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2124

dc->hwss.program_output_csc(dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2152

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2159

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2170

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2218

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2223

dcn10_enable_plane(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2225

update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2232

dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2241

dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2245

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2261

dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2266

dcn10_program_pipe(dc, pipe_ctx, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2270

program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2275

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2280

pp_display_cfg->min_engine_clock_khz = dc->res_pool->dccg->clks.dcfclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2281

pp_display_cfg->min_memory_clock_khz = dc->res_pool->dccg->clks.fclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2282

pp_display_cfg->min_engine_clock_deep_sleep_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2283

pp_display_cfg->min_dcfc_deep_sleep_clock_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2284

pp_display_cfg->min_dcfclock_khz = dc->res_pool->dccg->clks.dcfclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2285

pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2288

if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2290

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2292

dc->prev_display_config = *pp_display_cfg;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2295

static void optimize_shared_resources(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2297

if (dc->current_state->stream_count == 0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2299

dcn10_pplib_apply_display_requirements(dc, dc->current_state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2302

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2303

dcn_bw_notify_pplib_of_wm_ranges(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2306

static void ready_shared_resources(struct dc *dc, struct dc_state *context)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2309

if (dc->current_state->stream_count == 0 &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2311

dcn10_pplib_apply_display_requirements(dc, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2315

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2321

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2324

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2339

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2348

find_top_pipe_for_stream(dc, context, stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2349

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2356

dcn10_pipe_control_lock(dc, top_pipe_to_program, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

236

void dcn10_log_hw_state(struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2360

dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2364

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2367

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2378

dcn10_disable_plane(dc, old_pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

239

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2391

dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

240

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2400

program_all_pipe_in_tree(dc, top_pipe_to_program, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2402

dcn10_pipe_control_lock(dc, top_pipe_to_program, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2405

false_optc_underflow_wa(dc, stream, tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2407

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2409

dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2411

if (dc->hwseq->wa.DEGVIDCN10_254)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2412

hubbub1_wm_change_req_wa(dc->res_pool->hubbub);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2416

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2420

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2421

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2423

if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2427

dc->res_pool->dccg->funcs->update_clocks(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2428

dc->res_pool->dccg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2432

dcn10_pplib_apply_display_requirements(dc, context);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2435

hubbub1_program_watermarks(dc->res_pool->hubbub,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2437

dc->res_pool->ref_clock_inKhz / 1000,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2440

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2441

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

245

dcn10_log_hubbub_state(dc, log_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

247

dcn10_log_hubp_states(dc, log_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2536

static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2569

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2575

if (dc->debug.sanity_checks) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2576

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2595

if (dc->debug.sanity_checks) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2596

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2602

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2636

if (hws->ctx->dc->res_pool->hubbub != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2637

struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2642

hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2653

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2762

void dcn10_hw_sequencer_construct(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2764

dc->hwss = dcn10_funcs;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

350

dc->current_state->bw.dcn.clk.dcfclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

351

dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

352

dc->current_state->bw.dcn.clk.dispclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

353

dc->current_state->bw.dcn.clk.dppclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

354

dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

355

dc->current_state->bw.dcn.clk.fclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

356

dc->current_state->bw.dcn.clk.socclk_khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

358

log_mpc_crc(dc, log_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

426

if (hws->ctx->dc->debug.disable_dpp_power_gate)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

478

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

539

static void undo_DEGVIDCN10_253_wa(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

541

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

542

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

559

static void apply_DEGVIDCN10_253_wa(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

561

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

562

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

565

if (dc->debug.disable_stutter)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

571

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

572

if (!dc->res_pool->hubps[i]->power_gated)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

589

static void bios_golden_init(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

591

struct dc_bios *bp = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

598

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

606

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

613

if (!dc->hwseq->wa.false_optc_underflow)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

618

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

619

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

624

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

636

struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

69

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

690

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

701

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

735

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

740

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

746

if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

751

dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

766

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

767

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

770

if (i == dc->res_pool->pipe_count)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

778

static bool dcn10_hw_wa_force_recovery(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

78

static void log_mpc_crc(struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

784

if (!dc->debug.recovery_enabled)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

787

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

789

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

81

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

812

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

814

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

82

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

823

hubbub1_soft_reset(dc->res_pool->hubbub, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

825

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

827

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

835

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

837

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

846

hubbub1_soft_reset(dc->res_pool->hubbub, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

847

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

849

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

862

void dcn10_verify_allow_pstate_change_high(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

866

if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

868

dcn10_log_hw_state(dc, NULL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

871

if (dcn10_hw_wa_force_recovery(dc)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

873

if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

880

void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

884

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

900

dc->optimized_required = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

905

if (dc->debug.sanity_checks)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

906

dcn10_verify_allow_pstate_change_high(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

909

static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

911

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

913

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

93

void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

931

static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

937

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

949

dc->optimized_required = false; /* We're powering off, no need to optimize */

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

95

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

951

plane_atomic_power_down(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

961

static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

963

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

968

plane_atomic_disable(dc, pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

970

apply_DEGVIDCN10_253_wa(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

976

static void dcn10_init_hw(struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

979

struct abm *abm = dc->res_pool->abm;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

980

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

981

struct dce_hwseq *hws = dc->hwseq;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

982

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

983

struct dc_state *context = dc->current_state;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

985

if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

99

hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

990

if (!dc->debug.disable_clock_gate) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

999

enable_power_gating_plane(dc->hwseq, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

31

struct dc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

33

void dcn10_hw_sequencer_construct(struct dc *dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

40

void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

42

void dcn10_verify_allow_pstate_change_high(struct dc *dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

45

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

50

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

108

static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned int bufSize, bool invarOnly)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

110

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

111

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

117

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

187

static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

189

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

229

static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

231

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

286

static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

288

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

326

static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

328

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

381

static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

383

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

412

static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

414

struct resource_pool *pool = dc->res_pool;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

469

static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

476

dc->current_state->bw.dcn.clk.dcfclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

477

dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

478

dc->current_state->bw.dcn.clk.dispclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

479

dc->current_state->bw.dcn.clk.dppclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

480

dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

481

dc->current_state->bw.dcn.clk.fclk_khz,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

482

dc->current_state->bw.dcn.clk.socclk_khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

487

void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

512

chars_printed = dcn10_get_hubbub_state(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

518

chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

524

chars_printed = dcn10_get_rq_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

530

chars_printed = dcn10_get_dlg_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

536

chars_printed = dcn10_get_ttu_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

542

chars_printed = dcn10_get_cm_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

548

chars_printed = dcn10_get_mpcc_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

554

chars_printed = dcn10_get_otg_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

560

chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

71

static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

73

struct dc_context *dc_ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

80

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

83

hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

599

if (enc10->base.ctx->dc->debug.hdmi20_disable &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

722

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1031

const struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1064

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1070

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1073

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1077

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1112

static bool dcn10_get_dcc_compression_cap(const struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1116

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1117

dc->res_pool->hubbub,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1183

struct dc *dc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1188

struct dc_context *ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1215

if (dc->ctx->dce_version == DCN_VERSION_1_01)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1218

dc->caps.max_video_width = 3840;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1219

dc->caps.max_downscale_ratio = 200;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1220

dc->caps.i2c_speed_in_khz = 100;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1221

dc->caps.max_cursor_size = 256;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1222

dc->caps.max_slave_planes = 1;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1223

dc->caps.is_apu = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1224

dc->caps.post_blend_color_processing = false;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1226

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1228

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1229

dc->debug = debug_defaults_drv;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1231

dc->debug = debug_defaults_diags;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1251

if (dc->ctx->dce_version == DCN_VERSION_1_0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1267

if (dc->ctx->dce_version == DCN_VERSION_1_01)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1312

dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1313

memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1314

memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1317

if (dc->ctx->dce_version == DCN_VERSION_1_01) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1318

struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1319

struct dcn_ip_params *dcn_ip = dc->dcn_ip;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1320

struct display_mode_lib *dml = &dc->dml;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1328

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1329

dc->dcn_soc->urgent_latency = 3;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1330

dc->debug.disable_dmcu = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1331

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1335

dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1336

ASSERT(dc->dcn_soc->number_of_channels < 3);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1337

if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1338

dc->dcn_soc->number_of_channels = 2;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1340

if (dc->dcn_soc->number_of_channels == 1) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1341

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1342

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1343

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1344

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1345

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1346

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1352

if (!dc->debug.disable_pplib_clock_request)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1353

dcn_bw_update_from_pplib(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1354

dcn_bw_sync_calcs_and_dml(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1355

if (!dc->debug.disable_pplib_wm_range) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1356

dc->res_pool = &pool->base;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1357

dcn_bw_notify_pplib_of_wm_ranges(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1362

init_data.ctx = dc->ctx;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1446

dc->dml.ip.max_num_dpp = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1447

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1463

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1464

(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1468

dcn10_hw_sequencer_construct(dc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1469

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1471

dc->cap_funcs = cap_funcs;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1484

struct dc *dc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1492

if (construct(num_virtual_links, dc, pool))

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.h

34

struct dc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.h

43

struct dc *dc);

sys/dev/drm/amd/display/dc/inc/core_types.h

100

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/core_types.h

104

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/core_types.h

115

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/core_types.h

120

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/core_types.h

55

const struct dc *dc;

sys/dev/drm/amd/display/dc/inc/dce_calcs.h

36

struct dc;

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

37

struct dc;

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

623

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

627

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

630

void dcn_bw_update_from_pplib(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

631

void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/dcn_calcs.h

632

void dcn_bw_sync_calcs_and_dml(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw/display_clock.h

58

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

102

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

106

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

114

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

128

void (*power_down)(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

130

void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

133

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

139

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

148

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

153

void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

172

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

176

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

181

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

197

struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

201

struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

205

void (*log_hw_state)(struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

207

void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

209

void (*wait_for_mpcc_disconnect)(struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

213

void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

214

void (*optimize_shared_resources)(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

216

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

233

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

73

void (*init_hw)(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

76

struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

79

struct dc *dc, struct dc_state *context);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

82

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

95

void (*program_output_csc)(struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

154

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

159

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

72

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

77

struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

82

void dc_destroy_resource_pool(struct dc *dc);

sys/dev/drm/amd/display/dc/inc/resource.h

85

const struct dc *dc,

sys/dev/drm/amd/display/dc/inc/resource.h

92

const struct dc *dc,

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

200

struct dc *core_dc = irq_service->ctx->dc;

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

202

dc_interrupt_to_irq_source(irq_service->ctx->dc,

sys/dev/drm/amd/display/include/logger_interface.h

141

unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)

sys/dev/drm/amd/display/include/logger_interface.h

145

unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \

sys/dev/drm/amd/display/include/logger_interface.h

146

if (dc->debug.performance_trace) { \

sys/dev/drm/amd/display/include/logger_interface.h

46

struct dc *dc,

sys/dev/drm/amd/display/include/logger_interface.h

51

struct dc *dc,

sys/dev/drm/amd/display/include/logger_interface.h

55

void post_surface_trace(struct dc *dc);

sys/dev/drm/amd/display/include/logger_interface.h

58

struct dc *dc,

sys/dev/drm/amd/display/include/logger_interface.h

62

struct dc *dc,

sys/dev/drm/amd/display/modules/freesync/freesync.c

46

struct dc *dc;

sys/dev/drm/amd/display/modules/freesync/freesync.c

470

if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,

sys/dev/drm/amd/display/modules/freesync/freesync.c

52

struct mod_freesync *mod_freesync_create(struct dc *dc)

sys/dev/drm/amd/display/modules/freesync/freesync.c

60

if (dc == NULL)

sys/dev/drm/amd/display/modules/freesync/freesync.c

63

core_freesync->dc = dc;

sys/dev/drm/amd/display/modules/inc/mod_freesync.h

122

struct mod_freesync *mod_freesync_create(struct dc *dc);

sys/dev/drm/amd/display/modules/inc/mod_stats.h

39

struct mod_stats *mod_stats_create(struct dc *dc);

sys/dev/drm/amd/display/modules/stats/stats.c

100

struct dc *dc = NULL;

sys/dev/drm/amd/display/modules/stats/stats.c

106

dc = core_stats->dc;

sys/dev/drm/amd/display/modules/stats/stats.c

111

struct mod_stats *mod_stats_create(struct dc *dc)

sys/dev/drm/amd/display/modules/stats/stats.c

118

if (dc == NULL)

sys/dev/drm/amd/display/modules/stats/stats.c

126

core_stats->dc = dc;

sys/dev/drm/amd/display/modules/stats/stats.c

129

if (dm_read_persistent_data(dc->ctx, NULL, NULL,

sys/dev/drm/amd/display/modules/stats/stats.c

136

if (dm_read_persistent_data(dc->ctx, NULL, NULL,

sys/dev/drm/amd/display/modules/stats/stats.c

197

struct dc *dc = NULL;

sys/dev/drm/amd/display/modules/stats/stats.c

211

dc = core_stats->dc;

sys/dev/drm/amd/display/modules/stats/stats.c

212

logger = dc->ctx->logger;

sys/dev/drm/amd/display/modules/stats/stats.c

78

struct dc *dc;

sys/dev/misc/dcons/dcons.c

112

dcons_putc(struct dcons_softc *dc, int c)

sys/dev/misc/dcons/dcons.c

116

ch = &dc->o;

sys/dev/misc/dcons/dcons.c

132

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons.c

134

dc = &sc[port];

sys/dev/misc/dcons/dcons.c

138

dc->o.size = osize;

sys/dev/misc/dcons/dcons.c

139

dc->i.size = size - osize;

sys/dev/misc/dcons/dcons.c

140

dc->o.buf = (char *)buf + offset;

sys/dev/misc/dcons/dcons.c

141

dc->i.buf = dc->o.buf + osize;

sys/dev/misc/dcons/dcons.c

142

dc->o.gen = dc->i.gen = 0;

sys/dev/misc/dcons/dcons.c

143

dc->o.pos = dc->i.pos = 0;

sys/dev/misc/dcons/dcons.c

144

dc->o.ptr = &buf->optr[port];

sys/dev/misc/dcons/dcons.c

145

dc->i.ptr = &buf->iptr[port];

sys/dev/misc/dcons/dcons.c

146

dc->brk_state = STATE0;

sys/dev/misc/dcons/dcons.c

151

buf->optr[port] = DCONS_MAKE_PTR(&dc->o);

sys/dev/misc/dcons/dcons.c

152

buf->iptr[port] = DCONS_MAKE_PTR(&dc->i);

sys/dev/misc/dcons/dcons.c

161

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons.c

168

dc = &sc[port];

sys/dev/misc/dcons/dcons.c

169

dc->o.size = ntohl(buf->osize[port]);

sys/dev/misc/dcons/dcons.c

170

dc->i.size = ntohl(buf->isize[port]);

sys/dev/misc/dcons/dcons.c

171

dc->o.buf = (char *)buf + ntohl(buf->ooffset[port]);

sys/dev/misc/dcons/dcons.c

172

dc->i.buf = (char *)buf + ntohl(buf->ioffset[port]);

sys/dev/misc/dcons/dcons.c

173

dc->o.gen = ntohl(buf->optr[port]) >> DCONS_GEN_SHIFT;

sys/dev/misc/dcons/dcons.c

174

dc->i.gen = ntohl(buf->iptr[port]) >> DCONS_GEN_SHIFT;

sys/dev/misc/dcons/dcons.c

175

dc->o.pos = ntohl(buf->optr[port]) & DCONS_POS_MASK;

sys/dev/misc/dcons/dcons.c

176

dc->i.pos = ntohl(buf->iptr[port]) & DCONS_POS_MASK;

sys/dev/misc/dcons/dcons.c

177

dc->o.ptr = &buf->optr[port];

sys/dev/misc/dcons/dcons.c

178

dc->i.ptr = &buf->iptr[port];

sys/dev/misc/dcons/dcons.c

179

dc->brk_state = STATE0;

sys/dev/misc/dcons/dcons.c

181

s += dc->o.size + dc->i.size;

sys/dev/misc/dcons/dcons.c

48

dcons_ischar(struct dcons_softc *dc)

sys/dev/misc/dcons/dcons.c

53

ch = &dc->i;

sys/dev/misc/dcons/dcons.c

76

dcons_checkc(struct dcons_softc *dc)

sys/dev/misc/dcons/dcons.c

82

ch = &dc->i;

sys/dev/misc/dcons/dcons_os.c

141

dcons_check_break(struct dcons_softc *dc, int c)

sys/dev/misc/dcons/dcons_os.c

146

switch (dc->brk_state) {

sys/dev/misc/dcons/dcons_os.c

149

dc->brk_state = STATE2;

sys/dev/misc/dcons/dcons_os.c

151

dc->brk_state = STATE0;

sys/dev/misc/dcons/dcons_os.c

154

dc->brk_state = STATE0;

sys/dev/misc/dcons/dcons_os.c

157

if (dc->flags & DC_GDB)

sys/dev/misc/dcons/dcons_os.c

164

dc->brk_state = STATE1;

sys/dev/misc/dcons/dcons_os.c

168

#define dcons_check_break(dc, c) (c)

sys/dev/misc/dcons/dcons_os.c

172

dcons_os_checkc(struct dcons_softc *dc)

sys/dev/misc/dcons/dcons_os.c

179

c = dcons_check_break(dc, dcons_checkc(dc));

sys/dev/misc/dcons/dcons_os.c

188

dcons_os_getc(struct dcons_softc *dc)

sys/dev/misc/dcons/dcons_os.c

192

while ((c = dcons_os_checkc(dc)) == -1);

sys/dev/misc/dcons/dcons_os.c

198

dcons_os_putc(struct dcons_softc *dc, int c)

sys/dev/misc/dcons/dcons_os.c

203

dcons_putc(dc, c);

sys/dev/misc/dcons/dcons_os.c

317

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons_os.c

320

dc = (struct dcons_softc *)tp->t_dev->si_drv1;

sys/dev/misc/dcons/dcons_os.c

329

dcons_os_putc(dc, clist_getc(&tp->t_outq));

sys/dev/misc/dcons/dcons_os.c

340

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons_os.c

344

dc = &sc[i];

sys/dev/misc/dcons/dcons_os.c

345

tp = ((DEV)dc->dev)->si_tty;

sys/dev/misc/dcons/dcons_os.c

347

while ((c = dcons_os_checkc(dc)) != -1) {

sys/dev/misc/dcons/dcons_os.c

393

struct dcons_softc *dc = (struct dcons_softc *)cp->cn_arg;

sys/dev/misc/dcons/dcons_os.c

394

return (dcons_os_getc(dc));

sys/dev/misc/dcons/dcons_os.c

399

struct dcons_softc *dc = (struct dcons_softc *)cp->cn_arg;

sys/dev/misc/dcons/dcons_os.c

400

return (dcons_os_checkc(dc));

sys/dev/misc/dcons/dcons_os.c

405

struct dcons_softc *dc = (struct dcons_softc *)cp->cn_arg;

sys/dev/misc/dcons/dcons_os.c

406

dcons_os_putc(dc, c);

sys/dev/misc/dcons/dcons_os.c

412

struct dcons_softc *dc = (struct dcons_softc *)private;

sys/dev/misc/dcons/dcons_os.c

413

return (dcons_os_getc(dc));

sys/dev/misc/dcons/dcons_os.c

418

struct dcons_softc *dc = (struct dcons_softc *)private;

sys/dev/misc/dcons/dcons_os.c

419

return (dcons_os_checkc(dc));

sys/dev/misc/dcons/dcons_os.c

424

struct dcons_softc *dc = (struct dcons_softc *)private;

sys/dev/misc/dcons/dcons_os.c

425

dcons_os_putc(dc, c);

sys/dev/misc/dcons/dcons_os.c

484

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons_os.c

488

dc = &sc[port];

sys/dev/misc/dcons/dcons_os.c

489

dc->flags = flags;

sys/dev/misc/dcons/dcons_os.c

492

dc->dev = (void *)dev;

sys/dev/misc/dcons/dcons_os.c

493

dev->si_drv1 = (void *)dc;

sys/dev/misc/dcons/dcons_os.c

499

tp->t_dev = dc->dev;

sys/dev/misc/dcons/dcons_os.c

523

struct dcons_softc *dc;

sys/dev/misc/dcons/dcons_os.c

525

dc = &sc[port];

sys/dev/misc/dcons/dcons_os.c

527

tp = ((DEV)dc->dev)->si_tty;

sys/dev/misc/dcons/dcons_os.c

539

tsleep((void *)dc, 0, "dcodtc", hz/4);

sys/dev/misc/dcons/dcons_os.c

541

tsleep((void *)dc, PWAIT, "dcodtc", hz/4);

sys/dev/misc/dcons/dcons_os.c

544

destroy_dev(dc->dev);

sys/dev/misc/puc/puc.c

571

devclass_t dc;

sys/dev/misc/puc/puc.c

580

dc = devclass_find(name);

sys/dev/misc/puc/puc.c

581

if (dc == NULL)

sys/dev/misc/puc/puc.c

583

while (devclass_get_device(dc, unit))

sys/dev/netif/dc/if_dc.c

325

DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);

sys/dev/netif/em/if_em.c

4109

adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);

sys/dev/netif/em/if_em.c

4244

(long long)adapter->stats.dc);

sys/dev/netif/emx/if_emx.c

3653

sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);

sys/dev/netif/emx/if_emx.c

3773

(long long)sc->stats.dc);

sys/dev/netif/ig_hal/e1000_hw.h

563

u64 dc;

sys/dev/netif/igb/if_igb.c

3191

stats->dc += E1000_READ_REG(hw, E1000_DC);

sys/dev/raid/hpt27xx/hpt27xx_osm_bsd.c

1170

devclass_t dc = devclass_find("pci");

sys/dev/raid/hpt27xx/hpt27xx_osm_bsd.c

1172

if (dc){

sys/dev/raid/hpt27xx/hpt27xx_osm_bsd.c

1173

dlfirst = TAILQ_FIRST(&dc->drivers);

sys/dev/raid/hptrr/hptrr_osm_bsd.c

1150

devclass_t dc = devclass_find("pci");

sys/dev/raid/hptrr/hptrr_osm_bsd.c

1152

if (dc){

sys/dev/raid/hptrr/hptrr_osm_bsd.c

1153

dlfirst = TAILQ_FIRST(&dc->drivers);

sys/dev/raid/mfi/mfi.c

3454

devclass_t dc;

sys/dev/raid/mfi/mfi.c

3459

dc = devclass_find("mfi");

sys/dev/raid/mfi/mfi.c

3460

if (dc == NULL) {

sys/dev/raid/mfi/mfi.c

3466

sc = devclass_get_softc(dc, i);

sys/dev/serial/sio/sio.c

392

devclass_t dc;

sys/dev/serial/sio/sio.c

403

dc = device_get_devclass(dev);

sys/dev/serial/sio/sio.c

404

while (devclass_get_device(dc, unit))

sys/dev/virtual/amazon/ena/ena.c

3105

devclass_t dc;

sys/dev/virtual/amazon/ena/ena.c

3109

dc = devclass_find("ena");

sys/dev/virtual/amazon/ena/ena.c

3110

if (unlikely(dc == NULL)) {

sys/dev/virtual/amazon/ena/ena.c

3115

max = devclass_get_maxunit(dc);

sys/dev/virtual/amazon/ena/ena.c

3117

adapter = devclass_get_softc(dc, max);

sys/kern/subr_bus.c

1005

devclass_get_drivers(devclass_t dc, driver_t ***listp, int *countp)

sys/kern/subr_bus.c

1012

TAILQ_FOREACH(dl, &dc->drivers, link)

sys/kern/subr_bus.c

1019

TAILQ_FOREACH(dl, &dc->drivers, link) {

sys/kern/subr_bus.c

1035

devclass_get_count(devclass_t dc)

sys/kern/subr_bus.c

1040

for (i = 0; i < dc->maxunit; i++)

sys/kern/subr_bus.c

1041

if (dc->devices[i])

sys/kern/subr_bus.c

1047

devclass_get_maxunit(devclass_t dc)

sys/kern/subr_bus.c

1049

return(dc->maxunit);

sys/kern/subr_bus.c

1053

devclass_set_parent(devclass_t dc, devclass_t pdc)

sys/kern/subr_bus.c

1055

dc->parent = pdc;

sys/kern/subr_bus.c

1059

devclass_get_parent(devclass_t dc)

sys/kern/subr_bus.c

1061

return(dc->parent);

sys/kern/subr_bus.c

1065

devclass_alloc_unit(devclass_t dc, int *unitp)

sys/kern/subr_bus.c

1069

PDEBUG(("unit %d in devclass %s", unit, DEVCLANAME(dc)));

sys/kern/subr_bus.c

1073

if (unit >= 0 && unit < dc->maxunit &&

sys/kern/subr_bus.c

1074

dc->devices[unit] != NULL) {

sys/kern/subr_bus.c

1077

dc->name, dc->name, unit);

sys/kern/subr_bus.c

1079

while (++unit < dc->maxunit && dc->devices[unit] != NULL)

sys/kern/subr_bus.c

1085

while (unit < dc->maxunit && dc->devices[unit] != NULL)

sys/kern/subr_bus.c

1094

if (unit >= dc->maxunit) {

sys/kern/subr_bus.c

1112

if (dc->devices) {

sys/kern/subr_bus.c

1113

bcopy(dc->devices,

sys/kern/subr_bus.c

1115

sizeof(device_t) * dc->maxunit);

sys/kern/subr_bus.c

1116

kfree(dc->devices, M_BUS);

sys/kern/subr_bus.c

1118

dc->devices = newlist;

sys/kern/subr_bus.c

1119

dc->maxunit = newsize;

sys/kern/subr_bus.c

1121

PDEBUG(("now: unit %d in devclass %s", unit, DEVCLANAME(dc)));

sys/kern/subr_bus.c

1128

devclass_add_device(devclass_t dc, device_t dev)

sys/kern/subr_bus.c

1132

PDEBUG(("%s in devclass %s", DEVICENAME(dev), DEVCLANAME(dc)));

sys/kern/subr_bus.c

1134

buflen = strlen(dc->name) + 5;

sys/kern/subr_bus.c

1139

if ((error = devclass_alloc_unit(dc, &dev->unit)) != 0) {

sys/kern/subr_bus.c

1144

dc->devices[dev->unit] = dev;

sys/kern/subr_bus.c

1145

dev->devclass = dc;

sys/kern/subr_bus.c

1146

ksnprintf(dev->nameunit, buflen, "%s%d", dc->name, dev->unit);

sys/kern/subr_bus.c

115

devclass_t dc = (devclass_t)arg1;

sys/kern/subr_bus.c

1152

devclass_delete_device(devclass_t dc, device_t dev)

sys/kern/subr_bus.c

1154

if (!dc || !dev)

sys/kern/subr_bus.c

1157

PDEBUG(("%s in devclass %s", DEVICENAME(dev), DEVCLANAME(dc)));

sys/kern/subr_bus.c

1159

if (dev->devclass != dc || dc->devices[dev->unit] != dev) {

sys/kern/subr_bus.c

1161

"%p/%p %d %p/%p\n", dev->devclass, dc, dev->unit,

sys/kern/subr_bus.c

1162

dc->devices[dev->unit], dev);

sys/kern/subr_bus.c

1164

dc->devices[dev->unit] = NULL;

sys/kern/subr_bus.c

1178

devclass_t dc;

sys/kern/subr_bus.c

1183

dc = devclass_find_internal(name, NULL, TRUE);

sys/kern/subr_bus.c

1184

if (!dc) {

sys/kern/subr_bus.c

1189

dc = NULL;

sys/kern/subr_bus.c

120

value = dc->parent ? dc->parent->name : "";

sys/kern/subr_bus.c

1211

if (devclass_add_device(dc, dev) != 0) {

sys/kern/subr_bus.c

129

devclass_sysctl_init(devclass_t dc)

sys/kern/subr_bus.c

132

if (dc->sysctl_tree != NULL)

sys/kern/subr_bus.c

134

sysctl_ctx_init(&dc->sysctl_ctx);

sys/kern/subr_bus.c

135

dc->sysctl_tree = SYSCTL_ADD_NODE(&dc->sysctl_ctx,

sys/kern/subr_bus.c

136

SYSCTL_STATIC_CHILDREN(_dev), OID_AUTO, dc->name,

sys/kern/subr_bus.c

1362

devclass_t dc;

sys/kern/subr_bus.c

1365

dc = devclass_find(classname);

sys/kern/subr_bus.c

1366

if (!dc)

sys/kern/subr_bus.c

1370

child = devclass_get_device(dc, unit);

sys/kern/subr_bus.c

1374

for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {

sys/kern/subr_bus.c

1375

child = devclass_get_device(dc, unit);

sys/kern/subr_bus.c

138

SYSCTL_ADD_PROC(&dc->sysctl_ctx, SYSCTL_CHILDREN(dc->sysctl_tree),

sys/kern/subr_bus.c

1384

first_matching_driver(devclass_t dc, device_t dev)

sys/kern/subr_bus.c

1387

return(devclass_find_driver_internal(dc, dev->devclass->name));

sys/kern/subr_bus.c

1389

return(TAILQ_FIRST(&dc->drivers));

sys/kern/subr_bus.c

1393

next_matching_driver(devclass_t dc, device_t dev, driverlink_t last)

sys/kern/subr_bus.c

140

dc, DEVCLASS_SYSCTL_PARENT, devclass_sysctl_handler, "A",

sys/kern/subr_bus.c

1408

devclass_t dc;

sys/kern/subr_bus.c

1414

dc = dev->devclass;

sys/kern/subr_bus.c

1415

if (!dc)

sys/kern/subr_bus.c

1421

for (; dc; dc = dc->parent) {

sys/kern/subr_bus.c

1422

for (dl = first_matching_driver(dc, child); dl;

sys/kern/subr_bus.c

1423

dl = next_matching_driver(dc, child, dl)) {

sys/kern/subr_bus.c

1496

devclass_t dc;

sys/kern/subr_bus.c

1502

dc = dev->devclass;

sys/kern/subr_bus.c

1503

if (!dc)

sys/kern/subr_bus.c

1509

for (; dc; dc = dc->parent) {

sys/kern/subr_bus.c

1510

for (dl = first_matching_driver(dc, child); dl;

sys/kern/subr_bus.c

1511

dl = next_matching_driver(dc, child, dl)) {

sys/kern/subr_bus.c

191

devclass_t dc = dev->devclass;

sys/kern/subr_bus.c

1910

devclass_t dc;

sys/kern/subr_bus.c

1924

dc = devclass_find_internal(classname, NULL, TRUE);

sys/kern/subr_bus.c

1925

if (!dc)

sys/kern/subr_bus.c

1928

error = devclass_add_device(dc, dev);

sys/kern/subr_bus.c

195

devclass_sysctl_init(dc);

sys/kern/subr_bus.c

198

SYSCTL_CHILDREN(dc->sysctl_tree), OID_AUTO,

sys/kern/subr_bus.c

199

dev->nameunit + strlen(dc->name),

sys/kern/subr_bus.c

2168

devclass_t dc;

sys/kern/subr_bus.c

2171

dc = device_get_devclass(dev);

sys/kern/subr_bus.c

2172

if (unit < dc->maxunit && dc->devices[unit])

sys/kern/subr_bus.c

2174

err = devclass_delete_device(dc, dev);

sys/kern/subr_bus.c

2178

err = devclass_add_device(dc, dev);

sys/kern/subr_bus.c

226

devclass_t dc = dev->devclass;

sys/kern/subr_bus.c

230

sysctl_rename_oid(dev->sysctl_tree, dev->nameunit + strlen(dc->name));

sys/kern/subr_bus.c

2812

devclass_t dc = dev->devclass;

sys/kern/subr_bus.c

2815

TAILQ_FOREACH(dl, &dc->drivers, link) {

sys/kern/subr_bus.c

3767

print_devclass_short(devclass_t dc, int indent)

sys/kern/subr_bus.c

3769

if (!dc)

sys/kern/subr_bus.c

3772

indentprintf(("devclass %s: max units = %d\n", dc->name, dc->maxunit));

sys/kern/subr_bus.c

3776

print_devclass(devclass_t dc, int indent)

sys/kern/subr_bus.c

3780

if (!dc)

sys/kern/subr_bus.c

3783

print_devclass_short(dc, indent);

sys/kern/subr_bus.c

3785

print_driver_list(dc->drivers, indent+1);

sys/kern/subr_bus.c

3788

for (i = 0; i < dc->maxunit; i++)

sys/kern/subr_bus.c

3789

if (dc->devices[i])

sys/kern/subr_bus.c

3790

print_device(dc->devices[i], indent+1);

sys/kern/subr_bus.c

3796

devclass_t dc;

sys/kern/subr_bus.c

3799

TAILQ_FOREACH(dc, &devclasses, link) {

sys/kern/subr_bus.c

3800

print_devclass_short(dc, 0);

sys/kern/subr_bus.c

3807

devclass_t dc;

sys/kern/subr_bus.c

3810

TAILQ_FOREACH(dc, &devclasses, link) {

sys/kern/subr_bus.c

3811

print_devclass(dc, 0);

sys/kern/subr_bus.c

742

devclass_t dc;

sys/kern/subr_bus.c

748

TAILQ_FOREACH(dc, &devclasses, link)

sys/kern/subr_bus.c

749

if (!strcmp(dc->name, classname))

sys/kern/subr_bus.c

752

if (create && !dc) {

sys/kern/subr_bus.c

754

dc = kmalloc(sizeof(struct devclass) + strlen(classname) + 1,

sys/kern/subr_bus.c

756

dc->parent = NULL;

sys/kern/subr_bus.c

757

dc->name = (char*) (dc + 1);

sys/kern/subr_bus.c

758

strcpy(dc->name, classname);

sys/kern/subr_bus.c

759

dc->devices = NULL;

sys/kern/subr_bus.c

760

dc->maxunit = 0;

sys/kern/subr_bus.c

761

TAILQ_INIT(&dc->drivers);

sys/kern/subr_bus.c

762

TAILQ_INSERT_TAIL(&devclasses, dc, link);

sys/kern/subr_bus.c

776

if (parentname && dc && !dc->parent &&

sys/kern/subr_bus.c

778

dc->parent = devclass_find_internal(parentname, NULL, FALSE);

sys/kern/subr_bus.c

780

return(dc);

sys/kern/subr_bus.c

79

static void print_devclass_short(devclass_t dc, int indent);

sys/kern/subr_bus.c

798

devclass_t dc;

sys/kern/subr_bus.c

80

static void print_devclass(devclass_t dc, int indent);

sys/kern/subr_bus.c

800

if ((dc = devclass_find(classname)) != NULL)

sys/kern/subr_bus.c

801

return(devclass_get_device(dc, unit));

sys/kern/subr_bus.c

806

devclass_add_driver(devclass_t dc, driver_t *driver)

sys/kern/subr_bus.c

830

TAILQ_INSERT_TAIL(&dc->drivers, dl, link);

sys/kern/subr_bus.c

841

for (i = 0; i < dc->maxunit; i++) {

sys/kern/subr_bus.c

842

if ((dev = dc->devices[i]) != NULL) {

sys/kern/subr_bus.c

855

devclass_t dc = devclass_find(driver->name);

sys/kern/subr_bus.c

863

if (!dc)

sys/kern/subr_bus.c

888

for (i = 0; i < dc->maxunit; i++)

sys/kern/subr_bus.c

889

if (dc->devices[i]) {

sys/kern/subr_bus.c

890

dev = dc->devices[i];

sys/kern/subr_bus.c

909

devclass_find_driver_internal(devclass_t dc, const char *classname)

sys/kern/subr_bus.c

913

PDEBUG(("%s in devclass %s", classname, DEVCLANAME(dc)));

sys/kern/subr_bus.c

915

TAILQ_FOREACH(dl, &dc->drivers, link)

sys/kern/subr_bus.c

924

devclass_find_driver(devclass_t dc, const char *classname)

sys/kern/subr_bus.c

928

dl = devclass_find_driver_internal(dc, classname);

sys/kern/subr_bus.c

936

devclass_get_name(devclass_t dc)

sys/kern/subr_bus.c

938

return(dc->name);

sys/kern/subr_bus.c

942

devclass_get_device(devclass_t dc, int unit)

sys/kern/subr_bus.c

944

if (dc == NULL || unit < 0 || unit >= dc->maxunit)

sys/kern/subr_bus.c

946

return(dc->devices[unit]);

sys/kern/subr_bus.c

950

devclass_get_softc(devclass_t dc, int unit)

sys/kern/subr_bus.c

954

dev = devclass_get_device(dc, unit);

sys/kern/subr_bus.c

962

devclass_get_devices(devclass_t dc, device_t **devlistp, int *devcountp)

sys/kern/subr_bus.c

969

for (i = 0; i < dc->maxunit; i++)

sys/kern/subr_bus.c

970

if (dc->devices[i])

sys/kern/subr_bus.c

976

for (i = 0; i < dc->maxunit; i++)

sys/kern/subr_bus.c

977

if (dc->devices[i]) {

sys/kern/subr_bus.c

978

list[count] = dc->devices[i];

sys/netproto/802_11/wlan/ieee80211_ioctl.c

709

struct ieee80211_devcaps_req *dc;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

722

dc = (struct ieee80211_devcaps_req *)

sys/netproto/802_11/wlan/ieee80211_ioctl.c

725

dc = (struct ieee80211_devcaps_req *)

sys/netproto/802_11/wlan/ieee80211_ioctl.c

729

if (dc == NULL)

sys/netproto/802_11/wlan/ieee80211_ioctl.c

731

dc->dc_drivercaps = ic->ic_caps;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

732

dc->dc_cryptocaps = ic->ic_cryptocaps;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

733

dc->dc_htcaps = ic->ic_htcaps;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

734

ci = &dc->dc_chaninfo;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

739

error = copyout(dc, ireq->i_data, IEEE80211_DEVCAPS_SPACE(dc));

sys/netproto/802_11/wlan/ieee80211_ioctl.c

740

IEEE80211_FREE(dc, M_TEMP);

sys/sys/bus.h

410

int devclass_add_driver(devclass_t dc, kobj_class_t driver);

sys/sys/bus.h

411

int devclass_delete_driver(devclass_t dc, kobj_class_t driver);

sys/sys/bus.h

415

kobj_class_t devclass_find_driver(devclass_t dc, const char *classname);

sys/sys/bus.h

416

const char *devclass_get_name(devclass_t dc);

sys/sys/bus.h

417

device_t devclass_get_device(devclass_t dc, int unit);

sys/sys/bus.h

418

void *devclass_get_softc(devclass_t dc, int unit);

sys/sys/bus.h

419

int devclass_get_devices(devclass_t dc, device_t **listp, int *countp);

sys/sys/bus.h

420

int devclass_get_drivers(devclass_t dc, driver_t ***listp, int *countp);

sys/sys/bus.h

421

int devclass_get_count(devclass_t dc);

sys/sys/bus.h

422

int devclass_get_maxunit(devclass_t dc);

sys/sys/bus.h

423

void devclass_set_parent(devclass_t dc, devclass_t pdc);

sys/sys/bus.h

424

devclass_t devclass_get_parent(devclass_t dc);

tools/regression/include/tgmath/tgmath.c

170

double complex dc;

tools/regression/include/tgmath/tgmath.c

341

RUN_TEST(FNC(dc), double complex) && \

tools/regression/include/tgmath/tgmath.c

351

RUN_TEST(FNC(dc), double) && \

tools/regression/include/tgmath/tgmath.c

360

RUN_TEST(FNC(ldc, dc), long double complex) && \

tools/regression/include/tgmath/tgmath.c

366

RUN_TEST(FNC(dc, ldc), long double complex) && \

tools/regression/include/tgmath/tgmath.c

372

RUN_TEST(FNC(ld, dc), long double complex) && \

tools/regression/include/tgmath/tgmath.c

375

RUN_TEST(FNC(dc, 1.l), long double complex) && \

tools/regression/include/tgmath/tgmath.c

377

RUN_TEST(FNC(dc, dc), double complex) && \

tools/regression/include/tgmath/tgmath.c

378

RUN_TEST(FNC(dc, fc), double complex) && \

tools/regression/include/tgmath/tgmath.c

379

RUN_TEST(FNC(dc, d), double complex) && \

tools/regression/include/tgmath/tgmath.c

380

RUN_TEST(FNC(dc, f), double complex) && \

tools/regression/include/tgmath/tgmath.c

381

RUN_TEST(FNC(dc, ull), double complex) && \

tools/regression/include/tgmath/tgmath.c

382

RUN_TEST(FNC(I, dc), double complex) && \

tools/regression/include/tgmath/tgmath.c

383

RUN_TEST(FNC(1., dc), double complex) && \

tools/regression/include/tgmath/tgmath.c

384

RUN_TEST(FNC(1, dc), double complex) && \

tools/regression/include/tgmath/tgmath.c

593

PASS_REAL_FIXED_ARG_REAL_RET(scalbln, dc));

usr.bin/bc/bc.y

1070

pid = waitpid(dc, &status, WCONTINUED | WNOHANG);

usr.bin/bc/bc.y

108

static pid_t dc;

usr.bin/bc/bc.y

1138

dc = fork();

usr.bin/bc/bc.y

1139

if (dc == -1)

usr.bin/bc/bc.y

1141

else if (dc != 0) {

usr.bin/bc/bc.y

288

if (dc) {

usr.bin/strfile/strfile.c

133

char *sp, *nsp, dc;

usr.bin/strfile/strfile.c

145

dc = Delimch;

usr.bin/strfile/strfile.c

164

Tbl.str_delim = dc;

usr.bin/strfile/strfile.c

171

if (sp == NULL || (sp[0] == dc && sp[1] == '\n')) {

usr.bin/window/wwmove.c

44

int dr, dc;

usr.bin/window/wwmove.c

48

dc = col - w->ww_w.l;

usr.bin/window/wwmove.c

52

w->ww_w.l += dc;

usr.bin/window/wwmove.c

53

w->ww_w.r += dc;

usr.bin/window/wwmove.c

57

w->ww_b.l += dc;

usr.bin/window/wwmove.c

58

w->ww_b.r += dc;

usr.bin/window/wwmove.c

68

w->ww_cur.c += dc;

usr.bin/window/wwmove.c

72

w->ww_win[i] -= dc;

usr.bin/window/wwmove.c

76

w->ww_fmap[i] -= dc;

usr.bin/window/wwmove.c

92

w->ww_buf[i] -= dc;

usr.sbin/dconschat/dconschat.c

127

dread(struct dcons_state *dc, void *buf, size_t n, off_t offset)

usr.sbin/dconschat/dconschat.c

129

switch (dc->type) {

usr.sbin/dconschat/dconschat.c

131

return (pread(dc->fd, buf, n, offset));

usr.sbin/dconschat/dconschat.c

133

return (kvm_read(dc->kd, offset, buf, n));

usr.sbin/dconschat/dconschat.c

139

dwrite(struct dcons_state *dc, void *buf, size_t n, off_t offset)

usr.sbin/dconschat/dconschat.c

141

if ((dc->flags & F_RD_ONLY) != 0)

usr.sbin/dconschat/dconschat.c

144

switch (dc->type) {

usr.sbin/dconschat/dconschat.c

146

return (pwrite(dc->fd, buf, n, offset));

usr.sbin/dconschat/dconschat.c

148

return (kvm_write(dc->kd, offset, buf, n));

usr.sbin/dconschat/dconschat.c

156

struct dcons_state *dc;

usr.sbin/dconschat/dconschat.c

158

dc = ≻

usr.sbin/dconschat/dconschat.c

160

tcsetattr(STDIN_FILENO, TCSADRAIN, &dc->tsave);

usr.sbin/dconschat/dconschat.c

171

dconschat_get_crom(struct dcons_state *dc)

usr.sbin/dconschat/dconschat.c

182

if (dread(dc, &buf, 4, addr + i) < 0) {

usr.sbin/dconschat/dconschat.c

216

dc->paddr = ((off_t)hi << 24) | lo;

usr.sbin/dconschat/dconschat.c

222

dconschat_ready(struct dcons_state *dc, int ready, const char *reason)

usr.sbin/dconschat/dconschat.c

227

old = (dc->flags & F_READY) ? 1 : 0;

usr.sbin/dconschat/dconschat.c

230

dc->flags |= F_READY;

usr.sbin/dconschat/dconschat.c

235

dc->flags &= ~F_READY;

usr.sbin/dconschat/dconschat.c

244

dconschat_fetch_header(struct dcons_state *dc)

usr.sbin/dconschat/dconschat.c

251

if (dc->paddr == 0 && (dc->flags & F_USE_CROM) != 0) {

usr.sbin/dconschat/dconschat.c

252

if (dconschat_get_crom(dc)) {

usr.sbin/dconschat/dconschat.c

253

dconschat_ready(dc, 0, "get crom failed");

usr.sbin/dconschat/dconschat.c

259

if (dread(dc, &dbuf, DCONS_HEADER_SIZE, dc->paddr) < 0) {

usr.sbin/dconschat/dconschat.c

260

dconschat_ready(dc, 0, "read header failed");

usr.sbin/dconschat/dconschat.c

264

if ((dc->flags & F_USE_CROM) !=0)

usr.sbin/dconschat/dconschat.c

265

dc->paddr = 0;

usr.sbin/dconschat/dconschat.c

267

dconschat_ready(dc, 0, ebuf);

usr.sbin/dconschat/dconschat.c

275

dconschat_ready(dc, 0, ebuf);

usr.sbin/dconschat/dconschat.c

284

o = &dc->port[j].o;

usr.sbin/dconschat/dconschat.c

285

newbuf = dc->paddr + ntohl(dbuf.ooffset[j]);

usr.sbin/dconschat/dconschat.c

296

i = &dc->port[j].i;

usr.sbin/dconschat/dconschat.c

300

i->buf = dc->paddr + ntohl(dbuf.ioffset[j]);

usr.sbin/dconschat/dconschat.c

310

if (IS_CONSOLE(&dc->port[j]) && new &&

usr.sbin/dconschat/dconschat.c

311

(dc->flags & F_REPLAY) !=0) {

usr.sbin/dconschat/dconschat.c

318

dconschat_ready(dc, 1, NULL);

usr.sbin/dconschat/dconschat.c

323

dconschat_get_ptr (struct dcons_state *dc) {

usr.sbin/dconschat/dconschat.c

329

dlen = dread(dc, &ptr, sizeof(ptr),

usr.sbin/dconschat/dconschat.c

330

dc->paddr + __offsetof(struct dcons_buf, magic));

usr.sbin/dconschat/dconschat.c

336

dconschat_ready(dc, 0, "get ptr failed");

usr.sbin/dconschat/dconschat.c

340

dconschat_ready(dc, 0, "wrong magic");

usr.sbin/dconschat/dconschat.c

345

dc->port[i].optr = ntohl(ptr[i + 1]);

usr.sbin/dconschat/dconschat.c

346

dc->port[i].iptr = ntohl(ptr[DCONS_NPORT + i + 1]);

usr.sbin/dconschat/dconschat.c

353

dconschat_read_dcons(struct dcons_state *dc, int port, char *buf, int len)

usr.sbin/dconschat/dconschat.c

360

ch = &dc->port[port].o;

usr.sbin/dconschat/dconschat.c

361

ptr = dc->port[port].optr;

usr.sbin/dconschat/dconschat.c

412

dlen = dread(dc, buf, rlen, ch->buf + ch->pos);

usr.sbin/dconschat/dconschat.c

417

dconschat_ready(dc, 0, "read buffer failed");

usr.sbin/dconschat/dconschat.c

433

dconschat_write_dcons(struct dcons_state *dc, int port, char *buf, int blen)

usr.sbin/dconschat/dconschat.c

440

ch = &dc->port[port].i;

usr.sbin/dconschat/dconschat.c

441

ptr = dc->port[port].iptr;

usr.sbin/dconschat/dconschat.c

450

len = dwrite(dc, buf, wlen, ch->buf + ch->pos);

usr.sbin/dconschat/dconschat.c

455

dconschat_ready(dc, 0, "write buffer failed");

usr.sbin/dconschat/dconschat.c

471

dc->port[port].iptr = ptr;

usr.sbin/dconschat/dconschat.c

476

len = dwrite(dc, &ptr, sizeof(u_int32_t),

usr.sbin/dconschat/dconschat.c

477

dc->paddr + __offsetof(struct dcons_buf, iptr[port]));

usr.sbin/dconschat/dconschat.c

482

dconschat_ready(dc, 0, "write ptr failed");

usr.sbin/dconschat/dconschat.c

500

dconschat_init_socket(struct dcons_state *dc, int port, char *host, int sport)

usr.sbin/dconschat/dconschat.c

508

p = &dc->port[port];

usr.sbin/dconschat/dconschat.c

522

tcgetattr(STDIN_FILENO, &dc->tsave) == 0) {

usr.sbin/dconschat/dconschat.c

525

traw = dc->tsave;

usr.sbin/dconschat/dconschat.c

532

kevent(dc->kq, &kev, 1, NULL, 0, &dc->zero);

usr.sbin/dconschat/dconschat.c

565

error = kevent(dc->kq, &kev, 1, NULL, 0, &dc->to);

usr.sbin/dconschat/dconschat.c

572

dconschat_accept_socket(struct dcons_state *dc, struct dcons_port *p)

usr.sbin/dconschat/dconschat.c

589

if (IS_CONSOLE(p) && (dc->flags & F_TELNET) != 0) {

usr.sbin/dconschat/dconschat.c

605

kevent(dc->kq, &kev, 1, NULL, 0, &dc->zero);

usr.sbin/dconschat/dconschat.c

610

dconschat_read_filter(struct dcons_state *dc, struct dcons_port *p,

usr.sbin/dconschat/dconschat.c

617

if ((dc->flags & F_TELNET) != 0) {

usr.sbin/dconschat/dconschat.c

640

switch (dc->escape_state) {

usr.sbin/dconschat/dconschat.c

643

dc->escape_state = STATE2;

usr.sbin/dconschat/dconschat.c

645

dc->escape_state = STATE0;

usr.sbin/dconschat/dconschat.c

648

dc->escape_state = STATE0;

usr.sbin/dconschat/dconschat.c

653

dc->escape_state = STATE1;

usr.sbin/dconschat/dconschat.c

656

if (*sp == 0x3 && (dc->flags & F_ALT_BREAK) != 0) {

usr.sbin/dconschat/dconschat.c

675

dconschat_read_socket(struct dcons_state *dc, struct dcons_port *p)

usr.sbin/dconschat/dconschat.c

683

dconschat_read_filter(dc, p, rbuf, len, wbuf, &wlen);

usr.sbin/dconschat/dconschat.c

685

if (wlen > 0 && (dc->flags & F_READY) != 0) {

usr.sbin/dconschat/dconschat.c

686

dconschat_write_dcons(dc, p->port, wbuf, wlen);

usr.sbin/dconschat/dconschat.c

705

kevent(dc->kq, &kev, 1, NULL, 0, &dc->zero);

usr.sbin/dconschat/dconschat.c

711

kevent(dc->kq, &kev, 1, NULL, 0, &dc->zero);

usr.sbin/dconschat/dconschat.c

718

dconschat_proc_socket(struct dcons_state *dc)

usr.sbin/dconschat/dconschat.c

724

n = kevent(dc->kq, NULL, 0, elist, NEVENT, &dc->to);

usr.sbin/dconschat/dconschat.c

729

dconschat_accept_socket(dc, p);

usr.sbin/dconschat/dconschat.c

731

dconschat_read_socket(dc, p);

usr.sbin/dconschat/dconschat.c

738

dconschat_proc_dcons(struct dcons_state *dc)

usr.sbin/dconschat/dconschat.c

744

error = dconschat_get_ptr(dc);

usr.sbin/dconschat/dconschat.c

750

p = &dc->port[port];

usr.sbin/dconschat/dconschat.c

753

while ((len = dconschat_read_dcons(dc, port, buf,

usr.sbin/dconschat/dconschat.c

756

dconschat_get_ptr(dc);

usr.sbin/dconschat/dconschat.c

758

if ((dc->flags & F_ONE_SHOT) != 0 && len <= 0)

usr.sbin/dconschat/dconschat.c

765

dconschat_start_session(struct dcons_state *dc)

usr.sbin/dconschat/dconschat.c

770

if ((dc->flags & F_READY) == 0 &&

usr.sbin/dconschat/dconschat.c

772

dconschat_fetch_header(dc);

usr.sbin/dconschat/dconschat.c

773

if ((dc->flags & F_READY) != 0)

usr.sbin/dconschat/dconschat.c

774

dconschat_proc_dcons(dc);

usr.sbin/dconschat/dconschat.c

775

dconschat_proc_socket(dc);

usr.sbin/dconschat/dconschat.c

810

struct dcons_state *dc;

usr.sbin/dconschat/dconschat.c

819

dc = ≻

usr.sbin/dconschat/dconschat.c

820

dc->flags |= USE_CROM ? F_USE_CROM : 0;

usr.sbin/dconschat/dconschat.c

829

dc->paddr = strtoull(optarg, NULL, 0);

usr.sbin/dconschat/dconschat.c

830

dc->flags &= ~F_USE_CROM;

usr.sbin/dconschat/dconschat.c

833

dc->flags |= F_ALT_BREAK;

usr.sbin/dconschat/dconschat.c

841

dc->flags |= F_REPLAY;

usr.sbin/dconschat/dconschat.c

849

dc->type = TYPE_FW;

usr.sbin/dconschat/dconschat.c

873

dc->flags |= F_RD_ONLY;

usr.sbin/dconschat/dconschat.c

876

dc->flags |= F_TELNET;

usr.sbin/dconschat/dconschat.c

879

dc->flags |= F_ONE_SHOT | F_REPLAY;

usr.sbin/dconschat/dconschat.c

885

if (dc->paddr == 0 && (dc->flags & F_USE_CROM) == 0) {

usr.sbin/dconschat/dconschat.c

902

switch (dc->type) {

usr.sbin/dconschat/dconschat.c

908

dc->fd = open(devicename, O_RDWR);

usr.sbin/dconschat/dconschat.c

909

if (dc->fd >= 0)

usr.sbin/dconschat/dconschat.c

914

error = ioctl(dc->fd, FW_SDEUI64, &eui);

usr.sbin/dconschat/dconschat.c

923

dc->kd = kvm_open(sysfile, core, NULL,

usr.sbin/dconschat/dconschat.c

924

(dc->flags & F_RD_ONLY) ? O_RDONLY : O_RDWR, "dconschat");

usr.sbin/dconschat/dconschat.c

925

if (dc->kd == NULL)

usr.sbin/dconschat/dconschat.c

928

if (kvm_nlist(dc->kd, nl) < 0)

usr.sbin/dconschat/dconschat.c

929

errx(1, "kvm_nlist: %s", kvm_geterr(dc->kd));

usr.sbin/dconschat/dconschat.c

931

if (kvm_read(dc->kd, nl[0].n_value, &dcons_buf,

usr.sbin/dconschat/dconschat.c

933

errx(1, "kvm_read: %s", kvm_geterr(dc->kd));

usr.sbin/dconschat/dconschat.c

934

dc->paddr = (uintptr_t)dcons_buf;

usr.sbin/dconschat/dconschat.c

936

printf("dcons_buf: 0x%x\n", (uint)dc->paddr);

usr.sbin/dconschat/dconschat.c

940

dconschat_fetch_header(dc);

usr.sbin/dconschat/dconschat.c

943

dc->kq = kqueue();

usr.sbin/dconschat/dconschat.c

945

dc->to.tv_sec = 1;

usr.sbin/dconschat/dconschat.c

946

dc->to.tv_nsec = 0;

usr.sbin/dconschat/dconschat.c

948

dc->to.tv_sec = 0;

usr.sbin/dconschat/dconschat.c

949

dc->to.tv_nsec = 1000 * 1000 * 1000 / poll_hz;

usr.sbin/dconschat/dconschat.c

951

dc->zero.tv_sec = 0;

usr.sbin/dconschat/dconschat.c

952

dc->zero.tv_nsec = 0;

usr.sbin/dconschat/dconschat.c

954

dconschat_init_socket(dc, i,

usr.sbin/dconschat/dconschat.c

957

dconschat_start_session(dc);

usr.sbin/dconschat/dconschat.c

960

freeaddrinfo(dc->port[i].res);