crypto/libressl/apps/openssl/apps.c

1117

cnf = config;

crypto/libressl/apps/openssl/apps.h

138

extern CONF *config;

crypto/libressl/apps/openssl/openssl.c

357

CONF *config = NULL;

crypto/libressl/apps/openssl/openssl.c

434

config = NCONF_new(NULL);

crypto/libressl/apps/openssl/openssl.c

435

i = NCONF_load(config, p, &errline);

crypto/libressl/apps/openssl/openssl.c

442

NCONF_free(config);

crypto/libressl/apps/openssl/openssl.c

443

config = NULL;

crypto/libressl/apps/openssl/openssl.c

446

NCONF_free(config);

crypto/libressl/apps/openssl/openssl.c

530

if (config != NULL) {

crypto/libressl/apps/openssl/openssl.c

531

NCONF_free(config);

crypto/libressl/apps/openssl/openssl.c

532

config = NULL;

crypto/libressl/apps/openssl/req.c

1100

if ((req_conf != NULL) && (req_conf != config))

crypto/libressl/apps/openssl/req.c

607

req_conf = config;

crypto/libressl/tls/tls.c

145

tls_config_set_error(struct tls_config *config, const char *fmt, ...)

crypto/libressl/tls/tls.c

153

rv = tls_error_vset(&config->error, errnum, fmt, ap);

crypto/libressl/tls/tls.c

160

tls_config_set_errorx(struct tls_config *config, const char *fmt, ...)

crypto/libressl/tls/tls.c

166

rv = tls_error_vset(&config->error, -1, fmt, ap);

crypto/libressl/tls/tls.c

254

tls_configure(struct tls *ctx, struct tls_config *config)

crypto/libressl/tls/tls.c

256

if (config == NULL)

crypto/libressl/tls/tls.c

257

config = tls_config_default;

crypto/libressl/tls/tls.c

259

pthread_mutex_lock(&config->mutex);

crypto/libressl/tls/tls.c

260

config->refcount++;

crypto/libressl/tls/tls.c

261

pthread_mutex_unlock(&config->mutex);

crypto/libressl/tls/tls.c

263

tls_config_free(ctx->config);

crypto/libressl/tls/tls.c

265

ctx->config = config;

crypto/libressl/tls/tls.c

266

ctx->keypair = config->keypair;

crypto/libressl/tls/tls.c

340

if (ctx->config->use_fake_private_key) {

crypto/libressl/tls/tls.c

352

tls_set_errorx(ctx, ctx->config->use_fake_private_key ?

crypto/libressl/tls/tls.c

362

if (ctx->config->use_fake_private_key) {

crypto/libressl/tls/tls.c

397

if (!ctx->config->skip_private_key_check)

crypto/libressl/tls/tls.c

412

if (ctx->config->sign_cb == NULL)

crypto/libressl/tls/tls.c

415

RSA_set_ex_data(rsa, 1, ctx->config) == 0 ||

crypto/libressl/tls/tls.c

427

if (ctx->config->sign_cb == NULL)

crypto/libressl/tls/tls.c

430

ECDSA_set_ex_data(eckey, 1, ctx->config) == 0 ||

crypto/libressl/tls/tls.c

486

if (!ctx->config->skip_private_key_check &&

crypto/libressl/tls/tls.c

516

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_0) == 0)

crypto/libressl/tls/tls.c

518

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_1) == 0)

crypto/libressl/tls/tls.c

520

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_2) == 0)

crypto/libressl/tls/tls.c

522

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_3) == 0)

crypto/libressl/tls/tls.c

525

if (ctx->config->alpn != NULL) {

crypto/libressl/tls/tls.c

526

if (SSL_CTX_set_alpn_protos(ssl_ctx, ctx->config->alpn,

crypto/libressl/tls/tls.c

527

ctx->config->alpn_len) != 0) {

crypto/libressl/tls/tls.c

533

if (ctx->config->ciphers != NULL) {

crypto/libressl/tls/tls.c

535

ctx->config->ciphers) != 1) {

crypto/libressl/tls/tls.c

541

if (ctx->config->verify_time == 0) {

crypto/libressl/tls/tls.c

562

if (ctx->config->verify_cert == 0)

crypto/libressl/tls/tls.c

583

size_t ca_len = ctx->config->ca_len;

crypto/libressl/tls/tls.c

584

char *ca_mem = ctx->config->ca_mem;

crypto/libressl/tls/tls.c

585

char *crl_mem = ctx->config->crl_mem;

crypto/libressl/tls/tls.c

586

size_t crl_len = ctx->config->crl_len;

crypto/libressl/tls/tls.c

598

if (ctx->config->verify_depth >= 0)

crypto/libressl/tls/tls.c

599

SSL_CTX_set_verify_depth(ssl_ctx, ctx->config->verify_depth);

crypto/libressl/tls/tls.c

601

if (ctx->config->verify_cert == 0)

crypto/libressl/tls/tls.c

605

if (ctx->config->ca_mem == NULL && ctx->config->ca_path == NULL) {

crypto/libressl/tls/tls.c

622

ctx->config->ca_path) != 1) {

crypto/libressl/tls/tls.c

682

tls_config_free(ctx->config);

crypto/libressl/tls/tls.c

683

ctx->config = NULL;

crypto/libressl/tls/tls_client.c

166

int sfd = ctx->config->session_fd;

crypto/libressl/tls/tls_client.c

224

int sfd = ctx->config->session_fd;

crypto/libressl/tls/tls_client.c

314

ctx->config->keypair, 0) != 0)

crypto/libressl/tls/tls_client.c

317

if (ctx->config->verify_name) {

crypto/libressl/tls/tls_client.c

327

if (ctx->config->ecdhecurves != NULL) {

crypto/libressl/tls/tls_client.c

328

if (SSL_CTX_set1_groups(ctx->ssl_ctx, ctx->config->ecdhecurves,

crypto/libressl/tls/tls_client.c

329

ctx->config->ecdhecurves_len) != 1) {

crypto/libressl/tls/tls_client.c

350

if (ctx->config->session_fd != -1) {

crypto/libressl/tls/tls_client.c

456

if (ctx->config->verify_name) {

crypto/libressl/tls/tls_client.c

473

if (ctx->config->session_fd != -1) {

crypto/libressl/tls/tls_config.c

100

config->refcount = 1;

crypto/libressl/tls/tls_config.c

101

config->session_fd = -1;

crypto/libressl/tls/tls_config.c

103

if ((config->keypair = tls_keypair_new()) == NULL)

crypto/libressl/tls/tls_config.c

109

if (tls_config_set_dheparams(config, "none") != 0)

crypto/libressl/tls/tls_config.c

111

if (tls_config_set_ecdhecurves(config, "default") != 0)

crypto/libressl/tls/tls_config.c

113

if (tls_config_set_ciphers(config, "secure") != 0)

crypto/libressl/tls/tls_config.c

116

if (tls_config_set_protocols(config, TLS_PROTOCOLS_DEFAULT) != 0)

crypto/libressl/tls/tls_config.c

118

if (tls_config_set_verify_depth(config, 6) != 0)

crypto/libressl/tls/tls_config.c

127

if (tls_config_set_session_id(config, sid, sizeof(sid)) != 0)

crypto/libressl/tls/tls_config.c

129

config->ticket_keyrev = arc4random();

crypto/libressl/tls/tls_config.c

130

config->ticket_autorekey = 1;

crypto/libressl/tls/tls_config.c

132

tls_config_prefer_ciphers_server(config);

crypto/libressl/tls/tls_config.c

134

tls_config_verify(config);

crypto/libressl/tls/tls_config.c

136

return (config);

crypto/libressl/tls/tls_config.c

139

tls_config_free(config);

crypto/libressl/tls/tls_config.c

153

tls_config_free(struct tls_config *config)

crypto/libressl/tls/tls_config.c

158

if (config == NULL)

crypto/libressl/tls/tls_config.c

161

pthread_mutex_lock(&config->mutex);

crypto/libressl/tls/tls_config.c

162

refcount = --config->refcount;

crypto/libressl/tls/tls_config.c

163

pthread_mutex_unlock(&config->mutex);

crypto/libressl/tls/tls_config.c

168

for (kp = config->keypair; kp != NULL; kp = nkp) {

crypto/libressl/tls/tls_config.c

173

free(config->error.msg);

crypto/libressl/tls/tls_config.c

175

free(config->alpn);

crypto/libressl/tls/tls_config.c

176

free((char *)config->ca_mem);

crypto/libressl/tls/tls_config.c

177

free((char *)config->ca_path);

crypto/libressl/tls/tls_config.c

178

free((char *)config->ciphers);

crypto/libressl/tls/tls_config.c

179

free((char *)config->crl_mem);

crypto/libressl/tls/tls_config.c

180

free(config->ecdhecurves);

crypto/libressl/tls/tls_config.c

182

pthread_mutex_destroy(&config->mutex);

crypto/libressl/tls/tls_config.c

184

free(config);

crypto/libressl/tls/tls_config.c

188

tls_config_keypair_add(struct tls_config *config, struct tls_keypair *keypair)

crypto/libressl/tls/tls_config.c

192

kp = config->keypair;

crypto/libressl/tls/tls_config.c

200

tls_config_error(struct tls_config *config)

crypto/libressl/tls/tls_config.c

202

return config->error.msg;

crypto/libressl/tls/tls_config.c

206

tls_config_clear_keys(struct tls_config *config)

crypto/libressl/tls/tls_config.c

210

for (kp = config->keypair; kp != NULL; kp = kp->next)

crypto/libressl/tls/tls_config.c

280

tls_config_parse_alpn(struct tls_config *config, const char *alpn,

crypto/libressl/tls/tls_config.c

293

tls_config_set_errorx(config, "alpn too large");

crypto/libressl/tls/tls_config.c

298

tls_config_set_errorx(config, "out of memory");

crypto/libressl/tls/tls_config.c

303

tls_config_set_errorx(config, "out of memory");

crypto/libressl/tls/tls_config.c

311

tls_config_set_errorx(config,

crypto/libressl/tls/tls_config.c

316

tls_config_set_errorx(config,

crypto/libressl/tls/tls_config.c

340

tls_config_set_alpn(struct tls_config *config, const char *alpn)

crypto/libressl/tls/tls_config.c

342

return tls_config_parse_alpn(config, alpn, &config->alpn,

crypto/libressl/tls/tls_config.c

343

&config->alpn_len);

crypto/libressl/tls/tls_config.c

347

tls_config_add_keypair_file_internal(struct tls_config *config,

crypto/libressl/tls/tls_config.c

354

if (tls_keypair_set_cert_file(keypair, &config->error, cert_file) != 0)

crypto/libressl/tls/tls_config.c

357

tls_keypair_set_key_file(keypair, &config->error, key_file) != 0)

crypto/libressl/tls/tls_config.c

360

tls_keypair_set_ocsp_staple_file(keypair, &config->error,

crypto/libressl/tls/tls_config.c

364

tls_config_keypair_add(config, keypair);

crypto/libressl/tls/tls_config.c

374

tls_config_add_keypair_mem_internal(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

382

if (tls_keypair_set_cert_mem(keypair, &config->error, cert, cert_len) != 0)

crypto/libressl/tls/tls_config.c

385

tls_keypair_set_key_mem(keypair, &config->error, key, key_len) != 0)

crypto/libressl/tls/tls_config.c

388

tls_keypair_set_ocsp_staple_mem(keypair, &config->error, staple,

crypto/libressl/tls/tls_config.c

392

tls_config_keypair_add(config, keypair);

crypto/libressl/tls/tls_config.c

402

tls_config_add_keypair_mem(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

405

return tls_config_add_keypair_mem_internal(config, cert, cert_len, key,

crypto/libressl/tls/tls_config.c

410

tls_config_add_keypair_file(struct tls_config *config,

crypto/libressl/tls/tls_config.c

413

return tls_config_add_keypair_file_internal(config, cert_file,

crypto/libressl/tls/tls_config.c

418

tls_config_add_keypair_ocsp_mem(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

422

return tls_config_add_keypair_mem_internal(config, cert, cert_len, key,

crypto/libressl/tls/tls_config.c

427

tls_config_add_keypair_ocsp_file(struct tls_config *config,

crypto/libressl/tls/tls_config.c

430

return tls_config_add_keypair_file_internal(config, cert_file,

crypto/libressl/tls/tls_config.c

435

tls_config_set_ca_file(struct tls_config *config, const char *ca_file)

crypto/libressl/tls/tls_config.c

437

return tls_config_load_file(&config->error, "CA", ca_file,

crypto/libressl/tls/tls_config.c

438

&config->ca_mem, &config->ca_len);

crypto/libressl/tls/tls_config.c

442

tls_config_set_ca_path(struct tls_config *config, const char *ca_path)

crypto/libressl/tls/tls_config.c

444

return tls_set_string(&config->ca_path, ca_path);

crypto/libressl/tls/tls_config.c

448

tls_config_set_ca_mem(struct tls_config *config, const uint8_t *ca, size_t len)

crypto/libressl/tls/tls_config.c

450

return tls_set_mem(&config->ca_mem, &config->ca_len, ca, len);

crypto/libressl/tls/tls_config.c

454

tls_config_set_cert_file(struct tls_config *config, const char *cert_file)

crypto/libressl/tls/tls_config.c

456

return tls_keypair_set_cert_file(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

461

tls_config_set_cert_mem(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

464

return tls_keypair_set_cert_mem(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

469

tls_config_set_ciphers(struct tls_config *config, const char *ciphers)

crypto/libressl/tls/tls_config.c

486

tls_config_set_errorx(config, "out of memory");

crypto/libressl/tls/tls_config.c

490

tls_config_set_errorx(config, "no ciphers for '%s'", ciphers);

crypto/libressl/tls/tls_config.c

495

return tls_set_string(&config->ciphers, ciphers);

crypto/libressl/tls/tls_config.c

503

tls_config_set_crl_file(struct tls_config *config, const char *crl_file)

crypto/libressl/tls/tls_config.c

505

return tls_config_load_file(&config->error, "CRL", crl_file,

crypto/libressl/tls/tls_config.c

506

&config->crl_mem, &config->crl_len);

crypto/libressl/tls/tls_config.c

510

tls_config_set_crl_mem(struct tls_config *config, const uint8_t *crl,

crypto/libressl/tls/tls_config.c

513

return tls_set_mem(&config->crl_mem, &config->crl_len, crl, len);

crypto/libressl/tls/tls_config.c

517

tls_config_set_dheparams(struct tls_config *config, const char *params)

crypto/libressl/tls/tls_config.c

528

tls_config_set_errorx(config, "invalid dhe param '%s'", params);

crypto/libressl/tls/tls_config.c

532

config->dheparams = keylen;

crypto/libressl/tls/tls_config.c

538

tls_config_set_ecdhecurve(struct tls_config *config, const char *curve)

crypto/libressl/tls/tls_config.c

545

tls_config_set_errorx(config, "invalid ecdhe curve '%s'",

crypto/libressl/tls/tls_config.c

550

return tls_config_set_ecdhecurves(config, curve);

crypto/libressl/tls/tls_config.c

554

tls_config_set_ecdhecurves(struct tls_config *config, const char *curves)

crypto/libressl/tls/tls_config.c

563

free(config->ecdhecurves);

crypto/libressl/tls/tls_config.c

564

config->ecdhecurves = NULL;

crypto/libressl/tls/tls_config.c

565

config->ecdhecurves_len = 0;

crypto/libressl/tls/tls_config.c

571

tls_config_set_errorx(config, "out of memory");

crypto/libressl/tls/tls_config.c

586

tls_config_set_errorx(config,

crypto/libressl/tls/tls_config.c

593

tls_config_set_errorx(config, "out of memory");

crypto/libressl/tls/tls_config.c

601

config->ecdhecurves = curves_list;

crypto/libressl/tls/tls_config.c

602

config->ecdhecurves_len = curves_num;

crypto/libressl/tls/tls_config.c

615

tls_config_set_key_file(struct tls_config *config, const char *key_file)

crypto/libressl/tls/tls_config.c

617

return tls_keypair_set_key_file(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

622

tls_config_set_key_mem(struct tls_config *config, const uint8_t *key,

crypto/libressl/tls/tls_config.c

625

return tls_keypair_set_key_mem(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

630

tls_config_set_keypair_file_internal(struct tls_config *config,

crypto/libressl/tls/tls_config.c

633

if (tls_config_set_cert_file(config, cert_file) != 0)

crypto/libressl/tls/tls_config.c

635

if (tls_config_set_key_file(config, key_file) != 0)

crypto/libressl/tls/tls_config.c

638

tls_config_set_ocsp_staple_file(config, ocsp_file) != 0)

crypto/libressl/tls/tls_config.c

645

tls_config_set_keypair_mem_internal(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

649

if (tls_config_set_cert_mem(config, cert, cert_len) != 0)

crypto/libressl/tls/tls_config.c

651

if (tls_config_set_key_mem(config, key, key_len) != 0)

crypto/libressl/tls/tls_config.c

654

(tls_config_set_ocsp_staple_mem(config, staple, staple_len) != 0))

crypto/libressl/tls/tls_config.c

661

tls_config_set_keypair_file(struct tls_config *config,

crypto/libressl/tls/tls_config.c

664

return tls_config_set_keypair_file_internal(config, cert_file, key_file,

crypto/libressl/tls/tls_config.c

669

tls_config_set_keypair_mem(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

672

return tls_config_set_keypair_mem_internal(config, cert, cert_len,

crypto/libressl/tls/tls_config.c

677

tls_config_set_keypair_ocsp_file(struct tls_config *config,

crypto/libressl/tls/tls_config.c

680

return tls_config_set_keypair_file_internal(config, cert_file, key_file,

crypto/libressl/tls/tls_config.c

685

tls_config_set_keypair_ocsp_mem(struct tls_config *config, const uint8_t *cert,

crypto/libressl/tls/tls_config.c

689

return tls_config_set_keypair_mem_internal(config, cert, cert_len,

crypto/libressl/tls/tls_config.c

695

tls_config_set_protocols(struct tls_config *config, uint32_t protocols)

crypto/libressl/tls/tls_config.c

697

config->protocols = protocols;

crypto/libressl/tls/tls_config.c

703

tls_config_set_session_fd(struct tls_config *config, int session_fd)

crypto/libressl/tls/tls_config.c

709

config->session_fd = session_fd;

crypto/libressl/tls/tls_config.c

714

tls_config_set_error(config, "failed to stat session file");

crypto/libressl/tls/tls_config.c

718

tls_config_set_errorx(config,

crypto/libressl/tls/tls_config.c

724

tls_config_set_errorx(config, "session file has incorrect "

crypto/libressl/tls/tls_config.c

730

tls_config_set_errorx(config, "session file has incorrect "

crypto/libressl/tls/tls_config.c

735

config->session_fd = session_fd;

crypto/libressl/tls/tls_config.c

741

tls_config_set_sign_cb(struct tls_config *config, tls_sign_cb cb, void *cb_arg)

crypto/libressl/tls/tls_config.c

743

config->use_fake_private_key = 1;

crypto/libressl/tls/tls_config.c

744

config->skip_private_key_check = 1;

crypto/libressl/tls/tls_config.c

745

config->sign_cb = cb;

crypto/libressl/tls/tls_config.c

746

config->sign_cb_arg = cb_arg;

crypto/libressl/tls/tls_config.c

752

tls_config_set_verify_depth(struct tls_config *config, int verify_depth)

crypto/libressl/tls/tls_config.c

754

config->verify_depth = verify_depth;

crypto/libressl/tls/tls_config.c

760

tls_config_prefer_ciphers_client(struct tls_config *config)

crypto/libressl/tls/tls_config.c

762

config->ciphers_server = 0;

crypto/libressl/tls/tls_config.c

766

tls_config_prefer_ciphers_server(struct tls_config *config)

crypto/libressl/tls/tls_config.c

768

config->ciphers_server = 1;

crypto/libressl/tls/tls_config.c

772

tls_config_insecure_noverifycert(struct tls_config *config)

crypto/libressl/tls/tls_config.c

774

config->verify_cert = 0;

crypto/libressl/tls/tls_config.c

778

tls_config_insecure_noverifyname(struct tls_config *config)

crypto/libressl/tls/tls_config.c

780

config->verify_name = 0;

crypto/libressl/tls/tls_config.c

784

tls_config_insecure_noverifytime(struct tls_config *config)

crypto/libressl/tls/tls_config.c

786

config->verify_time = 0;

crypto/libressl/tls/tls_config.c

790

tls_config_verify(struct tls_config *config)

crypto/libressl/tls/tls_config.c

792

config->verify_cert = 1;

crypto/libressl/tls/tls_config.c

793

config->verify_name = 1;

crypto/libressl/tls/tls_config.c

794

config->verify_time = 1;

crypto/libressl/tls/tls_config.c

798

tls_config_ocsp_require_stapling(struct tls_config *config)

crypto/libressl/tls/tls_config.c

800

config->ocsp_require_stapling = 1;

crypto/libressl/tls/tls_config.c

804

tls_config_verify_client(struct tls_config *config)

crypto/libressl/tls/tls_config.c

806

config->verify_client = 1;

crypto/libressl/tls/tls_config.c

810

tls_config_verify_client_optional(struct tls_config *config)

crypto/libressl/tls/tls_config.c

812

config->verify_client = 2;

crypto/libressl/tls/tls_config.c

816

tls_config_skip_private_key_check(struct tls_config *config)

crypto/libressl/tls/tls_config.c

818

config->skip_private_key_check = 1;

crypto/libressl/tls/tls_config.c

822

tls_config_use_fake_private_key(struct tls_config *config)

crypto/libressl/tls/tls_config.c

824

config->use_fake_private_key = 1;

crypto/libressl/tls/tls_config.c

825

config->skip_private_key_check = 1;

crypto/libressl/tls/tls_config.c

829

tls_config_set_ocsp_staple_file(struct tls_config *config, const char *staple_file)

crypto/libressl/tls/tls_config.c

831

return tls_keypair_set_ocsp_staple_file(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

836

tls_config_set_ocsp_staple_mem(struct tls_config *config, const uint8_t *staple,

crypto/libressl/tls/tls_config.c

839

return tls_keypair_set_ocsp_staple_mem(config->keypair, &config->error,

crypto/libressl/tls/tls_config.c

844

tls_config_set_session_id(struct tls_config *config,

crypto/libressl/tls/tls_config.c

848

tls_config_set_errorx(config, "session ID too large");

crypto/libressl/tls/tls_config.c

851

memset(config->session_id, 0, sizeof(config->session_id));

crypto/libressl/tls/tls_config.c

852

memcpy(config->session_id, session_id, len);

crypto/libressl/tls/tls_config.c

857

tls_config_set_session_lifetime(struct tls_config *config, int lifetime)

crypto/libressl/tls/tls_config.c

860

tls_config_set_errorx(config, "session lifetime too large");

crypto/libressl/tls/tls_config.c

864

tls_config_set_errorx(config, "session lifetime too small");

crypto/libressl/tls/tls_config.c

868

config->session_lifetime = lifetime;

crypto/libressl/tls/tls_config.c

873

tls_config_add_ticket_key(struct tls_config *config, uint32_t keyrev,

crypto/libressl/tls/tls_config.c

881

tls_config_set_errorx(config,

crypto/libressl/tls/tls_config.c

895

struct tls_ticket_key *tk = &config->ticket_keys[i];

crypto/libressl/tls/tls_config.c

905

tls_config_set_errorx(config, "ticket key already present");

crypto/libressl/tls/tls_config.c

909

memmove(&config->ticket_keys[1], &config->ticket_keys[0],

crypto/libressl/tls/tls_config.c

91

struct tls_config *config;

crypto/libressl/tls/tls_config.c

910

sizeof(config->ticket_keys) - sizeof(config->ticket_keys[0]));

crypto/libressl/tls/tls_config.c

911

config->ticket_keys[0] = newkey;

crypto/libressl/tls/tls_config.c

913

config->ticket_autorekey = 0;

crypto/libressl/tls/tls_config.c

919

tls_config_ticket_autorekey(struct tls_config *config)

crypto/libressl/tls/tls_config.c

925

rv = tls_config_add_ticket_key(config, config->ticket_keyrev++, key,

crypto/libressl/tls/tls_config.c

927

config->ticket_autorekey = 1;

crypto/libressl/tls/tls_config.c

94

if ((config = calloc(1, sizeof(*config))) == NULL)

crypto/libressl/tls/tls_config.c

97

if (pthread_mutex_init(&config->mutex, NULL) != 0)

crypto/libressl/tls/tls_internal.h

182

struct tls_config *config;

crypto/libressl/tls/tls_internal.h

254

int tls_config_ticket_autorekey(struct tls_config *config);

crypto/libressl/tls/tls_internal.h

324

void tls_config_skip_private_key_check(struct tls_config *config);

crypto/libressl/tls/tls_internal.h

325

void tls_config_use_fake_private_key(struct tls_config *config);

crypto/libressl/tls/tls_ocsp.c

318

if (ctx->config->ocsp_require_stapling) {

crypto/libressl/tls/tls_ocsp.c

329

if (ctx->config->verify_cert == 0 || ctx->config->verify_time == 0)

crypto/libressl/tls/tls_server.c

141

tls_server_ticket_key(struct tls_config *config, unsigned char *keyname)

crypto/libressl/tls/tls_server.c

148

if (config->ticket_autorekey == 1) {

crypto/libressl/tls/tls_server.c

149

if (now - 3 * (config->session_lifetime / 4) >

crypto/libressl/tls/tls_server.c

150

config->ticket_keys[0].time) {

crypto/libressl/tls/tls_server.c

151

if (tls_config_ticket_autorekey(config) == -1)

crypto/libressl/tls/tls_server.c

156

struct tls_ticket_key *tk = &config->ticket_keys[i];

crypto/libressl/tls/tls_server.c

157

if (now - config->session_lifetime > tk->time)

crypto/libressl/tls/tls_server.c

180

key = tls_server_ticket_key(tls_ctx->config, NULL);

crypto/libressl/tls/tls_server.c

201

key = tls_server_ticket_key(tls_ctx->config, keyname);

crypto/libressl/tls/tls_server.c

217

if (key != &tls_ctx->config->ticket_keys[0])

crypto/libressl/tls/tls_server.c

250

if (ctx->config->verify_client != 0) {

crypto/libressl/tls/tls_server.c

252

if (ctx->config->verify_client == 1)

crypto/libressl/tls/tls_server.c

258

if (ctx->config->alpn != NULL)

crypto/libressl/tls/tls_server.c

262

if (ctx->config->dheparams == -1)

crypto/libressl/tls/tls_server.c

264

else if (ctx->config->dheparams == 1024)

crypto/libressl/tls/tls_server.c

267

if (ctx->config->ecdhecurves != NULL) {

crypto/libressl/tls/tls_server.c

269

if (SSL_CTX_set1_groups(*ssl_ctx, ctx->config->ecdhecurves,

crypto/libressl/tls/tls_server.c

270

ctx->config->ecdhecurves_len) != 1) {

crypto/libressl/tls/tls_server.c

276

if (ctx->config->ciphers_server == 1)

crypto/libressl/tls/tls_server.c

284

if (ctx->config->session_lifetime > 0) {

crypto/libressl/tls/tls_server.c

286

SSL_CTX_set_timeout(*ssl_ctx, ctx->config->session_lifetime);

crypto/libressl/tls/tls_server.c

296

if (SSL_CTX_set_session_id_context(*ssl_ctx, ctx->config->session_id,

crypto/libressl/tls/tls_server.c

297

sizeof(ctx->config->session_id)) != 1) {

crypto/libressl/tls/tls_server.c

317

if (ctx->config->keypair->next == NULL)

crypto/libressl/tls/tls_server.c

322

for (kp = ctx->config->keypair->next; kp != NULL; kp = kp->next) {

crypto/libressl/tls/tls_server.c

346

ctx->config->keypair) == -1)

crypto/libressl/tls/tls_server.c

55

pthread_mutex_lock(&ctx->config->mutex);

crypto/libressl/tls/tls_server.c

56

ctx->config->refcount++;

crypto/libressl/tls/tls_server.c

57

pthread_mutex_unlock(&ctx->config->mutex);

crypto/libressl/tls/tls_server.c

59

conn_ctx->config = ctx->config;

crypto/libressl/tls/tls_server.c

60

conn_ctx->keypair = ctx->config->keypair;

crypto/libressl/tls/tls_server.c

72

ctx->config->alpn, ctx->config->alpn_len, in, inlen) ==

crypto/libressl/tls/tls_signer.c

312

struct tls_config *config;

crypto/libressl/tls/tls_signer.c

325

config = RSA_get_ex_data(rsa, 1);

crypto/libressl/tls/tls_signer.c

327

if (pubkey_hash == NULL || config == NULL)

crypto/libressl/tls/tls_signer.c

343

if (config->sign_cb(config->sign_cb_arg, pubkey_hash, from, from_len,

crypto/libressl/tls/tls_signer.c

387

struct tls_config *config;

crypto/libressl/tls/tls_signer.c

400

config = ECDSA_get_ex_data(eckey, 1);

crypto/libressl/tls/tls_signer.c

402

if (pubkey_hash == NULL || config == NULL)

crypto/libressl/tls/tls_signer.c

408

if (config->sign_cb(config->sign_cb_arg, pubkey_hash, dgst, dgst_len,

crypto/openssh/ssh.c

1099

config = optarg;

crypto/openssh/ssh.c

1338

config == NULL ? "" : " -F ",

crypto/openssh/ssh.c

1339

config == NULL ? "" : config,

crypto/openssh/ssh.c

146

char *config = NULL;

crypto/openssh/ssh.c

567

if (config != NULL) {

crypto/openssh/ssh.c

568

if (strcasecmp(config, "none") != 0 &&

crypto/openssh/ssh.c

569

!read_config_file(config, pw, host, host_name, &options,

crypto/openssh/ssh.c

573

"%.100s", config, strerror(errno));

games/hunt/huntd/conf.h

58

void config(void);

games/hunt/huntd/driver.c

100

config();

lib/libusb/libusb.h

436

int libusb_get_configuration(libusb_device_handle * devh, int *config);

lib/libusb/libusb.h

454

int libusb_get_active_config_descriptor(libusb_device * dev, struct libusb_config_descriptor **config);

lib/libusb/libusb.h

455

int libusb_get_config_descriptor(libusb_device * dev, uint8_t config_index, struct libusb_config_descriptor **config);

lib/libusb/libusb.h

456

int libusb_get_config_descriptor_by_value(libusb_device * dev, uint8_t bConfigurationValue, struct libusb_config_descriptor **config);

lib/libusb/libusb.h

457

void libusb_free_config_descriptor(struct libusb_config_descriptor *config);

lib/libusb/libusb01.c

459

usb_parse_configuration(struct usb_config_descriptor *config,

lib/libusb/libusb01.c

469

if ((buffer == NULL) || (config == NULL)) {

lib/libusb/libusb01.c

475

ps.b.currcfg = config;

lib/libusb/libusb01.c

518

if (dev->config == NULL) {

lib/libusb/libusb01.c

522

struct usb_config_descriptor *cf = &dev->config[c];

lib/libusb/libusb01.c

530

free(dev->config);

lib/libusb/libusb01.c

531

dev->config = NULL;

lib/libusb/libusb01.c

560

dev->config = malloc(size);

lib/libusb/libusb01.c

561

if (dev->config == NULL) {

lib/libusb/libusb01.c

565

memset(dev->config, 0, size);

lib/libusb/libusb01.c

576

usb_parse_configuration(dev->config + x, ptr);

lib/libusb/libusb01.c

739

if (dev->config == NULL) {

lib/libusb/libusb01.c

747

if ((dev->config + i)->bConfigurationValue ==

lib/libusb/libusb10.c

596

libusb_get_configuration(struct libusb20_device *pdev, int *config)

lib/libusb/libusb10.c

600

if (pdev == NULL || config == NULL)

lib/libusb/libusb10.c

607

*config = pconf->desc.bConfigurationValue;

lib/libusb/libusb10_desc.c

113

if (dev == NULL || config == NULL)

lib/libusb/libusb10_desc.c

116

*config = NULL;

lib/libusb/libusb10_desc.c

259

*config = pconfd;

lib/libusb/libusb10_desc.c

266

uint8_t bConfigurationValue, struct libusb_config_descriptor **config)

lib/libusb/libusb10_desc.c

273

if (dev == NULL || config == NULL)

lib/libusb/libusb10_desc.c

280

err = libusb_get_config_descriptor(dev, i, config);

lib/libusb/libusb10_desc.c

284

if ((*config)->bConfigurationValue == bConfigurationValue)

lib/libusb/libusb10_desc.c

287

libusb_free_config_descriptor(*config);

lib/libusb/libusb10_desc.c

290

*config = NULL;

lib/libusb/libusb10_desc.c

296

libusb_free_config_descriptor(struct libusb_config_descriptor *config)

lib/libusb/libusb10_desc.c

298

free(config);

lib/libusb/libusb10_desc.c

82

struct libusb_config_descriptor **config)

lib/libusb/libusb10_desc.c

90

return (libusb_get_config_descriptor(dev, config_index, config));

lib/libusb/libusb10_desc.c

95

struct libusb_config_descriptor **config)

lib/libusb/usb.h

235

struct usb_config_descriptor *config;

lib/libusb/usb.h

280

int usb_parse_configuration(struct usb_config_descriptor *config, uint8_t *buffer);

libexec/dma/conf.c

190

config.smarthost = data;

libexec/dma/conf.c

192

config.port = atoi(data);

libexec/dma/conf.c

194

config.aliases = data;

libexec/dma/conf.c

196

config.spooldir = data;

libexec/dma/conf.c

198

config.authpath= data;

libexec/dma/conf.c

200

config.certfile = data;

libexec/dma/conf.c

202

config.mailname = data;

libexec/dma/conf.c

217

config.masquerade_host = host;

libexec/dma/conf.c

218

config.masquerade_user = user;

libexec/dma/conf.c

220

config.features |= STARTTLS;

libexec/dma/conf.c

235

config.fingerprint = fingerprint;

libexec/dma/conf.c

237

config.features |= TLS_OPP;

libexec/dma/conf.c

239

config.features |= SECURETRANSFER;

libexec/dma/conf.c

241

config.features |= DEFER;

libexec/dma/conf.c

243

config.features |= INSECURE;

libexec/dma/conf.c

245

config.features |= FULLBOUNCE;

libexec/dma/conf.c

247

config.features |= NULLCLIENT;

libexec/dma/conf.c

254

if ((config.features & NULLCLIENT) && config.smarthost == NULL) {

libexec/dma/crypto.c

135

if (config.certfile != NULL) {

libexec/dma/crypto.c

136

error = init_cert_file(ctx, config.certfile);

libexec/dma/crypto.c

149

config.features |= NOSSL;

libexec/dma/crypto.c

169

config.features &= ~NOSSL;

libexec/dma/crypto.c

172

config.ssl = SSL_new(ctx);

libexec/dma/crypto.c

173

if (config.ssl == NULL) {

libexec/dma/crypto.c

180

SSL_set_connect_state(config.ssl);

libexec/dma/crypto.c

183

error = SSL_set_fd(config.ssl, fd);

libexec/dma/crypto.c

191

error = SSL_connect(config.ssl);

libexec/dma/crypto.c

199

cert = SSL_get_peer_certificate(config.ssl);

libexec/dma/crypto.c

205

if(config.fingerprint != NULL && verify_server_fingerprint(cert)) {

libexec/dma/crypto.c

96

if(memcmp(fingerprint, config.fingerprint, SHA256_DIGEST_LENGTH) != 0) {

libexec/dma/dma.c

106

if (config.masquerade_user) {

libexec/dma/dma.c

107

addr = config.masquerade_user;

libexec/dma/dma.c

119

if (config.masquerade_host)

libexec/dma/dma.c

120

from_host = config.masquerade_host;

libexec/dma/dma.c

142

yyin = fopen(config.aliases, "r");

libexec/dma/dma.c

214

if (strrchr(it->addr, '@') == NULL && (config.features & NULLCLIENT) == 0) {

libexec/dma/dma.c

581

if (config.authpath != NULL)

libexec/dma/dma.c

582

parse_authfile(config.authpath);

libexec/dma/dma.c

600

errlog(EX_SOFTWARE, "could not parse aliases file `%s'", config.aliases);

libexec/dma/dma.c

609

errlog(EX_CANTCREAT, "can not create temp file in `%s'", config.spooldir);

libexec/dma/dma.c

632

if (config.features & DEFER || queue_only)

libexec/dma/dma.c

79

struct config config = {

libexec/dma/dma.h

177

extern struct config config;

libexec/dma/mail.c

104

config.features & FULLBOUNCE ?

libexec/dma/mail.c

112

if (config.features & FULLBOUNCE) {

libexec/dma/net.c

100

while ((s = SSL_write(config.ssl, (const char*)cmd, len)) <= 0) {

libexec/dma/net.c

101

s = SSL_get_error(config.ssl, s);

libexec/dma/net.c

151

if (((config.features & SECURETRANSFER) != 0) &&

libexec/dma/net.c

152

(config.features & NOSSL) == 0) {

libexec/dma/net.c

153

if ((rlen = SSL_read(config.ssl, buff + len, sizeof(buff) - len)) == -1) {

libexec/dma/net.c

273

if ((config.features & INSECURE) != 0 ||

libexec/dma/net.c

274

(config.features & SECURETRANSFER) != 0) {

libexec/dma/net.c

349

if (config.ssl != NULL) {

libexec/dma/net.c

350

if (((config.features & SECURETRANSFER) != 0) &&

libexec/dma/net.c

351

((config.features & NOSSL) == 0))

libexec/dma/net.c

352

SSL_shutdown(config.ssl);

libexec/dma/net.c

353

SSL_free(config.ssl);

libexec/dma/net.c

500

if ((config.features & SECURETRANSFER) == 0 ||

libexec/dma/net.c

501

(config.features & STARTTLS) != 0) {

libexec/dma/net.c

502

config.features |= NOSSL;

libexec/dma/net.c

505

config.features &= ~NOSSL;

libexec/dma/net.c

508

if ((config.features & SECURETRANSFER) != 0) {

libexec/dma/net.c

509

error = smtp_init_crypto(fd, config.features, &features);

libexec/dma/net.c

515

if ((config.features & STARTTLS) == 0)

libexec/dma/net.c

630

if (config.smarthost != NULL) {

libexec/dma/net.c

631

host = config.smarthost;

libexec/dma/net.c

632

port = config.port;

libexec/dma/net.c

98

if (((config.features & SECURETRANSFER) != 0) &&

libexec/dma/net.c

99

((config.features & NOSSL) == 0)) {

libexec/dma/spool.c

249

if (asprintf(&it->queuefn, "%s/Q%s", config.spooldir, it->queueid) <= 0)

libexec/dma/spool.c

251

if (asprintf(&it->mailfn, "%s/M%s", config.spooldir, it->queueid) <= 0)

libexec/dma/spool.c

294

spooldir = opendir(config.spooldir);

libexec/dma/spool.c

305

if (asprintf(&queuefn, "%s/Q%s", config.spooldir, de->d_name + 1) < 0)

libexec/dma/spool.c

307

if (asprintf(&mailfn, "%s/M%s", config.spooldir, de->d_name + 1) < 0)

libexec/dma/spool.c

410

if (asprintf(&flushfn, "%s/%s", config.spooldir, SPOOL_FLUSHFILE) < 0)

libexec/dma/spool.c

434

if (asprintf(&flushfn, "%s/%s", config.spooldir, SPOOL_FLUSHFILE) < 0)

libexec/dma/spool.c

82

if (snprintf(fn, sizeof(fn), "%s/%s", config.spooldir, "tmp_XXXXXXXXXX") <= 0)

libexec/dma/util.c

67

if (config.mailname == NULL || !*config.mailname)

libexec/dma/util.c

70

if (config.mailname[0] == '/') {

libexec/dma/util.c

77

fp = fopen(config.mailname, "r");

libexec/dma/util.c

96

snprintf(name, sizeof(name), "%s", config.mailname);

sbin/devd/devd.cc

161

config cfg;

sbin/devd/devd.cc

180

event_proc::matches(config &c) const

sbin/devd/devd.cc

191

event_proc::run(config &c) const

sbin/devd/devd.cc

267

action::do_action(config &c)

sbin/devd/devd.cc

275

match::match(config &c, const char *var, const char *re) :

sbin/devd/devd.cc

289

match::do_match(config &c)

sbin/devd/devd.cc

316

media::media(config &, const char *var, const char *type)

sbin/devd/devd.cc

339

media::do_match(config &c)

sbin/devd/devd.cc

415

config::reset(void)

sbin/devd/devd.cc

426

config::parse_one_file(const char *fn)

sbin/devd/devd.cc

439

config::parse_files_in_dir(const char *dirname)

sbin/devd/devd.cc

470

config::sort_vector(vector<event_proc *> &v)

sbin/devd/devd.cc

476

config::parse(void)

sbin/devd/devd.cc

490

config::open_pidfile()

sbin/devd/devd.cc

505

config::write_pidfile()

sbin/devd/devd.cc

512

config::close_pidfile()

sbin/devd/devd.cc

519

config::remove_pidfile()

sbin/devd/devd.cc

526

config::add_attach(int prio, event_proc *p)

sbin/devd/devd.cc

533

config::add_detach(int prio, event_proc *p)

sbin/devd/devd.cc

540

config::add_directory(const char *dir)

sbin/devd/devd.cc

546

config::add_nomatch(int prio, event_proc *p)

sbin/devd/devd.cc

553

config::add_notify(int prio, event_proc *p)

sbin/devd/devd.cc

560

config::set_pidfile(const char *fn)

sbin/devd/devd.cc

566

config::push_var_table()

sbin/devd/devd.cc

576

config::pop_var_table()

sbin/devd/devd.cc

584

config::set_variable(const char *var, const char *val)

sbin/devd/devd.cc

590

config::get_variable(const string &var)

sbin/devd/devd.cc

602

config::is_id_char(char ch) const

sbin/devd/devd.cc

609

config::expand_one(const char *&src, string &dst)

sbin/devd/devd.cc

653

config::expand_string(const char *src, const char *prepend, const char *append)

sbin/devd/devd.cc

685

config::chop_var(char *&buffer, char *&lhs, char *&rhs) const

sbin/devd/devd.cc

722

config::set_vars(char *buffer)

sbin/devd/devd.cc

736

config::find_and_execute(char type)

sbin/devd/devd.hh

103

media(config &, const char *var, const char *type);

sbin/devd/devd.hh

105

virtual bool do_match(config &);

sbin/devd/devd.hh

106

virtual bool do_action(config &) { return true; }

sbin/devd/devd.hh

120

virtual bool do_match(config &) { return true; }

sbin/devd/devd.hh

121

virtual bool do_action(config &);

sbin/devd/devd.hh

134

bool matches(config &) const;

sbin/devd/devd.hh

135

bool run(config &) const;

sbin/devd/devd.hh

32

class config;

sbin/devd/devd.hh

72

virtual bool do_match(config &) = 0;

sbin/devd/devd.hh

75

virtual bool do_action(config &) = 0;

sbin/devd/devd.hh

85

match(config &, const char *var, const char *re);

sbin/devd/devd.hh

87

virtual bool do_match(config &);

sbin/devd/devd.hh

88

virtual bool do_action(config &) { return true; }

sbin/devd/parse.y

64

: config

sbin/devd/parse.y

65

| config_list config

sbin/devd/parse.y

68

config

sbin/dhclient/clparse.c

164

parse_option_decl(cfile, &config->send_options[0]);

sbin/dhclient/clparse.c

167

code = parse_option_decl(cfile, &config->defaults[0]);

sbin/dhclient/clparse.c

169

config->default_actions[code] = ACTION_DEFAULT;

sbin/dhclient/clparse.c

172

code = parse_option_decl(cfile, &config->defaults[0]);

sbin/dhclient/clparse.c

174

config->default_actions[code] = ACTION_SUPERSEDE;

sbin/dhclient/clparse.c

179

config->default_actions[ignorelist[i]] = ACTION_IGNORE;

sbin/dhclient/clparse.c

182

code = parse_option_decl(cfile, &config->defaults[0]);

sbin/dhclient/clparse.c

184

config->default_actions[code] = ACTION_APPEND;

sbin/dhclient/clparse.c

187

code = parse_option_decl(cfile, &config->defaults[0]);

sbin/dhclient/clparse.c

189

config->default_actions[code] = ACTION_PREPEND;

sbin/dhclient/clparse.c

198

config->requested_option_count =

sbin/dhclient/clparse.c

199

parse_option_list(cfile, config->requested_options);

sbin/dhclient/clparse.c

202

memset(config->required_options, 0,

sbin/dhclient/clparse.c

203

sizeof(config->required_options));

sbin/dhclient/clparse.c

204

parse_option_list(cfile, config->required_options);

sbin/dhclient/clparse.c

207

parse_lease_time(cfile, &config->link_timeout);

sbin/dhclient/clparse.c

210

parse_lease_time(cfile, &config->timeout);

sbin/dhclient/clparse.c

213

parse_lease_time(cfile, &config->retry_interval);

sbin/dhclient/clparse.c

216

parse_lease_time(cfile, &config->select_interval);

sbin/dhclient/clparse.c

219

parse_lease_time(cfile, &config->reboot_timeout);

sbin/dhclient/clparse.c

222

parse_lease_time(cfile, &config->backoff_cutoff);

sbin/dhclient/clparse.c

225

parse_lease_time(cfile, &config->initial_interval);

sbin/dhclient/clparse.c

228

config->script_name = parse_string(cfile);

sbin/dhclient/clparse.c

61

config->link_timeout = 30;

sbin/dhclient/clparse.c

62

config->timeout = 60;

sbin/dhclient/clparse.c

63

config->select_interval = 0;

sbin/dhclient/clparse.c

64

config->reboot_timeout = 10;

sbin/dhclient/clparse.c

65

config->retry_interval = 300;

sbin/dhclient/clparse.c

66

config->backoff_cutoff = 15;

sbin/dhclient/clparse.c

67

config->initial_interval = 3;

sbin/dhclient/clparse.c

68

config->bootp_policy = ACCEPT;

sbin/dhclient/clparse.c

69

config->script_name = _PATH_DHCLIENT_SCRIPT;

sbin/dhclient/clparse.c

70

config->requested_options

sbin/dhclient/clparse.c

71

[config->requested_option_count++] = DHO_SUBNET_MASK;

sbin/dhclient/clparse.c

72

config->requested_options

sbin/dhclient/clparse.c

73

[config->requested_option_count++] = DHO_BROADCAST_ADDRESS;

sbin/dhclient/clparse.c

739

list->next = config->reject_list;

sbin/dhclient/clparse.c

74

config->requested_options

sbin/dhclient/clparse.c

740

config->reject_list = list;

sbin/dhclient/clparse.c

75

[config->requested_option_count++] = DHO_TIME_OFFSET;

sbin/dhclient/clparse.c

76

config->requested_options

sbin/dhclient/clparse.c

77

[config->requested_option_count++] = DHO_CLASSLESS_ROUTES;

sbin/dhclient/clparse.c

78

config->requested_options

sbin/dhclient/clparse.c

79

[config->requested_option_count++] = DHO_ROUTERS;

sbin/dhclient/clparse.c

80

config->requested_options

sbin/dhclient/clparse.c

81

[config->requested_option_count++] = DHO_DOMAIN_NAME;

sbin/dhclient/clparse.c

82

config->requested_options

sbin/dhclient/clparse.c

83

[config->requested_option_count++] = DHO_DOMAIN_NAME_SERVERS;

sbin/dhclient/clparse.c

84

config->requested_options

sbin/dhclient/clparse.c

85

[config->requested_option_count++] = DHO_HOST_NAME;

sbin/dhclient/dhclient.c

1006

client->interval = config->initial_interval;

sbin/dhclient/dhclient.c

1013

if (client->interval > config->backoff_cutoff)

sbin/dhclient/dhclient.c

1014

client->interval = ((config->backoff_cutoff / 2)

sbin/dhclient/dhclient.c

1016

config->backoff_cutoff));

sbin/dhclient/dhclient.c

1018

client->interval = config->initial_interval;

sbin/dhclient/dhclient.c

1023

client->first_sending + config->timeout)

sbin/dhclient/dhclient.c

1025

config->timeout) - cur_time + 1;

sbin/dhclient/dhclient.c

1128

set_timeout_interval(config->retry_interval, state_init);

sbin/dhclient/dhclient.c

1156

interval > config->reboot_timeout) {

sbin/dhclient/dhclient.c

1179

client->interval = config->initial_interval;

sbin/dhclient/dhclient.c

1185

if (client->interval > config->backoff_cutoff)

sbin/dhclient/dhclient.c

1186

client->interval = ((config->backoff_cutoff / 2) +

sbin/dhclient/dhclient.c

1259

options[i].data = config->requested_options;

sbin/dhclient/dhclient.c

1260

options[i].len = config->requested_option_count;

sbin/dhclient/dhclient.c

1274

config->send_options[i].data) {

sbin/dhclient/dhclient.c

1275

options[i].data = config->send_options[i].data;

sbin/dhclient/dhclient.c

1276

options[i].len = config->send_options[i].len;

sbin/dhclient/dhclient.c

1320

options[i].data = config->requested_options;

sbin/dhclient/dhclient.c

1321

options[i].len = config->requested_option_count;

sbin/dhclient/dhclient.c

1342

if (!options[i].data && config->send_options[i].data) {

sbin/dhclient/dhclient.c

1343

options[i].data = config->send_options[i].data;

sbin/dhclient/dhclient.c

1344

options[i].len = config->send_options[i].len;

sbin/dhclient/dhclient.c

1409

if (config->send_options[i].len) {

sbin/dhclient/dhclient.c

1410

options[i].data = config->send_options[i].data;

sbin/dhclient/dhclient.c

1411

options[i].len = config->send_options[i].len;

sbin/dhclient/dhclient.c

1609

switch (config->default_actions[i]) {

sbin/dhclient/dhclient.c

1618

else if (config->defaults[i].len)

sbin/dhclient/dhclient.c

1620

pretty_print_option(i, &config->defaults[i],

sbin/dhclient/dhclient.c

1625

if (config->defaults[i].len)

sbin/dhclient/dhclient.c

1627

pretty_print_option(i, &config->defaults[i],

sbin/dhclient/dhclient.c

1632

o.len = config->defaults[i].len + lease->options[i].len;

sbin/dhclient/dhclient.c

1637

config->defaults[i].data,

sbin/dhclient/dhclient.c

1639

memcpy(o.data, config->defaults[i].data,

sbin/dhclient/dhclient.c

1640

config->defaults[i].len);

sbin/dhclient/dhclient.c

1641

memcpy(o.data + config->defaults[i].len,

sbin/dhclient/dhclient.c

1651

o.len = config->defaults[i].len + lease->options[i].len;

sbin/dhclient/dhclient.c

1656

config->defaults[i].data,

sbin/dhclient/dhclient.c

1661

config->defaults[i].data,

sbin/dhclient/dhclient.c

1662

config->defaults[i].len);

sbin/dhclient/dhclient.c

1757

scriptName = config->script_name;

sbin/dhclient/dhclient.c

400

config = calloc(1, sizeof(*config));

sbin/dhclient/dhclient.c

401

if (config == NULL)

sbin/dhclient/dhclient.c

438

if (++i > config->link_timeout) {

sbin/dhclient/dhclient.c

805

for (i = 0; config->required_options[i]; i++) {

sbin/dhclient/dhclient.c

806

if (!options[config->required_options[i]].len) {

sbin/dhclient/dhclient.c

844

stop_selecting = client->first_sending + config->select_interval;

sbin/dhclient/dhclient.c

89

struct client_config *config;

sbin/dhclient/dhclient.c

992

if (interval > config->timeout) {

sbin/dhclient/dhcpd.h

205

extern struct client_config *config;

sbin/dhclient/options.c

532

for (ap = config->reject_list; ap && handler; ap = ap->next)

sbin/hammer/cmd_cleanup.c

149

struct hammer_ioc_config config;

sbin/hammer/cmd_cleanup.c

201

bzero(&config, sizeof(config));

sbin/hammer/cmd_cleanup.c

203

if (ioctl(fd, HAMMERIOC_GET_CONFIG, &config) == 0 &&

sbin/hammer/cmd_cleanup.c

204

config.head.error == 0) {

sbin/hammer/cmd_cleanup.c

272

migrate_config(fp, &config);

sbin/hammer/cmd_cleanup.c

275

if (ioctl(fd, HAMMERIOC_SET_CONFIG, &config) < 0) {

sbin/hammer/cmd_cleanup.c

282

config_init(path, &config);

sbin/hammer/cmd_cleanup.c

283

if (ioctl(fd, HAMMERIOC_SET_CONFIG, &config) < 0) {

sbin/hammer/cmd_cleanup.c

308

config_init(path, &config);

sbin/hammer/cmd_cleanup.c

311

fwrite(config.config.text, 1,

sbin/hammer/cmd_cleanup.c

312

strlen(config.config.text), fp);

sbin/hammer/cmd_cleanup.c

316

migrate_config(fp, &config);

sbin/hammer/cmd_cleanup.c

400

cbase = config.config.text;

sbin/hammer/cmd_cleanup.c

552

config_init(const char *path, struct hammer_ioc_config *config)

sbin/hammer/cmd_cleanup.c

563

bzero(config->config.text, sizeof(config->config.text));

sbin/hammer/cmd_cleanup.c

564

snprintf(config->config.text, sizeof(config->config.text) - 1, "%s%s",

sbin/hammer/cmd_cleanup.c

579

migrate_config(FILE *fp, struct hammer_ioc_config *config)

sbin/hammer/cmd_cleanup.c

583

n = fread(config->config.text, 1, sizeof(config->config.text) - 1, fp);

sbin/hammer/cmd_cleanup.c

585

bzero(config->config.text + n, sizeof(config->config.text) - n);

sbin/hammer/cmd_cleanup.c

71

static void config_init(const char *path, struct hammer_ioc_config *config);

sbin/hammer/cmd_cleanup.c

72

static void migrate_config(FILE *fp, struct hammer_ioc_config *config);

sbin/hammer/cmd_config.c

104

struct hammer_ioc_config config;

sbin/hammer/cmd_config.c

121

config_get(dirpath, &config);

sbin/hammer/cmd_config.c

122

if (config.head.error == ENOENT) {

sbin/hammer/cmd_config.c

123

snprintf(config.config.text, sizeof(config.config.text),

sbin/hammer/cmd_config.c

134

config.head.error = 0;

sbin/hammer/cmd_config.c

136

if (config.head.error) {

sbin/hammer/cmd_config.c

138

strerror(config.head.error));

sbin/hammer/cmd_config.c

157

write(fd, config.config.text, strlen(config.config.text));

sbin/hammer/cmd_config.c

193

n = read(fd, config.config.text, sizeof(config.config.text) - 1);

sbin/hammer/cmd_config.c

198

if (n == sizeof(config.config.text) - 1) {

sbin/hammer/cmd_config.c

200

sizeof(config.config.text) - 1);

sbin/hammer/cmd_config.c

203

bzero(config.config.text + n, sizeof(config.config.text) - n);

sbin/hammer/cmd_config.c

204

config_set(dirpath, &config);

sbin/hammer/cmd_config.c

211

config_get(const char *dirpath, struct hammer_ioc_config *config)

sbin/hammer/cmd_config.c

226

if (ioctl(fd, HAMMERIOC_GET_CONFIG, config) < 0) {

sbin/hammer/cmd_config.c

235

config_set(const char *dirpath, struct hammer_ioc_config *config)

sbin/hammer/cmd_config.c

250

if (ioctl(fd, HAMMERIOC_SET_CONFIG, config) < 0) {

sbin/hammer/cmd_config.c

37

static void config_get(const char *dirpath, struct hammer_ioc_config *config);

sbin/hammer/cmd_config.c

38

static void config_set(const char *dirpath, struct hammer_ioc_config *config);

sbin/hammer/cmd_config.c

52

struct hammer_ioc_config config;

sbin/hammer/cmd_config.c

57

bzero(&config, sizeof(config));

sbin/hammer/cmd_config.c

59

config_get(".", &config);

sbin/hammer/cmd_config.c

60

if (config.head.error == 0) {

sbin/hammer/cmd_config.c

61

printf("%s", config.config.text);

sbin/hammer/cmd_config.c

70

config_get(dirpath, &config);

sbin/hammer/cmd_config.c

71

if (config.head.error == 0) {

sbin/hammer/cmd_config.c

72

printf("%s", config.config.text);

sbin/hammer/cmd_config.c

79

config_get(dirpath, &config); /* ignore errors */

sbin/hammer/cmd_config.c

80

config.head.error = 0;

sbin/hammer/cmd_config.c

87

n = read(fd, config.config.text, sizeof(config.config.text) - 1);

sbin/hammer/cmd_config.c

88

if (n == sizeof(config.config.text) - 1) {

sbin/hammer/cmd_config.c

90

sizeof(config.config.text) - 1);

sbin/hammer/cmd_config.c

93

bzero(config.config.text + n, sizeof(config.config.text) - n);

sbin/hammer/cmd_config.c

94

config_set(dirpath, &config);

sbin/hammer/cmd_show.c

841

char *p = strdup(data->config.text);

sbin/hammer2/zlib/hammer2_zlib_deflate.c

130

local const config configuration_table[10] = {

sbin/natacontrol/natacontrol.c

516

struct ata_ioc_raid_config config;

sbin/natacontrol/natacontrol.c

518

bzero(&config, sizeof(config));

sbin/natacontrol/natacontrol.c

522

config.type = AR_RAID0;

sbin/natacontrol/natacontrol.c

525

config.type = AR_RAID1;

sbin/natacontrol/natacontrol.c

528

config.type = AR_RAID01;

sbin/natacontrol/natacontrol.c

530

config.type = AR_RAID5;

sbin/natacontrol/natacontrol.c

532

config.type = AR_SPAN;

sbin/natacontrol/natacontrol.c

534

config.type = AR_JBOD;

sbin/natacontrol/natacontrol.c

536

if (!config.type) {

sbin/natacontrol/natacontrol.c

546

if (config.type == AR_RAID0 ||

sbin/natacontrol/natacontrol.c

547

config.type == AR_RAID01 ||

sbin/natacontrol/natacontrol.c

548

config.type == AR_RAID5) {

sbin/natacontrol/natacontrol.c

550

sscanf(argv[3], "%d", &config.interleave) != 1) {

sbin/natacontrol/natacontrol.c

568

config.disks[disk] = dev;

sbin/natacontrol/natacontrol.c

571

if ((config.type == AR_RAID1 || config.type == AR_RAID01) &&

sbin/natacontrol/natacontrol.c

578

config.total_disks = disk;

sbin/natacontrol/natacontrol.c

579

if (ioctl(fd, IOCATARAIDCREATE, &config) < 0)

sbin/natacontrol/natacontrol.c

582

printf("ar%d created\n", config.lun);

sbin/natacontrol/natacontrol.c

592

struct ata_ioc_raid_config config;

sbin/natacontrol/natacontrol.c

594

config.lun = ar_arg(argv[2]);

sbin/natacontrol/natacontrol.c

595

if (!(sscanf(argv[3], "ad%d", &config.disks[0]) == 1)) {

sbin/natacontrol/natacontrol.c

600

if (ioctl(fd, IOCATARAIDADDSPARE, &config) < 0)

sys/bus/isa/isa_common.c

112

struct isa_config *config,

sys/bus/isa/isa_common.c

127

result->ic_nmem = config->ic_nmem;

sys/bus/isa/isa_common.c

128

for (i = 0; i < config->ic_nmem; i++) {

sys/bus/isa/isa_common.c

130

for (start = config->ic_mem[i].ir_start,

sys/bus/isa/isa_common.c

131

end = config->ic_mem[i].ir_end,

sys/bus/isa/isa_common.c

132

size = config->ic_mem[i].ir_size,

sys/bus/isa/isa_common.c

133

align = config->ic_mem[i].ir_align;

sys/bus/isa/isa_common.c

176

struct isa_config *config,

sys/bus/isa/isa_common.c

191

result->ic_nport = config->ic_nport;

sys/bus/isa/isa_common.c

192

for (i = 0; i < config->ic_nport; i++) {

sys/bus/isa/isa_common.c

194

for (start = config->ic_port[i].ir_start,

sys/bus/isa/isa_common.c

195

end = config->ic_port[i].ir_end,

sys/bus/isa/isa_common.c

196

size = config->ic_port[i].ir_size,

sys/bus/isa/isa_common.c

197

align = config->ic_port[i].ir_align;

sys/bus/isa/isa_common.c

263

struct isa_config *config,

sys/bus/isa/isa_common.c

278

result->ic_nirq = config->ic_nirq;

sys/bus/isa/isa_common.c

279

for (i = 0; i < config->ic_nirq; i++) {

sys/bus/isa/isa_common.c

280

u_int32_t mask = config->ic_irqmask[i];

sys/bus/isa/isa_common.c

322

struct isa_config *config,

sys/bus/isa/isa_common.c

337

result->ic_ndrq = config->ic_ndrq;

sys/bus/isa/isa_common.c

338

for (i = 0; i < config->ic_ndrq; i++) {

sys/bus/isa/isa_common.c

339

u_int32_t mask = config->ic_drqmask[i];

sys/bus/isa/isa_common.c

383

struct isa_config config;

sys/bus/isa/isa_common.c

386

bzero(&config, sizeof config);

sys/bus/isa/isa_common.c

389

if (!isa_find_memory(child, &ice->ice_config, &config))

sys/bus/isa/isa_common.c

392

if (!isa_find_port(child, &ice->ice_config, &config))

sys/bus/isa/isa_common.c

395

if (!isa_find_irq(child, &ice->ice_config, &config))

sys/bus/isa/isa_common.c

398

if (!isa_find_drq(child, &ice->ice_config, &config))

sys/bus/isa/isa_common.c

408

&config, 1);

sys/bus/isa/isa_common.c

420

bzero(&config, sizeof config);

sys/bus/isa/isa_common.c

422

idev->id_config_cb(idev->id_config_arg, &config, 0);

sys/bus/isa/isa_common.c

457

struct isa_config config;

sys/bus/isa/isa_common.c

459

bzero(&config, sizeof config);

sys/bus/isa/isa_common.c

461

idev->id_config_cb(idev->id_config_arg, &config, 0);

sys/bus/isa/isa_common.c

940

int priority, struct isa_config *config)

sys/bus/isa/isa_common.c

947

newice->ice_config = *config;

sys/bus/isa/isavar.h

36

typedef void isa_config_cb(void *arg, struct isa_config *config, int enable);

sys/bus/isa/pnp.c

236

pnp_set_config(void *arg, struct isa_config *config, int enable)

sys/bus/isa/pnp.c

257

for (i = 0; i < config->ic_nmem; i++) {

sys/bus/isa/pnp.c

258

u_int32_t start = config->ic_mem[i].ir_start;

sys/bus/isa/pnp.c

259

u_int32_t size = config->ic_mem[i].ir_size;

sys/bus/isa/pnp.c

274

for (i = 0; i < config->ic_nport; i++) {

sys/bus/isa/pnp.c

275

u_int32_t start = config->ic_port[i].ir_start;

sys/bus/isa/pnp.c

284

for (i = 0; i < config->ic_nirq; i++) {

sys/bus/isa/pnp.c

285

int irq = ffs(config->ic_irqmask[i]) - 1;

sys/bus/isa/pnp.c

297

for (i = 0; i < config->ic_ndrq; i++) {

sys/bus/isa/pnp.c

298

int drq = ffs(config->ic_drqmask[i]) - 1;

sys/bus/isa/pnp.c

322

int ldn, struct isa_config *config)

sys/bus/isa/pnp.c

336

if (config == NULL)

sys/bus/isa/pnp.c

339

config->ic_nport++;

sys/bus/isa/pnp.c

340

config->ic_port[config->ic_nport - 1] = config->ic_port[0];

sys/bus/isa/pnp.c

341

config->ic_port[config->ic_nport - 1].ir_start += qp->arg1;

sys/bus/isa/pnp.c

342

config->ic_port[config->ic_nport - 1].ir_end += qp->arg1;

sys/bus/isa/pnp.c

345

config->ic_nport++;

sys/bus/isa/pnp.c

346

config->ic_port[config->ic_nport - 1] = config->ic_port[0];

sys/bus/isa/pnp.c

347

config->ic_port[config->ic_nport - 1].ir_start += qp->arg2;

sys/bus/isa/pnp.c

348

config->ic_port[config->ic_nport - 1].ir_end += qp->arg2;

sys/bus/isa/pnpparse.c

101

if (config->ic_nirq == ISA_NIRQ) {

sys/bus/isa/pnpparse.c

107

config->ic_irqmask[config->ic_nirq] = 0;

sys/bus/isa/pnpparse.c

108

config->ic_nirq++;

sys/bus/isa/pnpparse.c

114

config->ic_irqmask[config->ic_nirq] = I16(res);

sys/bus/isa/pnpparse.c

115

config->ic_nirq++;

sys/bus/isa/pnpparse.c

119

if (config->ic_ndrq == ISA_NDRQ) {

sys/bus/isa/pnpparse.c

125

config->ic_drqmask[config->ic_ndrq] = 0;

sys/bus/isa/pnpparse.c

126

config->ic_ndrq++;

sys/bus/isa/pnpparse.c

132

config->ic_drqmask[config->ic_ndrq] = res[0];

sys/bus/isa/pnpparse.c

133

config->ic_ndrq++;

sys/bus/isa/pnpparse.c

137

if (config->ic_nport == ISA_NPORT) {

sys/bus/isa/pnpparse.c

143

config->ic_port[config->ic_nport].ir_start = 0;

sys/bus/isa/pnpparse.c

144

config->ic_port[config->ic_nport].ir_end = 0;

sys/bus/isa/pnpparse.c

145

config->ic_port[config->ic_nport].ir_size = 0;

sys/bus/isa/pnpparse.c

146

config->ic_port[config->ic_nport].ir_align = 0;

sys/bus/isa/pnpparse.c

147

config->ic_nport++;

sys/bus/isa/pnpparse.c

158

config->ic_port[config->ic_nport].ir_start =

sys/bus/isa/pnpparse.c

160

config->ic_port[config->ic_nport].ir_end =

sys/bus/isa/pnpparse.c

162

config->ic_port[config->ic_nport].ir_size = res[6];

sys/bus/isa/pnpparse.c

167

config->ic_port[config->ic_nport].ir_align = res[5];

sys/bus/isa/pnpparse.c

168

config->ic_nport++;

sys/bus/isa/pnpparse.c

170

isa_get_logicalid(dev), ldn, config);

sys/bus/isa/pnpparse.c

174

if (config->ic_nport == ISA_NPORT) {

sys/bus/isa/pnpparse.c

180

config->ic_port[config->ic_nport].ir_start = 0;

sys/bus/isa/pnpparse.c

181

config->ic_port[config->ic_nport].ir_end = 0;

sys/bus/isa/pnpparse.c

182

config->ic_port[config->ic_nport].ir_size = 0;

sys/bus/isa/pnpparse.c

183

config->ic_port[config->ic_nport].ir_align = 0;

sys/bus/isa/pnpparse.c

184

config->ic_nport++;

sys/bus/isa/pnpparse.c

195

config->ic_port[config->ic_nport].ir_start = I16(res);

sys/bus/isa/pnpparse.c

196

config->ic_port[config->ic_nport].ir_end =

sys/bus/isa/pnpparse.c

198

config->ic_port[config->ic_nport].ir_size = res[2];

sys/bus/isa/pnpparse.c

199

config->ic_port[config->ic_nport].ir_align = 1;

sys/bus/isa/pnpparse.c

200

config->ic_nport++;

sys/bus/isa/pnpparse.c

238

if (config->ic_nmem == ISA_NMEM) {

sys/bus/isa/pnpparse.c

244

config->ic_mem[config->ic_nmem].ir_start = 0;

sys/bus/isa/pnpparse.c

245

config->ic_mem[config->ic_nmem].ir_end = 0;

sys/bus/isa/pnpparse.c

246

config->ic_mem[config->ic_nmem].ir_size = 0;

sys/bus/isa/pnpparse.c

247

config->ic_mem[config->ic_nmem].ir_align = 0;

sys/bus/isa/pnpparse.c

248

config->ic_nmem++;

sys/bus/isa/pnpparse.c

260

config->ic_mem[config->ic_nmem].ir_start =

sys/bus/isa/pnpparse.c

262

config->ic_mem[config->ic_nmem].ir_end =

sys/bus/isa/pnpparse.c

264

config->ic_mem[config->ic_nmem].ir_size =

sys/bus/isa/pnpparse.c

266

config->ic_mem[config->ic_nmem].ir_align = I16(res + 5);

sys/bus/isa/pnpparse.c

267

if (!config->ic_mem[config->ic_nmem].ir_align)

sys/bus/isa/pnpparse.c

268

config->ic_mem[config->ic_nmem].ir_align =

sys/bus/isa/pnpparse.c

270

config->ic_nmem++;

sys/bus/isa/pnpparse.c

274

if (config->ic_nmem == ISA_NMEM) {

sys/bus/isa/pnpparse.c

280

config->ic_mem[config->ic_nmem].ir_start = 0;

sys/bus/isa/pnpparse.c

281

config->ic_mem[config->ic_nmem].ir_end = 0;

sys/bus/isa/pnpparse.c

282

config->ic_mem[config->ic_nmem].ir_size = 0;

sys/bus/isa/pnpparse.c

283

config->ic_mem[config->ic_nmem].ir_align = 0;

sys/bus/isa/pnpparse.c

284

config->ic_nmem++;

sys/bus/isa/pnpparse.c

295

config->ic_mem[config->ic_nmem].ir_start = I32(res + 1);

sys/bus/isa/pnpparse.c

296

config->ic_mem[config->ic_nmem].ir_end =

sys/bus/isa/pnpparse.c

298

config->ic_mem[config->ic_nmem].ir_size = I32(res + 13);

sys/bus/isa/pnpparse.c

299

config->ic_mem[config->ic_nmem].ir_align = I32(res + 9);

sys/bus/isa/pnpparse.c

300

config->ic_nmem++;

sys/bus/isa/pnpparse.c

304

if (config->ic_nmem == ISA_NMEM) {

sys/bus/isa/pnpparse.c

310

config->ic_mem[config->ic_nmem].ir_start = 0;

sys/bus/isa/pnpparse.c

311

config->ic_mem[config->ic_nmem].ir_end = 0;

sys/bus/isa/pnpparse.c

312

config->ic_mem[config->ic_nmem].ir_size = 0;

sys/bus/isa/pnpparse.c

313

config->ic_mem[config->ic_nmem].ir_align = 0;

sys/bus/isa/pnpparse.c

323

config->ic_mem[config->ic_nmem].ir_start = I32(res + 1);

sys/bus/isa/pnpparse.c

324

config->ic_mem[config->ic_nmem].ir_end =

sys/bus/isa/pnpparse.c

326

config->ic_mem[config->ic_nmem].ir_size = I32(res + 5);

sys/bus/isa/pnpparse.c

327

config->ic_mem[config->ic_nmem].ir_align = 1;

sys/bus/isa/pnpparse.c

328

config->ic_nmem++;

sys/bus/isa/pnpparse.c

348

struct isa_config *config, int ldn)

sys/bus/isa/pnpparse.c

352

res = pnp_scan_resources(dev, resources, len, config,

sys/bus/isa/pnpparse.c

411

struct isa_config *config;

sys/bus/isa/pnpparse.c

427

config = &configs[0];

sys/bus/isa/pnpparse.c

454

config);

sys/bus/isa/pnpparse.c

457

config, ldn);

sys/bus/isa/pnpparse.c

465

config = &configs[ncfgs];

sys/bus/isa/pnpparse.c

491

pnp_merge_resources(dev, &configs[0], config);

sys/bus/isa/pnpparse.c

493

config, ldn);

sys/bus/isa/pnpparse.c

502

config = &configs[0];

sys/bus/isa/pnpparse.c

503

bzero(config, sizeof(*config));

sys/bus/isa/pnpparse.c

518

if (pnp_parse_desc(dev, tag, p, l, config, ldn))

sys/bus/isa/pnpparse.c

538

pnp_parse_desc(dev, tag, p, l, config, ldn)) {

sys/bus/isa/pnpparse.c

568

struct isa_config *config, int ldn, pnp_scan_cb *cb)

sys/bus/isa/pnpparse.c

583

if ((*cb)(dev, tag, p, l, config, ldn))

sys/bus/isa/pnpparse.c

596

if ((*cb)(dev, tag, p, l, config, ldn))

sys/bus/isa/pnpparse.c

62

struct isa_config *config, int ldn)

sys/bus/isa/pnpvar.h

59

struct isa_config *config, int ldn);

sys/bus/isa/pnpvar.h

65

struct isa_config *config, int ldn);

sys/bus/isa/pnpvar.h

67

struct isa_config *config, int ldn, pnp_scan_cb *cb);

sys/bus/isa/pnpvar.h

69

void pnp_check_quirks(u_int32_t vendor_id, u_int32_t logical_id, int ldn, struct isa_config *config);

sys/bus/pci/vga_pci.c

120

config = pci_read_config(pcib, PCIR_BRIDGECTL_1, 2);

sys/bus/pci/vga_pci.c

121

if ((config & PCIB_BCR_VGA_ENABLE) == 0) {

sys/bus/pci/vga_pci.c

126

config = pci_read_config(dev, PCIR_COMMAND, 2);

sys/bus/pci/vga_pci.c

127

if ((config & (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN)) == 0) {

sys/bus/pci/vga_pci.c

136

pci_write_config(dev, PCIR_COMMAND, config | PCIM_CMD_INTxDIS, 2);

sys/bus/pci/vga_pci.c

170

uint16_t config;

sys/bus/pci/vga_pci.c

197

config = pci_read_config(pcib, PCIR_BRIDGECTL_1, 2);

sys/bus/pci/vga_pci.c

198

if ((config & PCIB_BCR_VGA_ENABLE) == 0) {

sys/bus/pci/vga_pci.c

199

config |= PCIB_BCR_VGA_ENABLE;

sys/bus/pci/vga_pci.c

200

pci_write_config(pcib, PCIR_BRIDGECTL_1, config, 2);

sys/bus/pci/vga_pci.c

82

uint16_t config;

sys/bus/u4b/serial/uvisor.c

371

uvisor_init(struct uvisor_softc *sc, struct usb_device *udev, struct usb_config *config)

sys/bus/u4b/serial/uvisor.c

454

config[0].endpoint = (port & 0xF); /* output */

sys/bus/u4b/serial/uvisor.c

455

config[1].endpoint = (port >> 4); /* input */

sys/bus/u4b/serial/uvisor.c

458

config[0].endpoint = (port & 0xF); /* output */

sys/bus/u4b/serial/uvisor.c

459

config[1].endpoint = (port & 0xF); /* input */

sys/dev/disk/ahci/atascsi.h

68

u_int16_t config; /* 0 */

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

150

dmirror_write(dm_target_crypt_config_t config, struct bio *bio)

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

157

for(i = 0; i < XXX config->ndisks; i++) {

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

158

disk = &config->disks[i];

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

215

if (retries < disk->config->max_retries) {

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

245

dmirror_read(dm_target_crypt_config_t config, struct bio *bio)

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

251

for(i = 0; i < XXX config->ndisks; i++) {

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

252

disk = &config->disks[i];

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

276

for (i = 0; i < config->ndisks; i++) {

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

277

disk = &config->disks[i];

sys/dev/disk/dm/dmirror/dm_target_dmirror.c

295

m_disk = &config->disks[i];

sys/dev/disk/nata/ata-all.c

659

if ((atadev->param.config & ATA_PROTO_ATAPI) &&

sys/dev/disk/nata/ata-all.c

660

(atadev->param.config != ATA_CFA_MAGIC1) &&

sys/dev/disk/nata/ata-all.c

661

(atadev->param.config != ATA_CFA_MAGIC2)) {

sys/dev/disk/nata/ata-all.c

663

(atadev->param.config & ATA_DRQ_MASK) != ATA_DRQ_INTR &&

sys/dev/disk/nata/ata-disk.c

95

if (!(atadev->param.config & ATA_PROTO_ATAPI) ||

sys/dev/disk/nata/ata-disk.c

96

(atadev->param.config == ATA_CFA_MAGIC1) ||

sys/dev/disk/nata/ata-disk.c

97

(atadev->param.config == ATA_CFA_MAGIC2) ||

sys/dev/disk/nata/ata-disk.c

98

(atadev->param.config == ATA_CFA_MAGIC3))

sys/dev/disk/nata/ata-lowlevel.c

348

(atadev->param.config &

sys/dev/disk/nata/ata-lowlevel.c

683

if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)

sys/dev/disk/nata/ata-lowlevel.c

707

(atadev->param.config & ATA_PROTO_MASK) ==

sys/dev/disk/nata/ata-queue.c

197

if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)

sys/dev/disk/nata/ata-raid.c

1033

ata_raid_create(struct ata_ioc_raid_config *config)

sys/dev/disk/nata/ata-raid.c

1051

for (disk = 0; disk < config->total_disks; disk++) {

sys/dev/disk/nata/ata-raid.c

1053

config->disks[disk]))) {

sys/dev/disk/nata/ata-raid.c

1058

config->disks[disk] = -1;

sys/dev/disk/nata/ata-raid.c

1148

config->disks[disk] = -1;

sys/dev/disk/nata/ata-raid.c

1154

if (total_disks != config->total_disks) {

sys/dev/disk/nata/ata-raid.c

1159

switch (config->type) {

sys/dev/disk/nata/ata-raid.c

1190

rdp->type = config->type;

sys/dev/disk/nata/ata-raid.c

1196

while (config->interleave >>= 1)

sys/dev/disk/nata/ata-raid.c

1265

for (disk = 0; disk < config->total_disks; disk++) {

sys/dev/disk/nata/ata-raid.c

1267

config->disks[disk]))) {

sys/dev/disk/nata/ata-raid.c

1276

config->lun = array;

sys/dev/disk/nata/ata-raid.c

1317

ata_raid_addspare(struct ata_ioc_raid_config *config)

sys/dev/disk/nata/ata-raid.c

1323

if (!(rdp = ata_raid_arrays[config->lun]))

sys/dev/disk/nata/ata-raid.c

1340

config->disks[0] ))) {

sys/dev/disk/nata/ata-raid.c

244

struct ata_ioc_raid_config *config = (struct ata_ioc_raid_config *)data;

sys/dev/disk/nata/ata-raid.c

254

error = ata_raid_create(config);

sys/dev/disk/nata/ata-raid.c

262

error = ata_raid_addspare(config);

sys/dev/disk/nata/ata-raid.c

88

static int ata_raid_create(struct ata_ioc_raid_config *config);

sys/dev/disk/nata/ata-raid.c

90

static int ata_raid_addspare(struct ata_ioc_raid_config *config);

sys/dev/disk/nata/atapi-cd.c

128

if ((atadev->param.config & ATA_PROTO_ATAPI) &&

sys/dev/disk/nata/atapi-cd.c

129

(atadev->param.config & ATA_ATAPI_TYPE_MASK) == ATA_ATAPI_TYPE_CDROM)

sys/dev/disk/nata/atapi-cd.c

894

(atadev->param.config & ATA_PROTO_MASK) ==

sys/dev/disk/nata/atapi-fd.c

291

(atadev->param.config & ATA_PROTO_MASK) ==

sys/dev/disk/nata/atapi-fd.c

90

if ((atadev->param.config & ATA_PROTO_ATAPI) &&

sys/dev/disk/nata/atapi-fd.c

91

(atadev->param.config & ATA_ATAPI_TYPE_MASK) == ATA_ATAPI_TYPE_DIRECT)

sys/dev/disk/nata/atapi-tape.c

103

if ((atadev->param.config & ATA_PROTO_ATAPI) &&

sys/dev/disk/nata/atapi-tape.c

104

(atadev->param.config & ATA_ATAPI_TYPE_MASK) == ATA_ATAPI_TYPE_TAPE)

sys/dev/disk/nata/atapi-tape.c

455

(atadev->param.config & ATA_PROTO_MASK) ==

sys/dev/disk/nata/chipsets/ata-siliconimage.c

528

if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)

sys/dev/disk/sili/atascsi.h

62

u_int16_t config; /* 0 */

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

424

cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

425

cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

426

cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

109

struct tile_config *config)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

113

config->gb_addr_config = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

114

config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

116

config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

119

config->tile_config_ptr = adev->gfx.config.tile_mode_array;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

120

config->num_tile_configs =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

121

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

122

config->macro_tile_config_ptr =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

123

adev->gfx.config.macrotile_mode_array;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

124

config->num_macro_tile_configs =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

125

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

152

struct tile_config *config)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

156

config->gb_addr_config = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

158

config->tile_config_ptr = adev->gfx.config.tile_mode_array;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

159

config->num_tile_configs =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

160

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

161

config->macro_tile_config_ptr =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

162

adev->gfx.config.macrotile_mode_array;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

163

config->num_macro_tile_configs =

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

164

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

741

adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

742

adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

743

adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

744

adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

745

adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

746

adev->gfx.config.max_texture_channel_caches =

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

349

adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

350

adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

351

adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

352

adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

353

adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

354

adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

355

adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

356

adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

357

adev->gfx.config.gs_prim_buffer_depth =

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

359

adev->gfx.config.double_offchip_lds_buf =

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

144

if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

145

(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

474

uint32_t *config, no_regs = 0;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

479

config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

480

if (!config)

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

484

config[no_regs++] = 3;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

485

config[no_regs++] = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

486

config[no_regs++] = adev->gfx.config.max_tile_pipes;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

487

config[no_regs++] = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

488

config[no_regs++] = adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

489

config[no_regs++] = adev->gfx.config.max_backends_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

490

config[no_regs++] = adev->gfx.config.max_texture_channel_caches;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

491

config[no_regs++] = adev->gfx.config.max_gprs;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

492

config[no_regs++] = adev->gfx.config.max_gs_threads;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

493

config[no_regs++] = adev->gfx.config.max_hw_contexts;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

494

config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

495

config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

496

config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

497

config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

498

config[no_regs++] = adev->gfx.config.num_tile_pipes;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

499

config[no_regs++] = adev->gfx.config.backend_enable_mask;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

500

config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

501

config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

502

config[no_regs++] = adev->gfx.config.shader_engine_tile_size;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

503

config[no_regs++] = adev->gfx.config.num_gpus;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

504

config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

505

config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

506

config[no_regs++] = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

507

config[no_regs++] = adev->gfx.config.num_rbs;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

510

config[no_regs++] = adev->rev_id;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

511

config[no_regs++] = adev->pg_flags;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

512

config[no_regs++] = adev->cg_flags;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

515

config[no_regs++] = adev->family;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

516

config[no_regs++] = adev->external_rev_id;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

519

config[no_regs++] = adev->pdev->device;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

520

config[no_regs++] = adev->pdev->revision;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

521

config[no_regs++] = adev->pdev->subsystem_device;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

522

config[no_regs++] = adev->pdev->subsystem_vendor;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

527

value = config[*pos >> 2];

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

530

kfree(config);

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

540

kfree(config);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1379

adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1380

adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1381

adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1382

adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1383

adev->gfx.config.max_texture_channel_caches =

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1385

adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1386

adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1387

adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1388

adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1389

adev->gfx.config.double_offchip_lds_buf =

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

247

struct amdgpu_gfx_config config;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

695

dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

696

dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

706

dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

707

dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

708

adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

709

dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

747

adev->gfx.config.double_offchip_lds_buf;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

760

dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

761

dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

762

dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

763

dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

764

dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

765

dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;

sys/dev/drm/amd/amdgpu/cik.c

1037

return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;

sys/dev/drm/amd/amdgpu/cik.c

1039

return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;

sys/dev/drm/amd/amdgpu/cik.c

1041

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;

sys/dev/drm/amd/amdgpu/cik.c

1043

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;

sys/dev/drm/amd/amdgpu/cik.c

1061

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/cik.c

1063

return adev->gfx.config.mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/cik.c

1097

return adev->gfx.config.tile_mode_array[idx];

sys/dev/drm/amd/amdgpu/cik.c

1115

return adev->gfx.config.macrotile_mode_array[idx];

sys/dev/drm/amd/amdgpu/cik_sdma.c

452

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1025

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1027

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1031

tile = adev->gfx.config.tile_mode_array;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1032

macrotile = adev->gfx.config.macrotile_mode_array;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1034

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1630

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1631

adev->gfx.config.max_sh_per_se);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1673

unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1674

unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1792

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1793

adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1797

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1798

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1801

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1807

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1808

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1810

num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1811

adev->gfx.config.max_shader_engines, 16);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1815

if (!adev->gfx.config.backend_enable_mask ||

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1816

adev->gfx.config.num_rbs >= num_rb_pipes) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1821

adev->gfx.config.backend_enable_mask,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1826

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1827

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1829

adev->gfx.config.rb_config[i][j].rb_backend_disable =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1831

adev->gfx.config.rb_config[i][j].user_rb_backend_disable =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1833

adev->gfx.config.rb_config[i][j].raster_config =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1835

adev->gfx.config.rb_config[i][j].raster_config_1 =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1885

adev->gfx.config.double_offchip_lds_buf = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1904

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1905

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1906

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1989

((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1990

(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1991

(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1992

(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2496

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2536

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2537

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3393

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3394

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3910

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4336

adev->gfx.config.max_shader_engines = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4337

adev->gfx.config.max_tile_pipes = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4338

adev->gfx.config.max_cu_per_sh = 7;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4339

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4340

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4341

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4342

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4343

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4344

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4346

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4347

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4348

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4349

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4353

adev->gfx.config.max_shader_engines = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4354

adev->gfx.config.max_tile_pipes = 16;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4355

adev->gfx.config.max_cu_per_sh = 11;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4356

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4357

adev->gfx.config.max_backends_per_se = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4358

adev->gfx.config.max_texture_channel_caches = 16;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4359

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4360

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4361

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4363

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4364

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4365

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4366

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4370

adev->gfx.config.max_shader_engines = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4371

adev->gfx.config.max_tile_pipes = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4372

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4373

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4374

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4375

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4376

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4377

adev->gfx.config.max_gs_threads = 16;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4378

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4380

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4381

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4382

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4383

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4389

adev->gfx.config.max_shader_engines = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4390

adev->gfx.config.max_tile_pipes = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4391

adev->gfx.config.max_cu_per_sh = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4392

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4393

adev->gfx.config.max_backends_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4394

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4395

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4396

adev->gfx.config.max_gs_threads = 16;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4397

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4399

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4400

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4401

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4402

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4408

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4409

mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4411

adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4412

adev->gfx.config.mem_max_burst_length_bytes = 256;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4436

adev->gfx.config.mem_row_size_in_kb = 2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4438

adev->gfx.config.mem_row_size_in_kb = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4441

adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4442

if (adev->gfx.config.mem_row_size_in_kb > 4)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4443

adev->gfx.config.mem_row_size_in_kb = 4;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4446

adev->gfx.config.shader_engine_tile_size = 32;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4447

adev->gfx.config.num_gpus = 1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4448

adev->gfx.config.multi_gpu_tile_size = 64;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4452

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4464

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5185

ao_cu_num = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5192

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5193

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5204

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1291

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1292

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1790

adev->gfx.config.max_shader_engines = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1791

adev->gfx.config.max_tile_pipes = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1792

adev->gfx.config.max_cu_per_sh = 6;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1793

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1794

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1795

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1796

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1797

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1798

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1800

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1801

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1802

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1803

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1807

adev->gfx.config.max_shader_engines = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1808

adev->gfx.config.max_tile_pipes = 16;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1809

adev->gfx.config.max_cu_per_sh = 16;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1810

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1811

adev->gfx.config.max_backends_per_se = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1812

adev->gfx.config.max_texture_channel_caches = 16;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1813

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1814

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1815

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1817

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1818

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1819

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1820

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1828

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1829

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1830

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1832

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1833

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1834

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1835

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1843

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1844

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1845

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1847

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1848

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1849

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1850

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1854

adev->gfx.config.max_shader_engines = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1855

adev->gfx.config.max_tile_pipes = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1856

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1857

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1858

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1859

adev->gfx.config.max_texture_channel_caches = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1860

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1861

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1862

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1864

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1865

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1866

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1867

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1871

adev->gfx.config.max_shader_engines = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1872

adev->gfx.config.max_tile_pipes = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1873

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1874

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1875

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1876

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1877

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1878

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1879

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1881

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1882

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1883

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1884

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1888

adev->gfx.config.max_shader_engines = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1889

adev->gfx.config.max_tile_pipes = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1890

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1891

adev->gfx.config.max_backends_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1892

adev->gfx.config.max_cu_per_sh = 3;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1893

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1894

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1895

adev->gfx.config.max_gs_threads = 16;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1896

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1898

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1899

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1900

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1901

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1905

adev->gfx.config.max_shader_engines = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1906

adev->gfx.config.max_tile_pipes = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1907

adev->gfx.config.max_cu_per_sh = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1908

adev->gfx.config.max_sh_per_se = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1909

adev->gfx.config.max_backends_per_se = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1910

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1911

adev->gfx.config.max_gprs = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1912

adev->gfx.config.max_gs_threads = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1913

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1915

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1916

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1917

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1918

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1924

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1925

mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1927

adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1928

adev->gfx.config.mem_max_burst_length_bytes = 256;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1952

adev->gfx.config.mem_row_size_in_kb = 2;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1954

adev->gfx.config.mem_row_size_in_kb = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1957

adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1958

if (adev->gfx.config.mem_row_size_in_kb > 4)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1959

adev->gfx.config.mem_row_size_in_kb = 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1962

adev->gfx.config.shader_engine_tile_size = 32;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1963

adev->gfx.config.num_gpus = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1964

adev->gfx.config.multi_gpu_tile_size = 64;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1967

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1979

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2202

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2203

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2206

modearray = adev->gfx.config.tile_mode_array;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2207

mod2array = adev->gfx.config.macrotile_mode_array;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3559

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3560

adev->gfx.config.max_sh_per_se);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3611

unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3612

unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3721

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3722

adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3726

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3727

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3730

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3736

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3737

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3739

num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3740

adev->gfx.config.max_shader_engines, 16);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3744

if (!adev->gfx.config.backend_enable_mask ||

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3745

adev->gfx.config.num_rbs >= num_rb_pipes) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3750

adev->gfx.config.backend_enable_mask,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3755

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3756

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3758

adev->gfx.config.rb_config[i][j].rb_backend_disable =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3760

adev->gfx.config.rb_config[i][j].user_rb_backend_disable =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3762

adev->gfx.config.rb_config[i][j].raster_config =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3764

adev->gfx.config.rb_config[i][j].raster_config_1 =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3821

adev->gfx.config.double_offchip_lds_buf = 1;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3825

adev->gfx.config.double_offchip_lds_buf = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3836

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3837

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3838

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3892

(adev->gfx.config.sc_prim_fifo_size_frontend <<

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3894

(adev->gfx.config.sc_prim_fifo_size_backend <<

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3896

(adev->gfx.config.sc_hiz_tile_fifo_size <<

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3898

(adev->gfx.config.sc_earlyz_tile_fifo_size <<

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3918

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3919

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4243

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4279

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4280

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7101

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7119

ao_cu_num = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7124

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7125

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7136

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1396

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1397

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1398

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1399

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1400

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1404

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1405

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1406

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1407

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1408

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1413

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1414

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1415

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1416

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1417

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1427

adev->gfx.config.max_hw_contexts = 8;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1428

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1429

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1430

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1431

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1442

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1444

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1446

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1450

adev->gfx.config.max_tile_pipes =

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1451

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1453

adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1455

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1458

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1460

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1463

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1465

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1468

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1470

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1473

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1475

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1495

ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1899

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1900

adev->gfx.config.max_sh_per_se);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1910

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1911

adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1914

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1915

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1918

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1925

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1926

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1972

adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2010

(adev->gfx.config.sc_prim_fifo_size_frontend <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2012

(adev->gfx.config.sc_prim_fifo_size_backend <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2014

(adev->gfx.config.sc_hiz_tile_fifo_size <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2016

(adev->gfx.config.sc_earlyz_tile_fifo_size <<

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2028

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2029

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2613

WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4972

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4990

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4991

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

5002

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

5004

if (counter < adev->gfx.config.max_cu_per_sh)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

937

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

938

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

944

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

427

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

665

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/soc15.c

324

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/soc15.c

326

return adev->gfx.config.db_debug2;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

580

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

581

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

582

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

282

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

283

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

284

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

614

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

615

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

616

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

707

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

709

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

711

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1055

tmp = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

324

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

326

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

328

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

330

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

332

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

334

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

336

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

338

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

340

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

342

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

344

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

346

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

400

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

402

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

404

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

406

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

408

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

410

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

412

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

414

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

416

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

418

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vi.c

561

return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;

sys/dev/drm/amd/amdgpu/vi.c

563

return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;

sys/dev/drm/amd/amdgpu/vi.c

565

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;

sys/dev/drm/amd/amdgpu/vi.c

567

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;

sys/dev/drm/amd/amdgpu/vi.c

585

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/vi.c

587

return adev->gfx.config.mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/vi.c

621

return adev->gfx.config.tile_mode_array[idx];

sys/dev/drm/amd/amdgpu/vi.c

639

return adev->gfx.config.macrotile_mode_array[idx];

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2400

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2402

adev->gfx.config.gb_addr_config_fields.num_banks;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2404

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2406

adev->gfx.config.gb_addr_config_fields.num_se;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2408

adev->gfx.config.gb_addr_config_fields.max_compress_frags;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2410

adev->gfx.config.gb_addr_config_fields.num_rb_per_se;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5123

struct mod_freesync_config config = {0};

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5131

config.state = new_crtc_state->freesync_enabled ?

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5134

config.min_refresh_in_uhz =

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5136

config.max_refresh_in_uhz =

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5138

config.vsif_supported = true;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5143

&config, &vrr);

sys/dev/drm/amd/display/dc/core/dc.c

760

dc->config = init_params->flags;

sys/dev/drm/amd/display/dc/core/dc_link.c

181

struct gpio_hpd_config config;

sys/dev/drm/amd/display/dc/core/dc_link.c

183

config.delay_on_connect = delay_on_connect_in_ms;

sys/dev/drm/amd/display/dc/core/dc_link.c

184

config.delay_on_disconnect = delay_on_disconnect_in_ms;

sys/dev/drm/amd/display/dc/core/dc_link.c

186

dal_irq_setup_hpd_filter(hpd, &config);

sys/dev/drm/amd/display/dc/core/dc_link.c

2687

struct gpio_hpd_config config;

sys/dev/drm/amd/display/dc/core/dc_link.c

2689

config.delay_on_connect = 0;

sys/dev/drm/amd/display/dc/core/dc_link.c

2690

config.delay_on_disconnect = 0;

sys/dev/drm/amd/display/dc/core/dc_link.c

2692

dal_irq_setup_hpd_filter(hpd, &config);

sys/dev/drm/amd/display/dc/core/dc_resource.c

2673

if (!dc->config.disable_disp_pll_sharing)

sys/dev/drm/amd/display/dc/dc.h

282

struct dc_config config;

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1000

enum csc_color_mode config,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1008

if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1082

enum csc_color_mode config =

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1089

configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1098

enum csc_color_mode config =

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1122

config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1132

configure_graphics_mode(xfm_dce, config,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2667

if (dc->config.gpu_vm_support)

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

360

enum csc_color_mode config,

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

375

if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC)

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

676

enum csc_color_mode config =

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

701

config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

714

configure_graphics_mode_v(xfm_dce, config,

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

726

enum csc_color_mode config =

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

733

configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1372

if (dc->config.fbc_support)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1684

if (dc->config.gpu_vm_support)

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

348

struct gpio_hpd_config *config)

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

352

if (!config)

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

356

config_data.config.hpd = *config;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

511

config_data.config.ddc.type = config_type;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

516

config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

517

config_data.config.ddc.clock_en_bit_present = hw_clock->store.en != 0;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

580

config_data.config.ddc.type = config_type;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

581

config_data.config.ddc.data_en_bit_present = false;

sys/dev/drm/amd/display/dc/gpio/gpio_service.c

582

config_data.config.ddc.clock_en_bit_present = false;

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

134

if (config_data->config.ddc.data_en_bit_present ||

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

135

config_data->config.ddc.clock_en_bit_present)

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

86

switch (config_data->config.ddc.type) {

sys/dev/drm/amd/display/dc/gpio/hw_hpd.c

111

DC_HPD_CONNECT_INT_DELAY, config_data->config.hpd.delay_on_connect / 10,

sys/dev/drm/amd/display/dc/gpio/hw_hpd.c

112

DC_HPD_DISCONNECT_INT_DELAY, config_data->config.hpd.delay_on_disconnect / 10);

sys/dev/drm/amd/display/include/gpio_service_interface.h

75

struct gpio_hpd_config *config);

sys/dev/drm/amd/display/include/gpio_types.h

329

} config;

sys/dev/drm/amd/include/atomfirmware.h

2744

uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT

sys/dev/drm/amd/include/kgd_kfd_interface.h

399

int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);

sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c

963

num_se = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1054

num_se = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

1102

num_se = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

942

num_se = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

993

num_se = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1912

uint16_t config;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1914

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1915

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1918

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1919

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1925

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1926

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1928

config = VR_SMIO_PATTERN_1;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1929

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1933

config = VR_SMIO_PATTERN_2;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1934

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1827

uint16_t config;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1829

config = VR_MERGED_WITH_VDDC;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1830

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1834

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1835

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1843

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1844

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1846

config = VR_SMIO_PATTERN_1;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1847

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1849

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1850

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1854

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1855

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1857

config = VR_SMIO_PATTERN_2;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1858

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1860

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1861

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1599

uint16_t config;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1601

config = VR_MERGED_WITH_VDDC;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1602

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1606

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1607

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1615

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1616

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1618

config = VR_SMIO_PATTERN_1;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1619

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1621

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1622

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1626

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1627

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1631

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1632

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1750

uint16_t config;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1754

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1755

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1758

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1759

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1766

config = VR_MERGED_WITH_VDDC;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1767

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1771

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1772

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1781

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1782

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1784

config = VR_SMIO_PATTERN_1;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1785

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1790

config = VR_SMIO_PATTERN_2;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1791

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1681

uint16_t config;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1683

config = VR_MERGED_WITH_VDDC;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1684

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1688

config = VR_SVI2_PLANE_1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1689

table->VRConfig |= config;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1697

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1698

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1700

config = VR_SMIO_PATTERN_1;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1701

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1703

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1704

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1708

if (config != VR_SVI2_PLANE_2) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1709

config = VR_SVI2_PLANE_2;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1710

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1719

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1720

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1723

config = VR_SMIO_PATTERN_2;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1724

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1731

config = VR_STATIC_VOLTAGE;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1732

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/drm/drm_atomic.c

1002

if (config->funcs->atomic_check) {

sys/dev/drm/drm_atomic.c

1003

ret = config->funcs->atomic_check(state->dev, state);

sys/dev/drm/drm_atomic.c

1042

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/drm/drm_atomic.c

1051

return config->funcs->atomic_commit(state->dev, state, false);

sys/dev/drm/drm_atomic.c

1071

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/drm/drm_atomic.c

1080

return config->funcs->atomic_commit(state->dev, state, true);

sys/dev/drm/drm_atomic.c

1110

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic.c

1119

list_for_each_entry(plane, &config->plane_list, head) {

sys/dev/drm/drm_atomic.c

1127

list_for_each_entry(crtc, &config->crtc_list, head) {

sys/dev/drm/drm_atomic.c

115

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic.c

117

if (!config->funcs->atomic_state_alloc) {

sys/dev/drm/drm_atomic.c

130

return config->funcs->atomic_state_alloc(dev);

sys/dev/drm/drm_atomic.c

145

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic.c

165

for (i = 0; i < config->num_crtc; i++) {

sys/dev/drm/drm_atomic.c

185

for (i = 0; i < config->num_total_plane; i++) {

sys/dev/drm/drm_atomic.c

235

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic.c

237

if (config->funcs->atomic_state_clear)

sys/dev/drm/drm_atomic.c

238

config->funcs->atomic_state_clear(state);

sys/dev/drm/drm_atomic.c

254

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/drm/drm_atomic.c

260

if (config->funcs->atomic_state_free) {

sys/dev/drm/drm_atomic.c

261

config->funcs->atomic_state_free(state);

sys/dev/drm/drm_atomic.c

773

struct drm_mode_config *config = &connector->dev->mode_config;

sys/dev/drm/drm_atomic.c

778

ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);

sys/dev/drm/drm_atomic.c

786

int alloc = max(index + 1, config->num_connector);

sys/dev/drm/drm_atomic.c

869

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/drm/drm_atomic.c

880

ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);

sys/dev/drm/drm_atomic.c

964

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

424

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

428

if (property == config->prop_active)

sys/dev/drm/drm_atomic_uapi.c

430

else if (property == config->prop_mode_id) {

sys/dev/drm/drm_atomic_uapi.c

436

} else if (property == config->degamma_lut_property) {

sys/dev/drm/drm_atomic_uapi.c

444

} else if (property == config->ctm_property) {

sys/dev/drm/drm_atomic_uapi.c

452

} else if (property == config->gamma_lut_property) {

sys/dev/drm/drm_atomic_uapi.c

460

} else if (property == config->prop_out_fence_ptr) {

sys/dev/drm/drm_atomic_uapi.c

488

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

490

if (property == config->prop_active)

sys/dev/drm/drm_atomic_uapi.c

492

else if (property == config->prop_mode_id)

sys/dev/drm/drm_atomic_uapi.c

494

else if (property == config->degamma_lut_property)

sys/dev/drm/drm_atomic_uapi.c

496

else if (property == config->ctm_property)

sys/dev/drm/drm_atomic_uapi.c

498

else if (property == config->gamma_lut_property)

sys/dev/drm/drm_atomic_uapi.c

500

else if (property == config->prop_out_fence_ptr)

sys/dev/drm/drm_atomic_uapi.c

515

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

517

if (property == config->prop_fb_id) {

sys/dev/drm/drm_atomic_uapi.c

522

} else if (property == config->prop_in_fence_fd) {

sys/dev/drm/drm_atomic_uapi.c

533

} else if (property == config->prop_crtc_id) {

sys/dev/drm/drm_atomic_uapi.c

536

} else if (property == config->prop_crtc_x) {

sys/dev/drm/drm_atomic_uapi.c

538

} else if (property == config->prop_crtc_y) {

sys/dev/drm/drm_atomic_uapi.c

540

} else if (property == config->prop_crtc_w) {

sys/dev/drm/drm_atomic_uapi.c

542

} else if (property == config->prop_crtc_h) {

sys/dev/drm/drm_atomic_uapi.c

544

} else if (property == config->prop_src_x) {

sys/dev/drm/drm_atomic_uapi.c

546

} else if (property == config->prop_src_y) {

sys/dev/drm/drm_atomic_uapi.c

548

} else if (property == config->prop_src_w) {

sys/dev/drm/drm_atomic_uapi.c

550

} else if (property == config->prop_src_h) {

sys/dev/drm/drm_atomic_uapi.c

588

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

590

if (property == config->prop_fb_id) {

sys/dev/drm/drm_atomic_uapi.c

592

} else if (property == config->prop_in_fence_fd) {

sys/dev/drm/drm_atomic_uapi.c

594

} else if (property == config->prop_crtc_id) {

sys/dev/drm/drm_atomic_uapi.c

596

} else if (property == config->prop_crtc_x) {

sys/dev/drm/drm_atomic_uapi.c

598

} else if (property == config->prop_crtc_y) {

sys/dev/drm/drm_atomic_uapi.c

600

} else if (property == config->prop_crtc_w) {

sys/dev/drm/drm_atomic_uapi.c

602

} else if (property == config->prop_crtc_h) {

sys/dev/drm/drm_atomic_uapi.c

604

} else if (property == config->prop_src_x) {

sys/dev/drm/drm_atomic_uapi.c

606

} else if (property == config->prop_src_y) {

sys/dev/drm/drm_atomic_uapi.c

608

} else if (property == config->prop_src_w) {

sys/dev/drm/drm_atomic_uapi.c

610

} else if (property == config->prop_src_h) {

sys/dev/drm/drm_atomic_uapi.c

671

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

673

if (property == config->prop_crtc_id) {

sys/dev/drm/drm_atomic_uapi.c

676

} else if (property == config->dpms_property) {

sys/dev/drm/drm_atomic_uapi.c

682

} else if (property == config->tv_select_subconnector_property) {

sys/dev/drm/drm_atomic_uapi.c

684

} else if (property == config->tv_left_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

686

} else if (property == config->tv_right_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

688

} else if (property == config->tv_top_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

690

} else if (property == config->tv_bottom_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

692

} else if (property == config->tv_mode_property) {

sys/dev/drm/drm_atomic_uapi.c

694

} else if (property == config->tv_brightness_property) {

sys/dev/drm/drm_atomic_uapi.c

696

} else if (property == config->tv_contrast_property) {

sys/dev/drm/drm_atomic_uapi.c

698

} else if (property == config->tv_flicker_reduction_property) {

sys/dev/drm/drm_atomic_uapi.c

700

} else if (property == config->tv_overscan_property) {

sys/dev/drm/drm_atomic_uapi.c

702

} else if (property == config->tv_saturation_property) {

sys/dev/drm/drm_atomic_uapi.c

704

} else if (property == config->tv_hue_property) {

sys/dev/drm/drm_atomic_uapi.c

706

} else if (property == config->link_status_property) {

sys/dev/drm/drm_atomic_uapi.c

720

} else if (property == config->aspect_ratio_property) {

sys/dev/drm/drm_atomic_uapi.c

722

} else if (property == config->content_type_property) {

sys/dev/drm/drm_atomic_uapi.c

732

} else if (property == config->writeback_fb_id_property) {

sys/dev/drm/drm_atomic_uapi.c

738

} else if (property == config->writeback_out_fence_ptr_property) {

sys/dev/drm/drm_atomic_uapi.c

762

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_atomic_uapi.c

764

if (property == config->prop_crtc_id) {

sys/dev/drm/drm_atomic_uapi.c

766

} else if (property == config->dpms_property) {

sys/dev/drm/drm_atomic_uapi.c

768

} else if (property == config->tv_select_subconnector_property) {

sys/dev/drm/drm_atomic_uapi.c

770

} else if (property == config->tv_left_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

772

} else if (property == config->tv_right_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

774

} else if (property == config->tv_top_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

776

} else if (property == config->tv_bottom_margin_property) {

sys/dev/drm/drm_atomic_uapi.c

778

} else if (property == config->tv_mode_property) {

sys/dev/drm/drm_atomic_uapi.c

780

} else if (property == config->tv_brightness_property) {

sys/dev/drm/drm_atomic_uapi.c

782

} else if (property == config->tv_contrast_property) {

sys/dev/drm/drm_atomic_uapi.c

784

} else if (property == config->tv_flicker_reduction_property) {

sys/dev/drm/drm_atomic_uapi.c

786

} else if (property == config->tv_overscan_property) {

sys/dev/drm/drm_atomic_uapi.c

788

} else if (property == config->tv_saturation_property) {

sys/dev/drm/drm_atomic_uapi.c

790

} else if (property == config->tv_hue_property) {

sys/dev/drm/drm_atomic_uapi.c

792

} else if (property == config->link_status_property) {

sys/dev/drm/drm_atomic_uapi.c

794

} else if (property == config->aspect_ratio_property) {

sys/dev/drm/drm_atomic_uapi.c

796

} else if (property == config->content_type_property) {

sys/dev/drm/drm_atomic_uapi.c

802

} else if (property == config->writeback_fb_id_property) {

sys/dev/drm/drm_atomic_uapi.c

805

} else if (property == config->writeback_out_fence_ptr_property) {

sys/dev/drm/drm_color_mgmt.c

155

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_color_mgmt.c

159

config->degamma_lut_property, 0);

sys/dev/drm/drm_color_mgmt.c

161

config->degamma_lut_size_property,

sys/dev/drm/drm_color_mgmt.c

167

config->ctm_property, 0);

sys/dev/drm/drm_color_mgmt.c

171

config->gamma_lut_property, 0);

sys/dev/drm/drm_color_mgmt.c

173

config->gamma_lut_size_property,

sys/dev/drm/drm_connector.c

167

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_connector.c

171

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/drm/drm_connector.c

172

freed = llist_del_all(&config->connector_free_list);

sys/dev/drm/drm_connector.c

173

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/drm/drm_connector.c

199

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_connector.c

219

ret = ida_simple_get(&config->connector_ida, 0, 32, GFP_KERNEL);

sys/dev/drm/drm_connector.c

257

spin_lock_irq(&config->connector_list_lock);

sys/dev/drm/drm_connector.c

258

list_add_tail(&connector->head, &config->connector_list);

sys/dev/drm/drm_connector.c

259

config->num_connector++;

sys/dev/drm/drm_connector.c

260

spin_unlock_irq(&config->connector_list_lock);

sys/dev/drm/drm_connector.c

265

config->edid_property,

sys/dev/drm/drm_connector.c

269

config->dpms_property, 0);

sys/dev/drm/drm_connector.c

272

config->link_status_property,

sys/dev/drm/drm_connector.c

276

config->non_desktop_property,

sys/dev/drm/drm_connector.c

280

drm_object_attach_property(&connector->base, config->prop_crtc_id, 0);

sys/dev/drm/drm_connector.c

289

ida_simple_remove(&config->connector_ida, connector->index);

sys/dev/drm/drm_connector.c

602

struct drm_mode_config *config = &conn->dev->mode_config;

sys/dev/drm/drm_connector.c

604

lockdep_assert_held(&config->connector_list_lock);

sys/dev/drm/drm_connector.c

609

llist_add(&conn->free_node, &config->connector_free_list);

sys/dev/drm/drm_connector.c

610

schedule_work(&config->connector_free_work);

sys/dev/drm/drm_connector.c

624

struct drm_mode_config *config = &iter->dev->mode_config;

sys/dev/drm/drm_connector.c

628

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/drm/drm_connector.c

629

lhead = old_conn ? &old_conn->head : &config->connector_list;

sys/dev/drm/drm_connector.c

632

if (lhead->next == &config->connector_list) {

sys/dev/drm/drm_connector.c

645

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/drm/drm_connector.c

662

struct drm_mode_config *config = &iter->dev->mode_config;

sys/dev/drm/drm_connector.c

667

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/drm/drm_connector.c

669

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/drm/drm_crtc.c

275

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_crtc.c

282

if (WARN_ON(config->num_crtc >= 32))

sys/dev/drm/drm_crtc.c

322

list_add_tail(&crtc->head, &config->crtc_list);

sys/dev/drm/drm_crtc.c

323

crtc->index = config->num_crtc++;

sys/dev/drm/drm_crtc.c

339

drm_object_attach_property(&crtc->base, config->prop_active, 0);

sys/dev/drm/drm_crtc.c

340

drm_object_attach_property(&crtc->base, config->prop_mode_id, 0);

sys/dev/drm/drm_crtc.c

342

config->prop_out_fence_ptr, 0);

sys/dev/drm/drm_crtc.c

569

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_crtc.c

708

if (crtc_req->count_connectors > config->num_connector) {

sys/dev/drm/drm_fb_helper.c

861

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_fb_helper.c

872

fb_helper->crtc_info = kcalloc(config->num_crtc, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL);

sys/dev/drm/drm_fb_helper.c

876

fb_helper->crtc_count = config->num_crtc;

sys/dev/drm/drm_framebuffer.c

282

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_framebuffer.c

291

if ((config->min_width > r->width) || (r->width > config->max_width)) {

sys/dev/drm/drm_framebuffer.c

293

r->width, config->min_width, config->max_width);

sys/dev/drm/drm_framebuffer.c

296

if ((config->min_height > r->height) || (r->height > config->max_height)) {

sys/dev/drm/drm_framebuffer.c

298

r->height, config->min_height, config->max_height);

sys/dev/drm/drm_modeset_lock.c

100

mutex_lock(&config->mutex);

sys/dev/drm/drm_modeset_lock.c

118

WARN_ON(config->acquire_ctx);

sys/dev/drm/drm_modeset_lock.c

124

config->acquire_ctx = ctx;

sys/dev/drm/drm_modeset_lock.c

146

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_modeset_lock.c

147

struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;

sys/dev/drm/drm_modeset_lock.c

152

config->acquire_ctx = NULL;

sys/dev/drm/drm_modeset_lock.c

92

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_plane.c

149

drm_object_attach_property(&plane->base, config->modifiers_property,

sys/dev/drm/drm_plane.c

181

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_plane.c

186

if (WARN_ON(config->num_total_plane >= 32))

sys/dev/drm/drm_plane.c

259

list_add_tail(&plane->head, &config->plane_list);

sys/dev/drm/drm_plane.c

260

plane->index = config->num_total_plane++;

sys/dev/drm/drm_plane.c

263

config->plane_type_property,

sys/dev/drm/drm_plane.c

267

drm_object_attach_property(&plane->base, config->prop_fb_id, 0);

sys/dev/drm/drm_plane.c

268

drm_object_attach_property(&plane->base, config->prop_in_fence_fd, -1);

sys/dev/drm/drm_plane.c

269

drm_object_attach_property(&plane->base, config->prop_crtc_id, 0);

sys/dev/drm/drm_plane.c

270

drm_object_attach_property(&plane->base, config->prop_crtc_x, 0);

sys/dev/drm/drm_plane.c

271

drm_object_attach_property(&plane->base, config->prop_crtc_y, 0);

sys/dev/drm/drm_plane.c

272

drm_object_attach_property(&plane->base, config->prop_crtc_w, 0);

sys/dev/drm/drm_plane.c

273

drm_object_attach_property(&plane->base, config->prop_crtc_h, 0);

sys/dev/drm/drm_plane.c

274

drm_object_attach_property(&plane->base, config->prop_src_x, 0);

sys/dev/drm/drm_plane.c

275

drm_object_attach_property(&plane->base, config->prop_src_y, 0);

sys/dev/drm/drm_plane.c

276

drm_object_attach_property(&plane->base, config->prop_src_w, 0);

sys/dev/drm/drm_plane.c

277

drm_object_attach_property(&plane->base, config->prop_src_h, 0);

sys/dev/drm/drm_plane.c

280

if (config->allow_fb_modifiers)

sys/dev/drm/drm_plane.c

88

const struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/drm_scdc_helper.c

166

u8 config;

sys/dev/drm/drm_scdc_helper.c

169

ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);

sys/dev/drm/drm_scdc_helper.c

176

config |= SCDC_SCRAMBLING_ENABLE;

sys/dev/drm/drm_scdc_helper.c

178

config &= ~SCDC_SCRAMBLING_ENABLE;

sys/dev/drm/drm_scdc_helper.c

180

ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);

sys/dev/drm/drm_scdc_helper.c

221

u8 config;

sys/dev/drm/drm_scdc_helper.c

224

ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);

sys/dev/drm/drm_scdc_helper.c

231

config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;

sys/dev/drm/drm_scdc_helper.c

233

config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;

sys/dev/drm/drm_scdc_helper.c

235

ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);

sys/dev/drm/i915/i915_drv.h

1138

struct mipi_config *config;

sys/dev/drm/i915/i915_pmu.c

25

static u8 engine_config_sample(u64 config)

sys/dev/drm/i915/i915_pmu.c

27

return config & I915_PMU_SAMPLE_MASK;

sys/dev/drm/i915/i915_pmu.c

32

return engine_config_sample(event->attr.config);

sys/dev/drm/i915/i915_pmu.c

340

config_status(struct drm_i915_private *i915, u64 config)

sys/dev/drm/i915/i915_pmu.c

342

switch (config) {

sys/dev/drm/i915/i915_pmu.c

37

return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;

sys/dev/drm/i915/i915_pmu.c

415

ret = config_status(i915, event->attr.config);

sys/dev/drm/i915/i915_pmu.c

42

return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;

sys/dev/drm/i915/i915_pmu.c

45

static bool is_engine_config(u64 config)

sys/dev/drm/i915/i915_pmu.c

47

return config < __I915_PMU_OTHER(0);

sys/dev/drm/i915/i915_pmu.c

50

static unsigned int config_enabled_bit(u64 config)

sys/dev/drm/i915/i915_pmu.c

52

if (is_engine_config(config))

sys/dev/drm/i915/i915_pmu.c

53

return engine_config_sample(config);

sys/dev/drm/i915/i915_pmu.c

546

switch (event->attr.config) {

sys/dev/drm/i915/i915_pmu.c

55

return ENGINE_SAMPLE_BITS + (config - __I915_PMU_OTHER(0));

sys/dev/drm/i915/i915_pmu.c

58

static u64 config_enabled_mask(u64 config)

sys/dev/drm/i915/i915_pmu.c

60

return BIT_ULL(config_enabled_bit(config));

sys/dev/drm/i915/i915_pmu.c

65

return is_engine_config(event->attr.config);

sys/dev/drm/i915/i915_pmu.c

70

return config_enabled_bit(event->attr.config);

sys/dev/drm/i915/i915_pmu.c

786

.config = (__config), \

sys/dev/drm/i915/i915_pmu.c

798

add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)

sys/dev/drm/i915/i915_pmu.c

804

attr->val = config;

sys/dev/drm/i915/i915_pmu.c

826

u64 config;

sys/dev/drm/i915/i915_pmu.c

853

if (!config_status(i915, events[i].config))

sys/dev/drm/i915/i915_pmu.c

887

if (config_status(i915, events[i].config))

sys/dev/drm/i915/i915_pmu.c

895

i915_iter = add_i915_attr(i915_iter, str, events[i].config);

sys/dev/drm/i915/intel_audio.c

130

u32 config;

sys/dev/drm/i915/intel_audio.c

206

hdmi_audio_clock[i].config);

sys/dev/drm/i915/intel_audio.c

208

return hdmi_audio_clock[i].config;

sys/dev/drm/i915/intel_audio.c

875

hsw_audio_config_update(encoder, crtc->config);

sys/dev/drm/i915/intel_bios.c

1062

if (dev_priv->vbt.dsi.config->is_cmd_mode ||

sys/dev/drm/i915/intel_bios.c

1794

kfree(dev_priv->vbt.dsi.config);

sys/dev/drm/i915/intel_bios.c

1795

dev_priv->vbt.dsi.config = NULL;

sys/dev/drm/i915/intel_bios.c

762

if (!dev_priv->vbt.dsi.config->dual_link || version < 197) {

sys/dev/drm/i915/intel_bios.c

764

if (dev_priv->vbt.dsi.config->cabc_supported)

sys/dev/drm/i915/intel_bios.c

770

switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {

sys/dev/drm/i915/intel_bios.c

783

if (!dev_priv->vbt.dsi.config->cabc_supported)

sys/dev/drm/i915/intel_bios.c

786

switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {

sys/dev/drm/i915/intel_bios.c

806

const struct mipi_config *config;

sys/dev/drm/i915/intel_bios.c

839

config = &start->config[panel_type];

sys/dev/drm/i915/intel_bios.c

843

dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);

sys/dev/drm/i915/intel_bios.c

844

if (!dev_priv->vbt.dsi.config)

sys/dev/drm/i915/intel_bios.c

849

kfree(dev_priv->vbt.dsi.config);

sys/dev/drm/i915/intel_ddi.c

1066

int clock = crtc->config->port_clock;

sys/dev/drm/i915/intel_ddi.c

3596

u8 config;

sys/dev/drm/i915/intel_ddi.c

3632

ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);

sys/dev/drm/i915/intel_ddi.c

3638

if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==

sys/dev/drm/i915/intel_ddi.c

3640

!!(config & SCDC_SCRAMBLING_ENABLE) ==

sys/dev/drm/i915/intel_display.c

10314

struct drm_mode_config *config = &dev->mode_config;

sys/dev/drm/i915/intel_display.c

10326

WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));

sys/dev/drm/i915/intel_display.c

1034

crtc->config->base.adjusted_mode.crtc_clock;

sys/dev/drm/i915/intel_display.c

1042

return crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

12257

const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_display.c

12266

intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {

sys/dev/drm/i915/intel_display.c

12854

to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);

sys/dev/drm/i915/intel_display.c

14086

intel_crtc->config = crtc_state;

sys/dev/drm/i915/intel_display.c

1502

intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);

sys/dev/drm/i915/intel_display.c

15632

enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

1575

intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&

sys/dev/drm/i915/intel_display.c

16064

intel_dump_pipe_config(crtc, crtc->config,

sys/dev/drm/i915/intel_display.c

16098

put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);

sys/dev/drm/i915/intel_display.c

1678

assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);

sys/dev/drm/i915/intel_display.c

1704

if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))

sys/dev/drm/i915/intel_display.c

1713

intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))

sys/dev/drm/i915/intel_display.c

3536

scaler_state = &intel_crtc->config->scaler_state;

sys/dev/drm/i915/intel_display.c

4355

temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);

sys/dev/drm/i915/intel_display.c

4507

int clock = crtc->config->base.adjusted_mode.crtc_clock;

sys/dev/drm/i915/intel_display.c

4623

enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

4671

if (intel_crtc->config->fdi_lanes > 2)

sys/dev/drm/i915/intel_display.c

5099

&crtc->config->scaler_state;

sys/dev/drm/i915/intel_display.c

5101

if (crtc->config->pch_pfit.enabled) {

sys/dev/drm/i915/intel_display.c

5106

if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))

sys/dev/drm/i915/intel_display.c

5109

pfit_w = (crtc->config->pch_pfit.size >> 16) & 0xFFFF;

sys/dev/drm/i915/intel_display.c

5110

pfit_h = crtc->config->pch_pfit.size & 0xFFFF;

sys/dev/drm/i915/intel_display.c

5112

hscale = (crtc->config->pipe_src_w << 16) / pfit_w;

sys/dev/drm/i915/intel_display.c

5113

vscale = (crtc->config->pipe_src_h << 16) / pfit_h;

sys/dev/drm/i915/intel_display.c

5125

I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);

sys/dev/drm/i915/intel_display.c

5126

I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);

sys/dev/drm/i915/intel_display.c

5136

if (crtc->config->pch_pfit.enabled) {

sys/dev/drm/i915/intel_display.c

5146

I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);

sys/dev/drm/i915/intel_display.c

5147

I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);

sys/dev/drm/i915/intel_display.c

5650

if (intel_crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_display.c

5653

if (intel_crtc_has_dp_encoder(intel_crtc->config))

sys/dev/drm/i915/intel_display.c

5659

if (intel_crtc->config->has_pch_encoder) {

sys/dev/drm/i915/intel_display.c

5661

&intel_crtc->config->fdi_m_n, NULL);

sys/dev/drm/i915/intel_display.c

5670

if (intel_crtc->config->has_pch_encoder) {

sys/dev/drm/i915/intel_display.c

5689

dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

5692

if (intel_crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_display.c

5709

if (intel_crtc->config->has_pch_encoder) {

sys/dev/drm/i915/intel_display.c

5758

enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

5769

if (intel_crtc->config->shared_dpll)

sys/dev/drm/i915/intel_display.c

5777

if (intel_crtc_has_dp_encoder(intel_crtc->config))

sys/dev/drm/i915/intel_display.c

5788

intel_crtc->config->pixel_multiplier - 1);

sys/dev/drm/i915/intel_display.c

5791

if (intel_crtc->config->has_pch_encoder) {

sys/dev/drm/i915/intel_display.c

5793

&intel_crtc->config->fdi_m_n, NULL);

sys/dev/drm/i915/intel_display.c

5807

intel_crtc->config->pch_pfit.enabled;

sys/dev/drm/i915/intel_display.c

5847

if (intel_crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_display.c

5850

if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))

sys/dev/drm/i915/intel_display.c

5880

if (force || crtc->config->pch_pfit.enabled) {

sys/dev/drm/i915/intel_display.c

5913

if (intel_crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_display.c

5918

if (intel_crtc->config->has_pch_encoder) {

sys/dev/drm/i915/intel_display.c

5984

struct intel_crtc_state *pipe_config = crtc->config;

sys/dev/drm/i915/intel_display.c

6131

if (intel_crtc_has_dp_encoder(intel_crtc->config))

sys/dev/drm/i915/intel_display.c

6155

chv_prepare_pll(intel_crtc, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

6156

chv_enable_pll(intel_crtc, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

6158

vlv_prepare_pll(intel_crtc, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

6159

vlv_enable_pll(intel_crtc, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

6183

I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);

sys/dev/drm/i915/intel_display.c

6184

I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);

sys/dev/drm/i915/intel_display.c

6203

if (intel_crtc_has_dp_encoder(intel_crtc->config))

sys/dev/drm/i915/intel_display.c

6226

intel_crtc->config);

sys/dev/drm/i915/intel_display.c

6242

if (!crtc->config->gmch_pfit.control)

sys/dev/drm/i915/intel_display.c

6279

if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {

sys/dev/drm/i915/intel_display.c

6948

enum transcoder transcoder = crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

6960

INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {

sys/dev/drm/i915/intel_display.c

6980

dp_m_n = &crtc->config->dp_m_n;

sys/dev/drm/i915/intel_display.c

6981

dp_m2_n2 = &crtc->config->dp_m2_n2;

sys/dev/drm/i915/intel_display.c

6988

dp_m_n = &crtc->config->dp_m2_n2;

sys/dev/drm/i915/intel_display.c

6994

if (crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_display.c

6995

intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);

sys/dev/drm/i915/intel_display.c

7096

intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||

sys/dev/drm/i915/intel_display.c

7097

intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))

sys/dev/drm/i915/intel_display.c

7124

if (intel_crtc_has_dp_encoder(crtc->config))

sys/dev/drm/i915/intel_display.c

7407

enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

7408

const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_display.c

7422

if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))

sys/dev/drm/i915/intel_display.c

7474

((intel_crtc->config->pipe_src_w - 1) << 16) |

sys/dev/drm/i915/intel_display.c

7475

(intel_crtc->config->pipe_src_h - 1));

sys/dev/drm/i915/intel_display.c

7562

if (intel_crtc->config->double_wide)

sys/dev/drm/i915/intel_display.c

7569

if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)

sys/dev/drm/i915/intel_display.c

7573

switch (intel_crtc->config->pipe_bpp) {

sys/dev/drm/i915/intel_display.c

7589

if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

sys/dev/drm/i915/intel_display.c

7591

intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))

sys/dev/drm/i915/intel_display.c

7599

intel_crtc->config->limited_color_range)

sys/dev/drm/i915/intel_display.c

8518

switch (intel_crtc->config->pipe_bpp) {

sys/dev/drm/i915/intel_display.c

8536

if (intel_crtc->config->dither)

sys/dev/drm/i915/intel_display.c

8539

if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

sys/dev/drm/i915/intel_display.c

8544

if (intel_crtc->config->limited_color_range)

sys/dev/drm/i915/intel_display.c

8555

enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

8558

if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)

sys/dev/drm/i915/intel_display.c

8561

if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

sys/dev/drm/i915/intel_display.c

8574

struct intel_crtc_state *config = intel_crtc->config;

sys/dev/drm/i915/intel_display.c

8579

switch (intel_crtc->config->pipe_bpp) {

sys/dev/drm/i915/intel_display.c

8597

if (intel_crtc->config->dither)

sys/dev/drm/i915/intel_display.c

8600

if (config->ycbcr420) {

sys/dev/drm/i915/intel_display.c

8820

crtc->config->has_drrs) {

sys/dev/drm/i915/intel_display.c

9791

const struct drm_mode_config *config =

sys/dev/drm/i915/intel_display.c

9796

return width > 0 && width <= config->cursor_width &&

sys/dev/drm/i915/intel_display.c

9797

height > 0 && height <= config->cursor_height;

sys/dev/drm/i915/intel_dp.c

4410

if (crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_dp.c

4421

if (crtc->config->has_pch_encoder)

sys/dev/drm/i915/intel_dp.c

6229

intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,

sys/dev/drm/i915/intel_dp.c

6272

intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,

sys/dev/drm/i915/intel_dp.c

6315

intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,

sys/dev/drm/i915/intel_dpio_phy.c

658

if (intel_crtc->config->lane_count > 2) {

sys/dev/drm/i915/intel_dpio_phy.c

671

if (intel_crtc->config->lane_count > 2) {

sys/dev/drm/i915/intel_dpio_phy.c

679

for (i = 0; i < intel_crtc->config->lane_count; i++) {

sys/dev/drm/i915/intel_dpio_phy.c

687

for (i = 0; i < intel_crtc->config->lane_count; i++) {

sys/dev/drm/i915/intel_dpio_phy.c

710

for (i = 0; i < intel_crtc->config->lane_count; i++) {

sys/dev/drm/i915/intel_dpio_phy.c

724

if (intel_crtc->config->lane_count > 2) {

sys/dev/drm/i915/intel_dpio_phy.c

751

if (crtc->config->lane_count > 2) {

sys/dev/drm/i915/intel_dpio_phy.c

768

if (crtc->config->lane_count > 2) {

sys/dev/drm/i915/intel_dpll_mgr.c

138

struct intel_shared_dpll *pll = crtc->config->shared_dpll;

sys/dev/drm/i915/intel_dpll_mgr.c

165

struct intel_shared_dpll *pll = crtc->config->shared_dpll;

sys/dev/drm/i915/intel_dpll_mgr.c

209

struct intel_shared_dpll *pll = crtc->config->shared_dpll;

sys/dev/drm/i915/intel_dpll_mgr.c

417

if (crtc->config->shared_dpll == pll)

sys/dev/drm/i915/intel_drv.h

932

struct intel_crtc_state *config;

sys/dev/drm/i915/intel_dsi.h

138

struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi.h

140

const struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi.h

143

struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi.h

148

struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi.h

150

const struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi.h

153

struct intel_crtc_state *config);

sys/dev/drm/i915/intel_dsi_vbt.c

506

struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;

sys/dev/drm/i915/intel_fbdev.c

621

cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;

sys/dev/drm/i915/intel_fbdev.c

631

cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;

sys/dev/drm/i915/intel_fbdev.c

636

intel_crtc->config->base.adjusted_mode.crtc_hdisplay,

sys/dev/drm/i915/intel_fbdev.c

637

intel_crtc->config->base.adjusted_mode.crtc_vdisplay,

sys/dev/drm/i915/intel_hdmi.c

1656

struct intel_crtc_state *config,

sys/dev/drm/i915/intel_hdmi.c

1660

struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);

sys/dev/drm/i915/intel_hdmi.c

1668

config->port_clock /= 2;

sys/dev/drm/i915/intel_hdmi.c

1672

config->ycbcr420 = true;

sys/dev/drm/i915/intel_hdmi.c

1675

if (skl_update_scaler_crtc(config)) {

sys/dev/drm/i915/intel_hdmi.c

1680

intel_pch_panel_fitting(intel_crtc, config,

sys/dev/drm/i915/intel_overlay.c

1122

if (crtc->config->pipe_src_w > 1024 &&

sys/dev/drm/i915/intel_overlay.c

1123

crtc->config->gmch_pfit.control & PFIT_ENABLE) {

sys/dev/drm/i915/intel_overlay.c

887

if (crtc->config->double_wide)

sys/dev/drm/i915/intel_overlay.c

920

overlay->crtc->config;

sys/dev/drm/i915/intel_pm.c

2202

&crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2207

int hdisplay = crtc->config->pipe_src_w;

sys/dev/drm/i915/intel_pm.c

2283

&crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2310

&crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2358

&enabled->config->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2363

int hdisplay = enabled->config->pipe_src_w;

sys/dev/drm/i915/intel_pm.c

2416

adjusted_mode = &crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2629

const struct intel_wm_config *config,

sys/dev/drm/i915/intel_pm.c

2637

if (is_sprite && !config->sprites_enabled)

sys/dev/drm/i915/intel_pm.c

2641

if (level == 0 || config->num_pipes_active > 1) {

sys/dev/drm/i915/intel_pm.c

2653

if (config->sprites_enabled) {

sys/dev/drm/i915/intel_pm.c

2671

const struct intel_wm_config *config)

sys/dev/drm/i915/intel_pm.c

2674

if (level > 0 && config->num_pipes_active > 1)

sys/dev/drm/i915/intel_pm.c

2683

const struct intel_wm_config *config,

sys/dev/drm/i915/intel_pm.c

2687

max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);

sys/dev/drm/i915/intel_pm.c

2688

max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);

sys/dev/drm/i915/intel_pm.c

2689

max->cur = ilk_cursor_wm_max(dev, level, config);

sys/dev/drm/i915/intel_pm.c

3078

const struct intel_wm_config config = {

sys/dev/drm/i915/intel_pm.c

3086

ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/drm/i915/intel_pm.c

3273

const struct intel_wm_config *config,

sys/dev/drm/i915/intel_pm.c

3283

config->num_pipes_active > 1)

sys/dev/drm/i915/intel_pm.c

5460

struct intel_wm_config *config)

sys/dev/drm/i915/intel_pm.c

5471

config->sprites_enabled |= wm->sprites_enabled;

sys/dev/drm/i915/intel_pm.c

5472

config->sprites_scaled |= wm->sprites_scaled;

sys/dev/drm/i915/intel_pm.c

5473

config->num_pipes_active++;

sys/dev/drm/i915/intel_pm.c

5482

struct intel_wm_config config = {};

sys/dev/drm/i915/intel_pm.c

5486

ilk_compute_wm_config(dev, &config);

sys/dev/drm/i915/intel_pm.c

5488

ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/drm/i915/intel_pm.c

5489

ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);

sys/dev/drm/i915/intel_pm.c

5493

config.num_pipes_active == 1 && config.sprites_enabled) {

sys/dev/drm/i915/intel_pm.c

5494

ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);

sys/dev/drm/i915/intel_pm.c

5495

ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);

sys/dev/drm/i915/intel_pm.c

861

&crtc->config->base.adjusted_mode;

sys/dev/drm/i915/intel_vbt_defs.h

902

struct mipi_config config[MAX_MIPI_CONFIGURATIONS];

sys/dev/drm/i915/vlv_dsi.c

1109

adjusted_mode_sw = &crtc->config->base.adjusted_mode;

sys/dev/drm/i915/vlv_dsi.c

1797

if (dev_priv->vbt.dsi.config->dual_link)

sys/dev/drm/i915/vlv_dsi.c

1826

(dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {

sys/dev/drm/i915/vlv_dsi_pll.c

102

config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);

sys/dev/drm/i915/vlv_dsi_pll.c

103

config->dsi_pll.div =

sys/dev/drm/i915/vlv_dsi_pll.c

115

struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

125

ret = dsi_calc_mnp(dev_priv, config, dsi_clk);

sys/dev/drm/i915/vlv_dsi_pll.c

132

config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

sys/dev/drm/i915/vlv_dsi_pll.c

135

config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

sys/dev/drm/i915/vlv_dsi_pll.c

137

config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;

sys/dev/drm/i915/vlv_dsi_pll.c

140

config->dsi_pll.div, config->dsi_pll.ctrl);

sys/dev/drm/i915/vlv_dsi_pll.c

146

const struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

155

vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);

sys/dev/drm/i915/vlv_dsi_pll.c

157

config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);

sys/dev/drm/i915/vlv_dsi_pll.c

164

vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

sys/dev/drm/i915/vlv_dsi_pll.c

265

struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

282

config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;

sys/dev/drm/i915/vlv_dsi_pll.c

283

config->dsi_pll.div = pll_div;

sys/dev/drm/i915/vlv_dsi_pll.c

331

struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

345

config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);

sys/dev/drm/i915/vlv_dsi_pll.c

347

dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/drm/i915/vlv_dsi_pll.c

374

const struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

385

pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/drm/i915/vlv_dsi_pll.c

422

const struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

442

pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/drm/i915/vlv_dsi_pll.c

475

struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

511

config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;

sys/dev/drm/i915/vlv_dsi_pll.c

517

config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;

sys/dev/drm/i915/vlv_dsi_pll.c

523

const struct intel_crtc_state *config)

sys/dev/drm/i915/vlv_dsi_pll.c

533

I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);

sys/dev/drm/i915/vlv_dsi_pll.c

539

bxt_dsi_program_clocks(encoder->base.dev, port, config);

sys/dev/drm/i915/vlv_dsi_pll.c

541

glk_dsi_program_esc_clock(encoder->base.dev, config);

sys/dev/drm/i915/vlv_dsi_pll.c

55

struct intel_crtc_state *config,

sys/dev/drm/radeon/atombios_crtc.c

1288

num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

sys/dev/drm/radeon/atombios_crtc.c

1303

num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;

sys/dev/drm/radeon/atombios_crtc.c

1310

tmp = rdev->config.cayman.tile_config;

sys/dev/drm/radeon/atombios_crtc.c

1312

tmp = rdev->config.evergreen.tile_config;

sys/dev/drm/radeon/atombios_crtc.c

1344

u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;

sys/dev/drm/radeon/cik.c

2347

u32 *tile = rdev->config.cik.tile_mode_array;

sys/dev/drm/radeon/cik.c

2348

u32 *macrotile = rdev->config.cik.macrotile_mode_array;

sys/dev/drm/radeon/cik.c

2350

ARRAY_SIZE(rdev->config.cik.tile_mode_array);

sys/dev/drm/radeon/cik.c

2352

ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);

sys/dev/drm/radeon/cik.c

2355

u32 num_rbs = rdev->config.cik.max_backends_per_se *

sys/dev/drm/radeon/cik.c

2356

rdev->config.cik.max_shader_engines;

sys/dev/drm/radeon/cik.c

2358

switch (rdev->config.cik.mem_row_size_in_kb) {

sys/dev/drm/radeon/cik.c

2371

num_pipe_configs = rdev->config.cik.max_tile_pipes;

sys/dev/drm/radeon/cik.c

3155

rdev->config.cik.backend_enable_mask = enabled_rbs;

sys/dev/drm/radeon/cik.c

3204

rdev->config.cik.max_shader_engines = 2;

sys/dev/drm/radeon/cik.c

3205

rdev->config.cik.max_tile_pipes = 4;

sys/dev/drm/radeon/cik.c

3206

rdev->config.cik.max_cu_per_sh = 7;

sys/dev/drm/radeon/cik.c

3207

rdev->config.cik.max_sh_per_se = 1;

sys/dev/drm/radeon/cik.c

3208

rdev->config.cik.max_backends_per_se = 2;

sys/dev/drm/radeon/cik.c

3209

rdev->config.cik.max_texture_channel_caches = 4;

sys/dev/drm/radeon/cik.c

3210

rdev->config.cik.max_gprs = 256;

sys/dev/drm/radeon/cik.c

3211

rdev->config.cik.max_gs_threads = 32;

sys/dev/drm/radeon/cik.c

3212

rdev->config.cik.max_hw_contexts = 8;

sys/dev/drm/radeon/cik.c

3214

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/cik.c

3215

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/cik.c

3216

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/cik.c

3217

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/cik.c

3221

rdev->config.cik.max_shader_engines = 4;

sys/dev/drm/radeon/cik.c

3222

rdev->config.cik.max_tile_pipes = 16;

sys/dev/drm/radeon/cik.c

3223

rdev->config.cik.max_cu_per_sh = 11;

sys/dev/drm/radeon/cik.c

3224

rdev->config.cik.max_sh_per_se = 1;

sys/dev/drm/radeon/cik.c

3225

rdev->config.cik.max_backends_per_se = 4;

sys/dev/drm/radeon/cik.c

3226

rdev->config.cik.max_texture_channel_caches = 16;

sys/dev/drm/radeon/cik.c

3227

rdev->config.cik.max_gprs = 256;

sys/dev/drm/radeon/cik.c

3228

rdev->config.cik.max_gs_threads = 32;

sys/dev/drm/radeon/cik.c

3229

rdev->config.cik.max_hw_contexts = 8;

sys/dev/drm/radeon/cik.c

3231

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/cik.c

3232

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/cik.c

3233

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/cik.c

3234

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/cik.c

3238

rdev->config.cik.max_shader_engines = 1;

sys/dev/drm/radeon/cik.c

3239

rdev->config.cik.max_tile_pipes = 4;

sys/dev/drm/radeon/cik.c

3240

rdev->config.cik.max_cu_per_sh = 8;

sys/dev/drm/radeon/cik.c

3241

rdev->config.cik.max_backends_per_se = 2;

sys/dev/drm/radeon/cik.c

3242

rdev->config.cik.max_sh_per_se = 1;

sys/dev/drm/radeon/cik.c

3243

rdev->config.cik.max_texture_channel_caches = 4;

sys/dev/drm/radeon/cik.c

3244

rdev->config.cik.max_gprs = 256;

sys/dev/drm/radeon/cik.c

3245

rdev->config.cik.max_gs_threads = 16;

sys/dev/drm/radeon/cik.c

3246

rdev->config.cik.max_hw_contexts = 8;

sys/dev/drm/radeon/cik.c

3248

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/cik.c

3249

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/cik.c

3250

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/cik.c

3251

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/cik.c

3257

rdev->config.cik.max_shader_engines = 1;

sys/dev/drm/radeon/cik.c

3258

rdev->config.cik.max_tile_pipes = 2;

sys/dev/drm/radeon/cik.c

3259

rdev->config.cik.max_cu_per_sh = 2;

sys/dev/drm/radeon/cik.c

3260

rdev->config.cik.max_sh_per_se = 1;

sys/dev/drm/radeon/cik.c

3261

rdev->config.cik.max_backends_per_se = 1;

sys/dev/drm/radeon/cik.c

3262

rdev->config.cik.max_texture_channel_caches = 2;

sys/dev/drm/radeon/cik.c

3263

rdev->config.cik.max_gprs = 256;

sys/dev/drm/radeon/cik.c

3264

rdev->config.cik.max_gs_threads = 16;

sys/dev/drm/radeon/cik.c

3265

rdev->config.cik.max_hw_contexts = 8;

sys/dev/drm/radeon/cik.c

3267

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/cik.c

3268

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/cik.c

3269

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/cik.c

3270

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/cik.c

3293

rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;

sys/dev/drm/radeon/cik.c

3294

rdev->config.cik.mem_max_burst_length_bytes = 256;

sys/dev/drm/radeon/cik.c

3296

rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/drm/radeon/cik.c

3297

if (rdev->config.cik.mem_row_size_in_kb > 4)

sys/dev/drm/radeon/cik.c

3298

rdev->config.cik.mem_row_size_in_kb = 4;

sys/dev/drm/radeon/cik.c

3300

rdev->config.cik.shader_engine_tile_size = 32;

sys/dev/drm/radeon/cik.c

3301

rdev->config.cik.num_gpus = 1;

sys/dev/drm/radeon/cik.c

3302

rdev->config.cik.multi_gpu_tile_size = 64;

sys/dev/drm/radeon/cik.c

3306

switch (rdev->config.cik.mem_row_size_in_kb) {

sys/dev/drm/radeon/cik.c

3326

rdev->config.cik.tile_config = 0;

sys/dev/drm/radeon/cik.c

3327

switch (rdev->config.cik.num_tile_pipes) {

sys/dev/drm/radeon/cik.c

3329

rdev->config.cik.tile_config |= (0 << 0);

sys/dev/drm/radeon/cik.c

3332

rdev->config.cik.tile_config |= (1 << 0);

sys/dev/drm/radeon/cik.c

3335

rdev->config.cik.tile_config |= (2 << 0);

sys/dev/drm/radeon/cik.c

3340

rdev->config.cik.tile_config |= (3 << 0);

sys/dev/drm/radeon/cik.c

3343

rdev->config.cik.tile_config |=

sys/dev/drm/radeon/cik.c

3345

rdev->config.cik.tile_config |=

sys/dev/drm/radeon/cik.c

3347

rdev->config.cik.tile_config |=

sys/dev/drm/radeon/cik.c

3361

cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,

sys/dev/drm/radeon/cik.c

3362

rdev->config.cik.max_sh_per_se,

sys/dev/drm/radeon/cik.c

3363

rdev->config.cik.max_backends_per_se);

sys/dev/drm/radeon/cik.c

3365

rdev->config.cik.active_cus = 0;

sys/dev/drm/radeon/cik.c

3366

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/drm/radeon/cik.c

3367

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/drm/radeon/cik.c

3368

rdev->config.cik.active_cus +=

sys/dev/drm/radeon/cik.c

3402

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |

sys/dev/drm/radeon/cik.c

3403

SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |

sys/dev/drm/radeon/cik.c

3404

SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |

sys/dev/drm/radeon/cik.c

3405

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));

sys/dev/drm/radeon/cik.c

4003

WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);

sys/dev/drm/radeon/cik.c

5813

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/drm/radeon/cik.c

5814

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/drm/radeon/cik.c

6566

for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {

sys/dev/drm/radeon/cik.c

6580

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/drm/radeon/cik.c

6581

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/drm/radeon/cik.c

6585

for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {

sys/dev/drm/radeon/evergreen.c

2993

radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);

sys/dev/drm/radeon/evergreen.c

3139

rdev->config.evergreen.num_ses = 2;

sys/dev/drm/radeon/evergreen.c

3140

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3141

rdev->config.evergreen.max_tile_pipes = 8;

sys/dev/drm/radeon/evergreen.c

3142

rdev->config.evergreen.max_simds = 10;

sys/dev/drm/radeon/evergreen.c

3143

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3144

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3145

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3146

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3147

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/drm/radeon/evergreen.c

3148

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3149

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3150

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3151

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3152

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3153

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3155

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/evergreen.c

3156

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3157

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3161

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3162

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3163

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3164

rdev->config.evergreen.max_simds = 10;

sys/dev/drm/radeon/evergreen.c

3165

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3166

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3167

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3168

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3169

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/drm/radeon/evergreen.c

3170

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3171

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3172

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3173

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3174

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3175

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3177

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/evergreen.c

3178

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3179

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3183

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3184

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3185

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3186

rdev->config.evergreen.max_simds = 5;

sys/dev/drm/radeon/evergreen.c

3187

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3188

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3189

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3190

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3191

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3192

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3193

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3194

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3195

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3196

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3197

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3199

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/evergreen.c

3200

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3201

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3206

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3207

rdev->config.evergreen.max_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3208

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3209

rdev->config.evergreen.max_simds = 2;

sys/dev/drm/radeon/evergreen.c

3210

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3211

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3212

rdev->config.evergreen.max_threads = 192;

sys/dev/drm/radeon/evergreen.c

3213

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/drm/radeon/evergreen.c

3214

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3215

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3216

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/drm/radeon/evergreen.c

3217

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/evergreen.c

3218

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/drm/radeon/evergreen.c

3219

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/drm/radeon/evergreen.c

3220

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/drm/radeon/evergreen.c

3222

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/evergreen.c

3223

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3224

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3228

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3229

rdev->config.evergreen.max_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3230

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3231

rdev->config.evergreen.max_simds = 2;

sys/dev/drm/radeon/evergreen.c

3232

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3233

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3234

rdev->config.evergreen.max_threads = 192;

sys/dev/drm/radeon/evergreen.c

3235

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/drm/radeon/evergreen.c

3236

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3237

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3238

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/drm/radeon/evergreen.c

3239

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/evergreen.c

3240

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/drm/radeon/evergreen.c

3241

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/drm/radeon/evergreen.c

3242

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/drm/radeon/evergreen.c

3244

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/evergreen.c

3245

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3246

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3250

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3251

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3252

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3254

rdev->config.evergreen.max_simds = 3;

sys/dev/drm/radeon/evergreen.c

3257

rdev->config.evergreen.max_simds = 4;

sys/dev/drm/radeon/evergreen.c

3259

rdev->config.evergreen.max_simds = 5;

sys/dev/drm/radeon/evergreen.c

3260

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3261

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3262

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3263

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3264

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3265

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3266

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3267

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3268

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3269

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3270

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3272

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/evergreen.c

3273

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3274

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3278

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3279

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3280

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3281

rdev->config.evergreen.max_simds = 2;

sys/dev/drm/radeon/evergreen.c

3282

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3283

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3284

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3285

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3286

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/drm/radeon/evergreen.c

3287

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3288

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3289

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3290

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3291

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/drm/radeon/evergreen.c

3292

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3294

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/evergreen.c

3295

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3296

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3300

rdev->config.evergreen.num_ses = 2;

sys/dev/drm/radeon/evergreen.c

3301

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3302

rdev->config.evergreen.max_tile_pipes = 8;

sys/dev/drm/radeon/evergreen.c

3303

rdev->config.evergreen.max_simds = 7;

sys/dev/drm/radeon/evergreen.c

3304

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3305

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3306

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3307

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3308

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/drm/radeon/evergreen.c

3309

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3310

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3311

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3312

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3313

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3314

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3316

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/evergreen.c

3317

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3318

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3322

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3323

rdev->config.evergreen.max_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3324

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/drm/radeon/evergreen.c

3325

rdev->config.evergreen.max_simds = 6;

sys/dev/drm/radeon/evergreen.c

3326

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3327

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3328

rdev->config.evergreen.max_threads = 248;

sys/dev/drm/radeon/evergreen.c

3329

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/drm/radeon/evergreen.c

3330

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3331

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3332

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/drm/radeon/evergreen.c

3333

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/evergreen.c

3334

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/evergreen.c

3335

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/drm/radeon/evergreen.c

3336

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/drm/radeon/evergreen.c

3338

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/evergreen.c

3339

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3340

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3344

rdev->config.evergreen.num_ses = 1;

sys/dev/drm/radeon/evergreen.c

3345

rdev->config.evergreen.max_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3346

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/drm/radeon/evergreen.c

3347

rdev->config.evergreen.max_simds = 2;

sys/dev/drm/radeon/evergreen.c

3348

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/evergreen.c

3349

rdev->config.evergreen.max_gprs = 256;

sys/dev/drm/radeon/evergreen.c

3350

rdev->config.evergreen.max_threads = 192;

sys/dev/drm/radeon/evergreen.c

3351

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/drm/radeon/evergreen.c

3352

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/drm/radeon/evergreen.c

3353

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/drm/radeon/evergreen.c

3354

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/drm/radeon/evergreen.c

3355

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/evergreen.c

3356

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/drm/radeon/evergreen.c

3357

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/drm/radeon/evergreen.c

3358

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/drm/radeon/evergreen.c

3360

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/evergreen.c

3361

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/evergreen.c

3362

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/evergreen.c

3397

rdev->config.evergreen.tile_config = 0;

sys/dev/drm/radeon/evergreen.c

3398

switch (rdev->config.evergreen.max_tile_pipes) {

sys/dev/drm/radeon/evergreen.c

3401

rdev->config.evergreen.tile_config |= (0 << 0);

sys/dev/drm/radeon/evergreen.c

3404

rdev->config.evergreen.tile_config |= (1 << 0);

sys/dev/drm/radeon/evergreen.c

3407

rdev->config.evergreen.tile_config |= (2 << 0);

sys/dev/drm/radeon/evergreen.c

3410

rdev->config.evergreen.tile_config |= (3 << 0);

sys/dev/drm/radeon/evergreen.c

3415

rdev->config.evergreen.tile_config |= 1 << 4;

sys/dev/drm/radeon/evergreen.c

3419

rdev->config.evergreen.tile_config |= 0 << 4;

sys/dev/drm/radeon/evergreen.c

3422

rdev->config.evergreen.tile_config |= 1 << 4;

sys/dev/drm/radeon/evergreen.c

3426

rdev->config.evergreen.tile_config |= 2 << 4;

sys/dev/drm/radeon/evergreen.c

3430

rdev->config.evergreen.tile_config |= 0 << 8;

sys/dev/drm/radeon/evergreen.c

3431

rdev->config.evergreen.tile_config |=

sys/dev/drm/radeon/evergreen.c

3444

for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {

sys/dev/drm/radeon/evergreen.c

3457

for (i = 0; i < rdev->config.evergreen.max_backends; i++)

sys/dev/drm/radeon/evergreen.c

3461

for (i = 0; i < rdev->config.evergreen.max_backends; i++)

sys/dev/drm/radeon/evergreen.c

3465

for (i = 0; i < rdev->config.evergreen.num_ses; i++) {

sys/dev/drm/radeon/evergreen.c

3471

simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;

sys/dev/drm/radeon/evergreen.c

3475

rdev->config.evergreen.active_simds = hweight32(~tmp);

sys/dev/drm/radeon/evergreen.c

3488

if ((rdev->config.evergreen.max_backends == 1) &&

sys/dev/drm/radeon/evergreen.c

3499

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,

sys/dev/drm/radeon/evergreen.c

3502

rdev->config.evergreen.backend_map = tmp;

sys/dev/drm/radeon/evergreen.c

3528

smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);

sys/dev/drm/radeon/evergreen.c

3534

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/evergreen.c

3535

POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |

sys/dev/drm/radeon/evergreen.c

3536

SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

sys/dev/drm/radeon/evergreen.c

3538

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |

sys/dev/drm/radeon/evergreen.c

3539

SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |

sys/dev/drm/radeon/evergreen.c

3540

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));

sys/dev/drm/radeon/evergreen.c

3547

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |

sys/dev/drm/radeon/evergreen.c

3579

sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);

sys/dev/drm/radeon/evergreen.c

3580

sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);

sys/dev/drm/radeon/evergreen.c

3582

sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);

sys/dev/drm/radeon/evergreen.c

3583

sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);

sys/dev/drm/radeon/evergreen.c

3584

sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);

sys/dev/drm/radeon/evergreen.c

3585

sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);

sys/dev/drm/radeon/evergreen.c

3600

sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/drm/radeon/evergreen.c

3601

sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/drm/radeon/evergreen.c

3602

sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/drm/radeon/evergreen.c

3603

sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/drm/radeon/evergreen.c

3604

sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/drm/radeon/evergreen.c

3606

sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

3607

sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

3608

sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

3609

sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

3610

sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

3611

sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/drm/radeon/evergreen.c

4378

3 | (3 << (16 * rdev->config.cayman.max_shader_engines));

sys/dev/drm/radeon/evergreen.c

4381

tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;

sys/dev/drm/radeon/evergreen.c

4383

if (tmp == rdev->config.cayman.max_simds_per_se) {

sys/dev/drm/radeon/evergreen_cs.c

2684

tmp = p->rdev->config.cayman.tile_config;

sys/dev/drm/radeon/evergreen_cs.c

2687

tmp = p->rdev->config.evergreen.tile_config;

sys/dev/drm/radeon/ni.c

1000

rdev->config.cayman.max_gprs = 256;

sys/dev/drm/radeon/ni.c

1001

rdev->config.cayman.max_threads = 256;

sys/dev/drm/radeon/ni.c

1002

rdev->config.cayman.max_gs_threads = 32;

sys/dev/drm/radeon/ni.c

1003

rdev->config.cayman.max_stack_entries = 512;

sys/dev/drm/radeon/ni.c

1004

rdev->config.cayman.sx_num_of_sets = 8;

sys/dev/drm/radeon/ni.c

1005

rdev->config.cayman.sq_num_cf_insts = 2;

sys/dev/drm/radeon/ni.c

1007

rdev->config.cayman.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/ni.c

1008

rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/ni.c

1009

rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/ni.c

1033

rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/drm/radeon/ni.c

1034

if (rdev->config.cayman.mem_row_size_in_kb > 4)

sys/dev/drm/radeon/ni.c

1035

rdev->config.cayman.mem_row_size_in_kb = 4;

sys/dev/drm/radeon/ni.c

1037

rdev->config.cayman.shader_engine_tile_size = 32;

sys/dev/drm/radeon/ni.c

1038

rdev->config.cayman.num_gpus = 1;

sys/dev/drm/radeon/ni.c

1039

rdev->config.cayman.multi_gpu_tile_size = 64;

sys/dev/drm/radeon/ni.c

1042

rdev->config.cayman.num_tile_pipes = (1 << tmp);

sys/dev/drm/radeon/ni.c

1044

rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;

sys/dev/drm/radeon/ni.c

1046

rdev->config.cayman.num_shader_engines = tmp + 1;

sys/dev/drm/radeon/ni.c

1048

rdev->config.cayman.num_gpus = tmp + 1;

sys/dev/drm/radeon/ni.c

1050

rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;

sys/dev/drm/radeon/ni.c

1052

rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;

sys/dev/drm/radeon/ni.c

1062

rdev->config.cayman.tile_config = 0;

sys/dev/drm/radeon/ni.c

1063

switch (rdev->config.cayman.num_tile_pipes) {

sys/dev/drm/radeon/ni.c

1066

rdev->config.cayman.tile_config |= (0 << 0);

sys/dev/drm/radeon/ni.c

1069

rdev->config.cayman.tile_config |= (1 << 0);

sys/dev/drm/radeon/ni.c

1072

rdev->config.cayman.tile_config |= (2 << 0);

sys/dev/drm/radeon/ni.c

1075

rdev->config.cayman.tile_config |= (3 << 0);

sys/dev/drm/radeon/ni.c

1081

rdev->config.cayman.tile_config |= 1 << 4;

sys/dev/drm/radeon/ni.c

1085

rdev->config.cayman.tile_config |= 0 << 4;

sys/dev/drm/radeon/ni.c

1088

rdev->config.cayman.tile_config |= 1 << 4;

sys/dev/drm/radeon/ni.c

1092

rdev->config.cayman.tile_config |= 2 << 4;

sys/dev/drm/radeon/ni.c

1096

rdev->config.cayman.tile_config |=

sys/dev/drm/radeon/ni.c

1098

rdev->config.cayman.tile_config |=

sys/dev/drm/radeon/ni.c

1102

for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {

sys/dev/drm/radeon/ni.c

1114

for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)

sys/dev/drm/radeon/ni.c

1118

for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)

sys/dev/drm/radeon/ni.c

1122

for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {

sys/dev/drm/radeon/ni.c

1128

simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;

sys/dev/drm/radeon/ni.c

1132

rdev->config.cayman.active_simds = hweight32(~tmp);

sys/dev/drm/radeon/ni.c

1148

if ((rdev->config.cayman.max_backends_per_se == 1) &&

sys/dev/drm/radeon/ni.c

1160

rdev->config.cayman.max_backends_per_se *

sys/dev/drm/radeon/ni.c

1161

rdev->config.cayman.max_shader_engines,

sys/dev/drm/radeon/ni.c

1164

rdev->config.cayman.backend_map = tmp;

sys/dev/drm/radeon/ni.c

1168

for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)

sys/dev/drm/radeon/ni.c

1190

smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);

sys/dev/drm/radeon/ni.c

1206

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/ni.c

1207

POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |

sys/dev/drm/radeon/ni.c

1208

SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));

sys/dev/drm/radeon/ni.c

1210

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |

sys/dev/drm/radeon/ni.c

1211

SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |

sys/dev/drm/radeon/ni.c

1212

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));

sys/dev/drm/radeon/ni.c

1219

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |

sys/dev/drm/radeon/ni.c

1573

radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);

sys/dev/drm/radeon/ni.c

916

rdev->config.cayman.max_shader_engines = 2;

sys/dev/drm/radeon/ni.c

917

rdev->config.cayman.max_pipes_per_simd = 4;

sys/dev/drm/radeon/ni.c

918

rdev->config.cayman.max_tile_pipes = 8;

sys/dev/drm/radeon/ni.c

919

rdev->config.cayman.max_simds_per_se = 12;

sys/dev/drm/radeon/ni.c

920

rdev->config.cayman.max_backends_per_se = 4;

sys/dev/drm/radeon/ni.c

921

rdev->config.cayman.max_texture_channel_caches = 8;

sys/dev/drm/radeon/ni.c

922

rdev->config.cayman.max_gprs = 256;

sys/dev/drm/radeon/ni.c

923

rdev->config.cayman.max_threads = 256;

sys/dev/drm/radeon/ni.c

924

rdev->config.cayman.max_gs_threads = 32;

sys/dev/drm/radeon/ni.c

925

rdev->config.cayman.max_stack_entries = 512;

sys/dev/drm/radeon/ni.c

926

rdev->config.cayman.sx_num_of_sets = 8;

sys/dev/drm/radeon/ni.c

927

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/drm/radeon/ni.c

928

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/ni.c

929

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/ni.c

930

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/drm/radeon/ni.c

931

rdev->config.cayman.sq_num_cf_insts = 2;

sys/dev/drm/radeon/ni.c

933

rdev->config.cayman.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/ni.c

934

rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/ni.c

935

rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/ni.c

940

rdev->config.cayman.max_shader_engines = 1;

sys/dev/drm/radeon/ni.c

941

rdev->config.cayman.max_pipes_per_simd = 4;

sys/dev/drm/radeon/ni.c

942

rdev->config.cayman.max_tile_pipes = 2;

sys/dev/drm/radeon/ni.c

957

rdev->config.cayman.max_simds_per_se = 6;

sys/dev/drm/radeon/ni.c

958

rdev->config.cayman.max_backends_per_se = 2;

sys/dev/drm/radeon/ni.c

959

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/drm/radeon/ni.c

960

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/drm/radeon/ni.c

961

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/ni.c

962

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/ni.c

971

rdev->config.cayman.max_simds_per_se = 4;

sys/dev/drm/radeon/ni.c

972

rdev->config.cayman.max_backends_per_se = 2;

sys/dev/drm/radeon/ni.c

973

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/drm/radeon/ni.c

974

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/drm/radeon/ni.c

975

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/drm/radeon/ni.c

976

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/drm/radeon/ni.c

985

rdev->config.cayman.max_simds_per_se = 3;

sys/dev/drm/radeon/ni.c

986

rdev->config.cayman.max_backends_per_se = 1;

sys/dev/drm/radeon/ni.c

987

rdev->config.cayman.max_hw_contexts = 4;

sys/dev/drm/radeon/ni.c

988

rdev->config.cayman.sx_max_export_size = 128;

sys/dev/drm/radeon/ni.c

989

rdev->config.cayman.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/ni.c

990

rdev->config.cayman.sx_max_export_smx_size = 96;

sys/dev/drm/radeon/ni.c

992

rdev->config.cayman.max_simds_per_se = 2;

sys/dev/drm/radeon/ni.c

993

rdev->config.cayman.max_backends_per_se = 1;

sys/dev/drm/radeon/ni.c

994

rdev->config.cayman.max_hw_contexts = 4;

sys/dev/drm/radeon/ni.c

995

rdev->config.cayman.sx_max_export_size = 128;

sys/dev/drm/radeon/ni.c

996

rdev->config.cayman.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/ni.c

997

rdev->config.cayman.sx_max_export_smx_size = 96;

sys/dev/drm/radeon/ni.c

999

rdev->config.cayman.max_texture_channel_caches = 2;

sys/dev/drm/radeon/r100.c

2062

p->rdev->config.r100.reg_safe_bm,

sys/dev/drm/radeon/r100.c

2063

p->rdev->config.r100.reg_safe_bm_size,

sys/dev/drm/radeon/r100.c

2067

p->rdev->config.r100.reg_safe_bm,

sys/dev/drm/radeon/r100.c

2068

p->rdev->config.r100.reg_safe_bm_size,

sys/dev/drm/radeon/r100.c

2919

rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;

sys/dev/drm/radeon/r100.c

2920

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);

sys/dev/drm/radeon/r100.c

2922

rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;

sys/dev/drm/radeon/r100.c

2923

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);

sys/dev/drm/radeon/r100.c

3938

rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/r100.c

844

radeon_ring_write(ring, rdev->config.r100.hdp_cntl |

sys/dev/drm/radeon/r100.c

847

radeon_ring_write(ring, rdev->config.r100.hdp_cntl);

sys/dev/drm/radeon/r200.c

548

rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;

sys/dev/drm/radeon/r200.c

549

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);

sys/dev/drm/radeon/r300.c

1294

p->rdev->config.r300.reg_safe_bm,

sys/dev/drm/radeon/r300.c

1295

p->rdev->config.r300.reg_safe_bm_size,

sys/dev/drm/radeon/r300.c

1316

rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;

sys/dev/drm/radeon/r300.c

1317

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);

sys/dev/drm/radeon/r300.c

1418

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/r300.c

227

radeon_ring_write(ring, rdev->config.r300.hdp_cntl |

sys/dev/drm/radeon/r300.c

230

radeon_ring_write(ring, rdev->config.r300.hdp_cntl);

sys/dev/drm/radeon/r420.c

215

radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);

sys/dev/drm/radeon/r420.c

219

radeon_ring_write(ring, rdev->config.r300.resync_scratch);

sys/dev/drm/radeon/r420.c

237

radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);

sys/dev/drm/radeon/r420.c

283

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/r420.c

80

rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;

sys/dev/drm/radeon/r420.c

81

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);

sys/dev/drm/radeon/r520.c

203

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/r600.c

1995

rdev->config.r600.tiling_group_size = 256;

sys/dev/drm/radeon/r600.c

1998

rdev->config.r600.max_pipes = 4;

sys/dev/drm/radeon/r600.c

1999

rdev->config.r600.max_tile_pipes = 8;

sys/dev/drm/radeon/r600.c

2000

rdev->config.r600.max_simds = 4;

sys/dev/drm/radeon/r600.c

2001

rdev->config.r600.max_backends = 4;

sys/dev/drm/radeon/r600.c

2002

rdev->config.r600.max_gprs = 256;

sys/dev/drm/radeon/r600.c

2003

rdev->config.r600.max_threads = 192;

sys/dev/drm/radeon/r600.c

2004

rdev->config.r600.max_stack_entries = 256;

sys/dev/drm/radeon/r600.c

2005

rdev->config.r600.max_hw_contexts = 8;

sys/dev/drm/radeon/r600.c

2006

rdev->config.r600.max_gs_threads = 16;

sys/dev/drm/radeon/r600.c

2007

rdev->config.r600.sx_max_export_size = 128;

sys/dev/drm/radeon/r600.c

2008

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/r600.c

2009

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/drm/radeon/r600.c

2010

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/drm/radeon/r600.c

2014

rdev->config.r600.max_pipes = 2;

sys/dev/drm/radeon/r600.c

2015

rdev->config.r600.max_tile_pipes = 2;

sys/dev/drm/radeon/r600.c

2016

rdev->config.r600.max_simds = 3;

sys/dev/drm/radeon/r600.c

2017

rdev->config.r600.max_backends = 1;

sys/dev/drm/radeon/r600.c

2018

rdev->config.r600.max_gprs = 128;

sys/dev/drm/radeon/r600.c

2019

rdev->config.r600.max_threads = 192;

sys/dev/drm/radeon/r600.c

2020

rdev->config.r600.max_stack_entries = 128;

sys/dev/drm/radeon/r600.c

2021

rdev->config.r600.max_hw_contexts = 8;

sys/dev/drm/radeon/r600.c

2022

rdev->config.r600.max_gs_threads = 4;

sys/dev/drm/radeon/r600.c

2023

rdev->config.r600.sx_max_export_size = 128;

sys/dev/drm/radeon/r600.c

2024

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/r600.c

2025

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/drm/radeon/r600.c

2026

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/drm/radeon/r600.c

2032

rdev->config.r600.max_pipes = 1;

sys/dev/drm/radeon/r600.c

2033

rdev->config.r600.max_tile_pipes = 1;

sys/dev/drm/radeon/r600.c

2034

rdev->config.r600.max_simds = 2;

sys/dev/drm/radeon/r600.c

2035

rdev->config.r600.max_backends = 1;

sys/dev/drm/radeon/r600.c

2036

rdev->config.r600.max_gprs = 128;

sys/dev/drm/radeon/r600.c

2037

rdev->config.r600.max_threads = 192;

sys/dev/drm/radeon/r600.c

2038

rdev->config.r600.max_stack_entries = 128;

sys/dev/drm/radeon/r600.c

2039

rdev->config.r600.max_hw_contexts = 4;

sys/dev/drm/radeon/r600.c

2040

rdev->config.r600.max_gs_threads = 4;

sys/dev/drm/radeon/r600.c

2041

rdev->config.r600.sx_max_export_size = 128;

sys/dev/drm/radeon/r600.c

2042

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/r600.c

2043

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/drm/radeon/r600.c

2044

rdev->config.r600.sq_num_cf_insts = 1;

sys/dev/drm/radeon/r600.c

2047

rdev->config.r600.max_pipes = 4;

sys/dev/drm/radeon/r600.c

2048

rdev->config.r600.max_tile_pipes = 4;

sys/dev/drm/radeon/r600.c

2049

rdev->config.r600.max_simds = 4;

sys/dev/drm/radeon/r600.c

2050

rdev->config.r600.max_backends = 4;

sys/dev/drm/radeon/r600.c

2051

rdev->config.r600.max_gprs = 192;

sys/dev/drm/radeon/r600.c

2052

rdev->config.r600.max_threads = 192;

sys/dev/drm/radeon/r600.c

2053

rdev->config.r600.max_stack_entries = 256;

sys/dev/drm/radeon/r600.c

2054

rdev->config.r600.max_hw_contexts = 8;

sys/dev/drm/radeon/r600.c

2055

rdev->config.r600.max_gs_threads = 16;

sys/dev/drm/radeon/r600.c

2056

rdev->config.r600.sx_max_export_size = 128;

sys/dev/drm/radeon/r600.c

2057

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/r600.c

2058

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/drm/radeon/r600.c

2059

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/drm/radeon/r600.c

2079

switch (rdev->config.r600.max_tile_pipes) {

sys/dev/drm/radeon/r600.c

2095

rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;

sys/dev/drm/radeon/r600.c

2096

rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);

sys/dev/drm/radeon/r600.c

2111

tmp = rdev->config.r600.max_simds -

sys/dev/drm/radeon/r600.c

2113

rdev->config.r600.active_simds = tmp;

sys/dev/drm/radeon/r600.c

2117

for (i = 0; i < rdev->config.r600.max_backends; i++)

sys/dev/drm/radeon/r600.c

2121

for (i = 0; i < rdev->config.r600.max_backends; i++)

sys/dev/drm/radeon/r600.c

2125

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,

sys/dev/drm/radeon/r600.c

2128

rdev->config.r600.backend_map = tmp;

sys/dev/drm/radeon/r600.c

2130

rdev->config.r600.tile_config = tiling_config;

sys/dev/drm/radeon/r600.c

2304

tmp = rdev->config.r600.max_pipes * 16;

sys/dev/drm/radeon/r600.c

2710

radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);

sys/dev/drm/radeon/r600.c

2713

radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);

sys/dev/drm/radeon/r600_cs.c

2281

track->npipes = p->rdev->config.r600.tiling_npipes;

sys/dev/drm/radeon/r600_cs.c

2282

track->nbanks = p->rdev->config.r600.tiling_nbanks;

sys/dev/drm/radeon/r600_cs.c

2283

track->group_size = p->rdev->config.r600.tiling_group_size;

sys/dev/drm/radeon/r600_cs.c

2285

track->npipes = p->rdev->config.rv770.tiling_npipes;

sys/dev/drm/radeon/r600_cs.c

2286

track->nbanks = p->rdev->config.rv770.tiling_nbanks;

sys/dev/drm/radeon/r600_cs.c

2287

track->group_size = p->rdev->config.rv770.tiling_group_size;

sys/dev/drm/radeon/radeon.h

2324

union radeon_asic_config config;

sys/dev/drm/radeon/radeon_kms.c

288

*value = rdev->config.cik.tile_config;

sys/dev/drm/radeon/radeon_kms.c

290

*value = rdev->config.si.tile_config;

sys/dev/drm/radeon/radeon_kms.c

292

*value = rdev->config.cayman.tile_config;

sys/dev/drm/radeon/radeon_kms.c

294

*value = rdev->config.evergreen.tile_config;

sys/dev/drm/radeon/radeon_kms.c

296

*value = rdev->config.rv770.tile_config;

sys/dev/drm/radeon/radeon_kms.c

298

*value = rdev->config.r600.tile_config;

sys/dev/drm/radeon/radeon_kms.c

342

*value = rdev->config.cik.max_backends_per_se *

sys/dev/drm/radeon/radeon_kms.c

343

rdev->config.cik.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

345

*value = rdev->config.si.max_backends_per_se *

sys/dev/drm/radeon/radeon_kms.c

346

rdev->config.si.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

348

*value = rdev->config.cayman.max_backends_per_se *

sys/dev/drm/radeon/radeon_kms.c

349

rdev->config.cayman.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

351

*value = rdev->config.evergreen.max_backends;

sys/dev/drm/radeon/radeon_kms.c

353

*value = rdev->config.rv770.max_backends;

sys/dev/drm/radeon/radeon_kms.c

355

*value = rdev->config.r600.max_backends;

sys/dev/drm/radeon/radeon_kms.c

362

*value = rdev->config.cik.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

364

*value = rdev->config.si.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

366

*value = rdev->config.cayman.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

368

*value = rdev->config.evergreen.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

370

*value = rdev->config.rv770.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

372

*value = rdev->config.r600.max_tile_pipes;

sys/dev/drm/radeon/radeon_kms.c

382

*value = rdev->config.cik.backend_map;

sys/dev/drm/radeon/radeon_kms.c

384

*value = rdev->config.si.backend_map;

sys/dev/drm/radeon/radeon_kms.c

386

*value = rdev->config.cayman.backend_map;

sys/dev/drm/radeon/radeon_kms.c

388

*value = rdev->config.evergreen.backend_map;

sys/dev/drm/radeon/radeon_kms.c

390

*value = rdev->config.rv770.backend_map;

sys/dev/drm/radeon/radeon_kms.c

392

*value = rdev->config.r600.backend_map;

sys/dev/drm/radeon/radeon_kms.c

411

*value = rdev->config.cik.max_cu_per_sh;

sys/dev/drm/radeon/radeon_kms.c

413

*value = rdev->config.si.max_cu_per_sh;

sys/dev/drm/radeon/radeon_kms.c

415

*value = rdev->config.cayman.max_pipes_per_simd;

sys/dev/drm/radeon/radeon_kms.c

417

*value = rdev->config.evergreen.max_pipes;

sys/dev/drm/radeon/radeon_kms.c

419

*value = rdev->config.rv770.max_pipes;

sys/dev/drm/radeon/radeon_kms.c

421

*value = rdev->config.r600.max_pipes;

sys/dev/drm/radeon/radeon_kms.c

437

*value = rdev->config.cik.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

439

*value = rdev->config.si.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

441

*value = rdev->config.cayman.max_shader_engines;

sys/dev/drm/radeon/radeon_kms.c

443

*value = rdev->config.evergreen.num_ses;

sys/dev/drm/radeon/radeon_kms.c

449

*value = rdev->config.cik.max_sh_per_se;

sys/dev/drm/radeon/radeon_kms.c

451

*value = rdev->config.si.max_sh_per_se;

sys/dev/drm/radeon/radeon_kms.c

484

value = rdev->config.cik.tile_mode_array;

sys/dev/drm/radeon/radeon_kms.c

487

value = rdev->config.si.tile_mode_array;

sys/dev/drm/radeon/radeon_kms.c

496

value = rdev->config.cik.macrotile_mode_array;

sys/dev/drm/radeon/radeon_kms.c

508

*value = rdev->config.cik.backend_enable_mask;

sys/dev/drm/radeon/radeon_kms.c

510

*value = rdev->config.si.backend_enable_mask;

sys/dev/drm/radeon/radeon_kms.c

546

*value = rdev->config.cik.active_cus;

sys/dev/drm/radeon/radeon_kms.c

548

*value = rdev->config.si.active_cus;

sys/dev/drm/radeon/radeon_kms.c

550

*value = rdev->config.cayman.active_simds;

sys/dev/drm/radeon/radeon_kms.c

552

*value = rdev->config.evergreen.active_simds;

sys/dev/drm/radeon/radeon_kms.c

554

*value = rdev->config.rv770.active_simds;

sys/dev/drm/radeon/radeon_kms.c

556

*value = rdev->config.r600.active_simds;

sys/dev/drm/radeon/rs400.c

437

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/rs600.c

1010

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/rs600.c

947

rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;

sys/dev/drm/radeon/rs600.c

948

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);

sys/dev/drm/radeon/rs690.c

726

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/rv515.c

547

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/drm/radeon/rv515.c

607

rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;

sys/dev/drm/radeon/rv515.c

608

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);

sys/dev/drm/radeon/rv770.c

1187

rdev->config.rv770.tiling_group_size = 256;

sys/dev/drm/radeon/rv770.c

1190

rdev->config.rv770.max_pipes = 4;

sys/dev/drm/radeon/rv770.c

1191

rdev->config.rv770.max_tile_pipes = 8;

sys/dev/drm/radeon/rv770.c

1192

rdev->config.rv770.max_simds = 10;

sys/dev/drm/radeon/rv770.c

1193

rdev->config.rv770.max_backends = 4;

sys/dev/drm/radeon/rv770.c

1194

rdev->config.rv770.max_gprs = 256;

sys/dev/drm/radeon/rv770.c

1195

rdev->config.rv770.max_threads = 248;

sys/dev/drm/radeon/rv770.c

1196

rdev->config.rv770.max_stack_entries = 512;

sys/dev/drm/radeon/rv770.c

1197

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/drm/radeon/rv770.c

1198

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/drm/radeon/rv770.c

1199

rdev->config.rv770.sx_max_export_size = 128;

sys/dev/drm/radeon/rv770.c

1200

rdev->config.rv770.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/rv770.c

1201

rdev->config.rv770.sx_max_export_smx_size = 112;

sys/dev/drm/radeon/rv770.c

1202

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/drm/radeon/rv770.c

1204

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/drm/radeon/rv770.c

1205

rdev->config.rv770.sc_prim_fifo_size = 0xF9;

sys/dev/drm/radeon/rv770.c

1206

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/rv770.c

1207

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/drm/radeon/rv770.c

1210

rdev->config.rv770.max_pipes = 2;

sys/dev/drm/radeon/rv770.c

1211

rdev->config.rv770.max_tile_pipes = 4;

sys/dev/drm/radeon/rv770.c

1212

rdev->config.rv770.max_simds = 8;

sys/dev/drm/radeon/rv770.c

1213

rdev->config.rv770.max_backends = 2;

sys/dev/drm/radeon/rv770.c

1214

rdev->config.rv770.max_gprs = 128;

sys/dev/drm/radeon/rv770.c

1215

rdev->config.rv770.max_threads = 248;

sys/dev/drm/radeon/rv770.c

1216

rdev->config.rv770.max_stack_entries = 256;

sys/dev/drm/radeon/rv770.c

1217

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/drm/radeon/rv770.c

1218

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/drm/radeon/rv770.c

1219

rdev->config.rv770.sx_max_export_size = 256;

sys/dev/drm/radeon/rv770.c

1220

rdev->config.rv770.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/rv770.c

1221

rdev->config.rv770.sx_max_export_smx_size = 224;

sys/dev/drm/radeon/rv770.c

1222

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/drm/radeon/rv770.c

1224

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/drm/radeon/rv770.c

1225

rdev->config.rv770.sc_prim_fifo_size = 0xf9;

sys/dev/drm/radeon/rv770.c

1226

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/rv770.c

1227

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/drm/radeon/rv770.c

1228

if (rdev->config.rv770.sx_max_export_pos_size > 16) {

sys/dev/drm/radeon/rv770.c

1229

rdev->config.rv770.sx_max_export_pos_size -= 16;

sys/dev/drm/radeon/rv770.c

1230

rdev->config.rv770.sx_max_export_smx_size += 16;

sys/dev/drm/radeon/rv770.c

1234

rdev->config.rv770.max_pipes = 2;

sys/dev/drm/radeon/rv770.c

1235

rdev->config.rv770.max_tile_pipes = 2;

sys/dev/drm/radeon/rv770.c

1236

rdev->config.rv770.max_simds = 2;

sys/dev/drm/radeon/rv770.c

1237

rdev->config.rv770.max_backends = 1;

sys/dev/drm/radeon/rv770.c

1238

rdev->config.rv770.max_gprs = 256;

sys/dev/drm/radeon/rv770.c

1239

rdev->config.rv770.max_threads = 192;

sys/dev/drm/radeon/rv770.c

1240

rdev->config.rv770.max_stack_entries = 256;

sys/dev/drm/radeon/rv770.c

1241

rdev->config.rv770.max_hw_contexts = 4;

sys/dev/drm/radeon/rv770.c

1242

rdev->config.rv770.max_gs_threads = 8 * 2;

sys/dev/drm/radeon/rv770.c

1243

rdev->config.rv770.sx_max_export_size = 128;

sys/dev/drm/radeon/rv770.c

1244

rdev->config.rv770.sx_max_export_pos_size = 16;

sys/dev/drm/radeon/rv770.c

1245

rdev->config.rv770.sx_max_export_smx_size = 112;

sys/dev/drm/radeon/rv770.c

1246

rdev->config.rv770.sq_num_cf_insts = 1;

sys/dev/drm/radeon/rv770.c

1248

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/drm/radeon/rv770.c

1249

rdev->config.rv770.sc_prim_fifo_size = 0x40;

sys/dev/drm/radeon/rv770.c

1250

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/rv770.c

1251

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/drm/radeon/rv770.c

1254

rdev->config.rv770.max_pipes = 4;

sys/dev/drm/radeon/rv770.c

1255

rdev->config.rv770.max_tile_pipes = 4;

sys/dev/drm/radeon/rv770.c

1256

rdev->config.rv770.max_simds = 8;

sys/dev/drm/radeon/rv770.c

1257

rdev->config.rv770.max_backends = 4;

sys/dev/drm/radeon/rv770.c

1258

rdev->config.rv770.max_gprs = 256;

sys/dev/drm/radeon/rv770.c

1259

rdev->config.rv770.max_threads = 248;

sys/dev/drm/radeon/rv770.c

1260

rdev->config.rv770.max_stack_entries = 512;

sys/dev/drm/radeon/rv770.c

1261

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/drm/radeon/rv770.c

1262

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/drm/radeon/rv770.c

1263

rdev->config.rv770.sx_max_export_size = 256;

sys/dev/drm/radeon/rv770.c

1264

rdev->config.rv770.sx_max_export_pos_size = 32;

sys/dev/drm/radeon/rv770.c

1265

rdev->config.rv770.sx_max_export_smx_size = 224;

sys/dev/drm/radeon/rv770.c

1266

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/drm/radeon/rv770.c

1268

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/drm/radeon/rv770.c

1269

rdev->config.rv770.sc_prim_fifo_size = 0x100;

sys/dev/drm/radeon/rv770.c

1270

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/rv770.c

1271

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/drm/radeon/rv770.c

1273

if (rdev->config.rv770.sx_max_export_pos_size > 16) {

sys/dev/drm/radeon/rv770.c

1274

rdev->config.rv770.sx_max_export_pos_size -= 16;

sys/dev/drm/radeon/rv770.c

1275

rdev->config.rv770.sx_max_export_smx_size += 16;

sys/dev/drm/radeon/rv770.c

1313

tmp = rdev->config.rv770.max_simds -

sys/dev/drm/radeon/rv770.c

1315

rdev->config.rv770.active_simds = tmp;

sys/dev/drm/radeon/rv770.c

1317

switch (rdev->config.rv770.max_tile_pipes) {

sys/dev/drm/radeon/rv770.c

1332

rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;

sys/dev/drm/radeon/rv770.c

1336

for (i = 0; i < rdev->config.rv770.max_backends; i++)

sys/dev/drm/radeon/rv770.c

1340

for (i = 0; i < rdev->config.rv770.max_backends; i++)

sys/dev/drm/radeon/rv770.c

1344

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,

sys/dev/drm/radeon/rv770.c

1347

rdev->config.rv770.backend_map = tmp;

sys/dev/drm/radeon/rv770.c

1357

rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);

sys/dev/drm/radeon/rv770.c

1370

rdev->config.rv770.tile_config = gb_tiling_config;

sys/dev/drm/radeon/rv770.c

1408

smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);

sys/dev/drm/radeon/rv770.c

1441

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/rv770.c

1442

POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |

sys/dev/drm/radeon/rv770.c

1443

SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));

sys/dev/drm/radeon/rv770.c

1445

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |

sys/dev/drm/radeon/rv770.c

1446

SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |

sys/dev/drm/radeon/rv770.c

1447

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));

sys/dev/drm/radeon/rv770.c

1457

sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |

sys/dev/drm/radeon/rv770.c

1494

WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |

sys/dev/drm/radeon/rv770.c

1495

NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |

sys/dev/drm/radeon/rv770.c

1496

NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));

sys/dev/drm/radeon/rv770.c

1498

WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |

sys/dev/drm/radeon/rv770.c

1499

NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));

sys/dev/drm/radeon/rv770.c

1501

sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |

sys/dev/drm/radeon/rv770.c

1502

NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |

sys/dev/drm/radeon/rv770.c

1503

NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));

sys/dev/drm/radeon/rv770.c

1504

if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)

sys/dev/drm/radeon/rv770.c

1505

sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);

sys/dev/drm/radeon/rv770.c

1507

sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);

sys/dev/drm/radeon/rv770.c

1510

WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/drm/radeon/rv770.c

1511

NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));

sys/dev/drm/radeon/rv770.c

1513

WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/drm/radeon/rv770.c

1514

NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));

sys/dev/drm/radeon/rv770.c

1516

sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/drm/radeon/rv770.c

1517

SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/drm/radeon/rv770.c

1518

SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/drm/radeon/rv770.c

1519

SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));

sys/dev/drm/radeon/rv770.c

1553

num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;

sys/dev/drm/radeon/si.c

2481

u32 *tile = rdev->config.si.tile_mode_array;

sys/dev/drm/radeon/si.c

2483

ARRAY_SIZE(rdev->config.si.tile_mode_array);

sys/dev/drm/radeon/si.c

2486

switch (rdev->config.si.mem_row_size_in_kb) {

sys/dev/drm/radeon/si.c

3054

rdev->config.si.backend_enable_mask = enabled_rbs;

sys/dev/drm/radeon/si.c

3090

rdev->config.si.max_shader_engines = 2;

sys/dev/drm/radeon/si.c

3091

rdev->config.si.max_tile_pipes = 12;

sys/dev/drm/radeon/si.c

3092

rdev->config.si.max_cu_per_sh = 8;

sys/dev/drm/radeon/si.c

3093

rdev->config.si.max_sh_per_se = 2;

sys/dev/drm/radeon/si.c

3094

rdev->config.si.max_backends_per_se = 4;

sys/dev/drm/radeon/si.c

3095

rdev->config.si.max_texture_channel_caches = 12;

sys/dev/drm/radeon/si.c

3096

rdev->config.si.max_gprs = 256;

sys/dev/drm/radeon/si.c

3097

rdev->config.si.max_gs_threads = 32;

sys/dev/drm/radeon/si.c

3098

rdev->config.si.max_hw_contexts = 8;

sys/dev/drm/radeon/si.c

3100

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/si.c

3101

rdev->config.si.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/si.c

3102

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/si.c

3103

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/si.c

3107

rdev->config.si.max_shader_engines = 2;

sys/dev/drm/radeon/si.c

3108

rdev->config.si.max_tile_pipes = 8;

sys/dev/drm/radeon/si.c

3109

rdev->config.si.max_cu_per_sh = 5;

sys/dev/drm/radeon/si.c

3110

rdev->config.si.max_sh_per_se = 2;

sys/dev/drm/radeon/si.c

3111

rdev->config.si.max_backends_per_se = 4;

sys/dev/drm/radeon/si.c

3112

rdev->config.si.max_texture_channel_caches = 8;

sys/dev/drm/radeon/si.c

3113

rdev->config.si.max_gprs = 256;

sys/dev/drm/radeon/si.c

3114

rdev->config.si.max_gs_threads = 32;

sys/dev/drm/radeon/si.c

3115

rdev->config.si.max_hw_contexts = 8;

sys/dev/drm/radeon/si.c

3117

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/si.c

3118

rdev->config.si.sc_prim_fifo_size_backend = 0x100;

sys/dev/drm/radeon/si.c

3119

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/si.c

3120

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/si.c

3125

rdev->config.si.max_shader_engines = 1;

sys/dev/drm/radeon/si.c

3126

rdev->config.si.max_tile_pipes = 4;

sys/dev/drm/radeon/si.c

3127

rdev->config.si.max_cu_per_sh = 5;

sys/dev/drm/radeon/si.c

3128

rdev->config.si.max_sh_per_se = 2;

sys/dev/drm/radeon/si.c

3129

rdev->config.si.max_backends_per_se = 4;

sys/dev/drm/radeon/si.c

3130

rdev->config.si.max_texture_channel_caches = 4;

sys/dev/drm/radeon/si.c

3131

rdev->config.si.max_gprs = 256;

sys/dev/drm/radeon/si.c

3132

rdev->config.si.max_gs_threads = 32;

sys/dev/drm/radeon/si.c

3133

rdev->config.si.max_hw_contexts = 8;

sys/dev/drm/radeon/si.c

3135

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/si.c

3136

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/drm/radeon/si.c

3137

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/si.c

3138

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/si.c

3142

rdev->config.si.max_shader_engines = 1;

sys/dev/drm/radeon/si.c

3143

rdev->config.si.max_tile_pipes = 4;

sys/dev/drm/radeon/si.c

3144

rdev->config.si.max_cu_per_sh = 6;

sys/dev/drm/radeon/si.c

3145

rdev->config.si.max_sh_per_se = 1;

sys/dev/drm/radeon/si.c

3146

rdev->config.si.max_backends_per_se = 2;

sys/dev/drm/radeon/si.c

3147

rdev->config.si.max_texture_channel_caches = 4;

sys/dev/drm/radeon/si.c

3148

rdev->config.si.max_gprs = 256;

sys/dev/drm/radeon/si.c

3149

rdev->config.si.max_gs_threads = 16;

sys/dev/drm/radeon/si.c

3150

rdev->config.si.max_hw_contexts = 8;

sys/dev/drm/radeon/si.c

3152

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/si.c

3153

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/drm/radeon/si.c

3154

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/si.c

3155

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/si.c

3159

rdev->config.si.max_shader_engines = 1;

sys/dev/drm/radeon/si.c

3160

rdev->config.si.max_tile_pipes = 4;

sys/dev/drm/radeon/si.c

3161

rdev->config.si.max_cu_per_sh = 5;

sys/dev/drm/radeon/si.c

3162

rdev->config.si.max_sh_per_se = 1;

sys/dev/drm/radeon/si.c

3163

rdev->config.si.max_backends_per_se = 1;

sys/dev/drm/radeon/si.c

3164

rdev->config.si.max_texture_channel_caches = 2;

sys/dev/drm/radeon/si.c

3165

rdev->config.si.max_gprs = 256;

sys/dev/drm/radeon/si.c

3166

rdev->config.si.max_gs_threads = 16;

sys/dev/drm/radeon/si.c

3167

rdev->config.si.max_hw_contexts = 8;

sys/dev/drm/radeon/si.c

3169

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/drm/radeon/si.c

3170

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/drm/radeon/si.c

3171

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/drm/radeon/si.c

3172

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/drm/radeon/si.c

3197

rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;

sys/dev/drm/radeon/si.c

3198

rdev->config.si.mem_max_burst_length_bytes = 256;

sys/dev/drm/radeon/si.c

3200

rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/drm/radeon/si.c

3201

if (rdev->config.si.mem_row_size_in_kb > 4)

sys/dev/drm/radeon/si.c

3202

rdev->config.si.mem_row_size_in_kb = 4;

sys/dev/drm/radeon/si.c

3204

rdev->config.si.shader_engine_tile_size = 32;

sys/dev/drm/radeon/si.c

3205

rdev->config.si.num_gpus = 1;

sys/dev/drm/radeon/si.c

3206

rdev->config.si.multi_gpu_tile_size = 64;

sys/dev/drm/radeon/si.c

3210

switch (rdev->config.si.mem_row_size_in_kb) {

sys/dev/drm/radeon/si.c

3230

rdev->config.si.tile_config = 0;

sys/dev/drm/radeon/si.c

3231

switch (rdev->config.si.num_tile_pipes) {

sys/dev/drm/radeon/si.c

3233

rdev->config.si.tile_config |= (0 << 0);

sys/dev/drm/radeon/si.c

3236

rdev->config.si.tile_config |= (1 << 0);

sys/dev/drm/radeon/si.c

3239

rdev->config.si.tile_config |= (2 << 0);

sys/dev/drm/radeon/si.c

3244

rdev->config.si.tile_config |= (3 << 0);

sys/dev/drm/radeon/si.c

3249

rdev->config.si.tile_config |= 0 << 4;

sys/dev/drm/radeon/si.c

3252

rdev->config.si.tile_config |= 1 << 4;

sys/dev/drm/radeon/si.c

3256

rdev->config.si.tile_config |= 2 << 4;

sys/dev/drm/radeon/si.c

3259

rdev->config.si.tile_config |=

sys/dev/drm/radeon/si.c

3261

rdev->config.si.tile_config |=

sys/dev/drm/radeon/si.c

3278

si_setup_rb(rdev, rdev->config.si.max_shader_engines,

sys/dev/drm/radeon/si.c

3279

rdev->config.si.max_sh_per_se,

sys/dev/drm/radeon/si.c

3280

rdev->config.si.max_backends_per_se);

sys/dev/drm/radeon/si.c

3282

si_setup_spi(rdev, rdev->config.si.max_shader_engines,

sys/dev/drm/radeon/si.c

3283

rdev->config.si.max_sh_per_se,

sys/dev/drm/radeon/si.c

3284

rdev->config.si.max_cu_per_sh);

sys/dev/drm/radeon/si.c

3286

rdev->config.si.active_cus = 0;

sys/dev/drm/radeon/si.c

3287

for (i = 0; i < rdev->config.si.max_shader_engines; i++) {

sys/dev/drm/radeon/si.c

3288

for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {

sys/dev/drm/radeon/si.c

3289

rdev->config.si.active_cus +=

sys/dev/drm/radeon/si.c

3304

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |

sys/dev/drm/radeon/si.c

3305

SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |

sys/dev/drm/radeon/si.c

3306

SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |

sys/dev/drm/radeon/si.c

3307

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));

sys/dev/drm/radeon/si.c

3561

radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);

sys/dev/drm/radeon/si.c

5300

for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {

sys/dev/drm/radeon/si.c

5314

for (i = 0; i < rdev->config.si.max_shader_engines; i++) {

sys/dev/drm/radeon/si.c

5315

for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {

sys/dev/drm/radeon/si.c

5319

for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {

sys/dev/misc/kbd/kbd.c

109

kbd_reinit_struct(keyboard_t *kbd, int config, int pref)

sys/dev/misc/kbd/kbd.c

113

kbd->kb_config = config & ~KB_CONF_PROBE_ONLY;

sys/dev/misc/kbd/kbd.c

130

kbd_init_struct(keyboard_t *kbd, char *name, int type, int unit, int config,

sys/dev/misc/kbd/kbd.c

140

kbd_reinit_struct(kbd, config, pref);

sys/dev/misc/kbd/kbdreg.h

237

#define KEYBOARD_DRIVER(name, sw, config) \

sys/dev/misc/kbd/kbdreg.h

239

{ NULL }, #name, &sw, config \

sys/dev/misc/kbd/kbdreg.h

253

int unit, int config, int pref,

sys/dev/misc/kbd/kbdreg.h

256

int config, int pref);

sys/dev/misc/ppc/ppc.c

739

goto config;

sys/dev/misc/ppc/ppc.c

758

config:

sys/dev/misc/psm/psm.c

1090

if (sc->config & PSM_CONFIG_IGNPORTERROR)

sys/dev/misc/psm/psm.c

1097

if (sc->config & PSM_CONFIG_NORESET) {

sys/dev/misc/psm/psm.c

1424

sc->config = flags & PSM_CONFIG_FLAGS;

sys/dev/misc/psm/psm.c

1427

sc->config |=

sys/dev/misc/psm/psm.c

1542

if (sc->config & PSM_CONFIG_IGNPORTERROR)

sys/dev/misc/psm/psm.c

1552

if (sc->config & PSM_CONFIG_NORESET) {

sys/dev/misc/psm/psm.c

1637

if (sc->config & PSM_CONFIG_NOIDPROBE) {

sys/dev/misc/psm/psm.c

1658

sc->dflt_mode.accelfactor = (sc->config & PSM_CONFIG_ACCEL) >> 4;

sys/dev/misc/psm/psm.c

1659

if (sc->config & PSM_CONFIG_NOCHECKSYNC)

sys/dev/misc/psm/psm.c

1663

if (sc->config & PSM_CONFIG_FORCETAP)

sys/dev/misc/psm/psm.c

1680

if (sc->config & PSM_CONFIG_RESOLUTION)

sys/dev/misc/psm/psm.c

1683

(sc->config & PSM_CONFIG_RESOLUTION) - 1);

sys/dev/misc/psm/psm.c

2055

sc->config |= PSM_CONFIG_INITAFTERSUSPEND;

sys/dev/misc/psm/psm.c

2059

sc->config |= PSM_CONFIG_INITAFTERSUSPEND;

sys/dev/misc/psm/psm.c

2066

sc->config |= PSM_CONFIG_NOCHECKSYNC;

sys/dev/misc/psm/psm.c

2079

sc->config, sc->flags, sc->mode.packetsize);

sys/dev/misc/psm/psm.c

2082

sc->config & PSM_CONFIG_NOCHECKSYNC ? " (sync not checked)" : "");

sys/dev/misc/psm/psm.c

3061

} else if ((sc->config & PSM_CONFIG_NOCHECKSYNC) == 0 &&

sys/dev/misc/psm/psm.c

437

int config; /* driver configuration flags */

sys/dev/misc/psm/psm.c

4981

if (sc->config & PSM_CONFIG_FORCETAP)

sys/dev/misc/psm/psm.c

7474

if ((sc->config &

sys/dev/misc/psm/psm.c

7478

err = reinitialize(sc, sc->config & PSM_CONFIG_INITAFTERSUSPEND);

sys/dev/misc/syscons/syscons.c

2162

if ((sc->kbd == NULL) && (sc->config & SC_AUTODETECT_KBD)) {

sys/dev/misc/syscons/syscons.c

599

sc->config = flags;

sys/dev/misc/syscons/syscons.c

617

unit, (sc->config & SC_EFI_FB) ? "EFI_FB" : adapter_name(sc->adp),

sys/dev/misc/syscons/syscons.c

618

sc->vtys, sc->config);

sys/dev/misc/syscons/syscons.h

176

int config; /* configuration flags */

sys/dev/netif/ath/ath/if_ath.c

531

ah->config.no_pll_pwrsave = true;

sys/dev/netif/ath/ath_hal/ah_soc.h

42

uint32_t config; /* Board configuration */

sys/dev/netif/ig_hal/e1000_82575.h

70

} config;

sys/dev/netif/iwi/if_iwi.c

2624

struct iwi_configuration config;

sys/dev/netif/iwi/if_iwi.c

2642

memset(&config, 0, sizeof config);

sys/dev/netif/iwi/if_iwi.c

2643

config.bluetooth_coexistence = sc->bluetooth;

sys/dev/netif/iwi/if_iwi.c

2644

config.silence_threshold = 0x1e;

sys/dev/netif/iwi/if_iwi.c

2645

config.antenna = sc->antenna;

sys/dev/netif/iwi/if_iwi.c

2646

config.multicast_enabled = 1;

sys/dev/netif/iwi/if_iwi.c

2647

config.answer_pbreq = (ic->ic_opmode == IEEE80211_M_IBSS) ? 1 : 0;

sys/dev/netif/iwi/if_iwi.c

2648

config.disable_unicast_decryption = 1;

sys/dev/netif/iwi/if_iwi.c

2649

config.disable_multicast_decryption = 1;

sys/dev/netif/iwi/if_iwi.c

2651

config.allow_invalid_frames = 1;

sys/dev/netif/iwi/if_iwi.c

2652

config.allow_beacon_and_probe_resp = 1;

sys/dev/netif/iwi/if_iwi.c

2653

config.allow_mgt = 1;

sys/dev/netif/iwi/if_iwi.c

2656

error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config);

sys/dev/netif/iwi/if_iwi.c

2888

struct iwi_configuration config;

sys/dev/netif/iwi/if_iwi.c

2916

memset(&config, 0, sizeof config);

sys/dev/netif/iwi/if_iwi.c

2917

config.bluetooth_coexistence = sc->bluetooth;

sys/dev/netif/iwi/if_iwi.c

2918

config.antenna = sc->antenna;

sys/dev/netif/iwi/if_iwi.c

2919

config.multicast_enabled = 1;

sys/dev/netif/iwi/if_iwi.c

2921

config.use_protection = 1;

sys/dev/netif/iwi/if_iwi.c

2922

config.answer_pbreq =

sys/dev/netif/iwi/if_iwi.c

2924

config.disable_unicast_decryption = 1;

sys/dev/netif/iwi/if_iwi.c

2925

config.disable_multicast_decryption = 1;

sys/dev/netif/iwi/if_iwi.c

2927

error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config);

sys/dev/powermng/lm/lm78.c

425

u_int i, config;

sys/dev/powermng/lm/lm78.c

434

config = sc->lm_readreg(sc, LM_CONFIG);

sys/dev/powermng/lm/lm78.c

435

sc->lm_writereg(sc, LM_CONFIG, config | 0x01);

sys/dev/raid/hpt27xx/himfuncs.h

50

_HIM_INTERFACE(void, get_adapter_config, (void *adapter, HIM_ADAPTER_CONFIG *config))

sys/dev/raid/hpt27xx/himfuncs.h

67

_HIM_INTERFACE(void, get_device_config, (void *dev, HIM_DEVICE_CONFIG *config))

sys/dev/raid/hptiop/hptiop.c

100

struct hpt_iop_request_get_config *config);

sys/dev/raid/hptiop/hptiop.c

1006

config->header.size = sizeof(struct hpt_iop_request_set_config);

sys/dev/raid/hptiop/hptiop.c

1007

config->header.type = IOP_REQUEST_TYPE_SET_CONFIG;

sys/dev/raid/hptiop/hptiop.c

1008

config->header.flags = IOP_REQUEST_FLAG_SYNC_REQUEST;

sys/dev/raid/hptiop/hptiop.c

1009

config->header.result = IOP_RESULT_PENDING;

sys/dev/raid/hptiop/hptiop.c

1010

config->header.context = 0;

sys/dev/raid/hptiop/hptiop.c

1013

(u_int32_t *)config,

sys/dev/raid/hptiop/hptiop.c

102

struct hpt_iop_request_set_config *config);

sys/dev/raid/hptiop/hptiop.c

1027

struct hpt_iop_request_set_config *config)

sys/dev/raid/hptiop/hptiop.c

1035

(u_int8_t *)config + sizeof(struct hpt_iop_request_header),

sys/dev/raid/hptiop/hptiop.c

104

struct hpt_iop_request_set_config *config);

sys/dev/raid/hptiop/hptiop.c

1054

struct hpt_iop_request_set_config *config)

sys/dev/raid/hptiop/hptiop.c

106

struct hpt_iop_request_set_config *config);

sys/dev/raid/hptiop/hptiop.c

1062

(u_int8_t *)config + sizeof(struct hpt_iop_request_header),

sys/dev/raid/hptiop/hptiop.c

1506

hba->u.mvfrey.config = (struct hpt_iop_request_get_config *)

sys/dev/raid/hptiop/hptiop.c

1509

if (!hba->u.mvfrey.config) {

sys/dev/raid/hptiop/hptiop.c

910

struct hpt_iop_request_get_config * config)

sys/dev/raid/hptiop/hptiop.c

914

config->header.size = sizeof(struct hpt_iop_request_get_config);

sys/dev/raid/hptiop/hptiop.c

915

config->header.type = IOP_REQUEST_TYPE_GET_CONFIG;

sys/dev/raid/hptiop/hptiop.c

916

config->header.flags = IOP_REQUEST_FLAG_SYNC_REQUEST;

sys/dev/raid/hptiop/hptiop.c

917

config->header.result = IOP_RESULT_PENDING;

sys/dev/raid/hptiop/hptiop.c

918

config->header.context = 0;

sys/dev/raid/hptiop/hptiop.c

925

req32, (u_int32_t *)config,

sys/dev/raid/hptiop/hptiop.c

934

req32, (u_int32_t *)config,

sys/dev/raid/hptiop/hptiop.c

943

struct hpt_iop_request_get_config * config)

sys/dev/raid/hptiop/hptiop.c

96

struct hpt_iop_request_get_config *config);

sys/dev/raid/hptiop/hptiop.c

961

*config = *req;

sys/dev/raid/hptiop/hptiop.c

966

struct hpt_iop_request_get_config * config)

sys/dev/raid/hptiop/hptiop.c

968

struct hpt_iop_request_get_config *info = hba->u.mvfrey.config;

sys/dev/raid/hptiop/hptiop.c

978

config->interface_version = info->interface_version;

sys/dev/raid/hptiop/hptiop.c

979

config->firmware_version = info->firmware_version;

sys/dev/raid/hptiop/hptiop.c

98

struct hpt_iop_request_get_config *config);

sys/dev/raid/hptiop/hptiop.c

980

config->max_requests = info->max_requests;

sys/dev/raid/hptiop/hptiop.c

981

config->request_size = info->request_size;

sys/dev/raid/hptiop/hptiop.c

982

config->max_sg_count = info->max_sg_count;

sys/dev/raid/hptiop/hptiop.c

983

config->data_transfer_length = info->data_transfer_length;

sys/dev/raid/hptiop/hptiop.c

984

config->alignment_mask = info->alignment_mask;

sys/dev/raid/hptiop/hptiop.c

985

config->max_devices = info->max_devices;

sys/dev/raid/hptiop/hptiop.c

986

config->sdram_size = info->sdram_size;

sys/dev/raid/hptiop/hptiop.c

989

config->max_requests, config->request_size,

sys/dev/raid/hptiop/hptiop.c

990

config->data_transfer_length, config->max_devices,

sys/dev/raid/hptiop/hptiop.c

991

config->sdram_size));

sys/dev/raid/hptiop/hptiop.c

997

struct hpt_iop_request_set_config *config)

sys/dev/raid/hptiop/hptiop.h

350

struct hpt_iop_request_get_config *config;

sys/dev/raid/hptiop/hptiop.h

442

struct hpt_iop_request_get_config *config);

sys/dev/raid/hptiop/hptiop.h

444

struct hpt_iop_request_set_config *config);

sys/dev/raid/hptrr/himfuncs.h

51

_HIM_INTERFACE(void, get_adapter_config, (void *adapter, HIM_ADAPTER_CONFIG *config))

sys/dev/raid/hptrr/himfuncs.h

68

_HIM_INTERFACE(void, get_device_config, (void *dev, HIM_DEVICE_CONFIG *config))

sys/dev/raid/vinum/vinumext.h

126

void format_config(char *config, int len);

sys/dev/raid/vinum/vinumio.c

423

format_config(char *config, int len)

sys/dev/raid/vinum/vinumio.c

427

char *s = config;

sys/dev/raid/vinum/vinumio.c

428

char *configend = &config[len];

sys/dev/raid/vinum/vinumio.c

430

bzero(config, len);

sys/dev/raid/vinum/vinumio.c

547

if (s > &config[len - 2])

sys/dev/raid/vinum/vinumio.c

574

char *config; /* point to config data */

sys/dev/raid/vinum/vinumio.c

586

config = Malloc(MAXCONFIG); /* get space for the config data */

sys/dev/raid/vinum/vinumio.c

587

CHECKALLOC(config, "Can't allocate config data");

sys/dev/raid/vinum/vinumio.c

589

format_config(config, MAXCONFIG);

sys/dev/raid/vinum/vinumio.c

634

error = write_drive(drive, config, MAXCONFIG, VINUM_CONFIG_OFFSET); /* first config copy */

sys/dev/raid/vinum/vinumio.c

636

error = write_drive(drive, config, MAXCONFIG, VINUM_CONFIG_OFFSET + MAXCONFIG); /* second copy */

sys/dev/raid/vinum/vinumio.c

659

Free(config);

sys/dev/sound/pci/hda/hdaa.c

1001

config = hdaa_widget_pin_patch(config, res);

sys/dev/sound/pci/hda/hdaa.c

1005

if (config != orig)

sys/dev/sound/pci/hda/hdaa.c

1008

w->nid, orig, config);

sys/dev/sound/pci/hda/hdaa.c

1010

w->wclass.pin.newconf = w->wclass.pin.config = config;

sys/dev/sound/pci/hda/hdaa.c

1113

conf = w->wclass.pin.config;

sys/dev/sound/pci/hda/hdaa.c

1568

w->wclass.pin.config = hda_command(dev,

sys/dev/sound/pci/hda/hdaa.c

1649

uint32_t config;

sys/dev/sound/pci/hda/hdaa.c

1653

config = w->wclass.pin.config;

sys/dev/sound/pci/hda/hdaa.c

1654

devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >>

sys/dev/sound/pci/hda/hdaa.c

1656

conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >>

sys/dev/sound/pci/hda/hdaa.c

1658

color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >>

sys/dev/sound/pci/hda/hdaa.c

3202

if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config)

sys/dev/sound/pci/hda/hdaa.c

3244

assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

3245

seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

3252

type = w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa.c

3294

HDA_CONFIG_DEFAULTCONF_LOCATION(w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

3296

HDA_CONFIG_DEFAULTCONF_LOCATION(w->wclass.pin.config)) {

sys/dev/sound/pci/hda/hdaa.c

4190

if ((w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa.c

4200

} else if ((w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa.c

4777

switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {

sys/dev/sound/pci/hda/hdaa.c

4782

if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK)

sys/dev/sound/pci/hda/hdaa.c

4836

switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {

sys/dev/sound/pci/hda/hdaa.c

5106

(w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa.c

5748

w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

576

(HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0)

sys/dev/sound/pci/hda/hdaa.c

5803

hdaa_dump_pin_config(w, w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

6087

hdaa_dump_pin_config(w, w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

6322

w->wclass.pin.config = w->wclass.pin.newconf;

sys/dev/sound/pci/hda/hdaa.c

6921

t1 = HDA_CONFIG_DEFAULTCONF_DEVICE(w->wclass.pin.config);

sys/dev/sound/pci/hda/hdaa.c

728

(HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0)

sys/dev/sound/pci/hda/hdaa.c

801

(HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) {

sys/dev/sound/pci/hda/hdaa.c

854

hdaa_widget_pin_patch(uint32_t config, const char *str)

sys/dev/sound/pci/hda/hdaa.c

868

config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK;

sys/dev/sound/pci/hda/hdaa.c

869

config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

872

config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK;

sys/dev/sound/pci/hda/hdaa.c

873

config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

876

config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK;

sys/dev/sound/pci/hda/hdaa.c

877

config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

880

config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK;

sys/dev/sound/pci/hda/hdaa.c

882

config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

887

config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT);

sys/dev/sound/pci/hda/hdaa.c

892

config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK;

sys/dev/sound/pci/hda/hdaa.c

894

config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

899

config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT);

sys/dev/sound/pci/hda/hdaa.c

904

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa.c

906

config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

912

config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT);

sys/dev/sound/pci/hda/hdaa.c

917

config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK;

sys/dev/sound/pci/hda/hdaa.c

919

config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

925

config |= (i << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT);

sys/dev/sound/pci/hda/hdaa.c

930

config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;

sys/dev/sound/pci/hda/hdaa.c

932

config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) &

sys/dev/sound/pci/hda/hdaa.c

938

config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT);

sys/dev/sound/pci/hda/hdaa.c

944

return (config);

sys/dev/sound/pci/hda/hdaa.c

979

uint32_t config, orig;

sys/dev/sound/pci/hda/hdaa.c

982

config = orig = w->wclass.pin.config;

sys/dev/sound/pci/hda/hdaa.c

990

config = strtol(res + 2, NULL, 16);

sys/dev/sound/pci/hda/hdaa.c

992

config = hdaa_widget_pin_patch(config, res);

sys/dev/sound/pci/hda/hdaa.c

999

config = strtol(res + 2, NULL, 16);

sys/dev/sound/pci/hda/hdaa.h

124

uint32_t config;

sys/dev/sound/pci/hda/hdaa.h

269

uint32_t hdaa_widget_pin_patch(uint32_t config, const char *str);

sys/dev/sound/pci/hda/hdaa_patches.c

151

uint32_t config, orig, id, subid;

sys/dev/sound/pci/hda/hdaa_patches.c

154

config = orig = w->wclass.pin.config;

sys/dev/sound/pci/hda/hdaa_patches.c

165

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

166

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;

sys/dev/sound/pci/hda/hdaa_patches.c

169

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

170

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;

sys/dev/sound/pci/hda/hdaa_patches.c

183

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

184

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;

sys/dev/sound/pci/hda/hdaa_patches.c

187

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

188

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;

sys/dev/sound/pci/hda/hdaa_patches.c

191

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

192

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;

sys/dev/sound/pci/hda/hdaa_patches.c

195

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

196

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;

sys/dev/sound/pci/hda/hdaa_patches.c

199

config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

200

config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;

sys/dev/sound/pci/hda/hdaa_patches.c

208

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

210

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |

sys/dev/sound/pci/hda/hdaa_patches.c

214

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

216

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |

sys/dev/sound/pci/hda/hdaa_patches.c

224

config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

225

config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;

sys/dev/sound/pci/hda/hdaa_patches.c

228

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

230

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |

sys/dev/sound/pci/hda/hdaa_patches.c

234

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

236

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |

sys/dev/sound/pci/hda/hdaa_patches.c

245

config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;

sys/dev/sound/pci/hda/hdaa_patches.c

246

config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;

sys/dev/sound/pci/hda/hdaa_patches.c

253

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

255

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |

sys/dev/sound/pci/hda/hdaa_patches.c

263

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

265

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |

sys/dev/sound/pci/hda/hdaa_patches.c

269

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

271

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |

sys/dev/sound/pci/hda/hdaa_patches.c

279

config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |

sys/dev/sound/pci/hda/hdaa_patches.c

281

config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |

sys/dev/sound/pci/hda/hdaa_patches.c

427

config = hdaa_widget_pin_patch(config, patch);

sys/dev/sound/pci/hda/hdaa_patches.c

429

if (config != orig)

sys/dev/sound/pci/hda/hdaa_patches.c

432

nid, orig, config);

sys/dev/sound/pci/hda/hdaa_patches.c

434

w->wclass.pin.config = config;

sys/dev/sound/pci/hda/hdaa_patches.c

604

if ((w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa_patches.c

618

if ((w->wclass.pin.config &

sys/dev/sound/pci/hda/hdaa_patches.c

640

(w->wclass.pin.config &

sys/dev/video/fb/fbreg.h

148

#define VIDEO_DRIVER(name, sw, config) \

sys/dev/video/fb/fbreg.h

150

#name, &sw, config \

sys/dev/virtual/hyperv/vmbus/vmbus.c

168

.config = cputimer_intr_default_config,

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

836

uint32_t config;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

840

config = vmxnet3_read_cmd(sc, VMXNET3_CMD_GET_INTRCFG);

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

842

sc->vmx_intr_type = config & 0x03;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

843

sc->vmx_intr_mask_mode = (config >> 2) & 0x03;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

879

uint32_t config;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

883

config = vmxnet3_read_cmd(sc, VMXNET3_CMD_GET_INTRCFG);

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

885

sc->vmx_intr_type = config & 0x03;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

886

sc->vmx_intr_mask_mode = (config >> 2) & 0x03;

sys/kern/kern_cputimer.c

312

cti->config(cti, sys_cputimer);

sys/kern/kern_cputimer.c

392

cti->config(cti, timer);

sys/net/bridge/bridgestp.c

395

struct bstp_config_unit *config)

sys/net/bridge/bridgestp.c

397

sc->sc_max_age = config->cu_max_age;

sys/net/bridge/bridgestp.c

398

sc->sc_hello_time = config->cu_hello_time;

sys/net/bridge/bridgestp.c

399

sc->sc_forward_delay = config->cu_forward_delay;

sys/net/bridge/bridgestp.c

400

sc->sc_topology_change = config->cu_topology_change;

sys/net/netmap/netmap_mem2.c

134

.config = netmap_mem_private_config,

sys/net/netmap/netmap_mem2.c

202

error = nmd->config(nmd);

sys/net/netmap/netmap_mem2.c

97

.config = netmap_mem_global_config,

sys/net/netmap/netmap_mem2.h

187

netmap_mem_config_t config;

sys/net/zlib.c

678

local config configuration_table[10] = {

sys/platform/pc64/apic/lapic.c

97

.config = cputimer_intr_default_config,

sys/platform/pc64/include/clock.h

68

#define TIMECOUNTER_INIT(name, config) \

sys/platform/pc64/include/clock.h

70

#name, config \

sys/platform/pc64/isa/clock.c

174

.config = i8254_intr_config,

sys/platform/vkernel64/platform/systimer.c

110

.config = cputimer_intr_default_config,

sys/sys/nata.h

41

/*000*/ u_int16_t config; /* configuration info */

sys/sys/systimer.h

205

void (*config)

sys/vfs/hammer/hammer_disk.h

1074

struct hammer_config_data config;

sys/vfs/hammer/hammer_ioctl.c

1046

&config->config,

sys/vfs/hammer/hammer_ioctl.c

1053

config->head.error = error;

sys/vfs/hammer/hammer_ioctl.c

954

struct hammer_ioc_config *config)

sys/vfs/hammer/hammer_ioctl.c

980

config->config = cursor.data->config;

sys/vfs/hammer/hammer_ioctl.c

983

config->head.error = error;

sys/vfs/hammer/hammer_ioctl.c

997

struct hammer_ioc_config *config)

sys/vfs/hammer/hammer_ioctl.h

437

struct hammer_config_data config;

sys/vfs/hammer2/zlib/hammer2_zlib_deflate.c

135

local const config configuration_table[10] = {

tools/tools/usbtest/usb_control_ep_test.c

610

struct libusb20_config *config;

tools/tools/usbtest/usb_control_ep_test.c

626

config = libusb20_dev_alloc_config(pdev,

tools/tools/usbtest/usb_control_ep_test.c

628

if (config == NULL) {

tools/tools/usbtest/usb_control_ep_test.c

636

for (n = 0; n != config->num_interface; n++) {

tools/tools/usbtest/usb_control_ep_test.c

645

for (m = 0; m != config->interface[n].num_altsetting; m++) {

usr.sbin/authpf/authpf.c

278

if (read_config(config)) {

usr.sbin/authpf/authpf.c

84

FILE *config;

usr.sbin/authpf/authpf.c

93

config = fopen(PATH_CONFFILE, "r");

usr.sbin/authpf/authpf.c

94

if (config == NULL) {

usr.sbin/bthcid/parser.y

73

config: line

usr.sbin/bthcid/parser.y

74

| config line

usr.sbin/inetd/inetd.c

189

void config(void);

usr.sbin/inetd/inetd.c

471

config();

usr.sbin/inetd/inetd.c

545

config();

usr.sbin/mailwrapper/mailwrapper.c

107

if ((line = fparseln(config, &len, &lineno, NULL, 0)) == NULL) {

usr.sbin/mailwrapper/mailwrapper.c

108

if (feof(config))

usr.sbin/mailwrapper/mailwrapper.c

142

fclose(config);

usr.sbin/mailwrapper/mailwrapper.c

82

FILE *config;

usr.sbin/mailwrapper/mailwrapper.c

93

if ((config = fopen(_PATH_MAILERCONF, "r")) == NULL) {

usr.sbin/makefs/hammer2/zlib/hammer2_zlib_deflate.c

135

local const config configuration_table[10] = {

usr.sbin/mfiutil/mfi_config.c

102

p += config->array_size;

usr.sbin/mfiutil/mfi_config.c

1020

free(config);

usr.sbin/mfiutil/mfi_config.c

1084

dump_config(int fd, struct mfi_config_data *config, const char *msg_prefix)

usr.sbin/mfiutil/mfi_config.c

109

mfi_config_lookup_volume(struct mfi_config_data *config, uint8_t target_id)

usr.sbin/mfiutil/mfi_config.c

1099

msg_prefix, config->array_count, config->log_drv_count,

usr.sbin/mfiutil/mfi_config.c

1100

config->spares_count);

usr.sbin/mfiutil/mfi_config.c

1101

printf(" array size: %u\n", config->array_size);

usr.sbin/mfiutil/mfi_config.c

1102

printf(" volume size: %u\n", config->log_drv_size);

usr.sbin/mfiutil/mfi_config.c

1103

printf(" spare size: %u\n", config->spares_size);

usr.sbin/mfiutil/mfi_config.c

1104

p = (char *)config->array;

usr.sbin/mfiutil/mfi_config.c

1106

for (i = 0; i < config->array_count; i++) {

usr.sbin/mfiutil/mfi_config.c

1129

p += config->array_size;

usr.sbin/mfiutil/mfi_config.c

1132

for (i = 0; i < config->log_drv_count; i++) {

usr.sbin/mfiutil/mfi_config.c

115

p = (char *)config->array + config->array_count * config->array_size;

usr.sbin/mfiutil/mfi_config.c

116

for (i = 0; i < config->log_drv_count; i++) {

usr.sbin/mfiutil/mfi_config.c

1161

p += config->log_drv_size;

usr.sbin/mfiutil/mfi_config.c

1164

for (i = 0; i < config->spares_count; i++) {

usr.sbin/mfiutil/mfi_config.c

1173

p += config->spares_size;

usr.sbin/mfiutil/mfi_config.c

1181

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_config.c

1197

if (mfi_config_read(fd, &config) < 0) {

usr.sbin/mfiutil/mfi_config.c

120

p += config->log_drv_size;

usr.sbin/mfiutil/mfi_config.c

1205

dump_config(fd, config, NULL);

usr.sbin/mfiutil/mfi_config.c

1206

free(config);

usr.sbin/mfiutil/mfi_config.c

1216

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_config.c

1244

config = malloc(len);

usr.sbin/mfiutil/mfi_config.c

1245

if (config == NULL) {

usr.sbin/mfiutil/mfi_config.c

1250

if (sysctlbyname(buf, config, &len, NULL, 0) < 0) {

usr.sbin/mfiutil/mfi_config.c

1253

free(config);

usr.sbin/mfiutil/mfi_config.c

1257

dump_config(fd, config, NULL);

usr.sbin/mfiutil/mfi_config.c

1258

free(config);

usr.sbin/mfiutil/mfi_config.c

518

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_config.c

554

config = NULL;

usr.sbin/mfiutil/mfi_config.c

59

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_config.c

67

config = NULL;

usr.sbin/mfiutil/mfi_config.c

692

if (mfi_config_read(fd, &config) < 0) {

usr.sbin/mfiutil/mfi_config.c

697

p = (char *)config->array;

usr.sbin/mfiutil/mfi_config.c

70

config = reallocf(config, config_size);

usr.sbin/mfiutil/mfi_config.c

700

state.array_count = config->array_count;

usr.sbin/mfiutil/mfi_config.c

701

if (config->array_count > 0) {

usr.sbin/mfiutil/mfi_config.c

702

state.arrays = calloc(config->array_count, sizeof(int));

usr.sbin/mfiutil/mfi_config.c

708

for (i = 0; i < config->array_count; i++) {

usr.sbin/mfiutil/mfi_config.c

71

if (config == NULL)

usr.sbin/mfiutil/mfi_config.c

711

p += config->array_size;

usr.sbin/mfiutil/mfi_config.c

713

qsort(state.arrays, config->array_count, sizeof(int),

usr.sbin/mfiutil/mfi_config.c

717

state.log_drv_count = config->log_drv_count;

usr.sbin/mfiutil/mfi_config.c

718

if (config->log_drv_count) {

usr.sbin/mfiutil/mfi_config.c

719

state.volumes = calloc(config->log_drv_count, sizeof(int));

usr.sbin/mfiutil/mfi_config.c

725

for (i = 0; i < config->log_drv_count; i++) {

usr.sbin/mfiutil/mfi_config.c

728

p += config->log_drv_size;

usr.sbin/mfiutil/mfi_config.c

73

if (mfi_dcmd_command(fd, opcode, config,

usr.sbin/mfiutil/mfi_config.c

730

qsort(state.volumes, config->log_drv_count, sizeof(int),

usr.sbin/mfiutil/mfi_config.c

734

free(config);

usr.sbin/mfiutil/mfi_config.c

76

free(config);

usr.sbin/mfiutil/mfi_config.c

760

config = calloc(1, config_size);

usr.sbin/mfiutil/mfi_config.c

761

if (config == NULL) {

usr.sbin/mfiutil/mfi_config.c

766

config->size = config_size;

usr.sbin/mfiutil/mfi_config.c

767

config->array_count = narrays;

usr.sbin/mfiutil/mfi_config.c

768

config->array_size = MFI_ARRAY_SIZE; /* XXX: Firmware hardcode */

usr.sbin/mfiutil/mfi_config.c

769

config->log_drv_count = nvolumes;

usr.sbin/mfiutil/mfi_config.c

770

config->log_drv_size = sizeof(struct mfi_ld_config);

usr.sbin/mfiutil/mfi_config.c

771

config->spares_count = 0;

usr.sbin/mfiutil/mfi_config.c

772

config->spares_size = 40; /* XXX: Firmware hardcode */

usr.sbin/mfiutil/mfi_config.c

773

cfg_arrays = (char *)config->array;

usr.sbin/mfiutil/mfi_config.c

774

cfg_volumes = cfg_arrays + config->array_size * narrays;

usr.sbin/mfiutil/mfi_config.c

779

cfg_arrays += config->array_size;

usr.sbin/mfiutil/mfi_config.c

788

cfg_volumes += config->log_drv_size;

usr.sbin/mfiutil/mfi_config.c

793

dump_config(fd, config, NULL);

usr.sbin/mfiutil/mfi_config.c

797

if (mfi_dcmd_command(fd, MFI_DCMD_CFG_ADD, config, config_size,

usr.sbin/mfiutil/mfi_config.c

806

free(config);

usr.sbin/mfiutil/mfi_config.c

81

if (config->size > config_size) {

usr.sbin/mfiutil/mfi_config.c

82

config_size = config->size;

usr.sbin/mfiutil/mfi_config.c

86

*configp = config;

usr.sbin/mfiutil/mfi_config.c

901

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_config.c

91

mfi_config_lookup_array(struct mfi_config_data *config, uint16_t array_ref)

usr.sbin/mfiutil/mfi_config.c

922

config = NULL;

usr.sbin/mfiutil/mfi_config.c

948

if (mfi_config_read(fd, &config) < 0) {

usr.sbin/mfiutil/mfi_config.c

955

config->array_count);

usr.sbin/mfiutil/mfi_config.c

966

p = (char *)config->array;

usr.sbin/mfiutil/mfi_config.c

967

for (i = 0; i < config->array_count; i++) {

usr.sbin/mfiutil/mfi_config.c

97

p = (char *)config->array;

usr.sbin/mfiutil/mfi_config.c

975

p += config->array_size;

usr.sbin/mfiutil/mfi_config.c

98

for (i = 0; i < config->array_count; i++) {

usr.sbin/mfiutil/mfi_config.c

983

ld = mfi_config_lookup_volume(config, target_id);

usr.sbin/mfiutil/mfi_config.c

993

ar = mfi_config_lookup_array(config,

usr.sbin/mfiutil/mfi_foreign.c

173

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_foreign.c

180

if (mfi_config_read_opcode(fd, opcode, &config, mbox, sizeof(mbox))

usr.sbin/mfiutil/mfi_foreign.c

198

dump_config(fd, config, prefix);

usr.sbin/mfiutil/mfi_foreign.c

199

free(config);

usr.sbin/mfiutil/mfi_show.c

293

struct mfi_config_data *config;

usr.sbin/mfiutil/mfi_show.c

316

if (mfi_config_read(fd, &config) < 0) {

usr.sbin/mfiutil/mfi_show.c

325

mfi_unit, config->array_count, config->log_drv_count,

usr.sbin/mfiutil/mfi_show.c

326

config->spares_count);

usr.sbin/mfiutil/mfi_show.c

327

p = (char *)config->array;

usr.sbin/mfiutil/mfi_show.c

329

for (i = 0; i < config->array_count; i++) {

usr.sbin/mfiutil/mfi_show.c

348

p += config->array_size;

usr.sbin/mfiutil/mfi_show.c

351

for (i = 0; i < config->log_drv_count; i++) {

usr.sbin/mfiutil/mfi_show.c

368

p += config->log_drv_size;

usr.sbin/mfiutil/mfi_show.c

371

for (i = 0; i < config->spares_count; i++) {

usr.sbin/mfiutil/mfi_show.c

387

p += config->spares_size;

usr.sbin/mfiutil/mfi_show.c

389

free(config);

usr.sbin/mfiutil/mfi_show.c

394

MFI_COMMAND(show, config, show_config);

usr.sbin/mfiutil/mfiutil.h

115

void dump_config(int fd, struct mfi_config_data *config, const char* msg_prefix);

usr.sbin/mptutil/mpt_show.c

379

MPT_COMMAND(show, config, show_config);

usr.sbin/nscd/config.c

252

add_configuration_entry(struct configuration *config,

usr.sbin/nscd/config.c

258

if (configuration_find_entry(config, entry->name) != NULL) {

usr.sbin/nscd/config.c

263

if (config->entries_size == config->entries_capacity) {

usr.sbin/nscd/config.c

266

config->entries_capacity *= 2;

usr.sbin/nscd/config.c

269

config->entries_capacity);

usr.sbin/nscd/config.c

271

memcpy(new_entries, config->entries,

usr.sbin/nscd/config.c

273

config->entries_size);

usr.sbin/nscd/config.c

275

free(config->entries);

usr.sbin/nscd/config.c

276

config->entries = new_entries;

usr.sbin/nscd/config.c

279

config->entries[config->entries_size++] = entry;

usr.sbin/nscd/config.c

280

qsort(config->entries, config->entries_size,

usr.sbin/nscd/config.c

289

configuration_get_entries_size(struct configuration *config)

usr.sbin/nscd/config.c

292

assert(config != NULL);

usr.sbin/nscd/config.c

294

return (config->entries_size);

usr.sbin/nscd/config.c

298

configuration_get_entry(struct configuration *config, size_t index)

usr.sbin/nscd/config.c

301

assert(config != NULL);

usr.sbin/nscd/config.c

302

assert(index < config->entries_size);

usr.sbin/nscd/config.c

304

return (config->entries[index]);

usr.sbin/nscd/config.c

308

configuration_find_entry(struct configuration *config,

usr.sbin/nscd/config.c

315

retval = bsearch(name, config->entries, config->entries_size,

usr.sbin/nscd/config.c

429

configuration_lock_rdlock(struct configuration *config)

usr.sbin/nscd/config.c

432

pthread_rwlock_rdlock(&config->rwlock);

usr.sbin/nscd/config.c

437

configuration_lock_wrlock(struct configuration *config)

usr.sbin/nscd/config.c

440

pthread_rwlock_wrlock(&config->rwlock);

usr.sbin/nscd/config.c

445

configuration_unlock(struct configuration *config)

usr.sbin/nscd/config.c

448

pthread_rwlock_unlock(&config->rwlock);

usr.sbin/nscd/config.c

527

fill_configuration_defaults(struct configuration *config)

usr.sbin/nscd/config.c

532

assert(config != NULL);

usr.sbin/nscd/config.c

534

if (config->socket_path != NULL)

usr.sbin/nscd/config.c

535

free(config->socket_path);

usr.sbin/nscd/config.c

538

config->socket_path = (char *)calloc(1, len + 1);

usr.sbin/nscd/config.c

539

assert(config->socket_path != NULL);

usr.sbin/nscd/config.c

540

memcpy(config->socket_path, DEFAULT_SOCKET_PATH, len);

usr.sbin/nscd/config.c

543

config->pidfile_path = (char *)calloc(1, len + 1);

usr.sbin/nscd/config.c

544

assert(config->pidfile_path != NULL);

usr.sbin/nscd/config.c

545

memcpy(config->pidfile_path, DEFAULT_PIDFILE_PATH, len);

usr.sbin/nscd/config.c

547

config->socket_mode = S_IFSOCK | S_IRUSR | S_IWUSR |

usr.sbin/nscd/config.c

549

config->force_unlink = 1;

usr.sbin/nscd/config.c

551

config->query_timeout = DEFAULT_QUERY_TIMEOUT;

usr.sbin/nscd/config.c

552

config->threads_num = DEFAULT_THREADS_NUM;

usr.sbin/nscd/config.c

554

for (i = 0; i < config->entries_size; ++i)

usr.sbin/nscd/config.c

555

destroy_configuration_entry(config->entries[i]);

usr.sbin/nscd/config.c

556

config->entries_size = 0;

usr.sbin/nscd/config.c

562

destroy_configuration(struct configuration *config)

usr.sbin/nscd/config.c

566

assert(config != NULL);

usr.sbin/nscd/config.c

567

free(config->pidfile_path);

usr.sbin/nscd/config.c

568

free(config->socket_path);

usr.sbin/nscd/config.c

570

for (i = 0; i < config->entries_size; ++i)

usr.sbin/nscd/config.c

571

destroy_configuration_entry(config->entries[i]);

usr.sbin/nscd/config.c

572

free(config->entries);

usr.sbin/nscd/config.c

574

pthread_rwlock_destroy(&config->rwlock);

usr.sbin/nscd/config.c

575

free(config);

usr.sbin/nscd/config.h

147

extern void configuration_lock_rdlock(struct configuration *config);

usr.sbin/nscd/config.h

148

extern void configuration_lock_wrlock(struct configuration *config);

usr.sbin/nscd/config.h

149

extern void configuration_unlock(struct configuration *config);

usr.sbin/nscd/nscd.c

113

size = configuration_get_entries_size(config);

usr.sbin/nscd/nscd.c

115

config_entry = configuration_get_entry(config, i);

usr.sbin/nscd/nscd.c

153

init_runtime_env(struct configuration *config)

usr.sbin/nscd/nscd.c

169

if (config->force_unlink == 1)

usr.sbin/nscd/nscd.c

170

unlink(config->socket_path);

usr.sbin/nscd/nscd.c

174

strlcpy(serv_addr.sun_path, config->socket_path,

usr.sbin/nscd/nscd.c

185

"%s", config->socket_path);

usr.sbin/nscd/nscd.c

190

config->socket_path);

usr.sbin/nscd/nscd.c

196

chmod(config->socket_path, config->socket_mode);

usr.sbin/nscd/nscd.c

225

struct configuration *config)

usr.sbin/nscd/nscd.c

274

struct configuration *config)

usr.sbin/nscd/nscd.c

462

struct configuration *config)

usr.sbin/nscd/nscd.c

479

struct configuration *config)

usr.sbin/nscd/nscd.c

502

accept_connection(event_data, env, config);

usr.sbin/nscd/nscd.c

517

env, config);

usr.sbin/nscd/nscd.c

521

env, config);

usr.sbin/nscd/nscd.c

98

init_cache_(struct configuration *config)

usr.sbin/nscd/parser.c

111

enable_cache(struct configuration *config, const char *entry_name, int flag)

usr.sbin/nscd/parser.c

116

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

122

set_positive_time_to_live(struct configuration *config,

usr.sbin/nscd/parser.c

134

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

144

set_negative_time_to_live(struct configuration *config,

usr.sbin/nscd/parser.c

156

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

168

set_keep_hot_count(struct configuration *config,

usr.sbin/nscd/parser.c

177

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

181

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

189

set_positive_policy(struct configuration *config,

usr.sbin/nscd/parser.c

197

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

205

set_negative_policy(struct configuration *config,

usr.sbin/nscd/parser.c

213

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

221

set_perform_actual_lookups(struct configuration *config,

usr.sbin/nscd/parser.c

229

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

237

set_suggested_size(struct configuration *config,

usr.sbin/nscd/parser.c

243

assert(config != NULL);

usr.sbin/nscd/parser.c

247

entry = find_create_entry(config, entry_name);

usr.sbin/nscd/parser.c

256

check_files(struct configuration *config, const char *entry_name, int flag)

usr.sbin/nscd/parser.c

320

set_threads_num(struct configuration *config, int value)

usr.sbin/nscd/parser.c

323

assert(config != NULL);

usr.sbin/nscd/parser.c

324

config->threads_num = value;

usr.sbin/nscd/parser.c

332

parse_config_file(struct configuration *config,

usr.sbin/nscd/parser.c

342

assert(config != NULL);

usr.sbin/nscd/parser.c

370

enable_cache(config, fields[1], value);

usr.sbin/nscd/parser.c

386

set_positive_time_to_live(config,

usr.sbin/nscd/parser.c

393

set_positive_policy(config, fields[1], value);

usr.sbin/nscd/parser.c

399

set_perform_actual_lookups(config, fields[1],

usr.sbin/nscd/parser.c

409

set_negative_time_to_live(config,

usr.sbin/nscd/parser.c

416

set_negative_policy(config,

usr.sbin/nscd/parser.c

426

set_suggested_size(config, fields[1], value);

usr.sbin/nscd/parser.c

434

set_threads_num(config, value);

usr.sbin/nscd/parser.c

443

set_keep_hot_count(config,

usr.sbin/nscd/parser.c

453

check_files(config,

usr.sbin/nscd/parser.c

87

find_create_entry(struct configuration *config,

usr.sbin/nscd/parser.c

94

entry = configuration_find_entry(config, entry_name);

usr.sbin/nscd/parser.c

98

res = add_configuration_entry(config, entry);

usr.sbin/pw/pw.c

100

char *config = NULL;

usr.sbin/pw/pw.c

211

config = getarg(&arglist, 'C') ? getarg(&arglist, 'C')->val : NULL;

usr.sbin/pw/pw.c

216

if (config == NULL) { /* Only override config location if -C not specified */

usr.sbin/pw/pw.c

217

config = malloc(MAXPATHLEN);

usr.sbin/pw/pw.c

218

snprintf(config, MAXPATHLEN, "%s/pw.conf", etcpath);

usr.sbin/pw/pw.c

229

cnf = read_userconfig(config);

usr.sbin/pw/pw_conf.c

228

extendarray(&config.groups, &config.numgroups, 200);

usr.sbin/pw/pw_conf.c

229

memset(config.groups, 0, config.numgroups * sizeof(char *));

usr.sbin/pw/pw_conf.c

271

config.default_password = boolean_val(q, 1);

usr.sbin/pw/pw_conf.c

274

config.reuse_uids = boolean_val(q, 0);

usr.sbin/pw/pw_conf.c

277

config.reuse_gids = boolean_val(q, 0);

usr.sbin/pw/pw_conf.c

280

config.nispasswd = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

284

config.dotdir = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

288

config.newmail = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

292

config.logfile = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

296

config.home = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

301

config.homemode = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

306

config.shelldir = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

317

config.shell_default = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

322

config.default_group = (q == NULL || !boolean_val(q, 1) || GETGRNAM(q) == NULL)

usr.sbin/pw/pw_conf.c

327

if (extendarray(&config.groups, &config.numgroups, i + 2) != -1)

usr.sbin/pw/pw_conf.c

328

config.groups[i++] = newstr(q);

usr.sbin/pw/pw_conf.c

331

while (i < config.numgroups)

usr.sbin/pw/pw_conf.c

332

config.groups[i++] = NULL;

usr.sbin/pw/pw_conf.c

335

config.default_class = (q == NULL || !boolean_val(q, 1))

usr.sbin/pw/pw_conf.c

340

config.min_uid = (uid_t) atol(q);

usr.sbin/pw/pw_conf.c

344

config.max_uid = (uid_t) atol(q);

usr.sbin/pw/pw_conf.c

348

config.min_gid = (gid_t) atol(q);

usr.sbin/pw/pw_conf.c

352

config.max_gid = (gid_t) atol(q);

usr.sbin/pw/pw_conf.c

356

config.expire_days = atoi(q);

usr.sbin/pw/pw_conf.c

360

config.password_days = atoi(q);

usr.sbin/pw/pw_conf.c

371

return &config;

usr.sbin/pw/pw_conf.c

400

val = boolean_str(config.default_password);

usr.sbin/pw/pw_conf.c

403

val = boolean_str(config.reuse_uids);

usr.sbin/pw/pw_conf.c

406

val = boolean_str(config.reuse_gids);

usr.sbin/pw/pw_conf.c

409

val = config.nispasswd ? config.nispasswd : "";

usr.sbin/pw/pw_conf.c

413

val = config.dotdir ? config.dotdir : boolean_str(0);

usr.sbin/pw/pw_conf.c

416

val = config.newmail ? config.newmail : boolean_str(0);

usr.sbin/pw/pw_conf.c

419

val = config.logfile ? config.logfile : boolean_str(0);

usr.sbin/pw/pw_conf.c

422

val = config.home;

usr.sbin/pw/pw_conf.c

425

sprintf(buf, "%04o", config.homemode);

usr.sbin/pw/pw_conf.c

429

val = config.shelldir;

usr.sbin/pw/pw_conf.c

445

val = config.shell_default ? config.shell_default : bourne_shell;

usr.sbin/pw/pw_conf.c

448

val = config.default_group ? config.default_group : "";

usr.sbin/pw/pw_conf.c

451

extendarray(&config.groups, &config.numgroups, 200);

usr.sbin/pw/pw_conf.c

452

for (j = k = 0; j < config.numgroups && config.groups[j] != NULL; j++) {

usr.sbin/pw/pw_conf.c

454

int l = snprintf(lbuf, sizeof lbuf, "%s\"%s\"", k ? "," : "", config.groups[j]);

usr.sbin/pw/pw_conf.c

465

val = config.default_class ? config.default_class : "";

usr.sbin/pw/pw_conf.c

468

sprintf(buf, "%lu", (unsigned long) config.min_uid);

usr.sbin/pw/pw_conf.c

472

sprintf(buf, "%lu", (unsigned long) config.max_uid);

usr.sbin/pw/pw_conf.c

476

sprintf(buf, "%lu", (unsigned long) config.min_gid);

usr.sbin/pw/pw_conf.c

480

sprintf(buf, "%lu", (unsigned long) config.max_gid);

usr.sbin/pw/pw_conf.c

484

sprintf(buf, "%d", config.expire_days);

usr.sbin/pw/pw_conf.c

488

sprintf(buf, "%d", config.password_days);

usr.sbin/pw/pw_conf.c

81

static struct userconf config =

usr.sbin/rrenumd/parser.y

120

config:

usr.sbin/rrenumd/rrenumd.c

462

config(&fp);

usr.sbin/rrenumd/rrenumd.c

94

static void config(FILE **);

usr.sbin/vnconfig/vnconfig.c

239

rv += config(&vndisks[i]);

usr.sbin/vnconfig/vnconfig.c

94

int config(struct vndisk *);