games/larn/signal.c

78

sigsetmask(sigblock(0) & ~BIT(SIGTSTP));

sbin/iscontrol/fsm.c

596

p->reason = BIT(7) | 0;

sbin/iscontrol/iscontrol.h

56

#define SESS_CONNECTED BIT(0)

sbin/iscontrol/iscontrol.h

57

#define SESS_DISCONNECT BIT(1)

sbin/iscontrol/iscontrol.h

58

#define SESS_LOGGEDIN BIT(2)

sbin/iscontrol/iscontrol.h

59

#define SESS_RECONNECT BIT(3)

sbin/iscontrol/iscontrol.h

60

#define SESS_REDIRECT BIT(4)

sbin/iscontrol/iscontrol.h

62

#define SESS_NEGODONE BIT(10) // XXX: kludge

sbin/iscontrol/iscontrol.h

64

#define SESS_FULLFEATURE BIT(29)

sbin/iscontrol/iscontrol.h

65

#define SESS_INITIALLOGIN1 BIT(30)

sbin/iscontrol/iscontrol.h

66

#define SESS_INITIALLOGIN BIT(31)

sys/dev/crypto/tpm/tpm_crb.c

55

#define TPM_LOC_STATE_ESTB BIT(0)

sys/dev/crypto/tpm/tpm_crb.c

56

#define TPM_LOC_STATE_ASSIGNED BIT(1)

sys/dev/crypto/tpm/tpm_crb.c

58

#define TPM_LOC_STATE_VALID BIT(7)

sys/dev/crypto/tpm/tpm_crb.c

63

#define TPM_LOC_CTRL_REQUEST BIT(0)

sys/dev/crypto/tpm/tpm_crb.c

64

#define TPM_LOC_CTRL_RELINQUISH BIT(1)

sys/dev/crypto/tpm/tpm_crb.c

66

#define TPM_CRB_CTRL_REQ_GO_READY BIT(0)

sys/dev/crypto/tpm/tpm_crb.c

67

#define TPM_CRB_CTRL_REQ_GO_IDLE BIT(1)

sys/dev/crypto/tpm/tpm_crb.c

69

#define TPM_CRB_CTRL_STS_ERR_BIT BIT(0)

sys/dev/crypto/tpm/tpm_crb.c

70

#define TPM_CRB_CTRL_STS_IDLE_BIT BIT(1)

sys/dev/crypto/tpm/tpm_crb.c

75

#define TPM_CRB_CTRL_START_CMD BIT(0)

sys/dev/crypto/tpm/tpm_crb.c

77

#define TPM_CRB_INT_ENABLE_BIT BIT(31)

sys/dev/crypto/tpm/tpm_tis.c

48

#define TPM_ACCESS_LOC_REQ BIT(1)

sys/dev/crypto/tpm/tpm_tis.c

49

#define TPM_ACCESS_LOC_Seize BIT(3)

sys/dev/crypto/tpm/tpm_tis.c

50

#define TPM_ACCESS_LOC_ACTIVE BIT(5)

sys/dev/crypto/tpm/tpm_tis.c

51

#define TPM_ACCESS_LOC_RELINQUISH BIT(5)

sys/dev/crypto/tpm/tpm_tis.c

52

#define TPM_ACCESS_VALID BIT(7)

sys/dev/crypto/tpm/tpm_tis.c

54

#define TPM_INT_ENABLE_GLOBAL_ENABLE BIT(31)

sys/dev/crypto/tpm/tpm_tis.c

55

#define TPM_INT_ENABLE_CMD_RDY BIT(7)

sys/dev/crypto/tpm/tpm_tis.c

56

#define TPM_INT_ENABLE_LOC_CHANGE BIT(2)

sys/dev/crypto/tpm/tpm_tis.c

57

#define TPM_INT_ENABLE_STS_VALID BIT(1)

sys/dev/crypto/tpm/tpm_tis.c

58

#define TPM_INT_ENABLE_DATA_AVAIL BIT(0)

sys/dev/crypto/tpm/tpm_tis.c

60

#define TPM_INT_STS_CMD_RDY BIT(7)

sys/dev/crypto/tpm/tpm_tis.c

61

#define TPM_INT_STS_LOC_CHANGE BIT(2)

sys/dev/crypto/tpm/tpm_tis.c

62

#define TPM_INT_STS_VALID BIT(1)

sys/dev/crypto/tpm/tpm_tis.c

63

#define TPM_INT_STS_DATA_AVAIL BIT(0)

sys/dev/crypto/tpm/tpm_tis.c

68

#define TPM_STS_VALID BIT(7)

sys/dev/crypto/tpm/tpm_tis.c

69

#define TPM_STS_CMD_RDY BIT(6)

sys/dev/crypto/tpm/tpm_tis.c

70

#define TPM_STS_CMD_START BIT(5)

sys/dev/crypto/tpm/tpm_tis.c

71

#define TPM_STS_DATA_AVAIL BIT(4)

sys/dev/crypto/tpm/tpm_tis.c

72

#define TPM_STS_DATA_EXPECTED BIT(3)

sys/dev/disk/amd/amd.h

132

#define PARITY_CHK BIT(0)

sys/dev/disk/amd/amd.h

133

#define SYNC_NEGO BIT(1)

sys/dev/disk/amd/amd.h

134

#define EN_DISCONNECT BIT(2)

sys/dev/disk/amd/amd.h

135

#define SEND_START BIT(3)

sys/dev/disk/amd/amd.h

136

#define TAG_QUEUING BIT(4)

sys/dev/disk/amd/amd.h

141

#define MORE2_DRV BIT(0)

sys/dev/disk/amd/amd.h

142

#define GREATER_1G BIT(1)

sys/dev/disk/amd/amd.h

143

#define RST_SCSI_BUS BIT(2)

sys/dev/disk/amd/amd.h

144

#define ACTIVE_NEGATION BIT(3)

sys/dev/disk/amd/amd.h

145

#define NO_SEEK BIT(4)

sys/dev/disk/amd/amd.h

146

#define LUN_CHECK BIT(5)

sys/dev/disk/amd/amd.h

253

#define SRB_READY BIT(1)

sys/dev/disk/amd/amd.h

254

#define SRB_MSGOUT BIT(2) /* ;arbitration+msg_out 1st byte */

sys/dev/disk/amd/amd.h

255

#define SRB_MSGIN BIT(3)

sys/dev/disk/amd/amd.h

256

#define SRB_MSGIN_MULTI BIT(4)

sys/dev/disk/amd/amd.h

257

#define SRB_COMMAND BIT(5)

sys/dev/disk/amd/amd.h

258

#define SRB_START BIT(6) /* ;arbitration+msg_out+command_out */

sys/dev/disk/amd/amd.h

259

#define SRB_DISCONNECT BIT(7)

sys/dev/disk/amd/amd.h

260

#define SRB_DATA_XFER BIT(8)

sys/dev/disk/amd/amd.h

261

#define SRB_XFERPAD BIT(9)

sys/dev/disk/amd/amd.h

262

#define SRB_STATUS BIT(10)

sys/dev/disk/amd/amd.h

263

#define SRB_COMPLETED BIT(11)

sys/dev/disk/amd/amd.h

264

#define SRB_ABORT_SENT BIT(12)

sys/dev/disk/amd/amd.h

265

#define DO_SYNC_NEGO BIT(13)

sys/dev/disk/amd/amd.h

266

#define SRB_UNEXPECT_RESEL BIT(14)

sys/dev/disk/amd/amd.h

271

#define RESET_DEV BIT(0)

sys/dev/disk/amd/amd.h

272

#define RESET_DETECT BIT(1)

sys/dev/disk/amd/amd.h

273

#define RESET_DONE BIT(2)

sys/dev/disk/amd/amd.h

278

#define ABORT_DEV_ BIT(0)

sys/dev/disk/amd/amd.h

283

#define SRB_OK BIT(0)

sys/dev/disk/amd/amd.h

284

#define ABORTION BIT(1)

sys/dev/disk/amd/amd.h

285

#define OVER_RUN BIT(2)

sys/dev/disk/amd/amd.h

286

#define UNDER_RUN BIT(3)

sys/dev/disk/amd/amd.h

287

#define PARITY_ERROR BIT(4)

sys/dev/disk/amd/amd.h

288

#define SRB_ERROR BIT(5)

sys/dev/disk/amd/amd.h

293

#define DATAOUT BIT(7)

sys/dev/disk/amd/amd.h

294

#define DATAIN BIT(6)

sys/dev/disk/amd/amd.h

295

#define RESIDUAL_VALID BIT(5)

sys/dev/disk/amd/amd.h

296

#define ENABLE_TIMER BIT(4)

sys/dev/disk/amd/amd.h

297

#define RESET_DEV0 BIT(2)

sys/dev/disk/amd/amd.h

298

#define ABORT_DEV BIT(1)

sys/dev/disk/amd/amd.h

299

#define AUTO_REQSENSE BIT(0)

sys/dev/disk/amd/amd.h

327

#define SYNC_ENABLE BIT(0)

sys/dev/disk/amd/amd.h

328

#define SYNC_NEGO_DONE BIT(1)

sys/dev/disk/amd/amd.h

329

#define WIDE_ENABLE BIT(2)

sys/dev/disk/amd/amd.h

330

#define WIDE_NEGO_DONE BIT(3)

sys/dev/disk/amd/amd.h

331

#define EN_TAG_QUEUING BIT(4)

sys/dev/disk/amd/amd.h

332

#define EN_ATN_STOP BIT(5)

sys/dev/disk/amd/amd.h

359

#define DMA_COMMAND BIT(7)

sys/dev/disk/amd/amd.h

381

#define INTERRUPT BIT(7)

sys/dev/disk/amd/amd.h

382

#define ILLEGAL_OP_ERR BIT(6)

sys/dev/disk/amd/amd.h

383

#define PARITY_ERR BIT(5)

sys/dev/disk/amd/amd.h

384

#define COUNT_2_ZERO BIT(4)

sys/dev/disk/amd/amd.h

385

#define GROUP_CODE_VALID BIT(3)

sys/dev/disk/amd/amd.h

386

#define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0))

sys/dev/disk/amd/amd.h

392

#define SCSI_RESET_ BIT(7)

sys/dev/disk/amd/amd.h

393

#define INVALID_CMD BIT(6)

sys/dev/disk/amd/amd.h

394

#define DISCONNECTED BIT(5)

sys/dev/disk/amd/amd.h

395

#define SERVICE_REQUEST BIT(4)

sys/dev/disk/amd/amd.h

396

#define SUCCESSFUL_OP BIT(3)

sys/dev/disk/amd/amd.h

397

#define RESELECTED BIT(2)

sys/dev/disk/amd/amd.h

398

#define SEL_ATTENTION BIT(1)

sys/dev/disk/amd/amd.h

399

#define SELECTED BIT(0)

sys/dev/disk/amd/amd.h

405

#define SYNC_OFFSET_FLAG BIT(3)

sys/dev/disk/amd/amd.h

406

#define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0))

sys/dev/disk/amd/amd.h

413

#define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0))

sys/dev/disk/amd/amd.h

414

#define CLK_FREQ_30MHZ (BIT(2)+BIT(1))

sys/dev/disk/amd/amd.h

415

#define CLK_FREQ_25MHZ (BIT(2)+BIT(0))

sys/dev/disk/amd/amd.h

416

#define CLK_FREQ_20MHZ BIT(2)

sys/dev/disk/amd/amd.h

417

#define CLK_FREQ_15MHZ (BIT(1)+BIT(0))

sys/dev/disk/amd/amd.h

418

#define CLK_FREQ_10MHZ BIT(1)

sys/dev/disk/amd/amd.h

424

#define EXTENDED_TIMING BIT(7)

sys/dev/disk/amd/amd.h

425

#define DIS_INT_ON_SCSI_RST BIT(6)

sys/dev/disk/amd/amd.h

426

#define PARITY_ERR_REPO BIT(4)

sys/dev/disk/amd/amd.h

427

#define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0))

sys/dev/disk/amd/amd.h

433

#define EN_FEATURE BIT(6)

sys/dev/disk/amd/amd.h

434

#define EN_SCSI2_CMD BIT(3)

sys/dev/disk/amd/amd.h

440

#define ID_MSG_CHECK BIT(7)

sys/dev/disk/amd/amd.h

441

#define EN_QTAG_MSG BIT(6)

sys/dev/disk/amd/amd.h

442

#define EN_GRP2_CMD BIT(5)

sys/dev/disk/amd/amd.h

443

#define FAST_SCSI BIT(4) /* ;10MB/SEC */

sys/dev/disk/amd/amd.h

444

#define FAST_CLK BIT(3) /* ;25 - 40 MHZ */

sys/dev/disk/amd/amd.h

451

#define EATER_25NS BIT(7)

sys/dev/disk/amd/amd.h

452

#define EATER_35NS BIT(6)

sys/dev/disk/amd/amd.h

453

#define EATER_0NS (BIT(7)+BIT(6))

sys/dev/disk/amd/amd.h

454

#define NEGATE_REQACKDATA BIT(2)

sys/dev/disk/amd/amd.h

455

#define NEGATE_REQACK BIT(3)

sys/dev/disk/amd/amd.h

467

#define READ_DIRECTION BIT(7)

sys/dev/disk/amd/amd.h

469

#define EN_DMA_INT BIT(6)

sys/dev/disk/amd/amd.h

470

#define MAP_TO_MDL BIT(5)

sys/dev/disk/amd/amd.h

471

#define DMA_DIAGNOSTIC BIT(4)

sys/dev/disk/amd/amd.h

473

#define DMA_BLAST_CMD BIT(0)

sys/dev/disk/amd/amd.h

474

#define DMA_ABORT_CMD BIT(1)

sys/dev/disk/amd/amd.h

475

#define DMA_START_CMD (BIT(1)|BIT(0))

sys/dev/disk/amd/amd.h

481

#define PCI_MS_ABORT BIT(6)

sys/dev/disk/amd/amd.h

482

#define BLAST_COMPLETE BIT(5)

sys/dev/disk/amd/amd.h

483

#define SCSI_INTERRUPT BIT(4)

sys/dev/disk/amd/amd.h

484

#define DMA_XFER_DONE BIT(3)

sys/dev/disk/amd/amd.h

485

#define DMA_XFER_ABORT BIT(2)

sys/dev/disk/amd/amd.h

486

#define DMA_XFER_ERROR BIT(1)

sys/dev/disk/amd/amd.h

487

#define POWER_DOWN BIT(0)

sys/dev/disk/iscsi/initiator/isc_sm.c

484

which = BIT(0) | BIT(1);

sys/dev/disk/iscsi/initiator/isc_sm.c

486

which |= BIT(2);

sys/dev/disk/iscsi/initiator/iscsi_subr.c

169

if(cmd->flag & (BIT(1)|BIT(2)))

sys/dev/disk/iscsi/initiator/iscsi_subr.c

318

while((pq = i_dqueue_snd(sp, BIT(0)|BIT(1)|BIT(2))) != NULL) {

sys/dev/disk/iscsi/initiator/iscsivar.h

475

if((which & BIT(0)) && (pq = TAILQ_FIRST(&sp->isnd)) != NULL) {

sys/dev/disk/iscsi/initiator/iscsivar.h

480

if((which & BIT(1)) && (pq = TAILQ_FIRST(&sp->wsnd)) != NULL) {

sys/dev/disk/iscsi/initiator/iscsivar.h

485

if((which & BIT(2)) && (pq = TAILQ_FIRST(&sp->csnd)) != NULL) {

sys/dev/disk/iscsi/initiator/iscsivar.h

65

#ifndef BIT

sys/dev/disk/iscsi/initiator/iscsivar.h

69

#define ISC_SM_RUN BIT(0)

sys/dev/disk/iscsi/initiator/iscsivar.h

70

#define ISC_SM_RUNNING BIT(1)

sys/dev/disk/iscsi/initiator/iscsivar.h

72

#define ISC_LINK_UP BIT(2)

sys/dev/disk/iscsi/initiator/iscsivar.h

73

#define ISC_CON_RUN BIT(3)

sys/dev/disk/iscsi/initiator/iscsivar.h

74

#define ISC_CON_RUNNING BIT(4)

sys/dev/disk/iscsi/initiator/iscsivar.h

75

#define ISC_KILL BIT(5)

sys/dev/disk/iscsi/initiator/iscsivar.h

76

#define ISC_OQNOTEMPTY BIT(6)

sys/dev/disk/iscsi/initiator/iscsivar.h

77

#define ISC_OWAITING BIT(7)

sys/dev/disk/iscsi/initiator/iscsivar.h

78

#define ISC_FFPHASE BIT(8)

sys/dev/disk/iscsi/initiator/iscsivar.h

79

#define ISC_FFPWAIT BIT(9)

sys/dev/disk/iscsi/initiator/iscsivar.h

81

#define ISC_MEMWAIT BIT(10)

sys/dev/disk/iscsi/initiator/iscsivar.h

82

#define ISC_SIGNALED BIT(11)

sys/dev/disk/iscsi/initiator/iscsivar.h

83

#define ISC_FROZEN BIT(12)

sys/dev/disk/iscsi/initiator/iscsivar.h

84

#define ISC_STALLED BIT(13)

sys/dev/disk/iscsi/initiator/iscsivar.h

86

#define ISC_HOLD BIT(14)

sys/dev/disk/iscsi/initiator/iscsivar.h

87

#define ISC_HOLDED BIT(15)

sys/dev/disk/iscsi/initiator/iscsivar.h

89

#define ISC_SHUTDOWN BIT(31)

sys/dev/drm/drm_atomic_helper.c

668

connectors_mask |= BIT(i);

sys/dev/drm/drm_atomic_helper.c

702

if (connectors_mask & BIT(i))

sys/dev/drm/drm_blend.c

308

BIT((ffs(rotation & DRM_MODE_ROTATE_MASK) + 1)

sys/dev/drm/drm_blend.c

559

unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) |

sys/dev/drm/drm_blend.c

560

BIT(DRM_MODE_BLEND_PREMULTI) |

sys/dev/drm/drm_blend.c

561

BIT(DRM_MODE_BLEND_COVERAGE);

sys/dev/drm/drm_blend.c

565

((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0)))

sys/dev/drm/drm_blend.c

577

if (!(BIT(props[i].type) & supported_modes))

sys/dev/drm/drm_color_mgmt.c

425

(supported_encodings & -BIT(DRM_COLOR_ENCODING_MAX)) != 0 ||

sys/dev/drm/drm_color_mgmt.c

426

(supported_encodings & BIT(default_encoding)) == 0))

sys/dev/drm/drm_color_mgmt.c

430

(supported_ranges & -BIT(DRM_COLOR_RANGE_MAX)) != 0 ||

sys/dev/drm/drm_color_mgmt.c

431

(supported_ranges & BIT(default_range)) == 0))

sys/dev/drm/drm_color_mgmt.c

436

if ((supported_encodings & BIT(i)) == 0)

sys/dev/drm/drm_color_mgmt.c

455

if ((supported_ranges & BIT(i)) == 0)

sys/dev/drm/drm_connector.c

1296

if (!(BIT(i) & scaling_mode_mask))

sys/dev/drm/drm_dp_helper.c

1279

{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },

sys/dev/drm/drm_dp_helper.c

1281

{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },

sys/dev/drm/i915/i915_drv.h

2251

BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \

sys/dev/drm/i915/i915_drv.h

2254

BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))

sys/dev/drm/i915/i915_drv.h

2402

#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))

sys/dev/drm/i915/i915_drv.h

2549

#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))

sys/dev/drm/i915/i915_drv.h

2550

#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))

sys/dev/drm/i915/i915_drv.h

2551

#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))

sys/dev/drm/i915/i915_drv.h

2552

#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))

sys/dev/drm/i915/i915_drv.h

2553

#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))

sys/dev/drm/i915/i915_drv.h

2554

#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))

sys/dev/drm/i915/i915_drv.h

2555

#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))

sys/dev/drm/i915/i915_drv.h

2556

#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))

sys/dev/drm/i915/i915_drv.h

2557

#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))

sys/dev/drm/i915/i915_drv.h

2558

#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))

sys/dev/drm/i915/i915_drv.h

2564

#define ENGINE_MASK(id) BIT(id)

sys/dev/drm/i915/i915_drv.h

2835

#define I915_ERROR_CAPTURE BIT(0)

sys/dev/drm/i915/i915_drv.h

3150

#define CLFLUSH_BEFORE BIT(0)

sys/dev/drm/i915/i915_drv.h

3151

#define CLFLUSH_AFTER BIT(1)

sys/dev/drm/i915/i915_gem.c

1140

obj_do_bit17_swizzling = BIT(17);

sys/dev/drm/i915/i915_gem.c

1590

obj_do_bit17_swizzling = BIT(17);

sys/dev/drm/i915/i915_gem.c

3088

obj->mm.page_sizes.sg |= BIT(i);

sys/dev/drm/i915/i915_gem.c

5877

unsigned int bit = BIT(engine->uabi_class);

sys/dev/drm/i915/i915_gem_clflush.h

33

#define I915_CLFLUSH_FORCE BIT(0)

sys/dev/drm/i915/i915_gem_clflush.h

34

#define I915_CLFLUSH_SYNC BIT(1)

sys/dev/drm/i915/i915_gem_execbuffer.c

51

#define __EXEC_OBJECT_HAS_REF BIT(31)

sys/dev/drm/i915/i915_gem_execbuffer.c

52

#define __EXEC_OBJECT_HAS_PIN BIT(30)

sys/dev/drm/i915/i915_gem_execbuffer.c

53

#define __EXEC_OBJECT_HAS_FENCE BIT(29)

sys/dev/drm/i915/i915_gem_execbuffer.c

54

#define __EXEC_OBJECT_NEEDS_MAP BIT(28)

sys/dev/drm/i915/i915_gem_execbuffer.c

55

#define __EXEC_OBJECT_NEEDS_BIAS BIT(27)

sys/dev/drm/i915/i915_gem_execbuffer.c

59

#define __EXEC_HAS_RELOC BIT(31)

sys/dev/drm/i915/i915_gem_execbuffer.c

60

#define __EXEC_VALIDATED BIT(30)

sys/dev/drm/i915/i915_gem_fence_reg.c

140

val |= BIT(I830_FENCE_TILING_Y_SHIFT);

sys/dev/drm/i915/i915_gem_fence_reg.c

173

val |= BIT(I830_FENCE_TILING_Y_SHIFT);

sys/dev/drm/i915/i915_gem_fence_reg.c

91

val |= BIT(I965_FENCE_TILING_Y_SHIFT);

sys/dev/drm/i915/i915_gem_gtt.c

3242

AGE_MATCH = BIT(0),

sys/dev/drm/i915/i915_gem_gtt.c

3243

TC_MATCH = BIT(1),

sys/dev/drm/i915/i915_gem_gtt.c

3244

CA_MATCH = BIT(2),

sys/dev/drm/i915/i915_gem_gtt.c

690

dma_unmap_page(vm->dma, p->daddr, BIT(p->order) << PAGE_SHIFT,

sys/dev/drm/i915/i915_gem_gtt.h

164

#define GEN8_PDE_IPS_64K BIT(11)

sys/dev/drm/i915/i915_gem_gtt.h

165

#define GEN8_PDE_PS_2M BIT(7)

sys/dev/drm/i915/i915_gem_object.h

146

#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)

sys/dev/drm/i915/i915_gem_object.h

147

#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)

sys/dev/drm/i915/i915_gem_object.h

56

#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)

sys/dev/drm/i915/i915_gem_object.h

57

#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)

sys/dev/drm/i915/i915_gem_object.h

58

#define I915_GEM_OBJECT_IS_PROXY BIT(2)

sys/dev/drm/i915/i915_irq.c

1717

*pin_mask |= BIT(pin);

sys/dev/drm/i915/i915_irq.c

1720

*long_mask |= BIT(pin);

sys/dev/drm/i915/i915_irq.c

276

if (dw & BIT(bit)) {

sys/dev/drm/i915/i915_irq.c

289

raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));

sys/dev/drm/i915/i915_irq.c

2978

raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));

sys/dev/drm/i915/i915_params.h

33

#define ENABLE_GUC_SUBMISSION BIT(0)

sys/dev/drm/i915/i915_params.h

34

#define ENABLE_GUC_LOAD_HUC BIT(1)

sys/dev/drm/i915/i915_pci.c

32

#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)

sys/dev/drm/i915/i915_pci.c

33

#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)

sys/dev/drm/i915/i915_pmu.c

105

enable &= ~BIT(I915_SAMPLE_BUSY);

sys/dev/drm/i915/i915_pmu.c

17

(BIT(I915_SAMPLE_BUSY) | \

sys/dev/drm/i915/i915_pmu.c

18

BIT(I915_SAMPLE_WAIT) | \

sys/dev/drm/i915/i915_pmu.c

19

BIT(I915_SAMPLE_SEMA))

sys/dev/drm/i915/i915_pmu.c

193

(BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA)))) {

sys/dev/drm/i915/i915_pmu.c

619

engine->pmu.enable |= BIT(sample);

sys/dev/drm/i915/i915_pmu.c

660

engine->pmu.enable &= ~BIT(sample);

sys/dev/drm/i915/i915_pvinfo.h

55

#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)

sys/dev/drm/i915/i915_pvinfo.h

56

#define VGT_CAPS_HWSP_EMULATION BIT(3)

sys/dev/drm/i915/i915_pvinfo.h

57

#define VGT_CAPS_HUGE_GTT BIT(4)

sys/dev/drm/i915/i915_reg.h

3849

#define CCID_EN BIT(0)

sys/dev/drm/i915/i915_reg.h

3850

#define CCID_EXTENDED_STATE_RESTORE BIT(2)

sys/dev/drm/i915/i915_reg.h

3851

#define CCID_EXTENDED_STATE_SAVE BIT(3)

sys/dev/drm/i915/i915_reg.h

8316

#define FORCEWAKE_KERNEL BIT(0)

sys/dev/drm/i915/i915_reg.h

8317

#define FORCEWAKE_USER BIT(1)

sys/dev/drm/i915/i915_reg.h

8318

#define FORCEWAKE_KERNEL_FALLBACK BIT(15)

sys/dev/drm/i915/i915_reg.h

8936

#define HDCP_AKSV_SEND_TRIGGER BIT(31)

sys/dev/drm/i915/i915_reg.h

8937

#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)

sys/dev/drm/i915/i915_reg.h

8938

#define HDCP_KEY_LOAD_TRIGGER BIT(8)

sys/dev/drm/i915/i915_reg.h

8940

#define HDCP_FUSE_IN_PROGRESS BIT(7)

sys/dev/drm/i915/i915_reg.h

8941

#define HDCP_FUSE_ERROR BIT(6)

sys/dev/drm/i915/i915_reg.h

8942

#define HDCP_FUSE_DONE BIT(5)

sys/dev/drm/i915/i915_reg.h

8943

#define HDCP_KEY_LOAD_STATUS BIT(1)

sys/dev/drm/i915/i915_reg.h

8944

#define HDCP_KEY_LOAD_DONE BIT(0)

sys/dev/drm/i915/i915_reg.h

8950

#define HDCP_DDIB_REP_PRESENT BIT(30)

sys/dev/drm/i915/i915_reg.h

8951

#define HDCP_DDIA_REP_PRESENT BIT(29)

sys/dev/drm/i915/i915_reg.h

8952

#define HDCP_DDIC_REP_PRESENT BIT(28)

sys/dev/drm/i915/i915_reg.h

8953

#define HDCP_DDID_REP_PRESENT BIT(27)

sys/dev/drm/i915/i915_reg.h

8954

#define HDCP_DDIF_REP_PRESENT BIT(26)

sys/dev/drm/i915/i915_reg.h

8955

#define HDCP_DDIE_REP_PRESENT BIT(25)

sys/dev/drm/i915/i915_reg.h

8962

#define HDCP_SHA1_BUSY BIT(16)

sys/dev/drm/i915/i915_reg.h

8963

#define HDCP_SHA1_READY BIT(17)

sys/dev/drm/i915/i915_reg.h

8964

#define HDCP_SHA1_COMPLETE BIT(18)

sys/dev/drm/i915/i915_reg.h

8965

#define HDCP_SHA1_V_MATCH BIT(19)

sys/dev/drm/i915/i915_reg.h

8995

#define HDCP_CONF_CAPTURE_AN BIT(0)

sys/dev/drm/i915/i915_reg.h

8996

#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))

sys/dev/drm/i915/i915_reg.h

9004

#define HDCP_STATUS_STREAM_A_ENC BIT(31)

sys/dev/drm/i915/i915_reg.h

9005

#define HDCP_STATUS_STREAM_B_ENC BIT(30)

sys/dev/drm/i915/i915_reg.h

9006

#define HDCP_STATUS_STREAM_C_ENC BIT(29)

sys/dev/drm/i915/i915_reg.h

9007

#define HDCP_STATUS_STREAM_D_ENC BIT(28)

sys/dev/drm/i915/i915_reg.h

9008

#define HDCP_STATUS_AUTH BIT(21)

sys/dev/drm/i915/i915_reg.h

9009

#define HDCP_STATUS_ENC BIT(20)

sys/dev/drm/i915/i915_reg.h

9010

#define HDCP_STATUS_RI_MATCH BIT(19)

sys/dev/drm/i915/i915_reg.h

9011

#define HDCP_STATUS_R0_READY BIT(18)

sys/dev/drm/i915/i915_reg.h

9012

#define HDCP_STATUS_AN_READY BIT(17)

sys/dev/drm/i915/i915_reg.h

9013

#define HDCP_STATUS_CIPHER BIT(16)

sys/dev/drm/i915/i915_request.h

279

#define I915_WAIT_INTERRUPTIBLE BIT(0)

sys/dev/drm/i915/i915_request.h

280

#define I915_WAIT_LOCKED BIT(1) /* struct_mutex held, handle GPU reset */

sys/dev/drm/i915/i915_request.h

281

#define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */

sys/dev/drm/i915/i915_request.h

282

#define I915_WAIT_FOR_IDLE_BOOST BIT(3)

sys/dev/drm/i915/i915_request.h

727

for (; mask ? idx = ffs(mask) - 1, 1 : 0; mask &= ~BIT(idx))

sys/dev/drm/i915/i915_scheduler.h

69

#define I915_DEPENDENCY_ALLOC BIT(0)

sys/dev/drm/i915/i915_sw_fence.c

18

#define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */

sys/dev/drm/i915/i915_syncmap.c

192

if (!(p->bitmap & BIT(idx)))

sys/dev/drm/i915/i915_syncmap.c

218

p->bitmap |= BIT(idx);

sys/dev/drm/i915/i915_syncmap.c

226

p->bitmap |= BIT(idx);

sys/dev/drm/i915/i915_syncmap.c

300

GEM_BUG_ON(!(p->parent->bitmap & BIT(idx)));

sys/dev/drm/i915/i915_sysfs.c

63

mask |= BIT(0);

sys/dev/drm/i915/i915_sysfs.c

65

mask |= BIT(1);

sys/dev/drm/i915/i915_sysfs.c

67

mask |= BIT(2);

sys/dev/drm/i915/i915_utils.h

117

mask &= ~BIT(__idx); \

sys/dev/drm/i915/i915_utils.h

75

(typeof(ptr))(__v & -BIT(n)); \

sys/dev/drm/i915/i915_utils.h

78

#define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1))

sys/dev/drm/i915/i915_utils.h

82

*(bits) = __v & (BIT(n) - 1); \

sys/dev/drm/i915/i915_utils.h

83

(typeof(ptr))(__v & -BIT(n)); \

sys/dev/drm/i915/i915_utils.h

88

GEM_BUG_ON(__bits & -BIT(n)); \

sys/dev/drm/i915/i915_vma.h

142

#define I915_VMA_RELEASE_MAP BIT(0)

sys/dev/drm/i915/i915_vma.h

84

#define I915_VMA_PIN_OVERFLOW BIT(5)

sys/dev/drm/i915/i915_vma.h

87

#define I915_VMA_GLOBAL_BIND BIT(6)

sys/dev/drm/i915/i915_vma.h

88

#define I915_VMA_LOCAL_BIND BIT(7)

sys/dev/drm/i915/i915_vma.h

91

#define I915_VMA_GGTT BIT(8)

sys/dev/drm/i915/i915_vma.h

92

#define I915_VMA_CAN_FENCE BIT(9)

sys/dev/drm/i915/i915_vma.h

93

#define I915_VMA_CLOSED BIT(10)

sys/dev/drm/i915/i915_vma.h

95

#define I915_VMA_USERFAULT BIT(I915_VMA_USERFAULT_BIT)

sys/dev/drm/i915/i915_vma.h

96

#define I915_VMA_GGTT_WRITE BIT(12)

sys/dev/drm/i915/intel_atomic_plane.c

130

crtc_state->active_planes |= BIT(intel_plane->id);

sys/dev/drm/i915/intel_atomic_plane.c

132

crtc_state->active_planes &= ~BIT(intel_plane->id);

sys/dev/drm/i915/intel_atomic_plane.c

135

crtc_state->nv12_planes |= BIT(intel_plane->id);

sys/dev/drm/i915/intel_atomic_plane.c

137

crtc_state->nv12_planes &= ~BIT(intel_plane->id);

sys/dev/drm/i915/intel_bios.c

763

dev_priv->vbt.dsi.bl_ports = BIT(port);

sys/dev/drm/i915/intel_bios.c

765

dev_priv->vbt.dsi.cabc_ports = BIT(port);

sys/dev/drm/i915/intel_bios.c

772

dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);

sys/dev/drm/i915/intel_bios.c

775

dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);

sys/dev/drm/i915/intel_bios.c

779

dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);

sys/dev/drm/i915/intel_bios.c

788

dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);

sys/dev/drm/i915/intel_bios.c

791

dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);

sys/dev/drm/i915/intel_bios.c

796

BIT(PORT_A) | BIT(PORT_C);

sys/dev/drm/i915/intel_crt.c

124

pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);

sys/dev/drm/i915/intel_ddi.c

3419

pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);

sys/dev/drm/i915/intel_ddi.c

3423

pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);

sys/dev/drm/i915/intel_ddi.c

3427

pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);

sys/dev/drm/i915/intel_ddi.c

3429

pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);

sys/dev/drm/i915/intel_ddi.c

3435

pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);

sys/dev/drm/i915/intel_device_info.c

175

ss_en_mask = BIT(sseu->max_subslices) - 1;

sys/dev/drm/i915/intel_device_info.c

179

if (s_en & BIT(s)) {

sys/dev/drm/i915/intel_device_info.c

183

sseu->slice_mask |= BIT(s);

sys/dev/drm/i915/intel_device_info.c

186

if (sseu->subslice_mask[s] & BIT(ss))

sys/dev/drm/i915/intel_device_info.c

255

sseu->subslice_mask[s] &= ~BIT(ss);

sys/dev/drm/i915/intel_device_info.c

284

sseu->slice_mask = BIT(0);

sys/dev/drm/i915/intel_device_info.c

296

sseu->subslice_mask[0] |= BIT(0);

sys/dev/drm/i915/intel_device_info.c

307

sseu->subslice_mask[0] |= BIT(1);

sys/dev/drm/i915/intel_device_info.c

359

if (!(sseu->slice_mask & BIT(s)))

sys/dev/drm/i915/intel_device_info.c

370

if (!(sseu->subslice_mask[s] & BIT(ss)))

sys/dev/drm/i915/intel_device_info.c

387

sseu->subslice_7eu[s] |= BIT(ss);

sys/dev/drm/i915/intel_device_info.c

418

#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))

sys/dev/drm/i915/intel_device_info.c

467

if (!(sseu->slice_mask & BIT(s)))

sys/dev/drm/i915/intel_device_info.c

477

if (!(sseu->subslice_mask[s] & BIT(ss)))

sys/dev/drm/i915/intel_device_info.c

532

sseu->slice_mask = BIT(0);

sys/dev/drm/i915/intel_device_info.c

533

sseu->subslice_mask[0] = BIT(0);

sys/dev/drm/i915/intel_device_info.c

536

sseu->slice_mask = BIT(0);

sys/dev/drm/i915/intel_device_info.c

537

sseu->subslice_mask[0] = BIT(0) | BIT(1);

sys/dev/drm/i915/intel_device_info.c

540

sseu->slice_mask = BIT(0) | BIT(1);

sys/dev/drm/i915/intel_device_info.c

541

sseu->subslice_mask[0] = BIT(0) | BIT(1);

sys/dev/drm/i915/intel_device_info.c

542

sseu->subslice_mask[1] = BIT(0) | BIT(1);

sys/dev/drm/i915/intel_device_info.c

814

disabled_mask |= BIT(PIPE_A);

sys/dev/drm/i915/intel_device_info.c

816

disabled_mask |= BIT(PIPE_B);

sys/dev/drm/i915/intel_device_info.c

818

disabled_mask |= BIT(PIPE_C);

sys/dev/drm/i915/intel_device_info.c

823

case BIT(PIPE_A):

sys/dev/drm/i915/intel_device_info.c

824

case BIT(PIPE_B):

sys/dev/drm/i915/intel_device_info.c

825

case BIT(PIPE_A) | BIT(PIPE_B):

sys/dev/drm/i915/intel_device_info.c

826

case BIT(PIPE_A) | BIT(PIPE_C):

sys/dev/drm/i915/intel_device_info.c

893

if (!(BIT(i) & vdbox_disable))

sys/dev/drm/i915/intel_device_info.c

905

if (!(BIT(i) & vebox_disable))

sys/dev/drm/i915/intel_display.c

10763

to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);

sys/dev/drm/i915/intel_display.c

11082

if ((output_types & BIT(i)) == 0)

sys/dev/drm/i915/intel_display.c

11092

output_types &= ~BIT(i);

sys/dev/drm/i915/intel_display.c

11373

BIT(encoder->compute_output_type(encoder, pipe_config,

sys/dev/drm/i915/intel_display.c

11376

pipe_config->output_types |= BIT(encoder->type);

sys/dev/drm/i915/intel_display.c

13952

BIT(DRM_COLOR_YCBCR_BT601) |

sys/dev/drm/i915/intel_display.c

13953

BIT(DRM_COLOR_YCBCR_BT709),

sys/dev/drm/i915/intel_display.c

13954

BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |

sys/dev/drm/i915/intel_display.c

13955

BIT(DRM_COLOR_YCBCR_FULL_RANGE),

sys/dev/drm/i915/intel_display.c

14095

intel_crtc->plane_ids_mask |= BIT(primary->id);

sys/dev/drm/i915/intel_display.c

14105

intel_crtc->plane_ids_mask |= BIT(plane->id);

sys/dev/drm/i915/intel_display.c

14113

intel_crtc->plane_ids_mask |= BIT(cursor->id);

sys/dev/drm/i915/intel_display.c

2811

crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);

sys/dev/drm/i915/intel_display.c

5165

WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));

sys/dev/drm/i915/intel_display.c

6666

if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))

sys/dev/drm/i915/intel_display.c

9569

for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {

sys/dev/drm/i915/intel_display.h

130

for_each_if((__crtc)->plane_ids_mask & BIT(__p))

sys/dev/drm/i915/intel_display.h

284

for_each_if((__mask) & BIT(__p))

sys/dev/drm/i915/intel_display.h

302

for_each_if((__ports_mask) & BIT(__port))

sys/dev/drm/i915/intel_dp.c

2909

pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);

sys/dev/drm/i915/intel_dp.c

2911

pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);

sys/dev/drm/i915/intel_dp.c

5754

allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);

sys/dev/drm/i915/intel_dp.c

5756

allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);

sys/dev/drm/i915/intel_dpio_phy.c

160

.pwron_mask = BIT(0),

sys/dev/drm/i915/intel_dpio_phy.c

170

.pwron_mask = BIT(1),

sys/dev/drm/i915/intel_dpio_phy.c

182

.pwron_mask = BIT(0),

sys/dev/drm/i915/intel_dpio_phy.c

192

.pwron_mask = BIT(3),

sys/dev/drm/i915/intel_dpio_phy.c

202

.pwron_mask = BIT(1),

sys/dev/drm/i915/intel_dpio_phy.c

577

return BIT(2) | BIT(0);

sys/dev/drm/i915/intel_dpio_phy.c

579

return BIT(3) | BIT(2) | BIT(0);

sys/dev/drm/i915/intel_dpio_phy.c

606

if (lane_lat_optim_mask & BIT(lane))

sys/dev/drm/i915/intel_dpio_phy.c

630

mask |= BIT(lane);

sys/dev/drm/i915/intel_drv.h

515

#define PLANE_HAS_FENCE BIT(0)

sys/dev/drm/i915/intel_dvo.c

158

pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);

sys/dev/drm/i915/intel_engine_cs.c

1175

which |= BIT(engine->uabi_class);

sys/dev/drm/i915/intel_engine_cs.c

273

BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));

sys/dev/drm/i915/intel_engine_cs.c

274

BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));

sys/dev/drm/i915/intel_engine_cs.c

303

if (WARN_ON(engine->context_size > BIT(20)))

sys/dev/drm/i915/intel_fbdev.c

393

if (conn_configured & BIT(i))

sys/dev/drm/i915/intel_fbdev.c

406

conn_configured |= BIT(i);

sys/dev/drm/i915/intel_fbdev.c

425

conn_configured |= BIT(i);

sys/dev/drm/i915/intel_fbdev.c

498

conn_configured |= BIT(i);

sys/dev/drm/i915/intel_guc_fwif.h

65

#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)

sys/dev/drm/i915/intel_guc_fwif.h

66

#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)

sys/dev/drm/i915/intel_guc_fwif.h

67

#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)

sys/dev/drm/i915/intel_guc_fwif.h

68

#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)

sys/dev/drm/i915/intel_guc_fwif.h

69

#define GUC_STAGE_DESC_ATTR_RESET BIT(4)

sys/dev/drm/i915/intel_guc_fwif.h

70

#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)

sys/dev/drm/i915/intel_guc_fwif.h

708

INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),

sys/dev/drm/i915/intel_guc_fwif.h

709

INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)

sys/dev/drm/i915/intel_guc_fwif.h

71

#define GUC_STAGE_DESC_ATTR_PCH BIT(6)

sys/dev/drm/i915/intel_guc_fwif.h

72

#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)

sys/dev/drm/i915/intel_hangcheck.c

249

i915_handle_error(dev_priv, BIT(engine->id), 0,

sys/dev/drm/i915/intel_hdmi.c

1203

pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);

sys/dev/drm/i915/intel_hotplug.c

305

long_hpd = long_port_mask & BIT(port);

sys/dev/drm/i915/intel_hotplug.c

306

short_hpd = short_port_mask & BIT(port);

sys/dev/drm/i915/intel_hotplug.c

316

old_bits |= BIT(encoder->hpd_pin);

sys/dev/drm/i915/intel_hotplug.c

421

if (!(BIT(pin) & pin_mask))

sys/dev/drm/i915/intel_hotplug.c

427

long_hpd = long_mask & BIT(pin);

sys/dev/drm/i915/intel_hotplug.c

434

long_hpd_pulse_mask |= BIT(pin);

sys/dev/drm/i915/intel_hotplug.c

435

dev_priv->hotplug.long_port_mask |= BIT(port);

sys/dev/drm/i915/intel_hotplug.c

437

short_hpd_pulse_mask |= BIT(pin);

sys/dev/drm/i915/intel_hotplug.c

438

dev_priv->hotplug.short_port_mask |= BIT(port);

sys/dev/drm/i915/intel_hotplug.c

446

if (!(BIT(pin) & pin_mask))

sys/dev/drm/i915/intel_hotplug.c

469

if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {

sys/dev/drm/i915/intel_hotplug.c

470

long_hpd = long_hpd_pulse_mask & BIT(pin);

sys/dev/drm/i915/intel_hotplug.c

472

dev_priv->hotplug.event_bits |= BIT(pin);

sys/dev/drm/i915/intel_hotplug.c

481

dev_priv->hotplug.event_bits &= ~BIT(pin);

sys/dev/drm/i915/intel_lrc.c

2099

(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));

sys/dev/drm/i915/intel_lrc.c

227

BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));

sys/dev/drm/i915/intel_lrc.c

228

BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));

sys/dev/drm/i915/intel_lrc.c

243

GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));

sys/dev/drm/i915/intel_lrc.c

255

GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));

sys/dev/drm/i915/intel_lrc.c

2752

regs[CTX_END] |= BIT(0);

sys/dev/drm/i915/intel_lvds.c

128

pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);

sys/dev/drm/i915/intel_lvds.c

973

allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);

sys/dev/drm/i915/intel_lvds.c

974

allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);

sys/dev/drm/i915/intel_lvds.c

975

allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);

sys/dev/drm/i915/intel_pm.c

1318

~BIT(PLANE_CURSOR));

sys/dev/drm/i915/intel_pm.c

1335

dirty |= BIT(plane->id);

sys/dev/drm/i915/intel_pm.c

1359

wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);

sys/dev/drm/i915/intel_pm.c

1639

return (active_planes & (BIT(PLANE_SPRITE0) |

sys/dev/drm/i915/intel_pm.c

1640

BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);

sys/dev/drm/i915/intel_pm.c

1649

unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/drm/i915/intel_pm.c

1682

if ((active_planes & BIT(plane_id)) == 0) {

sys/dev/drm/i915/intel_pm.c

1706

if ((active_planes & BIT(plane_id)) == 0)

sys/dev/drm/i915/intel_pm.c

1840

~BIT(PLANE_CURSOR));

sys/dev/drm/i915/intel_pm.c

1857

dirty |= BIT(plane->id);

sys/dev/drm/i915/intel_pm.c

1873

if (dirty & ~BIT(PLANE_CURSOR)) {

sys/dev/drm/i915/intel_pm.c

8276

if (params & BIT(31)) { /* OC supported */

sys/dev/drm/i915/intel_psr.c

148

u32 transcoders = BIT(TRANSCODER_EDP);

sys/dev/drm/i915/intel_psr.c

153

transcoders |= BIT(TRANSCODER_A) |

sys/dev/drm/i915/intel_psr.c

154

BIT(TRANSCODER_B) |

sys/dev/drm/i915/intel_psr.c

155

BIT(TRANSCODER_C);

sys/dev/drm/i915/intel_ringbuffer.c

1785

if (!(ctx->remap_slice & BIT(i)))

sys/dev/drm/i915/intel_ringbuffer.c

439

mask &= ~BIT(0);

sys/dev/drm/i915/intel_ringbuffer.c

721

if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))

sys/dev/drm/i915/intel_ringbuffer.h

1037

#define ENGINE_WAKEUP_WAITER BIT(0)

sys/dev/drm/i915/intel_ringbuffer.h

1038

#define ENGINE_WAKEUP_ASLEEP BIT(1)

sys/dev/drm/i915/intel_ringbuffer.h

108

for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \

sys/dev/drm/i915/intel_ringbuffer.h

109

(BIT(subslice__) & instdone_subslice_mask(dev_priv__)))

sys/dev/drm/i915/intel_ringbuffer.h

471

#define EMIT_INVALIDATE BIT(0)

sys/dev/drm/i915/intel_ringbuffer.h

472

#define EMIT_FLUSH BIT(1)

sys/dev/drm/i915/intel_ringbuffer.h

477

#define I915_DISPATCH_SECURE BIT(0)

sys/dev/drm/i915/intel_ringbuffer.h

478

#define I915_DISPATCH_PINNED BIT(1)

sys/dev/drm/i915/intel_ringbuffer.h

588

#define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)

sys/dev/drm/i915/intel_ringbuffer.h

589

#define I915_ENGINE_SUPPORTS_STATS BIT(1)

sys/dev/drm/i915/intel_ringbuffer.h

590

#define I915_ENGINE_HAS_PREEMPTION BIT(2)

sys/dev/drm/i915/intel_ringbuffer.h

741

return BIT(engine->id);

sys/dev/drm/i915/intel_runtime_pm.c

2139

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2338

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2418

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2477

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2645

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2776

.hsw.irq_pipe_mask = BIT(PIPE_B),

sys/dev/drm/i915/intel_runtime_pm.c

2950

.hsw.irq_pipe_mask = BIT(PIPE_C),

sys/dev/drm/i915/intel_sdvo.c

1450

pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);

sys/dev/drm/i915/intel_sprite.c

1900

BIT(DRM_COLOR_YCBCR_BT601) |

sys/dev/drm/i915/intel_sprite.c

1901

BIT(DRM_COLOR_YCBCR_BT709),

sys/dev/drm/i915/intel_sprite.c

1902

BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |

sys/dev/drm/i915/intel_sprite.c

1903

BIT(DRM_COLOR_YCBCR_FULL_RANGE),

sys/dev/drm/i915/intel_tv.c

868

pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);

sys/dev/drm/i915/intel_uncore.c

1369

d->mask = BIT(domain_id);

sys/dev/drm/i915/intel_uncore.c

1374

dev_priv->uncore.fw_domains |= BIT(domain_id);

sys/dev/drm/i915/intel_uncore.c

1393

dev_priv->uncore.fw_domains &= ~BIT(domain_id);

sys/dev/drm/i915/intel_uncore.c

1627

if (fw_domains & BIT(domain_id))

sys/dev/drm/i915/intel_uncore.c

1637

if (fw_domains & BIT(domain_id))

sys/dev/drm/i915/intel_uncore.h

51

FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),

sys/dev/drm/i915/intel_uncore.h

52

FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),

sys/dev/drm/i915/intel_uncore.h

53

FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),

sys/dev/drm/i915/intel_uncore.h

54

FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),

sys/dev/drm/i915/intel_uncore.h

55

FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),

sys/dev/drm/i915/intel_uncore.h

56

FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),

sys/dev/drm/i915/intel_uncore.h

57

FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),

sys/dev/drm/i915/intel_uncore.h

58

FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),

sys/dev/drm/i915/intel_uncore.h

59

FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),

sys/dev/drm/i915/intel_uncore.h

61

FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1

sys/dev/drm/i915/vlv_dsi.c

1258

pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);

sys/dev/drm/i915/vlv_dsi.c

1695

if (connector->encoder->crtc_mask == BIT(PIPE_B))

sys/dev/drm/i915/vlv_dsi.c

1715

allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);

sys/dev/drm/i915/vlv_dsi.c

1717

allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);

sys/dev/drm/i915/vlv_dsi.c

1791

intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);

sys/dev/drm/i915/vlv_dsi.c

1793

intel_encoder->crtc_mask = BIT(PIPE_A);

sys/dev/drm/i915/vlv_dsi.c

1795

intel_encoder->crtc_mask = BIT(PIPE_B);

sys/dev/drm/i915/vlv_dsi.c

1798

intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);

sys/dev/drm/i915/vlv_dsi.c

1800

intel_dsi->ports = BIT(port);

sys/dev/drm/i915/vlv_dsi.c

341

if (intel_dsi->ports == BIT(PORT_C))

sys/dev/drm/i915/vlv_dsi.c

709

if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {

sys/dev/drm/include/drm/drm_atomic_helper.h

84

#define DRM_PLANE_COMMIT_ACTIVE_ONLY BIT(0)

sys/dev/drm/include/drm/drm_atomic_helper.h

85

#define DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET BIT(1)

sys/dev/drm/include/drm/drm_dp_helper.h

1282

return desc->quirks & BIT(quirk);

sys/dev/drm/include/drm/drm_dp_helper.h

897

# define DP_BCAPS_REPEATER_PRESENT BIT(1)

sys/dev/drm/include/drm/drm_dp_helper.h

898

# define DP_BCAPS_HDCP_CAPABLE BIT(0)

sys/dev/drm/include/drm/drm_dp_helper.h

900

# define DP_BSTATUS_REAUTH_REQ BIT(3)

sys/dev/drm/include/drm/drm_dp_helper.h

901

# define DP_BSTATUS_LINK_FAILURE BIT(2)

sys/dev/drm/include/drm/drm_dp_helper.h

902

# define DP_BSTATUS_R0_PRIME_READY BIT(1)

sys/dev/drm/include/drm/drm_dp_helper.h

903

# define DP_BSTATUS_READY BIT(0)

sys/dev/drm/include/drm/drm_hdcp.h

23

#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))

sys/dev/drm/include/drm/drm_hdcp.h

24

#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))

sys/dev/drm/include/drm/drm_hdcp.h

36

#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)

sys/dev/drm/include/drm/drm_hdcp.h

37

#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)

sys/dev/drm/include/drm/drm_ioctl.h

101

DRM_MASTER = BIT(1),

sys/dev/drm/include/drm/drm_ioctl.h

112

DRM_ROOT_ONLY = BIT(2),

sys/dev/drm/include/drm/drm_ioctl.h

120

DRM_UNLOCKED = BIT(4),

sys/dev/drm/include/drm/drm_ioctl.h

130

DRM_RENDER_ALLOW = BIT(5),

sys/dev/drm/include/drm/drm_ioctl.h

89

DRM_AUTH = BIT(0),

sys/dev/drm/include/drm/drm_mipi_dsi.h

114

#define MIPI_DSI_MODE_VIDEO BIT(0)

sys/dev/drm/include/drm/drm_mipi_dsi.h

116

#define MIPI_DSI_MODE_VIDEO_BURST BIT(1)

sys/dev/drm/include/drm/drm_mipi_dsi.h

118

#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)

sys/dev/drm/include/drm/drm_mipi_dsi.h

120

#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)

sys/dev/drm/include/drm/drm_mipi_dsi.h

122

#define MIPI_DSI_MODE_VIDEO_HSE BIT(4)

sys/dev/drm/include/drm/drm_mipi_dsi.h

124

#define MIPI_DSI_MODE_VIDEO_HFP BIT(5)

sys/dev/drm/include/drm/drm_mipi_dsi.h

126

#define MIPI_DSI_MODE_VIDEO_HBP BIT(6)

sys/dev/drm/include/drm/drm_mipi_dsi.h

128

#define MIPI_DSI_MODE_VIDEO_HSA BIT(7)

sys/dev/drm/include/drm/drm_mipi_dsi.h

130

#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)

sys/dev/drm/include/drm/drm_mipi_dsi.h

132

#define MIPI_DSI_MODE_EOT_PACKET BIT(9)

sys/dev/drm/include/drm/drm_mipi_dsi.h

134

#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)

sys/dev/drm/include/drm/drm_mipi_dsi.h

136

#define MIPI_DSI_MODE_LPM BIT(11)

sys/dev/drm/include/drm/drm_mipi_dsi.h

21

#define MIPI_DSI_MSG_REQ_ACK BIT(0)

sys/dev/drm/include/drm/drm_mipi_dsi.h

23

#define MIPI_DSI_MSG_USE_LPM BIT(1)

sys/dev/drm/include/drm/drm_mm.h

121

DRM_MM_INSERT_ONCE = BIT(31),

sys/dev/drm/include/drm/drm_modeset_lock.h

99

#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0)

sys/dev/drm/include/linux/i2c.h

99

#define I2C_LOCK_SEGMENT BIT(1)

sys/dev/drm/linux_hdmi.c

113

ptr[0] |= BIT(4);

sys/dev/drm/linux_hdmi.c

117

ptr[0] |= BIT(3);

sys/dev/drm/linux_hdmi.c

120

ptr[0] |= BIT(2);

sys/dev/drm/linux_hdmi.c

131

ptr[2] |= BIT(7);

sys/dev/drm/linux_hdmi.c

291

ptr[4] |= BIT(7);

sys/dev/sound/pcm/feeder_eq.c

143

#define FEEDEQ_DECLARE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_eq.c

145

feed_eq_biquad_##SIGN##BIT##ENDIAN(struct feed_eq_info *info, \

sys/dev/sound/pcm/feeder_eq.c

159

dst += j * PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_eq.c

161

dst -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_eq.c

162

v = _PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \

sys/dev/sound/pcm/feeder_eq.c

164

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, v); \

sys/dev/sound/pcm/feeder_eq.c

177

v = _PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \

sys/dev/sound/pcm/feeder_eq.c

178

v <<= 32 - BIT; \

sys/dev/sound/pcm/feeder_eq.c

207

v >>= 32 - BIT; \

sys/dev/sound/pcm/feeder_eq.c

208

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, v); \

sys/dev/sound/pcm/feeder_eq.c

209

dst += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_eq.c

236

#define FEEDEQ_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_eq.c

238

AFMT_##SIGN##BIT##_##ENDIAN, \

sys/dev/sound/pcm/feeder_eq.c

239

feed_eq_biquad_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_format.c

78

#define FEEDFORMAT_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_format.c

80

AFMT_##SIGN##BIT##_##ENDIAN, \

sys/dev/sound/pcm/feeder_format.c

81

intpcm_read_##SIGN##BIT##ENDIAN, \

sys/dev/sound/pcm/feeder_format.c

82

intpcm_write_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_matrix.c

115

#define FEEDMATRIX_CLIP_CHECK(v, BIT) do { \

sys/dev/sound/pcm/feeder_matrix.c

116

if ((v) < PCM_S##BIT##_MIN || (v) > PCM_S##BIT##_MAX) \

sys/dev/sound/pcm/feeder_matrix.c

122

#define FEEDMATRIX_DECLARE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_matrix.c

124

feed_matrix_##SIGN##BIT##ENDIAN(struct feed_matrix_info *info, \

sys/dev/sound/pcm/feeder_matrix.c

135

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, \

sys/dev/sound/pcm/feeder_matrix.c

137

dst += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_matrix.c

141

v = _PCM_READ_##SIGN##BIT##_##ENDIAN( \

sys/dev/sound/pcm/feeder_matrix.c

143

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, \

sys/dev/sound/pcm/feeder_matrix.c

145

dst += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_matrix.c

153

v = _PCM_READ_##SIGN##BIT##_##ENDIAN( \

sys/dev/sound/pcm/feeder_matrix.c

161

FEEDMATRIX_CLIP_CHECK(accum, BIT); \

sys/dev/sound/pcm/feeder_matrix.c

163

v = (accum > PCM_S##BIT##_MAX) ? \

sys/dev/sound/pcm/feeder_matrix.c

164

PCM_S##BIT##_MAX : \

sys/dev/sound/pcm/feeder_matrix.c

165

((accum < PCM_S##BIT##_MIN) ? \

sys/dev/sound/pcm/feeder_matrix.c

166

PCM_S##BIT##_MIN : \

sys/dev/sound/pcm/feeder_matrix.c

168

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, v); \

sys/dev/sound/pcm/feeder_matrix.c

169

dst += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_matrix.c

196

#define FEEDMATRIX_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_matrix.c

198

AFMT_##SIGN##BIT##_##ENDIAN, \

sys/dev/sound/pcm/feeder_matrix.c

199

feed_matrix_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_mixer.c

100

feed_mixer_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_mixer.c

47

#define FEEDMIXER_DECLARE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_mixer.c

49

feed_mixer_##SIGN##BIT##ENDIAN(uint8_t *src, uint8_t *dst, \

sys/dev/sound/pcm/feeder_mixer.c

52

intpcm##BIT##_t z; \

sys/dev/sound/pcm/feeder_mixer.c

59

src -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_mixer.c

60

dst -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_mixer.c

61

count -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_mixer.c

62

x = PCM_READ_##SIGN##BIT##_##ENDIAN(src); \

sys/dev/sound/pcm/feeder_mixer.c

63

y = PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \

sys/dev/sound/pcm/feeder_mixer.c

64

z = INTPCM##BIT##_T(x) + y; \

sys/dev/sound/pcm/feeder_mixer.c

65

x = PCM_CLAMP_##SIGN##BIT(z); \

sys/dev/sound/pcm/feeder_mixer.c

66

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, x); \

sys/dev/sound/pcm/feeder_mixer.c

97

#define FEEDMIXER_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_mixer.c

99

AFMT_##SIGN##BIT##_##ENDIAN, PCM_##BIT##_BPS, \

sys/dev/sound/pcm/feeder_rate.c

436

#define Z_DECLARE_LINEAR(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

438

z_feed_linear_##SIGN##BIT##ENDIAN(struct z_info *info, uint8_t *dst) \

sys/dev/sound/pcm/feeder_rate.c

448

PCM_##BIT##_BPS); \

sys/dev/sound/pcm/feeder_rate.c

449

sy = sx - (info->channels * PCM_##BIT##_BPS); \

sys/dev/sound/pcm/feeder_rate.c

454

x = _PCM_READ_##SIGN##BIT##_##ENDIAN(sx); \

sys/dev/sound/pcm/feeder_rate.c

455

y = _PCM_READ_##SIGN##BIT##_##ENDIAN(sy); \

sys/dev/sound/pcm/feeder_rate.c

456

x = Z_LINEAR_INTERPOLATE_##BIT(z, x, y); \

sys/dev/sound/pcm/feeder_rate.c

457

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, x); \

sys/dev/sound/pcm/feeder_rate.c

458

sx += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

459

sy += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

460

dst += PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

472

#define Z_CLIP_CHECK(v, BIT) do { \

sys/dev/sound/pcm/feeder_rate.c

473

if ((v) > PCM_S##BIT##_MAX) { \

sys/dev/sound/pcm/feeder_rate.c

475

(intmax_t)(v), (intmax_t)PCM_S##BIT##_MAX); \

sys/dev/sound/pcm/feeder_rate.c

476

} else if ((v) < PCM_S##BIT##_MIN) { \

sys/dev/sound/pcm/feeder_rate.c

478

(intmax_t)(v), (intmax_t)PCM_S##BIT##_MIN); \

sys/dev/sound/pcm/feeder_rate.c

485

#define Z_CLAMP(v, BIT) \

sys/dev/sound/pcm/feeder_rate.c

486

(((v) > PCM_S##BIT##_MAX) ? PCM_S##BIT##_MAX : \

sys/dev/sound/pcm/feeder_rate.c

487

(((v) < PCM_S##BIT##_MIN) ? PCM_S##BIT##_MIN : (v)))

sys/dev/sound/pcm/feeder_rate.c

495

#define _Z_SINC_ACCUMULATE(SIGN, BIT, ENDIAN, adv) \

sys/dev/sound/pcm/feeder_rate.c

499

x = _PCM_READ_##SIGN##BIT##_##ENDIAN(p); \

sys/dev/sound/pcm/feeder_rate.c

500

v += Z_NORM_##BIT((intpcm64_t)x * coeff); \

sys/dev/sound/pcm/feeder_rate.c

502

p adv##= info->channels * PCM_##BIT##_BPS

sys/dev/sound/pcm/feeder_rate.c

520

#define Z_DECLARE_SINC(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

522

z_feed_sinc_##SIGN##BIT##ENDIAN(struct z_info *info, uint8_t *dst) \

sys/dev/sound/pcm/feeder_rate.c

533

ch = info->channels * PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

537

dst -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

538

ch -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

543

info->channels * PCM_##BIT##_BPS) + ch; \

sys/dev/sound/pcm/feeder_rate.c

545

Z_SINC_ACCUMULATE(SIGN, BIT, ENDIAN, +); \

sys/dev/sound/pcm/feeder_rate.c

549

PCM_##BIT##_BPS) + ch; \

sys/dev/sound/pcm/feeder_rate.c

551

Z_SINC_ACCUMULATE(SIGN, BIT, ENDIAN, -); \

sys/dev/sound/pcm/feeder_rate.c

553

v = Z_SCALE_##BIT(v, info->z_scale); \

sys/dev/sound/pcm/feeder_rate.c

555

v >>= Z_COEFF_SHIFT - Z_GUARD_BIT_##BIT; \

sys/dev/sound/pcm/feeder_rate.c

556

Z_CLIP_CHECK(v, BIT); \

sys/dev/sound/pcm/feeder_rate.c

557

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, Z_CLAMP(v, BIT)); \

sys/dev/sound/pcm/feeder_rate.c

561

#define Z_DECLARE_SINC_POLYPHASE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

563

z_feed_sinc_polyphase_##SIGN##BIT##ENDIAN(struct z_info *info, uint8_t *dst) \

sys/dev/sound/pcm/feeder_rate.c

570

ch = info->channels * PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

575

dst -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

576

ch -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

582

x = _PCM_READ_##SIGN##BIT##_##ENDIAN(p); \

sys/dev/sound/pcm/feeder_rate.c

583

v += Z_NORM_##BIT((intpcm64_t)x * *z_pcoeff); \

sys/dev/sound/pcm/feeder_rate.c

585

p += info->channels * PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

586

x = _PCM_READ_##SIGN##BIT##_##ENDIAN(p); \

sys/dev/sound/pcm/feeder_rate.c

587

v += Z_NORM_##BIT((intpcm64_t)x * *z_pcoeff); \

sys/dev/sound/pcm/feeder_rate.c

589

p += info->channels * PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_rate.c

592

v = Z_SCALE_##BIT(v, info->z_scale); \

sys/dev/sound/pcm/feeder_rate.c

594

v >>= Z_COEFF_SHIFT - Z_GUARD_BIT_##BIT; \

sys/dev/sound/pcm/feeder_rate.c

595

Z_CLIP_CHECK(v, BIT); \

sys/dev/sound/pcm/feeder_rate.c

596

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, Z_CLAMP(v, BIT)); \

sys/dev/sound/pcm/feeder_rate.c

600

#define Z_DECLARE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

601

Z_DECLARE_LINEAR(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

602

Z_DECLARE_SINC(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

603

Z_DECLARE_SINC_POLYPHASE(SIGN, BIT, ENDIAN)

sys/dev/sound/pcm/feeder_rate.c

637

#define Z_RESAMPLER_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_rate.c

639

AFMT_##SIGN##BIT##_##ENDIAN, \

sys/dev/sound/pcm/feeder_rate.c

642

[Z_RESAMPLER_LINEAR] = z_feed_linear_##SIGN##BIT##ENDIAN, \

sys/dev/sound/pcm/feeder_rate.c

643

[Z_RESAMPLER_SINC] = z_feed_sinc_##SIGN##BIT##ENDIAN, \

sys/dev/sound/pcm/feeder_rate.c

645

z_feed_sinc_polyphase_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_volume.c

103

#define FEEDVOLUME_ENTRY(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_volume.c

105

AFMT_##SIGN##BIT##_##ENDIAN, \

sys/dev/sound/pcm/feeder_volume.c

106

feed_volume_##SIGN##BIT##ENDIAN \

sys/dev/sound/pcm/feeder_volume.c

51

#define FEEDVOLUME_DECLARE(SIGN, BIT, ENDIAN) \

sys/dev/sound/pcm/feeder_volume.c

53

feed_volume_##SIGN##BIT##ENDIAN(int *vol, int *matrix, \

sys/dev/sound/pcm/feeder_volume.c

56

intpcm##BIT##_t v; \

sys/dev/sound/pcm/feeder_volume.c

60

dst += count * PCM_##BIT##_BPS * channels; \

sys/dev/sound/pcm/feeder_volume.c

64

dst -= PCM_##BIT##_BPS; \

sys/dev/sound/pcm/feeder_volume.c

66

x = PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \

sys/dev/sound/pcm/feeder_volume.c

67

v = FEEDVOLUME_CALC##BIT(x, vol[matrix[i]]); \

sys/dev/sound/pcm/feeder_volume.c

68

x = PCM_CLAMP_##SIGN##BIT(v); \

sys/dev/sound/pcm/feeder_volume.c

69

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, x); \

sys/dev/sound/pcm/intpcm.h

38

#define INTPCM_DECLARE_OP_WRITE(SIGN, BIT, ENDIAN, SHIFT) \

sys/dev/sound/pcm/intpcm.h

40

intpcm_write_##SIGN##BIT##ENDIAN(uint8_t *dst, intpcm_t v) \

sys/dev/sound/pcm/intpcm.h

43

_PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, v >> SHIFT); \

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

1001

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

1003

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

1005

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

1015

#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

1018

#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

644

ENA_ADMIN_RSS_L2_DA = BIT(0),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

647

ENA_ADMIN_RSS_L2_SA = BIT(1),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

650

ENA_ADMIN_RSS_L3_DA = BIT(2),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

653

ENA_ADMIN_RSS_L3_SA = BIT(3),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

656

ENA_ADMIN_RSS_L4_DP = BIT(4),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

659

ENA_ADMIN_RSS_L4_SP = BIT(5),

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

934

#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

936

#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

938

#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

946

#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

954

#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

958

#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

965

#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

967

#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

970

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

972

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

974

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

976

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

978

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

980

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

982

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

984

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

985

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

987

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

989

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

991

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

999

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1006

#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1008

#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1010

#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1018

#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1026

#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1030

#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1037

#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1039

#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1042

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1044

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1046

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1048

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1050

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1052

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1054

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1056

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1057

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1059

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1061

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1063

#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1071

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1073

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1075

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1077

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1087

#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

1090

#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

714

ENA_ADMIN_RSS_L2_DA = BIT(0),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

717

ENA_ADMIN_RSS_L2_SA = BIT(1),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

720

ENA_ADMIN_RSS_L3_DA = BIT(2),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

723

ENA_ADMIN_RSS_L3_SA = BIT(3),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

726

ENA_ADMIN_RSS_L4_DP = BIT(4),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_admin_defs.h

729

ENA_ADMIN_RSS_L4_SP = BIT(5),

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

311

#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

313

#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

315

#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

317

#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

319

#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

322

#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

324

#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

328

#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

330

#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

332

#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

334

#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

344

#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

348

#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

350

#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

352

#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

354

#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

356

#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

358

#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

360

#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

371

#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

374

#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

376

#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

378

#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

380

#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

389

#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

391

#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

393

#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

395

#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

397

#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

399

#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

401

#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

403

#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

410

#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)

sys/dev/virtual/amazon/ena/ena-com/ena_defs/ena_eth_io_defs.h

415

#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

312

#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

314

#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

316

#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

318

#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

320

#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

323

#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

325

#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

329

#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

331

#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

333

#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

335

#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

345

#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

349

#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

351

#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

353

#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

355

#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

357

#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

359

#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

361

#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

372

#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

375

#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

377

#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

379

#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

381

#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

390

#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

392

#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

394

#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

396

#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

398

#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

400

#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

402

#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

404

#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

411

#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_io_defs.h

416

#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)

sys/dev/virtual/amazon/ena/ena.c

3244

aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE);

sys/dev/virtual/amazon/ena/ena.c

3253

*wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));

sys/dev/virtual/amazon/ena/ena.h

116

#define ENA_MMIO_DISABLE_REG_READ BIT(0)

tools/tools/net80211/w00t/libw00t/w00t.c

210

if (present & BIT(IEEE80211_RADIOTAP_FLAGS)) {

tools/tools/net80211/w00t/libw00t/w00t.c

211

if (present & BIT(IEEE80211_RADIOTAP_TSFT))

tools/tools/net80211/wesside/wesside/wesside.c

2339

if (present & BIT(IEEE80211_RADIOTAP_FLAGS)) {

tools/tools/net80211/wesside/wesside/wesside.c

2340

if (present & BIT(IEEE80211_RADIOTAP_TSFT))

tools/tools/net80211/wlaninject/wlaninject.c

492

if (present & BIT(IEEE80211_RADIOTAP_FLAGS)) {

tools/tools/net80211/wlaninject/wlaninject.c

493

if (present & BIT(IEEE80211_RADIOTAP_TSFT))

usr.bin/lastcomm/lastcomm.c

233

BIT(ASU, 'S');

usr.bin/lastcomm/lastcomm.c

234

BIT(AFORK, 'F');

usr.bin/lastcomm/lastcomm.c

235

BIT(ACOMPAT, 'C');

usr.bin/lastcomm/lastcomm.c

236

BIT(ACORE, 'D');

usr.bin/lastcomm/lastcomm.c

237

BIT(AXSIG, 'X');

usr.bin/systat/convtbl.c

60

[SC_BIT] = { BIT, 1, "b", "bit" },

usr.bin/systat/convtbl.c

61

[SC_KILOBIT] = { BIT, KILO, "Kb", "kbit" },

usr.bin/systat/convtbl.c

62

[SC_MEGABIT] = { BIT, MEGA, "Mb", "mbit" },

usr.bin/systat/convtbl.c

63

[SC_GIGABIT] = { BIT, GIGA, "Gb", "gbit" },

usr.bin/systat/convtbl.c

64

[SC_TERABIT] = { BIT, TERA, "Tb", "tbit" },

usr.bin/systat/convtbl.c

65

[SC_AUTOBIT] = { BIT, 0, "", "autobit" },

usr.bin/systat/convtbl.c

89

tmp >= 1000 / (disp_bits ? BIT : BYTE) &&