#ifndef _MACHINE_PIO_H_
#define _MACHINE_PIO_H_
#ifdef __OPTIMIZE__
#define __use_immediate_port(port) \
(__builtin_constant_p((port)) && (port) < 0x100)
#else
#define __use_immediate_port(port) 0
#endif
#define inb(port) \
( __use_immediate_port(port) ? __inbc(port) : __inb(port))
static __inline u_int8_t
__inbc(unsigned port)
{
u_int8_t data;
__asm volatile("inb %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int8_t
__inb(unsigned port)
{
u_int8_t data;
__asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insb(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\tinsb" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define inw(port) \
( __use_immediate_port(port) ? __inwc(port) : __inw(port))
static __inline u_int16_t
__inwc(unsigned port)
{
u_int16_t data;
__asm volatile("inw %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int16_t
__inw(unsigned port)
{
u_int16_t data;
__asm volatile("inw %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insw(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\tinsw" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define inl(port) \
( __use_immediate_port(port) ? __inlc(port) : __inl(port))
static __inline u_int32_t
__inlc(unsigned port)
{
u_int32_t data;
__asm volatile("inl %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int32_t
__inl(unsigned port)
{
u_int32_t data;
__asm volatile("inl %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insl(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\tinsl" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define outb(port, data) \
(__use_immediate_port(port) ? __outbc(port, data) : \
__outb(port, data))
static __inline void
__outbc(unsigned port, u_int8_t data)
{
__asm volatile("outb %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outb(unsigned port, u_int8_t data)
{
__asm volatile("outb %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsb(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\toutsb" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
#define outw(port, data) \
( __use_immediate_port(port) ? __outwc(port, data) : \
__outw(port, data))
static __inline void
__outwc(unsigned port, u_int16_t data)
{
__asm volatile("outw %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outw(unsigned port, u_int16_t data)
{
__asm volatile("outw %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsw(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\toutsw" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
#define outl(port, data) \
( __use_immediate_port(port) ? __outlc(port, data) : \
__outl(port, data))
static __inline void
__outlc(unsigned port, u_int32_t data)
{
__asm volatile("outl %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outl(unsigned port, u_int32_t data)
{
__asm volatile("outl %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsl(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("repne\n\toutsl" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
#endif