LSHIFT
LSHIFT(K, K);
LSHIFT(K, K);
LSHIFT(K, K);
LSHIFT(K, K);
wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK);
tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) |
LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK));
test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
cfpp |= LSHIFT(16, ATW_CFPP_CFPMD);
LSHIFT(22, ATW_TOFS0_USCNT_MASK) |
ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */,
LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) |
LSHIFT(0xff, ATW_RSPT_MIRT_MASK));
ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) |
LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK));
LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK));
gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);
gpio |= LSHIFT(1, ATW_GPIO_EN_MASK);
gpio |= LSHIFT(1, ATW_GPIO_O_MASK);
LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));
LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK));
LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK));
LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)
reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK),
LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) |
LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
LSHIFT(addr, SI4126_TWI_ADDR_MASK);
reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK);
LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |
LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |
LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |
LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK));
LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |
LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK));
LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));
LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));
reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK);
bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);
bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK);
cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK);
cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK);
LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) |
LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |
LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval,
ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK));
ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
htole32(LSHIFT(dmamap->dm_segs[seg].ds_len,
reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
#define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK)
#define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK)
#define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK)
#define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK)
#define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK)
#define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK)
#define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK)
#define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK)
#define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK)
#define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK)
#define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ATW_TEST1_TESTMODE_MASK)
#define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ATW_TEST1_TESTMODE_MASK)
#define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ATW_TEST1_TESTMODE_MASK)
#define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ATW_TEST1_TESTMODE_MASK)
#define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK)
#define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK)
#define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK)
#define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK)
#define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK)
#define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK)
#define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK)
#define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK)
(LSHIFT(0x0c, ATW_MMIWADDR_GAIN_MASK) | \
LSHIFT(0x0a, ATW_MMIWADDR_RATE_MASK) | \
LSHIFT(0x0e, ATW_MMIWADDR_LENHI_MASK) | \
LSHIFT(0x10, ATW_MMIWADDR_LENLO_MASK))
(LSHIFT(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \
LSHIFT(RF3000_CTL, ATW_MMIWADDR_RATE_MASK))
(LSHIFT(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \
LSHIFT(0x7e, ATW_MMIRADDR1_RXSTAT_MASK))
(LSHIFT(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \
LSHIFT(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK))
(LSHIFT(0x0, ATW_MMIRADDR2_ID_MASK) | \
LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
(LSHIFT(0x7e, ATW_MMIRADDR2_ID_MASK) | \
LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
#define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK)
#define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK)
#define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK)
#define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK)
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \
#define MAX2820_SYNTH_R_22MHZ LSHIFT(0, MAX2820_SYNTH_R_MASK)
#define MAX2820_SYNTH_R_44MHZ LSHIFT(1, MAX2820_SYNTH_R_MASK)
#define MAX2820_SYNTH_R_DEFAULT LSHIFT(0, MAX2820_SYNTH_R_MASK)
#define MAX2820_CHANNEL_RSVD_DEFAULT LSHIFT(0, MAX2820_CHANNEL_RSVD)
#define MAX2820_CHANNEL_CF_DEFAULT LSHIFT(37, MAX2820_CHANNEL_CF_MASK)
#define MAX2820_RECEIVE_BW_8_5MHZ LSHIFT(0, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_BW_8MHZ LSHIFT(1, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_BW_7_5MHZ LSHIFT(2, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_BW_7MHZ LSHIFT(3, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_BW_6_5MHZ LSHIFT(4, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_BW_6MHZ LSHIFT(5, MAX2820_RECEIVE_BW_MASK)
#define MAX2820_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_2C_MASK)
#define MAX2820_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_1C_MASK)
#define MAX2820_RECEIVE_DL_DEFAULT LSHIFT(1, MAX2820_RECEIVE_DL_MASK)
#define MAX2820_RECEIVE_SF_DEFAULT LSHIFT(0, MAX2820_RECEIVE_SF)
#define MAX2820A_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_2C_MASK)
#define MAX2820A_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_1C_MASK)
#define MAX2820A_RECEIVE_RSVD0_DEFAULT LSHIFT(2, MAX2820A_RECEIVE_RSVD0_MASK)
#define MAX2820A_RECEIVE_RSVD1_DEFAULT LSHIFT(2,MAX2820_RECEIVE_RSVD1_MASK)
#define MAX2820_TRANSMIT_PA_DEFAULT LSHIFT(0, MAX2820_TRANSMIT_PA_MASK)
ctl = LSHIFT(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK);
LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK);
bintritv |= LSHIFT(1000, RTW_BINTRITV_BINTRITV);
RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND));
RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV));
u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY);
LSHIFT(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
syna = LSHIFT(nf, SA2400_SYNA_NF_MASK) | LSHIFT(n, SA2400_SYNA_N_MASK);
synb = LSHIFT(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |
LSHIFT(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */
agc = LSHIFT(25, SA2400_AGC_MAXGAIN_MASK);
agc |= LSHIFT(7, SA2400_AGC_BBPDELAY_MASK);
agc |= LSHIFT(15, SA2400_AGC_LNADELAY_MASK);
agc |= LSHIFT(27, SA2400_AGC_RXONDELAY_MASK);
manrx |= LSHIFT(1023, SA2400_MANRX_RXGAIN_MASK);
LSHIFT(freq - 2400, MAX2820_CHANNEL_CF_MASK));
LSHIFT(4, MAX2820A_RECEIVE_1C_MASK) |
LSHIFT(1, MAX2820A_RECEIVE_2C_MASK))) != 0)
LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK);
wrbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN |
LSHIFT(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK,
rdbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) |
return LSHIFT(data_and_addr, RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK |
bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) |
LSHIFT(addr, MAX2820_TWI_ADDR_MASK);
bits = LSHIFT(val, SA2400_TWI_DATA_MASK) |
LSHIFT(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN;
bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
LSHIFT(addr, SI4126_TWI_ADDR_MASK);
bits = LSHIFT(val, RTL8225_TWI_DATA_MASK) |
LSHIFT(addr, RTL8225_TWI_ADDR_MASK);
return LSHIFT(lodata, RTW8180_PHYCFG_MAC_MAXIM_LODATA_MASK) |
LSHIFT(hidata, RTW8180_PHYCFG_MAC_MAXIM_HIDATA_MASK) |
LSHIFT(addr, RTW8180_PHYCFG_MAC_MAXIM_ADDR_MASK);
reg = LSHIFT(addr, RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK) |
LSHIFT(val, RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK);
*rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM),
cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
#define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK)
#define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK)
#define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK)
#define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK)
#define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK)
#define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK)
#define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK)
#define RTW8180_BRSR_MBR_1MBPS LSHIFT(0, RTW8180_BRSR_MBR_MASK)
#define RTW8180_BRSR_MBR_2MBPS LSHIFT(1, RTW8180_BRSR_MBR_MASK)
#define RTW8180_BRSR_MBR_5MBPS LSHIFT(2, RTW8180_BRSR_MBR_MASK)
#define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK)
#define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK)
#define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK)
#define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK)
#define RTW8180_BRSR_MBR_11MBPS LSHIFT(3, RTW8180_BRSR_MBR_MASK)
#define RTW8185_RR_MAX_1MPBS LSHIFT(0, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_2MPBS LSHIFT(1, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_5MPBS LSHIFT(2, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_11MPBS LSHIFT(3, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_6MPBS LSHIFT(4, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_9MPBS LSHIFT(5, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_12MPBS LSHIFT(6, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_18MPBS LSHIFT(7, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_24MPBS LSHIFT(8, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_36MPBS LSHIFT(9, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_48MPBS LSHIFT(10, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MAX_54MPBS LSHIFT(11, RTW8185_RR_MAX_MASK)
#define RTW8185_RR_MIN_1MPBS LSHIFT(0, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_2MPBS LSHIFT(1, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_5MPBS LSHIFT(2, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_11MPBS LSHIFT(3, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_6MPBS LSHIFT(4, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_9MPBS LSHIFT(5, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_12MPBS LSHIFT(6, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_18MPBS LSHIFT(7, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_24MPBS LSHIFT(8, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_36MPBS LSHIFT(9, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_48MPBS LSHIFT(10, RTW8185_RR_MIN_MASK)
#define RTW8185_RR_MIN_54MPBS LSHIFT(11, RTW8185_RR_MIN_MASK)
#define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK)
#define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */
#define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */
#define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */
#define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */
#define RTW8180_RCR_RXFTH_64 LSHIFT(2, RTW8180_RCR_RXFTH_MASK)
#define RTW8180_RCR_RXFTH_128 LSHIFT(3, RTW8180_RCR_RXFTH_MASK)
#define RTW8180_RCR_RXFTH_256 LSHIFT(4, RTW8180_RCR_RXFTH_MASK)
#define RTW8180_RCR_RXFTH_512 LSHIFT(5, RTW8180_RCR_RXFTH_MASK)
#define RTW8180_RCR_RXFTH_1024 LSHIFT(6, RTW8180_RCR_RXFTH_MASK)
#define RTW8180_RCR_RXFTH_WHOLE LSHIFT(7, RTW8180_RCR_RXFTH_MASK)
#define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK)
#define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK)
#define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK)
#define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK)
#define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK)
#define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK)
#define RTW8180_CONFIG0_GL_USA LSHIFT(3, RTW8180_CONFIG0_GL_MASK)
#define RTW8180_CONFIG0_GL_EUROPE LSHIFT(2, RTW8180_CONFIG0_GL_MASK)
#define RTW8180_CONFIG0_GL_JAPAN LSHIFT(1, RTW8180_CONFIG0_GL_MASK)
#define RTW8180_CONFIG0_GL_JAPAN2 LSHIFT(0, RTW8180_CONFIG0_GL_MASK)
#define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK)
#define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK)
#define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK)
#define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK)
#define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK)
LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
#define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK)
#define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK)
#define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK)
#define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK)
#define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK)
#define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK)
#define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK)
#define RTW8180_SCR_KM_WEP104 LSHIFT(1, RTW8180_SCR_KM_MASK)
#define RTW8180_SCR_KM_WEP40 LSHIFT(0, RTW8180_SCR_KM_MASK)
LSHIFT(0, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
LSHIFT(1, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
LSHIFT(3, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
#define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK)
#define SA2400_OPMODE_MODE_SLEEP LSHIFT(0, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_TXRX LSHIFT(1, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_WAIT LSHIFT(2, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_RXMGC LSHIFT(3, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_FCALIB LSHIFT(4, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_DCALIB LSHIFT(5, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_FASTTXRXMGC LSHIFT(6, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_RESET LSHIFT(7, SA2400_OPMODE_MODE_MASK)
#define SA2400_OPMODE_MODE_VCOCALIB LSHIFT(8, SA2400_OPMODE_MODE_MASK)
SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK))
#define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK)
#define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK)
#define SA2400_SYNB_L_NORMAL LSHIFT(2, SA2400_SYNB_L_MASK)
#define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK)
#define SA2400_SYNC_CP_NORMAL_ LSHIFT(0, SA2400_SYNC_CP_MASK)
#define SA2400_SYNC_CP_THIRD_ LSHIFT(1, SA2400_SYNC_CP_MASK)
#define SA2400_SYNC_CP_NORMAL LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */
#define SA2400_SYNC_CP_THIRD LSHIFT(3, SA2400_SYNC_CP_MASK)
#define SI4126_MAIN_AUXSEL_RSVD LSHIFT(0x0, SI4126_MAIN_AUXSEL_MASK)
#define SI4126_MAIN_AUXSEL_FRCLOW LSHIFT(0x1, SI4126_MAIN_AUXSEL_MASK)
#define SI4126_MAIN_AUXSEL_LDETB LSHIFT(0x3, SI4126_MAIN_AUXSEL_MASK)
%left LSHIFT RSHIFT
| expr LSHIFT expr { $$ = $1 << $3; }