sys/dev/pci/drm/i915/display/intel_display_irq.c

224

intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]);

sys/dev/pci/drm/i915/display/intel_display_irq.c

225

intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));

sys/dev/pci/drm/i915/display/intel_display_regs.h

1278

#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \

sys/dev/pci/drm/i915/gvt/handlers.c

2490

MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2497

MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2504

MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

761

MMIO_D(GEN8_DE_PIPE_IMR(PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

765

MMIO_D(GEN8_DE_PIPE_IMR(PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

769

MMIO_D(GEN8_DE_PIPE_IMR(PIPE_C));